8K x 8 Static RAM
CY7C185A
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
Features
• High speed
—20 ns
• CMOS for optimum speed/power
• Low active power
—743 mW
• Low standb y Pow er
—220 mW
• TTL-compatibl e input s and outputs
• Easy memory expansion with CE1, CE2 and OE features
• A utomatic power-d ow n w hen deselected
Functional Description
The CY7C185A i s a high-performance CMOS static RAM or-
ganized as 8192 words by 8 bits. Easy memory expansion is
pro vided by an activ e LOW Chi p Enab le (CE1) , an active HIGH
Ch ip En able (CE 2), an active LOW Output Enable (OE), and
three- state drivers. The de vice has an auto ma ti c power-down
feature (CE1), reducing the power consumption by over 70%
when deselected. The CY7C185A is in the standard
300-mil-wide DIP package and leadless chip carrier.
Writing to the device is accomplished when the Chip Enable
one (CE1) and Write Enable (WE ) inputs are both LOW, and
the Chip Enab le two (CE2) input is HIGH.
Data on the eight I/O pi ns (I /O0 t hrough I /O7) is written into the
memory location specified on the address pins (A0 through
A12).
Reading the device is accomplished by taking Chip Enable
one (CE1) and Output Enable (OE) LOW, while taking Write
Enable (W E) and Chip Enable two (CE2) HIGH. Under these
conditions, the contents of the memory location specified on
the address pins will appear on the I/O pins.
The I/O pi ns remain i n a high-im pedance st ate when Chi p En-
able one (CE1) or Output Enable (OE) is HI GH, or W r ite En-
able (WE) or Chip Enable two (CE2) is LOW.
A die coat is used to ensure alpha imm unity.
28
Logic Block Diagram Pin Configurations
C185A–1
A1
A2
A3
A4
A5
A6
A7
A8
A0
A10
A9
A11
A12
I/O0
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12 19
18
A6
VCC
NC
A7
A8
A9
A10
A11
A12
I/O0
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
GND
Top View
LCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
WE
I/O3
I/O4
I/O2
I/O5
A5
A4
8K x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CE1
CE2
WE
OE
Top View
DIP
C185A–2
C185A–3
I/O1
Selection Guide[1]
7C185A–20 7C185A–25 7C185A–35 7C185A–45
Maximum Access Time (ns) 20 25 35 45
Maxim um Opera ting Curr ent ( mA) Military 135 125 125 125
Maximum Standby Current (mA) Military 40/20 40/20 30/20 30/20
Note:
1. For commercial specifications, see the CY7C185 data sheet.
CY7C185A
2
Maximum Ratings
(Above which the useful l ife may be impaired. For user guide-
li nes, not tes ted.)
Storage Temperature ... .. ......... ...... ..............–65°C to +150°C
Ambient Temperature with
Power Applied.............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pi n 2 8 to Pi n 14)... ... .. ..... ....... ........ ....... ..... ... –0.5V to +7.0V
DC Voltag e Appli ed to Output s
in High Z State[2] .....................................................–0 . 5V to + 7. 0 V
DC Input Voltage[2].................................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage... .. ...... .. ......... ...... .. ......... ... >2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Curr ent... .. ....... ...... .. .................... ....... .. .. . >200 mA
Operating Range
Range Ambient
Temperature[3] VCC
Military[4] –55°C to +125°C 5V ± 10%
Electrical Characteristics O v er t he O perating Ra ng e[4]
7C185A–20
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8. 0 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC V
VIL Input LOW Voltage[2] –0.5 0.8 V
IIX Input Load Current GND ≤ VI ≤ VCC –10 +10 µA
IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled –10 +10 µA
IOS Output Short Circuit Current[5] VCC = Max., V OUT = GND –300 mA
ICC VCC Operating Supply Current VCC = Max . IOUT = 0 mA Military 135 mA
ISB1 Autom a ti c CE1 P ower-Down
Current Max. VCC, CE1 ≥ VIH,
Min. Duty Cycle = 100% Military 40 mA
ISB2 Autom a ti c CE1 P ower-Down
Current Max. VCC, CE1 ≥ VCC –0.3V
VIN ≥ VCC –0. 3Vor V IN ≥ 0.3V Military 20 mA
Electrical Characteristics O v er t he O perating Ra ng e[4] (continued)
7C185A–25 7C185A–35, 45
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output H I GH Voltage VCC = Min., IOH = –4. 0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8. 0 mA 0.4 0.4 V
VIH Input HIGH Volta ge 2.2 VCC 2.2 VCC V
VIL Input LOW Voltage[2] –0.5 0.8 –0.5 0.8 V
IIX Input Load Curre nt GND ≤ VI ≤ VCC –10 +10 –10 +10 µA
IOZ Outpu t Leakage Current GND ≤ VI ≤ VCC, Output Disab led –10 +10 –10 +10 µA
IOS Outpu t Short
Circuit Cur rent[5] VCC = Max., V OUT = GND –300 –300 mA
ICC VCC Op er ati ng Supp l y
Current VCC = Max., IOUT = 0 mA Military 125 125 mA
ISB1 A uto ma ti c C E 1
P ower-Down Current Max. VCC, CE1 ≥ VIH,
Min. Du ty Cy cl e=100% Military 40 30 mA
ISB2 A uto ma ti c C E 1
P ower-Down Current Ma x . V CC, C E1 ≥ VCC –0.3V
VIN ≥ VCC –0.3V or VIN ≥ 0.3V Military 20 20 mA
Notes:
2. VIL (min.) = – 3.0V for pulse durations less than 30 ns.
3. TA is the case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C185A
3
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C , f = 1 MHz,
VCC = 5.0 V 10 pF
COUT Output Capacitance 10 pF
Note:
6. Tested initially and after any design or process changes that ma y affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481Ω
R2
255Ω
30pF GND
90% 90%
10%
≤5ns ≤5ns
5V
OUTPUT
R2
255Ω
5pF
(a) (b)
OUTPUT 1.73V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
R1 481Ω
10%
Equivalent to: THÉVENIN EQUIVALENT
C185A–4C185A–5
ALL INPUT PULSES
167Ω
CY7C185A
4
Switching Characteristics Ov er th e Op er at ing Ran ge [7]
7C185A–20 7C185A–25 7C185A–35 7C185A–45
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cyc le Ti m e 20 25 35 45 ns
tAA Address to Data Valid 20 25 35 45 ns
tOHA Data Hold from Addr ess Change 3333ns
tACE1 CE1 LOW to Data Valid 20 25 35 45 ns
tACE2 CE2 H IGH to Data V alid 20 25 35 30 ns
tDOE OE LOW to Data Valid 10 12 15 20 ns
tLZOE OE LOW to Low Z 3333ns
tHZOE OE HIGH to High Z[8] 810 12 15 ns
tLZCE1 CE1 LOW to Low Z[9] 5555ns
tLZCE2 CE2 HIGH to Low Z 3333ns
tHZCE CE1 HIGH to High Z[8, 9]
CE2 LOW to High Z 810 15 15 ns
tPU CE1 LOW to Power-Up 0000ns
tPD CE1 HIGH to P ower-Down 20 20 20 25 ns
WRITE CY CLE[10]
tWC Write Cycle Time 20 20 25 40 ns
tSCE1 CE1 LOW to Write End 15 20 25 30 ns
tSCE2 CE2 HIGH to Write End 15 20 25 30 ns
tAW Address Set-U p to Write End 15 20 25 30 ns
tHA Address Hold from Write End 0000ns
tSA Address Set-U p to Write Start 0000ns
tPWE WE Pulse Width 15 15 20 20 ns
tSD Data Se t-Up to Write End 10 10 15 15 ns
tHD Data Hold from Write End 0000ns
tLZWE WE HIG H to Low Z 3555ns
tHZWE WE LOW to High Z[8] 7 7 10 15 ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference le vels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given dev ice.
10. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
CY7C185A
5
Switching Waveforms
Notes:
11. Address valid prior to or coincident with CE transition LOW .
12. WE is HIGH for read cycle.
13. The internal write time of the memory is defined by the overlap of CE1 LOW , CE2 HIGH, and WE LO W . Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. Data I/O is high impedance if OE = VIH.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C185A–6
Read Cycle No. 1[10, 11]
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE tHZCE
tPD
OE
HIGH
DATA OUT
VCC
SUPPLY
CURRENT
CE2
CE1
OE
C185A–7
Read Cycle No. 2[1 1, 12]
DATA UNDEFINED HIGH IMPEDANCE
tHD
tHZOE
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE2
tSCE1
t
C185A–8
OE
DATA IN
DATA I/O
ADDRESS
CE2
CE1
WE
DATAIN VALID
Write Cycle No. 1 (WE C o nt ro lle d ) [13, 14]
WC
CY7C185A
6
Note:
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms (contin ued)
tWC
HIGH IMPEDANCE
tAW
tSA
tPWE
tHA
tHD
tSD
CE2
WE
DATA IN
DATA I/O
ADDRESS
tSCE2
tSCE1
CE1
C185A–9
DATAIN VALID
Write Cycle No. 2 (CE Controlled)[13, 14, 15 ]
CY7C185A
7
Typical DC and A C Characteristi cs
–55 25 125
1.2
1.0
0.8
OUTPUT SOURCE CURRENT (mA)
AMBIENT TEMPERATURE (°C)
0.6
0.4
0.2
0.0
NO RMALIZED I , I
CC
VCC =5.0V
VIN =5.0V
ICC
SB
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
–55 25 125
NORMALIZED tAA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.3
1.2
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NO RMALIZED I , I
CC SB
ICC
VCC =5.0V
VCC =5.0V
TA=25°C
VCC =5.0V
TA=25°C
ISB
TA=25°C
0.6
0.8
0
ISB
C185A–10
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED IPO
SUPPLY VOLTAG E (V)
TYPICALPOWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUTLOADING 1.25
1.00
0.75
10 20 30 40
NORMALIZED I CC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs. CYCLE TIME
0.0 5.0 0.0 1000 0.50
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25°C
VCC =0.5V
C185A–11
CY7C185A
8
Truth Ta ble
CE1CE2WE OE Input/Output Mode
H X X X High Z Deselect/
Power-Down
X L X X Hi gh Z Deselect
L H H L Data Out Read
L H L X Data In Write
L H H H High Z Deselect
Address Des ignators
Address
Name Address
Function Pin
Number
A4 X3 2
A5 X4 3
A6 X5 4
A7 X6 5
A8 X7 6
A9 Y1 7
A10 Y4 8
A11 Y3 9
A12 Y0 10
A0 Y2 21
A1 X0 23
A2 X1 24
Ordering Information
Speed
(ns) Orderi ng Code Package
Name Package Type Operating
Range
20 CY7C185A–20DMB D22 28-Lead (300-Mil) CerDIP Military
25 CY7C185A–25DMB D22 28-Lead (300-Mil) CerDIP Military
35 CY7C185A–35DMB D22 28-Lead (300-Mil) CerDIP Military
45 CY7C185A–45DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C185A
9
MIL ITARY SPECI F ICATIONS
Group A Subgroup Testing
Document #: 38–00114–C
DC C h ar acteri stic s
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
IOS 1, 2, 3
ICC 1, 2, 3
ISB1 1, 2, 3
ISB2 1, 2, 3
Switching Characteristics
Parameter Subgroups
READ CYCLE
tRC 7, 8, 9, 10, 11
tAA 7, 8, 9, 10, 11
tOHA 7, 8, 9, 10, 11
tACE1 7, 8, 9, 10, 11
tACE2 7, 8, 9, 10, 11
tDOE 7, 8, 9, 10, 11
WRITE CYCLE
tWC 7, 8, 9, 10, 11
tSCE1 7, 8, 9, 10, 11
tSCE2 7, 8, 9, 10, 11
tAW 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tSA 7, 8, 9, 10, 11
tPWE 7, 8, 9, 10, 11
tSD 7, 8, 9, 10, 11
tHD 7, 8, 9, 10, 11
CY7C185A
© Cypress Semiconductor Corporation, 1999. The i nformation contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The incl usion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag r am
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
