DATASHEET IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR Description Features The IDT5T40166 is an ultra-low phase noise clock generator that supports Gigabit Ethernet clock requirements. It is used in PCs, embedded systems, and high-end consumer applications to substantially increase system performance. The device provides one differential LVPECL clock at 125 MHz and one 25 MHz reference clock. * * * * * Packaged in 20-pin TSSOP Supports Gigabit Ethernet applications One differential LVPECL clock output for Gigabit Ethernet Uses external 25 MHz clock or crystal input Separate VDD pin for 25 MHz output clock to support 2.5 V operation Block Diagram VDD VDD 25 MHz crystal or clock 125M X1 125M Oscillator X2 High Performance PLL Clock Synthesizer 25M Optional tuning crystal capacitors VDD25M GND IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 1 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Pin Assignment GND 1 20 VDD VDD 2 19 GND GND 3 18 VDD XTAL/REFIN 4 17 NC XTALOUT 5 16 GND VDD 6 15 GND GND 7 14 VDD VDD25M 8 13 VDD 25M 9 12 125M GND 10 11 125M 20-pin (173 mil) TSSOP Pin Descriptions Pin Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND VDD GND XTAL/REFIN XTALOUT VDD GND VDD25M 25M GND 125M 125M VDD VDD GND GND Power Power Power Input -- Power Power Power Power Power Output Output Power Power Power Power 17 NC -- 18 VDD Power Connect to +3.3 V supply. 19 GND Power Connect to ground. 20 VDD Power Connect to +3.3 V supply. Connect to ground. Connect to +3.3 V supply. Connect to ground. Crystal connection. Connect to a fundamental mode crystal or clock input. Crystal connection. Connect to a fundamental mode crystal or leave open. Connect to +3.3 V supply. Connect to ground. Connect to +2.5 V supply. Supply for 25M clock. 25 MHz clock output. Connect to ground. 125 MHz clock output. Differential LVPECL. 125 MHz clock output. Complementary differential LVPECL. Connect to +3.3 V supply. Supply for 125M clock. Connect to +3.3 V supply. Connect to ground. Connect to ground. No connect. Internal test pin. Do not connect any signal on this pin. IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 2 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Application Information Decoupling Capacitors External Components As with any high-performance mixed-signal IC, the IDT5T40166 must be isolated from system power supply noise to perform optimally. A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F and 0.1 pF should be connected between VDD and GND as close to the device as possible. Decoupling capacitors of 0.01 F and 0.1 pF must be connected between each VDD and the PCB ground plane. On chip capacitors- Crystal capacitors is integrated to support 8 pF crystal load. Crystal should be connected as close to pins XTALIN and XTALOUT to optimize the initial accuracy. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01 F and 0.1 pF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the IDT5T40166. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. LVPECL Test Condition RLOAD = 50Ohm, CLOAD = 2pF IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 3 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5T40166. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C Parameter Supply Voltage Operating Supply Current Output Voltage Swing Input Capacitance Output Capacitance Symbol Conditions V Min. IDD VSWING CIN COUT Typ. 3.135 45 Pk-pk differential swing 0.5 Max. Units 3.465 V 55 mA 1.0 V Input pin capacitance 3 pF Output pin capacitance 5 pF 1. VDD power ramp must be monotonous. Unless stated otherwise, VDD25 = 2.5 V 5%, Ambient Temperature 0 to +70 C Parameter Supply Voltage Symbol V Conditions For 25M output Voltage1 VOH IOH = 8mA Output Low Voltage1 VOL IOL = 8mA Operating Supply Current IDD Output High IDT(R) GIGABIT ETHERNET CLOCK GENERATOR Min. Typ. 2.375 Max. Units 2.625 V 0.4 V 15 mA 2.0 V 8 4 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD=3.3 V 5%, VDD25M=2.5 V 5%, No Load, Ambient Temperature 0 to +70 C Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency Crystal Input 25 MHz Output Frequency LVPECL Output 125 MHz LVTTL Output 25 MHz Jitter, pk-pk1,2 Jitter, pk-pk Jitter, LTJ 3 Jitter, LTJ 3 Period pk-pk jitter for 125M clock 60 ps Period pk-pk jitter for 25M clock 100 ps Long term jitter for 125M clock 125 ps Long term jitter for 25M clock 100 ps Rise Time tOR 20-80% of VOH and VOL for 25M clock 400 ps Fall Time tOF 20-80% of VOH and VOL for 25M clock 400 ps tOR 20-80% of VOH and VOL for 125M clock 500 ps tOF 20-80% of VOH and VOL for 125M clock 500 ps Rise Time1,2 Fall Time1,2 Duty Cycle1,2 45 PPM Error Power-up Time Frequency Synthesis Error (not due to crystal CL) tSTABLE From power-up VDD = 3.3 V 1 Test setup is RL=50 ohms with 2 pF. 2 Measurement taken from a differential waveform. 3 1000th cycle jitter. IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 5 5.0 55 % 0 ppm 10 ms IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units JA Still air 93 C/W JA 1 m/s air flow 78 C/W JA 3 m/s air flow 65 C/W 20 C/W JC Marking Diagram 20 11 IDT5T401 66PGG #YYWWS 1 10 Notes: 1. "G" after the two-letter package code designates RoHS compliant package. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. # = ZA (Stepping). 4. S = assembly location code. 5. Bottom marking: country of origin if not USA. IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 6 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters Inches* 20 Symbol E1 A A1 A2 b c D E E1 e L a aaa E INDEX AREA 1 2 D Min Max 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 Min Max 0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A A2 A1 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 5T40166PGG see page 6 Tubes 20-pin TSSOP 0 to +70 C Tape and Reel 20-pin TSSOP 0 to +70 C 5T40166PGG8 "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 7 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Revision History Rev. Originator Date A A.T. 08/24/10 Description of Change New device/datasheet. IDT(R) GIGABIT ETHERNET CLOCK GENERATOR 8 IDT5T40166 REV A 082410 IDT5T40166 GIGABIT ETHERNET CLOCK GENERATOR CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA