CyberPro2010 Data Sheet "The Internet Multimedia Company!" Revision 1.A1F CyberPro2010 DATA SHEET CyberPro2010 Data Sheet September, 1997 1997 IGS Technologies, Inc. All rights reserved. Printed in the United States of America IGS Technologies, Inc. 4001 Burton Drive Santa Clara, CA 95054 Phone (408) 982-8588 FAX (408) 982-8591 http://www.igst.com ii IGS Technologies, Inc. CyberPro2010 DATA SHEET Table of Contents 1. FEATURES OVERVIEW.................................................................................................................................................. 1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 WORLD'S FIRST TV DIRECTTM OUTPUT ....................................................................................................................... 1-1 VL BUS INTERFACE .................................................................................................................................................. 1-1 DUOVISIONTM DUAL DISPLAY SUPPORT ...................................................................................................................... 1-1 64-BIT GUI, 128/64/32-BIT EDO INTERFACE ............................................................................................................... 1-1 FLEXIBLE VIDEO INPUTS ............................................................................................................................................ 1-1 SUPPORT FOR VIDEO GAMES ON TV........................................................................................................................... 1-1 RGB/COMPOSITE/S-VIDEO/AMD SCART TV ............................................................................................................. 1-1 MPEG MOVIE PLAYBACK ON TV................................................................................................................................ 1-1 VIDEO EDITING/PHONE/VIDEO CONFERENCING ON TV .................................................................................................. 1-1 2. FEATURES DESCRIPTION............................................................................................................................................. 2-1 2.1 INTEGRATED BRIDGE, GUI & ENCODER ...................................................................................................................... 2-1 2.2 2.3 2.4 2.5 FLICKER-FREE TV DIRECTTM OUTPUT ......................................................................................................................... 2-1 WORLD'S FIRST FLEXIBUSTM INTERFACE..................................................................................................................... 2-1 DUOVISIONTM DUAL DISPLAY SUPPORT ...................................................................................................................... 2-1 VIDEO CAPTURE AND PLAYBACK OUTPUT .................................................................................................................... 2-1 3. VL BUS INFORMATION.................................................................................................................................................. 3-1 3.1 3.2 3.3 3.4 3.5 AMD ELAN4XX CPU INTERFACES ............................................................................................................................. 3-1 POWER-UP BUS TYPE CONFIGURATION ....................................................................................................................... 3-1 VL PIN DESCRIPTION ................................................................................................................................................ 3-2 VL PIN DESCRIPTION TABLES .................................................................................................................................... 3-3 3.4.1 Host Interface (VL) .................................................................................................................................. 3-3 3.4.2 Memory Interface (VL) ............................................................................................................................. 3-4 3.4.3 Miscellaneous (VL).................................................................................................................................. 3-4 3.4.4 Power (VL).............................................................................................................................................. 3-5 3.4.5 Video Port Interface (VL) ......................................................................................................................... 3-5 3.4.6 CRT & TV Interface (VL).......................................................................................................................... 3-5 VL TIMING DIAGRAMS ............................................................................................................................................... 3-6 3.5.1 VL Bus LCLK Timing ............................................................................................................................... 3-6 3.5.2 VL Bus Write and Read Cycle.................................................................................................................. 3-6 3.5.3 VL Bus Input Setup and Hold Timing........................................................................................................ 3-7 3.5.4 VL Bus Output Valid Delay Timing ........................................................................................................... 3-7 3.5.5 VL Bus Output Float Delay Timing ........................................................................................................... 3-8 4. ADDRESSING MODES ................................................................................................................................................... 4-1 4.1 4.2 LEGEND FOR DECODE TABLES ................................................................................................................................... 4-1 VL LINEAR INFORMATION .......................................................................................................................................... 4-1 4.2.1 Address Map........................................................................................................................................... 4-1 4.2.2 VL Linear Address Decodes .................................................................................................................... 4-1 IGS Technologies, Inc. iii CyberPro2010 DATA SHEET Table of Contents 5. FRAME BUFFER MEMORY TIMING ............................................................................................................................... 5-1 5.1 5.2 EDO/FAST PAGE MODE ............................................................................................................................................ 5-1 5.1.1 Read Cycle ............................................................................................................................................. 5-1 5.1.2 Write Cycle ............................................................................................................................................. 5-2 5.1.3 Read-to-Write Cycle ................................................................................................................................ 5-2 5.1.4 Write-to-Read Cycle ................................................................................................................................ 5-3 5.1.5 Timing Parameters .................................................................................................................................. 5-3 MEMORY TIMING SPECIFICATIONS .............................................................................................................................. 5-4 5.2.1 Clock Waveforms .................................................................................................................................... 5-4 5.2.2 Clock Skew ............................................................................................................................................. 5-4 5.2.3 Clock Skew Parameters........................................................................................................................... 5-4 5.2.4 Output Timing ......................................................................................................................................... 5-5 5.2.5 Input Timing ............................................................................................................................................ 5-5 6. ELECTRICAL CHARACTERISTICS ................................................................................................................................ 6-1 6.1 6.2 6.3 ABSOLUTE MAXIMUM RATINGS ................................................................................................................................... 6-1 DC SPECIFICATIONS (DIGITAL)................................................................................................................................... 6-1 DAC CHARACTERISTICS............................................................................................................................................ 6-2 7. PACKAGE DIMENSIONS................................................................................................................................................ 7-1 iv IGS Technologies, Inc. CyberPro2010 DATA SHEET 1. Features Overview 1.1 World's First * * * * * TV 1.7 RGB/Composite/S-video/AMD SCART TV DirectTM Output * Six DAC's on-chip to support TV RGB, Composite, S-video and AMD SCART outputs * Best Text, Video quality for composite underscan TV output using 3-line buffers, Interpolation, 9-bit DAC for 8/16/24-bit colors * Flicker control bypass for best video quality on TV * Higher precision PLL to work with any TV world wide Integrated TV Encoder for Direct NTSC/PAL Only requires a single crystal for NTSC/PAL NTSC(640x480,60Hz), PAL(800x600/640x480,50Hz) Simultaneous S-video, composite & AMD SCART TV Simultaneous VGA & TV 1.2 VL Bus Interface * Direct Interface to 486 Embedded Processors via VL bus, including AMD Elan 400/410 1.3 DuoVisionTM Dual Display Support * DuoVision provides simultaneous display of graphics on VGA while playing MPEG movies on TV 1.4 64-bit GUI, 128/64/32-bit EDO Interface * 64-bit GUI engine, 200mhz RAMDAC, dual clock * Supports EDO DRAM from 1MB up to 4MB 1.5 Flexible Video Inputs * VBI data including Intercast, teletext, CC support * CCIR656/8-bit video input interface 1.8 MPEG Movie Playback on TV * MPEG-2 movie playback on TV using H/W MPEG-2 decoders/players * DirectDraw MPEG-1 playback on TV with S/W * High quality horizontal and vertical interpolation with jagged edge smoothing 1.9 Video Editing/Phone/Video Conferencing on TV * Three scaleable video windows plus PIP * Direct input from TV tuner, analog & digital camera via IGS video port and decoder ASIC * High quality multitap filtering during video capture * Mirror/upside down support for video conferencing 1.6 Support for Video Games on TV * Shadow registers provide complete compatibility for popular DOS, Windows, and other video games on TV RAM/ ROM Audio Speaker/Mic RAM Cable/Tel. Line Remote Control Keyboard Cable/ Modem IR Universal Remote AMD Elan400/410 Embedded CPU i CyberPro2010 VGA TV-Composite TV-S-video TV-SCART Video Camera (RGB, Composite, S-video) Video Decoder MPEG2 Decoder Figure 1-1. System Block Diagram Example IGS Technologies, Inc. 1-1 CyberPro2010 DATA SHEET THIS PAGE INTENTIONALLY LEFT BLANK 1-2 InteGraphics Systems, Inc. CyberPro2010 DATA SHEET 2. Features Description 2.1 Integrated Bridge, GUI & Encoder 2.3 World's First FlexiBusTM Interface The CyberPro2010 is the FIRST and ONLY multimedia accelerator that integrates three major components of an NC/SetTop/Internet Appliance/TV design; namely, CPU Bridge, GUI and video Accelerator, and NTSC/PAL TV Encoder. The flexuous feature incorporates the CPU bridge functions for most of the embedded CPU's which are designed into NC's, SetTops and Internet appliances. As indicated in Table 2-1, the CyberPro2010 has a glueless CPU bus interface to all PCI, VL bus and RISC CPU's, like IBM and Motorola PowerPC, NEC V83X, Hitachi SHX and ESS ES3208. In addition, the CyberPro2010 integrates high speed 200 MHz RAMDAC and clock. The CyberPro2010 has a 64-bit GUI multimedia accelerator which interfaces to true single cycle SDRAM, SGRAM and EDO DRAM frame buffer sizes from 1MB to 4MB. It provides VGA output up to 1600x1200 resolutions for enterprise NC applications. 2.2 Flicker-Free TV DirectTM Output The TVDirectTM feature incorporates an on-chip NTSC/PAL TV encoder which has a proprietary flicker free technology with a 3-line buffer. It provides the best TV quality for the majority of TV's worldwide, where composite input is the norm with its underscan interpolation techniques, high precision PLL and 9-bit DAC. Also, SetTops can be designed with several glueless connectors directly from the CyberPro2010 for simultaneous connections, including VGA, RGB at TV frequency, SCART, S-video and Composite TV outputs. In addition, any other RISC CPU can be interfaced through the non-multiplexed linear VL bus interfaced on-chip. This lowers the total BOM for an Internet appliance to a cost lower than any competitive solution on the market. 2.4 DuoVisionTM Dual Display Support The DuoVisionTM feature, unique to the CyberPro2010, enables simultaneous display on TV of video (DVD, MPEG, karaoke or video conferencing) and VGA graphics. 2.5 Video Capture and Playback Output The CyberPro2010 provides the best quality video capture and playback output on TV of any single chip solution, by using its multi-tap filters, interpolation techniques and multiple hardware windows capability. These features are very important for SetTop designs which require DVD or MPEG output on TV or video conferencing capability where the CyberPro2010 can interface directly to DVD decoders (connected to DVD drives, players or satellite equipment) or video decoders (connected to analog or digital cameras, or a VCR). strongARM RGB PowerPC SH MIPS NTSC CPU Bridge 64-bit GUI & Video Accelerator NTSC/PAL Encoder Java PAL SCART Composite x86 S-video Figure 2-1: Block Diagram IGS Technologies, Inc. 2-1 CyberPro2010 DATA SHEET THIS PAGE INTENTIONALLY LEFT BLANK 2-2 IGS Technologies, Inc. CyberPro2010 DATA SHEET 3. VL Bus Information * Faster memory means higher performance for the CyberPro2010, allowing use of EDO and FPM DRAM of 35-60ns. * For VL bus configuration, the memory bus bandwidth is always 32-bit for 1MB and 2MB. 3.1 AMD Elan4XX CPU Interfaces ADR[31:2] ADS# W/R# LRDY# CS#/AUX[1:0] LDEV# RDYTRN# INTR DAT[31:0] LCLK MIO# RESET# BE[3:0]# 3.2 Power-up Bus Type Configuration All memory addresses from RA8 to RA0 have an internal power-down. RA2 RA1 RA0 1 0 0 VL Standard 1 0 1 VL Linear Address IGS Technologies, Inc. Bus Type 3-1 CyberPro2010 DATA SHEET 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PVDD VDD I2CDA XTIN XTOUT VSS ADR20 ADR26 ADR21 ADR25 ADR22 ADR24 ADR23 WE/CAS7# WE/CAS6# RA8 RA0 VSS RA7 RA1 RA6 RA2 RA5 RA3 RA4 VSS VDD VSS PVDD M0D15 M0D0/JA0 M0D14 M0D1/JA1 M0D13 M0D2/JA2 M0D12 M0D3/JA3 M0D11 VSS M0D4 M0D10 M0D5 M0D9 M0D6 M0D8 M0D7 WE/CAS1# WE/CAS0# PVDD DAT0 DAT1 VSS 3.3 VL Pin Description 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 CyberPro2010 VL Bus Pinout 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VSS VDD DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 BE0# DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 VSS DAT14 DAT15 BE1# MIO# NC LDEV# PVDD LRDY# RDYRTN# ADS# BE2# DAT16 DAT17 DAT18 DAT19 DAT20 VSS DAT21 DAT22 DAT23 W/R# BE3# DAT24 DAT25 DAT26 DAT27 DAT28 DAT29 DAT30 DAT31 RESET# VSS VDD VDD VSS RCVCK VSS ADR7 ADR8 ADR6 ADR9 NC ADR5 ADR10 ADR4 ADR11 ADR3 ADR12 VSS PVDD ADR2 ADR13 NC ADR14 NC ADR15 HSYNC VSYNC/CSYNC NC DDC_CK ODD PIXCLK VSS QVSYNC HREF QHSYNC DDC_DA PA2 PA3 PA4 PA5 PA6 LCLK PA7 PA0 PA1 PORT2 NC PORT3 OE1# PORT0/CSYNC PORT1 INTR VACE# NC NC PVDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 RCMCK VSS VDD VSS I2CCK ADR27 ADR19 ADR28 ADR18 ADR29 ADR17 ADR30 ADR16 ADR31 VSS OE0# CAS/WE0# RAS0# WE/CAS2# WE/CAS3# M0D23 M0D24 MOD22 M0D25 M0D21 M0D26 M0D20 M0D27 VSS PVDD M0D19 M0D28 M0D18 M0D29 M0D17 M0D30 M0D16 M0D31 LUMA CAS/WE1# RAS1# WE/CAS4# WE/CAS5# IREF VDD B G R VDD COMP CHROMA VSS 3-2 IGS Technologies, Inc. CyberPro2010 DATA SHEET 3.4 VL Pin Description Tables 3.4.1 Host Interface (VL) Name Type Pin No. Description 170,168,166,164, 162,149,147,145, 144,146,148,150, 163,165,167,169, 20,18,16,12,10,8, 5,3,2,4,7,9,11,15 37 47 58 The address bus furnishes the physical memory or I/O port addresses to the VL bus target. ADR[31:2] I/O LCLK INTR RESET# I O I DAT[31:0] I/O BE[3:0]# I/O 59,60,61,62,63, 64,65,66,69,70, 71,73,74,75,76, 77,87,88,90,91, 92,93,94,95,97, 98,99,100,101, 102,106,107 67,78,86,96 W/R# I/O 68 ADS# RDYRTN# I/O I/O 79 80 LRDY# I/O 81 LDEV# I/O 83 MIO# I/O 85 IGS Technologies, Inc. The system input clock signal. Used to request an interrupt to the system. System reset. During power-up or a hardware reset, this signal must be at a logic low for at least 1ms. When this signal is low, the CyberPro2010 is in a reset state, all the pins are inactive, and the memory data bus is tri-state. Data bus. This is a bi-directional data path between VL bus devices and the CPU. Byte enable. The byte enables indicate which byte lanes of the 32bit data bus are involved with the current VL bus transfer. Writer or read status. This CPU output indicates the type of access currently executing on the VL bus. Address data strobe. ADS# indicates the start of the VL bus cycle. Ready return. RDYRTN# establishes a handshake so the VL bus target knows when the cycle has ended. Local ready. LRDY# begins the handshake that terminates the current active bus cycle when the target is not bursting. Device select. LDEV# is an active low output signal that responds to the current access, which means it is a valid cycle for the CyberPro2010. Memory or I/O status. This CPU output indicates the type of access currently executing on the VL bus. 3-3 CyberPro2010 DATA SHEET 3.4.2 Memory Interface (VL) Name Type OE1# WE/CAS[7:0]# O O M0D[31:0] I/O RA[8:0] O OE0# O O O CAS/WE[1:0]# RAS[1:0]# Pin No. Description 44 143,142,199,198, 176,175,110,109 194,192,190,188, 184,182,180,178, 177,179,181,183, 187,189,191,193, 127,125,123,121, 119,116,114,112, 111,113,115,117, 120,122,124,126 141,138,136, 134,132,133, 135,137,140, 172 196,173 197,174 Output enable. Used to control different banks of memory. Used to transfer data between DRAM and the CyberPro2010. Output address pins to DRAM. Output enable. Used to control output enable to the DRAM. Each of these signals is used to control one bank of DRAM. ROW ADDRESS STROBE[1:0]# is used to control the DRAM RAS# signal. 3.4.3 Miscellaneous (VL) Name Type NC Pin No. Description No connection. Port I/O programmable pin. RC filter for internal DOT clock. An output loop back pin for a crystal. An input pin for a crystal. 2 I C bus serial data input/output. RC memory clock. An input from the memory clock RC network to control the memory frequency. I2C bus serial clock input/output. DAC reference current. PORT2 PORT3 PORT0/ CSYNC PORT1 RCVCK XTOUT XTIN I2CDA RCMCK I/O I/O I/O 6,17,19,23,42,49,50, 84 41 43 45 I/O I O I I/O I 46 53 152 153 154 157 I2CCK IREF I/O O 161 200 3-4 Port I/O programmable pin. Port I/O programmable pin. Port I/O programmable pin/composite sync for TV. IGS Technologies, Inc. CyberPro2010 DATA SHEET 3.4.4 Power (VL) Name Type VSS I PVDD I VDD I Pin No. Description 1,13,27,52,54,57,72, 89,104,105,118, 129,131,139,151, 158,160,171,185, 208 14,51,82,108,128, 156,186 55,56,103,130,155, 159,201,205 0.0V I/O pad power, 3.3/5.0V. +5.0V. 3.4.5 Video Port Interface (VL) Name ODD PIXCLK QVSYNC QHSYNC HREF PA[7:0] VACE# Type I/O I/O I/O I/O I/O I/O O Pin No. Description 25 26 28 30 29 38,36-32,40,39 48 Odd/even field ID. Video port clock. Vertical sync for video port. Video port horizontal reference or sync. Horizontal Reference. Video port data. Video port enable. 3.4.6 CRT & TV Interface (VL) Name HSYNC VSYNC/ CSYNC DDC_CK DDC_DA LUMA B G R COMP CHROMA Type Pin No. Description O O 21 22 HSYNC to CRT/fast switch (SCART). VSYNC to CRT; composite sync to TV. I/O I/O O O O O O O 24 31 195 202 203 204 206 207 DDC2B clock. DDC2B data. Luminance output/TV blue. Blue analog output connected to the monitor/TV blue. Green analog output connected to the monitor/TV green. Red analog output connected to the monitor/TV red. Composite video output/TV red. Chrominance output//TV green. IGS Technologies, Inc. 3-5 CyberPro2010 DATA SHEET 3.5 VL Timing Diagrams 3.5.1 VL Bus LCLK Timing t1 t2 LCLK t3 t4 t5 3.5.2 VL Bus Write and Read Cycle A B C/D A B C/D A B LCLK ADS# ADR[31:2]#,BE[3:0]#, MIO#,W/R#,D/C# Valid Valid 2 W/R# Write DAT[31:0] Read 1 LDEV# LRDY# RDYRTN# 3-6 IGS Technologies, Inc. CyberPro2010 DATA SHEET 3.5.3 VL Bus Input Setup and Hold Timing LCLK t42 t43 t44 LRDY# t20(r) t21(w) t22 t47 t48 t12 t13 t8 t9 DAT31-0 RDYRTN# ADS# ADR[31:2]#,BE[3:0]#, MIO#,W/R#,D/C# 3.5.4 VL Bus Output Valid Delay Timing LCLK (100pf) t41 (100pf) t45 LRDY# ADR[31:2]#,BE[3:0]#, MIO#,W/R#,D/C# IGS Technologies, Inc. Valid N+1 min max Valid N t10 ADS# max Valid N t18 DAT31-0 min Valid N+1 min max Valid N t6 Valid N Valid N+1 min max Valid N+1 3-7 CyberPro2010 DATA SHEET 3.5.5 VL Bus Output Float Delay Timing LCLK t42 LRDY# t19 DAT31-0 Valid N t11 ADS# Valid N t7 ADR[31:2]#,BE[3:0]#, MIO#,W/R#,D/C# 3-8 Valid N IGS Technologies, Inc. CyberPro2010 DATA SHEET 4. Addressing Modes 4.2.1 Address Map 4.1 Legend for Decode Tables 1. 2. # 0 or one range x Don't Care C RISC processor chip select (active low) $ Binary range ($$$ : from 0 to 7) J Jumper setting at power-up (JJJJ : M0D[3:0] 3. 4. 4.2 VL Linear Information ADR[23:0] 5. ADR[31:24] 1st 1MB Memory 00JJ JJ00 2nd 1MB Memory 00JJ JJ00 Map I/O Write 00JJ JJ00 Map I/O Read BE0 00JJ JJ00 Map I/O Read BE1 00JJ JJ00 Map I/O Read BE2 00JJ JJ00 Map I/O Read BE3 00JJ JJ00 R/W Port [7:0] 00JJ JJ00 R/W TV 2K Byte 00JJ JJ00 COPREG R/W 00JJ JJ00 EPROM Read (R=0) 00JJ JJ00 COP Memory (R=1) 00JJ JJ00 M0D[3:0] has internal pull-down. At power-up, M0D[3:0] to decode the linear address. M0D[3:0] is mapped to linear address A[29:26]. Process addresses A[31:30] and A[25:24] are always zero. Example: At power-up, M0D[3:0] = 0101; then, linear address will be 0001,0100 or 14H. 4.2.2 VL Linear Address Decodes 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st 1MB Memory 0 0 0 0 # # # # # # # # # # # # # # # # # # x x 2nd 1MB Memory 0 0 0 1 # # # # # # # # # # # # # # # # # # x x Map I/O Write 1 0 0 0 0 0 0 0 # # x x # # # # # # # # # # x x Map I/O Read BE0 1 0 0 0 0 0 0 0 # # 0 0 # # # # # # # # # # x x Map I/O Read BE1 1 0 0 0 0 0 0 0 # # 0 1 # # # # # # # # # # x x Map I/O Read BE2 1 0 0 0 0 0 0 0 # # 1 0 # # # # # # # # # # x x Map I/O Read BE3 1 0 0 0 0 0 0 0 # # 1 1 # # # # # # # # # # x x R/W Port [7:0] 1 0 0 0 1 0 1 % 1 1 0 $ $ $ # # # # # # # # 0 0 R/W TV 2K Byte 1 0 0 0 1 0 1 % 1 1 1 0 x # # # # # # # # # 0 0 COPREG R/W 1 0 0 0 1 0 1 % 1 1 1 1 # # # # # # # # # # 0 0 ADR[23:0] IGS Technologies, Inc. 4-1 CyberPro2010 DATA SHEET THIS PAGE INTENTIONALLY LEFT BLANK 4-2 IGS Technologies, Inc. CyberPro2010 DATA SHEET 5. Frame Buffer Memory Timing For memory timing parameters, refer to the manufacturer's data manual. 5.1 EDO/Fast Page Mode All timing is relative to the memory clock (MCLK). 5.1.1 Read Cycle Read data latch position relationship (small vertical rectangle in the diagram under T4): 1. Coprocessor read (3CE.7A[7:6]): If the CAS wave form has been used for the memory read data latch, then 3CE.7A[6:5] controls the edge to latch the memory read data. 2. Other reads (3CE.79[5:4]): If the CAS wave form has been used for the memory read data latch, then 3CE.79[3:2] controls the edge to latch the memory read data. T1 RAS# T4 CAS# T2 T3 T5 MA[8:0] T6 Row T7 T8 Column WE# T9 T15 OE# M0D[31:0] M1D[31:0] IGS Technologies, Inc. Data 5-1 CyberPro2010 DATA SHEET 5.1.2 Write Cycle RAS# CAS# MA[8:0] Row Column T10 T11 WE# OE# T12 M0D[31:0] M1D[31:0] T13 Data 5.1.3 Read-to-Write Cycle RAS# T14 CAS# MA[8:0] Row Column Column T17 WE# T18 OE# M0D[31:0] M1D[31:0] 5-2 Data Word IGS Technologies, Inc. CyberPro2010 DATA SHEET 5.1.4 Write-to-Read Cycle RAS# T16 CAS# MA[8:0] Row Column Column T19 WE# T20 OE# M0D[31:0] M1D[31:0] RD Word 5.1.5 Timing Parameters Symbol T Periods (T = 1xMCLK) Register[Bits] T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 2.5-4T 2.5-4T 1T 0,2,4,6 ns 2.5-3T 2T 0.5-1T 1-1.5T 2-2.5T 0.5T 1.5T 0.5-1T 1-1.5T 1-3T 1T 1-2T 0.5-2.5T 1-3T 0.5T 1T 3CE.70[0]; 3CE.70[1] 3CE.70[0]; 3CE.70[2] Fixed 3CE.79[1:0] 3CE.70[0] Fixed 3CE.F4[0] 3CE.F4[0] 3CE.70[0] Fixed Fixed 3CE.73[5] Fixed 3CE.73[1]; 3CE.7A[0] Fixed 3CE.7A[1] 3CE.F8[1:0] 3CE.F8[3:2] Fixed Fixed IGS Technologies, Inc. 5-3 CyberPro2010 DATA SHEET 5.2 Memory Timing Specifications 5.2.1 Clock Waveforms 2.4V 5.0V Clock 2.0V 2.0V PP (MIN) 1.5V 0.8V 0.4V T_cyc T_high 0.6Vcc 3.3V Clock T_low 0.5Vcc 0.2Vcc PP (MIN) 0.4Vcc 0.3Vcc 0.2Vcc 5.2.2 Clock Skew CLK (@ Device #1 V_ih V_test V_il T_skew T_skew T_skew CLK (@ Device #2 V_ih V_test V_il 5.2.3 Clock Skew Parameters 5-4 Symbol 5.0V Signaling 3.3V Signaling Units V_test T_skew 1.5 2 (max) 0.4Vcc 2 (max) V ns IGS Technologies, Inc. CyberPro2010 DATA SHEET 5.2.4 Output Timing V_th CLK V_test V_tl T_val Output Delay V_test (5V Signal) V_step (3.3V Signal) Tri-state Output T_on T_off 5.2.5 Input Timing V_th CLK V_test T_su V_tl T_su V_th INPUT V_test Inputs Valid V_test V_max V_tl IGS Technologies, Inc. 5-5 CyberPro2010 DATA SHEET THIS PAGE INTENTIONALLY LEFT BLANK 5-6 IGS Technologies, Inc. CyberPro2010 DATA SHEET 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Ambient temperature ......................................... 0C to 55C Storage temperature.......................................... -65C to 150C Voltage on any digital pin ................................... -0.5V to Vcc + 0.5V Power supply voltage......................................... -0.5V to 7.0V Injection current (latch-up testing) ...................... 100mA Note: Stresses above those listed may cause permanent damage to the device. These are absolute stress ratings only. Functional operation at these or any conditions above those indicated in the operational ratings of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 6.2 DC Specifications (Digital) (Vcc = 5V 5%, TA = 0 to 70C, unless otherwise specified. Symbol Parameter IVcc Internal Power Supply Voltage 4.75 5.25 V 5.0V Operation BVcc I/O Bus Interface Power Supply Voltage 4.75 3.0 5.75 3.6 V V 5.0V Bus Interface 3.3V Bus Interface ICC Power Supply Current 350 mA MCLK = 50 MHz VCLK = 80MHZ VIL Input Low Voltage 0 0.8 V VIH Input High Voltage 2.0 Vcc + 0.5 V VOL Output Low Voltage 0.5 V IOL = 16mA VOH Output High Voltage V IOH = -10mA IOH Output High Current 16 mA VOH = 2.4V IOL Output Low Current 16 mA VOL = 0.5V IOZ Input Leakage 10 A 0 < VIN < VCC CIN Input Capacitance 7 pF COUT Output Capacitance 10 pF IGS Technologies, Inc. MIN MAX 2.4 -10 Units Test Conditions 6-1 CyberPro2010 DATA SHEET 6.3 DAC Characteristics (Vcc = 5V 5%, TA = 0 to 70 C) Parameter Resolution (each DAC) Output Current (White Level) Analog Output Rise/Fall Time Analog Output Settling Time Analog Output Skew DAC-to-DAC Matching Glitch Impulse Typical Integral Linearity Error Differential Linearity Error MAX 8 20 8 15 TBD 5 TBD 1 1 Units Bits mA ns ns ns % pV-Sec LSB LSB Test Note VO <1V 1,2 4 5 Notes: 1. IREF = 8.39mA. 2. Load is 37.5 and 10 pF per analog output. 3. TD is measured from the 50% point of VCLK to 50% point of full-scale transition. 4. Rise time is measured from 10% to 90% full-scale; fall time is measured from 90% to 10% full-scale. 5. Settling time is measured from 50% of full-scale transition to output remaining within 2% of final value. 6-2 IGS Technologies, Inc. CyberPro2010 DATA SHEET 7. Package Dimensions 30.60 (1.205) 28.00 (1.102) CyberPro2010 30.60 (1.205) 0.50 (0.020) 25.50 (1.020) 0.20 (0.008) 3.32 (0.131) 0-10 0.25 (0.010) 0.50 (0.020) 1.30 (0.051) 0.15 (0.006) THK Figure 7-1. CyberPro2010 Physical Dimensions IGS Technologies, Inc. 7-1