A-Data ADD6632A4B Revision History Revision 1 ( Dec. 2001 ) 1.Fister release. Revision 2 ( Apr. 2002 ) 1. Changed module current specification. 2. Add Performance range. 3. Changed AC Characteristics. 4. Changed typo size on module PCB in package dimensions. Rev2 Apr, 2002 1 A-Data ADD6632A4B Double Data Rate SDRAM 512K x 32 Bit x 4 Banks General Description Features The ADD6632A4B are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 2,097,152 words x 32 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and /CK. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications *2.5V for VDD power supply *SSTL_2 interface *MRS Cycle with address key programs -CAS Latency (3) -Burst Length (2,4) -Burst Type (sequential & Interleave) *4 banks operation *Differential clock input (CK, /CK) operation *Double data rate interface *Auto & Self refresh *4096 refresh cycle *DQM for masking *Package:100-pins280mil LQFP Ordering Information. Part No. Frequency Interface Package ADD6632A4B-5 ADD6632A4B-5.5 200Mhz 183Mhz SSTL_2 100-pins LQFP ADD6632A4B-6 166Mhz DQ31 DQ30 VSSQ DQ29 84 83 82 81 85 NC VDDQ VSS NC NC NC NC 91 90 89 88 86 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 40 41 42 43 44 45 46 47 48 49 NC NC NC NC NC NC NC A9 VSS A4 A6 A7 50 38 39 NC A5 36 37 A3 VDD A10 35 33 A2 34 31 32 A1 TOP VIEW 100-pin plastic LQFP 280 mil Rev2 Apr, 2002 87 DQS NC VSSQ 93 92 VDD VDDQ 96 95 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A0 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 /WE /CAS /RAS /CS BA0 BA1 94 DQ1 DQ0 97 100 DQ2 VSSQ 99 98 Pin Assignment DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CLK /CLK CKE DSF, MCL A8/AP A-Data ADD6632A4B Pin Description PIN NAME FUNCTION CK, /CK System Clock Differential clock input. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input Address Row / Column address are multiplexed on the same pins. except CK, CKE and L(U)DQM A0~A10 Row address : A0~A10 Column address : A0~A7 BA0~BA1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ31 Data L(U)DQM Data inputs / outputs are multiplexed on the same pins. Data Mask Makes data output Hi-Z, LDQS,UDQS Data Strobe Bi-directional Data Strobe. /RAS Row Address Strobe /CAS Column Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable VDD/VSS Enables write operation and row recharge. Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground VREF NC Power and Ground for the input buffers and the core logic. Power supply for output buffers. Reference Voltage Reference voltage for inputs for SSTL interface. No Connection This pin is recommended to be left No Connection on the device. Block Diagram CK CKE Clock Generator Bank3 Bank2 Mode Register Address Buffer & Refresh Counter Row Decoder Bank1 Address Bank0 /CAS /WE Rev2 Apr, 2002 Column Address Buffer & Refresh Counter Data Control Circuit 3 DQM DQS Column Decoder Data Latch /RAS Control Logic /CS Command Decoder Amplifier DQ0~DQn A-Data ADD6632A4B Absolute Maximum Ratings Parameter Symbol Value Unit VIN, Vout -0.3 ~ VDD+0.3 V VDD, VDDQ -0.3 ~ 4.6 V TSTG -55 ~ +150 Power dissipation PD 1 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Symbol Min Max Unit Note Supply voltage VDD 2.5 2.7 V Supply voltage VDDQ 2.5 2.7 Input logic high voltage VIH VREF+0.18 VDDQ+0.3 V Input logic low voltage VIL -0.3 VREF-0.18 V 2 Output logic high voltage VOH VTT+0.75 - V IOH=-15.2mA Output logic low voltage VOL - VTT-0.75 V IOL=15.2mA Input leakage current IIL -5 5 uA 3 Output leakage current IOL -5 5 uA 4 Reference Voltage VREF 1.25 1.35 V Termination Voltage VTT VREF-0.04 VREF+0.04 1 5 Note : 1. VDDQ must not exceed the level of VDDQ. 2.VIL(min)=-1.5V AC for pulse width 5ns acceptable. 3.Any input 0V VIN 3.6V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT 2.7V. 5. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value. Rev2 Apr, 2002 4 A-Data ADD6632A4B AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input rise / fall time TR / tF 1 Ns Output timing measurement reference level Voutfef 1.4 V CL 50 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Note: 1. 3.15V VDD Note 2 3.6V is applied for ADD6632A4B5. 2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit. Capacitance TA=25, f-=1Mhz Parameter Input capacitance Pin Symbol Min Max Unit CK, /CK Cl1 2.5 3.5 pF A0~A11,BA0,BA1,CKE,/CS,/RAS, Cl2 2.5 3.5 pF CI/O 4.0 5.5 pF /CAS,/WE,DQM Data input / output capacitance DQM Output load circuit V tt =0.5*V DDQ R T=50 Output Z0=50 C LOAD =30pF V REF =0.5*V DDQ Output Load Circuit (SSTL_2) Rev2 Apr, 2002 5 A-Data ADD6632A4B DC Characteristics II Parameter Symbol Test condition MAX Unit Note 165 mA 1 2 mA 60 mA 5 mA 130 mA 240 mA 1 160 mA 2 2 mA Burst length=2, One bank active Operating Current IDD1 tRCtRC(min),IOL=0mA Precharge standby current in power IDD2P CKEVIL(max), tCK=min down mode CKEVIH(min), /CSVIH(min), Precharge standby tCK=min input signals are current in Non power IDD2N changed one time during 2clks. down mode All other pins VDD-0.2V or 0.2V Active standby current in power IDD3P CKEVIL(max), tCK=min down mode CKEVIH(min), /CSVIH(min), Active standby tCK=min input signals are current in Non power IDD3N changed one time during 2clks. down mode All other pins VDD-0.2V or 0.2V tCKtCK(min),IOL=0 mA Burst mode operating IDD4 current All banks active tRRCtRRC(min), All banks Auto refresh current IDD5 active Self refresh current IDD6 CKE0.2V Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev2 Apr, 2002 6 A-Data ADD6632A4B AC Characteristics -5 Parameter -5.5 -6 Symbol Unit Min Max Min Max Min Max 5 8 5.5 8 6 8 ns System clock Cycle time tCK Clock high pulse width tCHW 0.45 0.55 0.45 0.55 0.45 0.55 CLK Clock low pulse width tCLW 0.45 0.55 0.45 0.55 0.45 0.55 CLK Access time form CK to /CK tAC -0.1- 0.1 -0.1 0.1 -0.1 0.1 CLK Data strobe edge to clock edge tDQSCK -0.1- 0.1 -0.1 0.1 -0.1 0.1 ns Clock to first rising edge of DQS delay tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CLK /RAS cycle time tRC 55 - 60.5 - 60 - ns /RAS to /CAS delay tRCD 15 - 16.5 - 18 - ns /RAS active time tRAS 35 120K 35 120K 42 120K ns /RAS precharge time tRP 16 - 16.5 - 18 - ns /RAS to /RAS bank active delay tRRD 10 - 11 - 12 - ns Data-in setup time (to DQS) tDS 0.5 - 0.5 - 0.5 - ns Data-in hold time (to DQS) tDH 1 1 - 1 - ns DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 ns DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 ns Input setup time tIS 0.9 - 0.9 - 1.1 - ns Input hold time tIH 0.9 - 0.9 - 1.1 - ns DQS-in high level width tDSH 0.4 0.6 0.4 0.6 0.4 0.6 CLK DQS-in low level width tDSL 0.4 0.6 0.4 0.6 0.4 0.6 CLK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Write preamble tWPRE 0.25 Data strobe edge to output data edge tDQSQ DQS read preamble tRPRE Rev2 Apr, 2002 7 0.25 0.5 0.9 1.1 0.25 0.5 0.9 1.1 0.9 CLK 0.5 ns 1.1 CLK A-Data ADD6632A4B Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A8/AP Mode Register Set H X L L L L X OP code No Operation H X L H H H X X Bank Active H X L L H H X H X L H L H X RA Read BA V L CA Read with Auto Precharge Write V H H X L H L L X CA Write with Auto Precharge L Precharge All Bank H X L L H L X Precharge select Bank H X L V X Burst Stop H X L H H L X X Auto Refresh H H L L L H X X Entry H L L L L H X H X X X Exit L H Self Refresh H H H H X X X Precharge L H H H Power down H X X X L H H H Exit H L X X L Entry L X H X X Entry H L X X X X X Exit L H X X X X X Clock Suspend X Rev2 Apr, 2002 V H 8 A-Data ADD6632A4B Package Information HD D E H A2 A A1 See Detail F L y Seating Plane L1 Symbol A A1 A2 b c D E e HD HE L L1 y Dimension in inch Dimension in mm Min Nom Max Min Nom Max 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1.35 0.009 0.013 0.015 0.004 0.006 0.008 0.547 0.551 0.10 0.15 1.40 1.45 0.22 0.32 0.38 0.10 0.15 0.20 0.555 13.90 14.00 14.10 0.783 0.787 0.791 19.90 20.00 20.10 0.020 0.026 0.032 0.498 0.65 0.626 0.630 0.634 15.90 16.00 0.862 0.866 0.870 21.90 22.00 22.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.003 0 0.802 16.10 7 0.08 0 7 280mil 100pin LQFP Package Rev2 Apr, 2002 9