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74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
Product specification
Supersedes data of 1997 Mar 04
IC24 Data Handbook
1998 Jun 10
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
2
1998 Jun 10 853–1935 19545
FEATURES
•Optimized for Low V oltage applications: 1.0 to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C
•Ideal for addressable register applications
•Data enable for address and data synchronization applications
•Eight positive-edge triggered D-type flip-flops
•Output capability: standard
•ICC category: MSI
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Qn) of
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
CP to QnCL = 15pF
V33V
13 ns
fmax Maximum clock frequency VCC = 3.3V 77 MHz
CIInput capacitance 3.5 pF
CPD Power dissipation capacitance per flip-flop Notes 1 and 2 20 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic DIL –40°C to +125°C74LV377 N 74LV377 N SOT146-1
20-Pin Plastic SO –40°C to +125°C74LV377 D 74LV377 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C74LV377 DB 74LV377 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +125°C74LV377 PW 74LV377PW DH SOT360-1
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1 E Data enable input (active-LOW)
2, 5, 6, 9, 12,
15, 16, 19 Q0 to Q7flip-flop outputs
3, 4, 7, 8, 13,
14, 17, 18 D0 to D7Data inputs
10 GND Ground (0V)
11 CP Clock input
(LOW-to-HIGH, edge-triggered)
20 VCC Positive supply voltage
FUNCTION TABLE
OPERATING MODES
INPUTS OUTPUTS
OPERATING
MODES
CP E DnQn
Load ‘‘1’’ ↑l h H
Load ‘‘0’’ ↑l l L
Hold (do nothing) ↑
Xh
HX
XNo change
No change
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
↑= LOW–to–HIGH CP transition
X = Don’t care
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 3
PIN CONFIGURATION
SV00667
Q0
Q1
Q2
Q3
GND
Q4
Q5
Q6
Q7
D0
D1
D2
D3
VCC
D4
D5
D6
D7
CP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
E
LOGIC SYMBOL
SV00668
1
2
3
45
67
89
Q0
D0
D1Q1
Q2
D2
D3Q3
Q4
D4
D5Q5
Q6
D6
D7Q719
18
17 16
1514
13 12
11
E
CP
LOGIC SYMBOL (IEEE/IEC)
SV00669
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
1C2
G1
2D
11
1
FUNCTIONAL DIAGRAM
SV00670
3
4
7
8
D0
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
11
1E
CP
OUTPUTS
FF1
to
FF8
2
5
6
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q719
16
15
12
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 4
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
VCC DC supply voltage See Note 1 1.0 3.3 3.6 V
VIInput voltage 0 – VCC V
VOOutput voltage 0 – VCC V
Tamb Operating ambient temperature range in free air See DC and AC
characteristics –40
–40 +85
+125 °C
tr, tfInput rise and fall times VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
–
–
–
–
–
–
–
500
200
100 ns/V
NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +4.6 V
±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
±IODC output source or sink current
– standard outputs –0.5V < VO < VCC + 0.5V 25 mA
±IGND,
±ICC
DC VCC or GND current for types with
–standard outputs 50 mA
Tstg Storage temperature range –65 to +150 °C
Power dissipation per package for temperature range: –40 to +125°C
Ptt
–plastic DIL above +70°C derate linearly with 12mW/K 750
mW
P
tot –plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
mW
–plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 5
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS
SYMBOL PARAMETER TEST CONDITIONS -40°C to +85°C -40°C to +125°CUNIT
MIN TYP1MAX MIN MAX
HIGH l l I t
VCC = 1.2V 0.9 0.9
VIH HIGH level Input
voltage
VCC = 2.0V 1.4 1.4 V
voltage
VCC = 2.7 to 3.6V 2.0 2.0
LOW l l I t
VCC = 1.2V 0.3 0.3
VIL LOW level Input
voltage
VCC = 2.0V 0.6 0.6 V
voltage
VCC = 2.7 to 3.6V 0.8 0.8
VCC = 1.2V ; V I = VIH or VIL; –IO = 100µA 1.2
HIGH level output VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8
voltage; all outputs VCC = 2.7V ; V I = VIH or VIL; –IO = 100µA 2.5 2.7 2.5
VOH VCC = 3.0V ; V I = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 V
HIGH level output
voltage;
STANDARD
outputs VCC = 3.0V ; V I = VIH or VIL; –IO = 6mA 2.40 2.82 2.20
VCC = 1.2V ; V I = VIH or VIL; IO = 100µA 0
LOW level output VCC = 2.0V ; V I = VIH or VIL; IO = 100µA 0 0.2 0.2
voltage; all outputs VCC = 2.7V ; V I = VIH or VIL; IO = 100µA 0 0.2 0.2
VOL VCC = 3.0V ; V I = VIH or VIL; IO = 100µA 0 0.2 0.2 V
LOW level output
voltage;
STANDARD
outputs VCC = 3.0V ; V I = VIH or VIL; IO = 6mA 0.25 0.40 0.50
IIInput leakage
current VCC = 3.6V ; V I = VCC or GND 1.0 1.0 µA
ICC Quiescent supply
current; MSI VCC = 3.6V ; V I = VCC or GND; IO = 0 20.0 160 µA
∆ICC Additional
quiescent supply
current per input VCC = 2.7V to 3.6V ; VI = VCC – 0.6V 500 850 µA
NOTE:
1. All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 6
AC CHARACTERISTICS
GND = 0V ; tr = tf ≤ 2.5ns; C L = 50pF; RL =1KW
CONDITION
LIMITS
SYMBOL PARAMETER WAVEFORM
CONDITION
–40 to +85 °C–40 to +125 °CUNIT
VCC(V) MIN TYP1MAX MIN MAX
1.2 – 80 – – –
t/t
Propagation delay
Figure 1
2.0 – 27 51 – 61
t
PHL/
t
PLH
gy
CP to Qn
Fig
u
re
1
2.7 – 20 38 – 45
3.0 to 3.6 – 15230 – 36
Cl k l idth
2.0 34 9 – 41 –
tWClock pulse width
HIGH or LOW
Figure 2 2.7 25 6 – 30 – ns
HIGH
or
LOW
3.0 to 3.6 20 52– 24 –
1.2 – 25 – – –
t
Set-up time
Figure 2
2.0 22 9 – 26 –
t
su Dn to CP
Fig
u
re
2
2.7 16 6 – 19 –
3.0 to 3.6 13 52– 15 –
1.2 – 10 – – –
t
Set-up time
Figure 2
2.0 22 4 – 26 –
t
su E to CP
Fig
u
re
2
2.7 16 3 – 19 –
3.0 to 3.6 13 22– 15 –
1.2 – –15 – – –
t
Hold time
Figure 2
2.0 5 –5 – 5 –
t
hDn to CP
Fig
u
re
2
2.7 5 –4 – 5 –
3.0 to 3.6 5 –32– 5 –
1.2 – –5 – – –
t
Hold time
Figure 2
2.0 5 –2 – 5 –
t
hE to CP
Fig
u
re
2
2.7 5 –2 – 5 –
3.0 to 3.6 5 –12– 5 –
Mi lk
2.0 14 40 – 12 –
fmax Maximum clock
p
ulse frequency
Figure 1 2.7 19 58 – 16 – MHz
ulse
frequency
3.0 to 3.6 24 702– 20 –
NOTES:
1. Unless otherwise stated, all typical values are at Tamb = 25°C.
2. Typical value measured at VCC = 3.3V.
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 7
AC WAVEFORMS
VM = 1.5V at VCC 2.7V
VM = 0.5V * VCC at VCC 2.7V
VOL and VOH are the typical output voltage drop that occur with the
output load.
SV00707
VM
CP INPUT
VOL
GND
VOH
VCC
Qn OUTPUT VM
tPLH
tPHL
tW
1/fmax
Figure 1. Clock (CP) to output (Qn) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
VM
E INPUT
CP INPUT
Dn INPUT
GND
GND
GND
STABLE
VCC
VCC
VCC
VM
VM
tsu
tsu
tW
th
th
th
tsu
SV00671
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
Figure 2. Data set-up and hold times from the data input (Dn)
and from the enable input (E) to the clock (CP).
TEST CIRCUIT
PULSE
GENERATOR
RT
VID.U.T.
VO
CLRL = 1k
VCC
Test Circuit for switching times
DEFINITIONS
VCC VI
< 2.7V VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
50pF
SV00901
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
2.7–3.6V 2.7V
Figure 3. Load circuitry for switching times
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 8
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 9
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 10
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 11
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Philips Semiconductors Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
1998 Jun 10 12
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04449
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