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AT89C51RD2/ED2
4235A–8051–04/03
Power Management Two power reduction modes are implemented in the AT89C51RD2/ED2: the Idle mode
and the Power-down mode. These modes are detailed in the following sections. In addi-
tion to these power reduction modes, the cl ocks of the core and p eripherals can be
dynamically divided by 2 using the X2 Mode described in Section “Clock”.
Idle Mode An ins tructi on that sets P CON.0 indica tes that it is the las t inst ructio n to b e execute d
before going into Id le mode. In Idle mode, the inte rnal clock s ignal is gate d off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-
served in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logica l states they had at the time Idl e was activ ated. ALE and PSEN hold at log ic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled inter rupt will
cause PCON.0 to be cleared by ha rdware, ter minat ing the Idl e mode. The in terru pt will
be serviced, and following RETI the next instruction to be executed will be the one fol-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during idle. For example, an instruction that activates idle can
also set one or both fla g bi ts. Wh en i dle i s t erm inat ed b y a n int err upt, the int erru pt s er-
vice routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode To save maximum power, a power-down mode can be invoked by software (refer to
PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed befor e VCC is res tored to its normal op erating le vel and mu st be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboa rd Interrupts are useful to exit from
power-d own. F or t hat, interr upt mu st be enabled and c onf igu re d as level or ed ge s ensi-
tive interrupt input. When Keyboard Interrupt occurs after a power-down mode, 1024
clocks are necessary to exit to power-down mode and enter in operating mode.
Holding th e pi n low r es tarts the o scil la tor bu t br in gin g the pi n hi gh completes the e xit as
detailed in Figure 33. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power-down exit will be completed when the first
input i s released. In thi s case the higher pri ority interrup t service routin e is executed.
Once th e interr upt is s ervic ed, the next i nstruc tion to be ex ecuted after RETI wil l be th e
one following the instruction that put AT89C51RD2/ED2 into power-down mode.