R01DS0192EJ0001 Rev. 0.01 Page 1 of 16
Oct 15, 2012
RL78/L1C
RENESAS MCU
Integrated LC D controller/driver, 12-bit resolution A/D Con verter, USB 2.0 controlle r (function), True Low Power Platform (as low as 112.5
A/MHz, and 0.61 A for RTC + LVD), 1.6 V to 3.6 V operation, 256 Kbyte Flash, 33 DMIPS at 24 MHz, for All LCD Based Applications
Preliminary Datasheet
Specifications in this document are tentative and subject to change.
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.6 V to 3.6 V operation from a single supply
• Stop (RAM retained): 0.25 A <T.B.D.>, (LVD enabled):
0.33 A <T.B.D.>
• Halt (RTC + LVD): 0.61 A <T.B.D.>
• Supports snooze
• Operating: 112.5 A/MHz <T.B.D.>
16-bit RL78 CPU Core
• Delivers 33 DMIPS at maximum operating frequency of 24 MHz
• Instruction Execution: 86% of instructions can be executed in 1 to 2
clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 16 to 32-bit result in 1 clock cycle
• MAC: 16 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug functi on
Code Flash Memory
• Density: 64 to 256 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection from block
erase/writing
• Self-programming with secure boot swap function and flash shield
window function
Data Flash Memory
• Data Flash with background operation
• Data flash size: 8 KB
• Erase Cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 3.6 V
RAM
• 8 KB to 16 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 24 MHz with +/- 1% accuracy over voltage (1.8 V to 3.6 V) and
temperature (-20°C to +85°C)
• Pre-configured settings: 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz,
4 MHz, 1 MHz (TYP.)
• 48 MHz for USB, 48 MHz for timer KB2
Reset and Supply Management
• Power-on reset (POR) monitor/ge nerator
• Low voltage detection (LVD) with 12 setting options (Interrupt and/or
reset function)
LCD Controller/Driver
• Up to 56 seg 4 com or 52 seg 8 com
• Supports capacitor split method, internal voltage boost method and
resistance division met hod
• Supports waveform types A and B
• Supports LCD contrast adjustment (18 steps)
• Supports LCD blinking
USB
• Complying with USB 2.0
• Corresponding to full-speed transfer (12Mbps) and low-speed
(1.5Mbps)
• Complying with Battery Charging Specification Revision 1.2
• Supports USB function controller
Data Transfer Controller (DTC)
• 33 sources & 24 different settings
• T ransfer data: 8 bits/16 bits
• Normal mode and repeat mode
Event Link Controller (ELC)
• Reduce interrupt intervention
• Link 31 events to specified peripheral function
Multiple Communication Interfaces
•Up to 4 I2C master
•Up to 1 I2C multi-master
•Up to 4 CSI (7-, 8-bit)
•Up to 4 UART (7-, 8-, 9-bit)
•Up to 1 LIN
Extended-Function Timers
• Multi-function 16-bit timer TAU: Up to 8 channels (remote control
output available)
• Multi-function 16-bit timer KB2: 3 channels
• High accuracy real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• 12-bit interval timer: 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 13 channels, 8/12-bit resolution, 3.375 s minimum
conversion time
• Supports 1.6 V
• D/A converter: 2 channels, 8-bit resolution
•2 window comparators, with ELC connection
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/ frequency detection
• ADC self-test
• I/O port read back functi on (echo)
General Purpose I/O
• High-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: -40 °C to +85°C
Package Type and Pin Count
• 80-pin plastic LQFP (fine pitch)(12 12)
• 100-pin plastic LQFP (fine pitch)(14 14)
R01DS0192EJ0001
Rev. 0.01
Oct 15, 2012
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 2 of 16
Oct 15, 2012
ROM, RAM capacities
Note This is about 15 KB when the self-programming function and data flash function are used.
Products with the USB
Flash ROM Data flash RAM RL78/L1C
80 pins 100 pins
256 KB 8 KB 16 KB Note R5F110MJ R5F110PJ
192 KB 8 KB 16 KB Note R5F110MH R5F110PH
128 KB 8 KB 12 KB R5F110MG R5F110PG
96 KB 8 KB 10 KB R5F110MF R5F110PF
64 KB 8 KB 8 KB R5F110ME R5F110PE
Products without the USB
Flash ROM Data flash RAM RL78/L1C
80 pins 100 pins
256 KB 8 KB 16 KB Note R5F111MJ R5F111PJ
192 KB 8 KB 16 KB Note R5F111MH R5F111PH
128 KB 8 KB 12 KB R5F111MG R5F111PG
96 KB 8 KB 10 KB R5F111MF R5F111PF
64 KB 8 KB 8 KB R5F111ME R5F111PE
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 3 of 16
Oct 15, 2012
1.2 Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/L1C
Products with the USB
Pin count Package Part Number
80 pins 80-pin plastic LQFP
(fine pitch) (12 12) R5F110MEAFB, R5F110MFAFB, R5F110MGAFB, R5F110MHAFB, R5F110MJAFB
100 pins 100-pin plastic LQFP
(fine pitch) (14 14) R5F110PEAFB, R5F110PFAFB, R5F110PGAFB, R5F110PHAFB, R5F110PJAFB
Products without the USB
Pin count Package Part Number
80 pins 80-pin plastic LQFP
(fine pitch) (12 12) R5F111MEAFB, R5F111MFAFB, R5F111MGAFB, R5F111MHAFB, R5F111MJAFB
100 pins 100-pin plastic LQFP
(fine pitch) (14 14) R5F111PEAFB, R5F111PFAFB, R5F111PGAFB, R5F111PHAFB, R5F111PJAFB
Part No. R 5 F 1 1 0 P E A x x x F B
Package type:
FB: LQFP, 0.50 mm pitch
ROM number (Omitted with blank products)
Classification:
A: Consumer applications, operating ambient temperature: -40 °C to +85°C
ROM capacity:
E: 64 KB
F: 96 KB
G: 128 KB
H: 192 KB
J: 256 KB
Pin count:
M: 80-pin
P: 100-pin
RL78/L1C
110: Products with the USB
111: Products without the USB
Memory type:
F: Flash memory
Renesas MCU
Renesas semiconductor product
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 4 of 16
Oct 15, 2012
1.3 Pin Configuration (Top View)
1.3.1 80-pin products (with the USB)
• 80-pin plastic LQFP (fine pitch) (12 12)
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Connect the UREGC pin to VSS pin via a capacitor (0.33 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
P11/RxD2/SI20/SDA20/SEG41/VCOUT0
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40
P27/TI05/TO05/(INTP5)/PCLBUZ1/SEG39
P26/SO00/TxD0/TOOLTxD/SEG38
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37
P24/SCK00/SCL00/SEG36
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
UREGC
UVBUS
UDM
UDP
AVDD
AVSS
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
P126/CAPL/(TI04)/(TO04)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
12345678910
11 12 13 14 15 16 17 18 19 20
60 5958 57 56 55 54 5352 51 50 49 48 4746 45 44 43 42 41
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/IVREF0
P43/(INTP7)/IVCMP0
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P12/TxD2/SO20/SEG42
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4/INTP6
P51/SEG5
P52/SEG6
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 5 of 16
Oct 15, 2012
1.3.2 80-pin products (without the USB)
• 80-pin plastic LQFP (fine pitch) (12 12)
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
P11/RxD2/SI20/SDA20/SEG41/VCOUT0
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40
P27/TI05/TO05/(INTP5)/PCLBUZ1/SEG39
P26/SO00/TxD0/TOOLTxD/SEG38
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37
P24/SCK00/SCL00/SEG36
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
P82
P83
P156/ANI6
P155/ANI5
AVDD
AVSS
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
P126/CAPL/(TI04)/(TO04)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
12345678910
11 12 13 14 15 16 17 18 19 20
60 5958 57 56 55 54 5352 51 50 49 48 4746 45 44 43 42 41
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/IVREF0
P43/(INTP7)/IVCMP0
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P12/TxD2/SO20/SEG42
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4/INTP6
P51/SEG5
P52/SEG6
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 6 of 16
Oct 15, 2012
1.3.3 100-pin products (with the USB)
• 1 00 -p i n pl a sti c LQ FP (fi n e pi tch) (14 14)
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Connect the UREGC pin to VSS pin via a capacitor (0.33 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
1 2 3 4 5 6 7 8 9 1011121314151617181920
P153/ANI3
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/(SCK10)/(SCL10)/IVREF0
P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP0
P42/TI05/TO05/(SO10)/(TxD1)/IVCMP1
P41/(TI07)/(TO07)/IVREF1
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
21 22 23 24 25
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P126/CAPL/(TI04)/(TO04)
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P36/SEG26
P37/SEG27
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
45
46
47
48
49
50
75 74 73 72 71 70 69 6867 66 65 64 63 6261 60 59 58 57
P12/TxD2/SO20/SEG42/VCOUT1
P13/SEG43
P14/SEG44
P15/SEG45
P16/SEG46
P17/SEG47
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
VDD1
VSS1
UREGC
UVBUS
UDM
UDP
P156/ANI6
P155/ANI5
AVDD
AVSS
P154/ANI4
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P24/SCK00/SCL00/SEG36 81
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37 80
P26/SO00/TxD0/TOOLTxD/SEG38 79
P27/(TI05)/(TO05)/(INTP5)/PCLBUZ1/SEG39 78
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40 77
P11/RxD2/SI20/SDA20/SEG41/VCOUT0 76 56
COM5/SEG1
55
COM6/SEG2
54
COM7/SEG3
53
P50/SEG4/INTP6
52
P51/SEG5
51
P52/SEG6
P53/SEG7
P54/SEG8
P55/SEG9
P56/SEG10
P57/SEG11
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 7 of 16
Oct 15, 2012
1.3.4 100-pin products (without the USB)
• 1 00 -p i n pl a sti c LQ FP (fi n e pi tch) (14 14)
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
1 2 3 4 5 6 7 8 9 1011121314151617181920
P153/ANI3
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/(SCK10)/(SCL10)/IVREF0
P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP0
P42/TI05/TO05/(SO10)/(TxD1)/IVCMP1
P41/(TI07)/(TO07)/IVREF1
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
21 22 23 24 25
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P126/CAPL/(TI04)/(TO04)
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P36/SEG26
P37/SEG27
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
45
46
47
48
49
50
75 74 73 72 71 70 69 6867 66 65 64 63 6261 60 59 58 57
P12/TxD2/SO20/SEG42/VCOUT1
P13/SEG43
P14/SEG44
P15/SEG45
P16/SEG46
P17/SEG47
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
VDD1
VSS1
P80
P81
P82
P83
P156/ANI6
P155/ANI5
AVDD
AVSS
P154/ANI4
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P24/SCK00/SCL00/SEG36 81
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37 80
P26/SO00/TxD0/TOOLTxD/SEG38 79
P27/(TI05)/(TO05)/(INTP5)/PCLBUZ1/SEG39 78
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40 77
P11/RxD2/SI20/SDA20/SEG41/VCOUT0 76 56
COM5/SEG1
55
COM6/SEG2
54
COM7/SEG3
53
P50/SEG4/INTP6
52
P51/SEG5
51
P52/SEG6
P53/SEG7
P54/SEG8
P55/SEG9
P56/SEG10
P57/SEG11
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 8 of 16
Oct 15, 2012
1.4 Pin Identification
ANI0 to ANI6, : Analog Input SCL00, SCL10, SCL20, SCL30 : Serial Clock Output
ANI16 to ANI21 SDAA0, SDA00, SDA10, : Serial Data Input/Output
ANO0, ANO1 : Analog Output SDA20, SDA30
AVDD : Analog Power Supply SEG0 to SEG55 : LCD Segment Output
AVREFM : Analog Reference Voltage SI00, SI10, SI20, SI30 : Serial Data Input
Minus SO00, SO10, SO20, SO30 : Serial Data Output
AVREFP : Analog Reference Voltage TI00 to TI07 : Timer Input
Plus TO00 to TO07 : Timer Output
AVSS : Analog Gro und TKBO00, TKBO01, TKBO10,
CAPH, CAPL : Capacitor for LCD TKBO11, TKBO20, TKBO21
COM0 to COM7, : LCD Common Output TOOL0 : Data Input/Output for Tool
COMEXP TOOLRxD, TOOLTxD : Data Input/Output for
EXCLK : External Clock Input External Device
(Main System Clock) UDM, UDP : USB Input/Output
EXCLKS : External Clock Input UREGC : USB Regulator Capacitance
(Subsystem Clock) UVBUS : USB Input/USB Power Supply
INTP0 to INTP7 : External Interrupt Input TxD0 to TxD3 : Transmit Data
IVCMP0, IVCMP1 : Comparator Input VCOUT0, VCOUT1 : Comparator Output
IVREF0, IVREF1 : Comparator Reference Input VDD0, VDD1 : Power Supply
KR0 to KR7 : Key Return VL1 to VL4 : LCD Power Supply
P00 to P07 : Port 0 VSS0, VSS1 : Ground
P10 to P17 : Port 1 X1, X2 : Crystal Oscillator
P20 to P27 : Port 2 (Main System Clock)
P30 to P37 : Port 3 XT1, XT2 : Crystal Oscillator
P40 to P46 : Port 4 (Subsystem Clock)
P50 to P57 : Port 5
P60 to P62 : Port 6
P70 to P77 : Port 7
P80 to P83 : Port 8
P121 to P127 : Port 12
P130, P137 : Port 13
P140 to P143 : Port 14
P150 to P156 : Port 15
PCLBUZ0, PCLBUZ1 : Programmable Clock Output/
Buzzer Output
REGC : Regulator Capacitance
REMOOUT : Remote Control Output
RESET :Reset
RTC1HZ : Real-time Clock Correction
Clock (1 Hz) Output
RxD0 to RxD3 : Receive Data
SCK00, SCK10,
SCK20, SCK30 : Serial Clock Input/Output
SCLA0 : Serial Clock Input/Output
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 9 of 16
Oct 15, 2012
1.5 Block Diagram
1.5.1 80-pin products (with the USB)
RTC1HZ
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
BUZZER OUTPUT PCLBUZ0,
PCLBUZ1
CLOCK OUTPUT
CONTROL
2
DATA TRANS FER
CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
CRC
SDAA0
SCLA0
SERIAL
INTERFACE IICA0
RAM
USB VOLTAGE
REGULATOR
UREGC
MULTIPLIE R &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE CODE FLASH MEMORY
DATA FLASH MEMORY
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2 UART2
RxD3
TxD3 UART3
SCK20
SO20
SI20 CSI20
SCK30
SO30
SI30 CSI30
SCL20
SDA20 IIC20
SCL30
SDA30 IIC30
USB
UVBUS
UDP
UDM
PORT 2 P20 to P27
8
PORT 6 P60, P61
2
PORT 7 P70 to P778
PORT 12 P121 to P124
4
P125 to P12 7
3
P137
PORT 13 P130
PORT 14 P140 to P1434
KEY RETURN KR0 to KR7
8
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0
ON-CHIP DEBUG
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
PLL
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL INTP0 to INTP7
8
ANO0
D/A CONVERTER ANO1
TIMER KB2_0
TKBO00
TKBO01
TIMER KB2_1
TKBO10
TKBO11
TIMER KB2_2
TKBO20
TKBO21
RESET
X1
X2/EXCLK
XT1
XT2/EXCLKS
PORT 0 P00 to P07
8
TIMER ARRAY
UNIT0 (8 ch)
ch 0
ch 1
ch 2
ch 3
ch 4
ch 5
ch 6
ch 7
REMOTE CARRIER
TI00/TO00
TI01/TO01
TI02/TO02
TI03/TO03
TI04/TO04
TI05/TO05
TI06/TO06
TI07/TO07
REMOOUT
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
SEG0 to SEG6, SEG12 to SEG25,
SEG27 to SEG42, SEG48 to SEG55 44
9COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
A/D CONVERTER
ANI2
ANI16 to ANI21
6
AVREFP/ANI0
AVREFM/ANI1
TOOLRxD,
TOOLTxD
AVSS,
VSS0
AVDD,
VDD0
PORT 1 P10 to P12
3
PORT 3 P30 to P35
6
PORT 4 P40, P43 to P465
PORT 5 P50 to P52
3
PORT 15 P150 to P1523
COMPARATOR
(1 ch)
COMPARATOR0 IVCMP0
IVREF0
VCOUT0
SERIAL ARRAY
UNIT0 (4 ch)
UART0
LINSEL
UART1
CSI00
CSI10
IIC00
IIC10
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK10
SI10
SO10
SCL00
SDA00
SCL10
SDA10
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 10 of 16
Oct 15, 2012
1.5.2 80-pin products (without the USB)
RTC1HZ
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
BUZZER OUTPUT PCLBUZ0,
PCLBUZ1
CLOCK OUTPUT
CONTROL
2
DATA TRANS FER
CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
CRC
SDAA0
SCLA0
SERIAL
INTERFACE IICA0
RAM
MULTIPLIE R &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE CODE FLASH MEMORY
DATA FLASH MEMORY
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2 UART2
RxD3
TxD3 UART3
SCK20
SO20
SI20 CSI20
SCK30
SO30
SI30 CSI30
SCL20
SDA20 IIC20
SCL30
SDA30 IIC30
A/D CONVERTER
3 ANI2, ANI5, ANI6
ANI16 to ANI21
6
AVREFP/ANI0
AVREFM/ANI1
PORT 2 P20 to P27
8
PORT 6 P60, P61
2
PORT 7 P70 to P778
TIMER KB2_0
TKBO00
TKBO01
TIMER KB2_1
TKBO10
TKBO11
TIMER KB2_2
TKBO20
TKBO21
SERIAL ARRAY
UNIT0 (4 ch)
UART0
LINSEL
UART1
CSI00
CSI10
IIC00
IIC10
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK10
SI10
SO10
SCL00
SDA00
SCL10
SDA10
PORT 0 P00 to P07
8
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
SEG0 to SEG6, SEG12 to SEG25,
SEG27 to SEG42, SEG48 to SEG55 44
9COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
TOOLRxD,
TOOLTxD
AVSS,
VSS0
AVDD,
VDD0
PORT 1 P10 to P12
3
PORT 3 P30 to P35
6
PORT 4 P40, P43 to P465
PORT 5 P50 to P52
3
PORT 12 P121 to P124
4
P125 to P12 7
3
P137
PORT 13 P130
PORT 14 P140 to P1434
KEY RETURN KR0 to KR7
8
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0
ON-CHIP DEBUG
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL INTP0 to INTP7
8
ANO0
D/A CONVERTER ANO1
PORT 15 P150 to P152,
P155, P156
5
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RESET
X1
X2/EXCLK
XT1
XT2/EXCLKS
COMPARATOR
(1 ch)
COMPARATOR0 IVCMP0
IVREF0
VCOUT0
PORT 8 P82, P832
TIMER ARRAY
UNIT0 (8 ch)
ch 0
ch 1
ch 2
ch 3
ch 4
ch 5
ch 6
ch 7
REMOTE CARRIER
TI00/TO00
TI01/TO01
TI02/TO02
TI03/TO03
TI04/TO04
TI05/TO05
TI06/TO06
TI07/TO07
REMOOUT
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 11 of 16
Oct 15, 2012
1.5.3 100-pin products (with the USB)
RTC1HZ
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
SEG0 to SEG55 56
9COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
BUZZER OUTPUT PCLBUZ0,
PCLBUZ1
CLOCK OUTPUT
CONTROL
2
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
CRC
TOOLRxD,
TOOLTxD
AVSS,
VSS0,
VSS1
AVDD,
VDD0,
VDD1
SDAA0
SCLA0
SERIAL
INTERFACE IICA0
RAM
USB VOLTAGE
REGULATOR
UREGC
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE CODE FLASH MEMORY
DATA FLASH MEMORY
A/D CONVERTER
5 ANI2 to ANI6
ANI16 to ANI21
6
AVREFP/ANI0
AVREFM/ANI1
USB
UVBUS
UDP
UDM
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30 to P37
8
PORT 4 P40 to P467
PORT 5 P50 to P57
8
PORT 6 P60, P61
2
PORT 7 P70 to P778
PORT 12 P121 to P124
4
P125 to P127
3
P137
PORT 13 P130
PORT 14 P140 to P1434
PORT 15 P150 to P1567
KEY RETURN KR0 to KR7
8
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0
ON-CHIP DEBUG
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
PLL
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL INTP0 to INTP7
8
ANO0
D/A CONVERTER ANO1
TIMER KB2_0
TKBO00
TKBO01
TIMER KB2_1
TKBO10
TKBO11
TIMER KB2_2
TKBO20
TKBO21
SERIAL ARRAY
UNIT0 (4 ch)
UART0
LINSEL
UART1
CSI00
CSI10
IIC00
IIC10
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK10
SI10
SO10
SCL00
SDA00
SCL10
SDA10
RESET
X1
X2/EXCLK
XT1
XT2/EXCLKS
PORT 0 P00 to P07
8
TIMER ARRAY
UNIT0 (8 ch)
ch 0
ch 1
ch 2
ch 3
ch 4
ch 5
ch 6
ch 7
REMOTE CARRIER
TI00/TO00
TI01/TO01
TI02/TO02
TI03/TO03
TI04/TO04
TI05/TO05
TI06/TO06
TI07/TO07
REMOOUT
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2 UART2
RxD3
TxD3 UART3
SCK20
SO20
SI20 CSI20
SCK30
SO30
SI30 CSI30
SCL20
SDA20 IIC20
SCL30
SDA30 IIC30
COMPARATOR
(2 ch)
COMPARATOR0 IVCMP0
IVREF0
VCOUT0
COMPARATOR1 IVCMP1
IVREF1
VCOUT1
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 12 of 16
Oct 15, 2012
1.5.4 100-pin products (without the USB)
RTC1HZ
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
SEG0 to SEG55 56
9COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
BUZZER OUTPUT PCLBUZ0,
PCLBUZ1
CLOCK OUTPUT
CONTROL
2
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
CRC
TOOLRxD,
TOOLTxD
AVSS,
VSS0,
VSS1
AVDD,
VDD0,
VDD1
SDAA0
SCLA0
SERIAL
INTERFACE IICA0
RAM
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE CODE FLASH MEMORY
DATA FLASH MEMORY
A/D CONVERTER
5 ANI2 to ANI6
ANI16 to ANI21
6
AVREFP/ANI0
AVREFM/ANI1
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30 to P37
8
PORT 4 P40 to P467
PORT 5 P50 to P57
8
PORT 6 P60, P61
2
TIMER KB2_0
TKBO00
TKBO01
TIMER KB2_1
TKBO10
TKBO11
TIMER KB2_2
TKBO20
TKBO21
SERIAL ARRAY
UNIT0 (4 ch)
UART0
LINSEL
UART1
CSI00
CSI10
IIC00
IIC10
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK10
SI10
SO10
SCL00
SDA00
SCL10
SDA10
PORT 0 P00 to P07
8
PORT 7 P70 to P778
PORT 12 P121 to P124
4
P125 to P127
3
P137
PORT 13 P130
PORT 14 P140 to P1434
PORT 15 P150 to P1567
KEY RETURN KR0 to KR7
8
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0
ON-CHIP DEBUG
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL INTP0 to INTP7
8
ANO0
D/A CONVERTER ANO1
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RESET
X1
X2/EXCLK
XT1
XT2/EXCLKS
COMPARATOR
(2 ch)
COMPARATOR0 IVCMP0
IVREF0
VCOUT0
COMPARATOR1 IVCMP1
IVREF1
VCOUT1
TIMER ARRAY
UNIT0 (8 ch)
ch 0
ch 1
ch 2
ch 3
ch 4
ch 5
ch 6
ch 7
REMOTE CARRIER
TI00/TO00
TI01/TO01
TI02/TO02
TI03/TO03
TI04/TO04
TI05/TO05
TI06/TO06
TI07/TO07
REMOOUT
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2 UART2
RxD3
TxD3 UART3
SCK20
SO20
SI20 CSI20
SCK30
SO30
SI30 CSI30
SCL20
SDA20 IIC20
SCL30
SDA30 IIC30
PORT 8 P80 to P83
4
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 13 of 16
Oct 15, 2012
1.6 Outline of Functions
Note 1. In the case of the 16 KB, this is about 15 KB when the self-programming function and data flash function are used.
Note 2. In the PLL clock 48 MHz operation, the system clock is 2/4/8 dividing ratio.
Note 3. The number of outputs varies, depending on the setting of channels in use and the number of the master.
[80-pin, 100-pi n prod uc ts (with the USB)] (1/2)
Item 80-pin 100-pin
R5F110Mx (x = E to H, J) R5F110Px (x = E to H, J)
Code flash memory (KB) 64 to 256 64 to 256
Data flash memory (KB) 8 8
RAM (KB) 8 to 16 Note 1 8 to 16 Note 1
Memory space 1 MB
Main system clock High-speed system clock X1 (crystal/cer amic) oscillation, external main system clock input (EXC LK)
1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock HS (high-speed main) operation mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V),
HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V,
LS (low-speed main) operation mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V),
LV (low-vol tage main) operation mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V)
PLL clock 6, 12, 24 MHz Note 2: VDD = 2.4 to 3.6 V
Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 3.6 V
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 3.6 V
General-purpose register 8 bits 32 regist ers (8 bits 8 registers 4 banks)
Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator clock: fHOCO = fIH = 24 MHz operation)
0.04167 s (PLL clock: fPLL = 48 MHz/fIH = 24 MHz Note 2 operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits 16 bits, 32 bits 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bit s)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 59 77
CMOS I/O 51 69
CMOS input 55
CMOS output 11
N-ch open-drain I/O
(6 V tolerance) 22
Timer 16-bit timer TAU 8 channels (with 1 channel remote control output function)(Timer outputs: 8, PWM outputs: 7 Note 3)
16-bit timer KB2 3 channels (PWM outputs: 6)
Watchdog timer 1 channel
12-bit interval timer 1 channel
High accuracy real-time
clock 1 channel
RTC out put 1 1 Hz (subsystem clock: fSUB = 32.768 kHz)
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 14 of 16
Oct 15, 2012
Note 1. The number in parentheses indicates the number of signal outputs when 8 coms are used.
Note 2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
(2/2)
Item 80-pin 100-pin
R5F110Mx (x = E to H, J) R5F110Px (x = E to H, J)
Clock output/buzzer output 2 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/12-bit resolution A/D converter 9 channels 13 channels
D/A converter 2 channels 2 channels
Comparator 1 channel 2 channels
Serial interface • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
I2C bus 1 channel 1 channel
USB Function 1 channel
LCD controller/driver Internal voltag e boosting meth od, capaci tor split metho d, an d e xternal resist ance division method
are switchable.
Segment signal output 44 (40) Note 1 56 (52) Note 1
Common signal output 4 (8) Note 1
Data transfer controller (DTC) 32 sources 33 sources
Event link controller (ELC) Event input: 30, Event trigger output: 22 Event input: 31, Event trigger output: 22
Vectored interrupt
sources Internal 36 37
External 9 9
Key interrupt 8 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 0.03 V
• Power-down-reset: 1.50 0.03 V
Voltage detector • Rising edge: 1.67 V to 3.13 V (12 stages)
• Falling edge: 1.63 V to 3.06 V (12 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 3.6 V
Operating ambient temperature TA = -40 to +85C
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 15 of 16
Oct 15, 2012
Note 1. In the case of the 16 KB, this is about 15 KB when the self-programming function and data flash function are used.
Note 2. The number of outputs varies, depending on the setting of channels in use and the number of the master.
[80-pin, 100-pin products (without the USB)] (1/2)
Item 80-pin 100-pin
R5F111Mx (x = E to H, J) R5F111Px (x = E to H, J)
Code flash memory (KB) 64 to 256 64 to 256
Data flash memory (KB) 8 8
RAM (KB) 8 to 16 Note 1 8 to 16 Note 1
Memory space 1 MB
Main system clock High-speed system clock X1 (crystal/cer amic) oscillation, external main system clock input (EXC LK)
1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock HS (high-speed main) operation mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V),
HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V,
LS (low-speed main) operation mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V),
LV (low-vol tage main) operation mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V)
Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 3.6 V
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 3.6 V
General-purpose register 8 bits 32 regist ers (8 bits 8 registers 4 banks)
Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator clock: fHOCO = fIH = 24 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits 16 bits, 32 bits 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bit s)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 63 81
CMOS I/O 55 73
CMOS input 55
CMOS output 11
N-ch open-drain I/O
(6 V tolerance) 22
Timer 16-bit timer TAU 8 channels (with 1 channel remote control output function)(Timer outputs: 8, PWM outputs: 7 Note 2)
16-bit timer KB2 3 channels (PWM outputs: 6)
Watchdog timer 1 channel
12-bit interval timer 1 channel
High accuracy real-time
clock 1 channel
RTC out put 1 1 Hz (subsystem clock: fSUB = 32.768 kHz)
RL78/L1C 1.OUTLINE
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0192EJ0001 Rev. 0.01 Page 16 of 16
Oct 15, 2012
Note 1. The number in parentheses indicates the number of signal outputs when 8 coms are used.
Note 2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
(2/2)
Item 80-pin 100-pin
R5F111Mx (x = E to H, J) R5F111Px (x = E to H, J)
Clock output/buzzer output 2 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/12-bit resolut i on A/D converter 11 channels 13 channels
D/A converter 2 channels 2 channels
Comparator 1 channel 2 channels
Serial interface • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
I2C bus 1 channel 1 channel
LCD controller/driver Internal voltag e boosting meth od, capaci tor split metho d, an d e xternal resist ance division method
are switchable.
Segment signal output 44 (40) Note 1 56 (52) Note 1
Common signal output 4 (8) Note 1
Data transfer controller (DTC) 30 sources 31 sources
Event link controller (ELC) Event input: 30, Event trigger output: 22 Event input: 31, Event trigger output: 22
Vectored interrupt
sources Internal 34 35
External 9 9
Key interrupt 8 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 0.03 V
• Power-down-reset: 1.50 0.03 V
Voltage detector • Rising edge: 1.67 V to 3.13 V (12 stages)
• Falling edge: 1.63 V to 3.06 V (12 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 3.6 V
Operating ambient temperature TA = -40 to +85C
1
RL78/L1C Datasheet
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Rev. Date Description
Page Summary
0.01 Oct 15, 2012 — First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
REVISION HIST ORY
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, et c., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up o r pull-down circuitry. Each unuse d pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequat e. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive m aterial. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare ha nds. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and exter nal interface, as a rule, s witch on the external power supply after s witching on the in ternal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct po wer on/off sequence m ust be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The curr ent injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device an d accord ing to related specifications governing the device.
Notice
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