STH310N10F7-2, STH310N10F7-6 N-channel 100 V, 1.9 m typ.,180 A, STripFETTM F7 Power MOSFETs in H2PAK-2 and H2PAK-6 packages Datasheet - production data Features TAB TAB Order code 1 2 H PAK-2 STH310N10F7-2 7 2 3 STH310N10F7-6 1 2 H PAK-6 Figure 1: Internal schematic diagram VDS RDS(on) max. ID 100 V 2.3 m 180 A Among the lowest RDS(on) on the market Excellent figure of merit (FoM) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Description These N-channel Power MOSFETs utilize STripFETTM F7 technology with an enhanced trench gate structure that results in very low onresistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code S(2,3,4,5,6,7) Marking 2 STH310N10F7-2 H PAK-2 310N10F7 STH310N10F7-6 November 2014 DocID024040 Rev 3 This is information on a product in full production. Package 2 H PAK-6 Packing Tape and reel 1/19 www.st.com Contents STH310N10F7-2, STH310N10F7-6 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/19 4.1 H2PAK-2 package information ......................................................... 10 4.2 H2PAK-6 package information ......................................................... 13 4.3 Packing information ......................................................................... 16 Revision history ............................................................................ 18 DocID024040 Rev 3 STH310N10F7-2, STH310N10F7-6 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage 20 V Drain current (continuous) at TC = 25 C 180 A Drain current (continuous) at TC = 100 C 120 A Drain current (pulsed) 720 A Total dissipation at TC = 25 C 315 W Derating factor 2.1 W/C 1 J (1) ID (2) ID PTOT (3) EAS Single pulse avalanche energy (TJ = 25 C L = 0.55 mH, IAS = 65 A) TJ Operating junction temperature Tstg Storage temperature -55 to 175 C C Notes: (1) (2) (3) Current limited by package Pulse width limited by safe operating area Starting TJ = 25 C, ID = 60 A, VDD = 50 V Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case 0.48 C/W Thermal resistance junction-pcb 35 C/W Notes: (1) When mounted on FR-4 board of 1 inch, 2 oz Cu DocID024040 Rev 3 3/19 Electrical characteristics 2 STH310N10F7-2, STH310N10F7-6 Electrical characteristics (TCASE = 25 C unless otherwise specified) Table 4: On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage (VGS= 0) ID = 250 A Min. Typ. Max. 100 Unit V VDS = 100 V 1 A VDS = 100 V; TC = 125 C 100 A 100 nA 4.5 V IDSS Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A RDS(on) Static drain-source onresistance VGS = 10 V, ID = 60 A 2.5 3.5 1.9 m 2.3 Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions Min. VDS = 25 V, f = 1 MHz, VGS = 0 Typ. Max. 12800 pF 3500 pF 170 - Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Unit pF - VDD = 50 V, ID = 180 A VGS = 10 V See Figure 14: "Gate charge test circuit" 180 nC 78 nC 34 nC Table 6: Switching times Symbol td(on) tr td(off) tf 4/19 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 50 V, ID = 90 A, RG = 4.7 , VGS= 10 V See Figure 13: "Switching times test circuit for resistive load" DocID024040 Rev 3 Min. Typ. Max. 62 ns 108 - 148 40 Unit ns - ns ns STH310N10F7-2, STH310N10F7-6 Electrical characteristics Table 7: Source-drain diode Symbol ISD (1) ISDM (2) VSD Parameter Test conditions Min. Typ. Source-drain current Source-drain current (pulsed) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 60 A, VGS = 0 ISD = 180 A, di/dt = 100 A/s, VDD = 80 V, Tj = 150 C - Max. Unit 180 A 720 A 1.5 V 85 ns 200 nC 4.7 A Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 s, duty cycle 1.5% DocID024040 Rev 3 5/19 Electrical characteristics 2.1 STH310N10F7-2, STH310N10F7-6 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area AM15430v1 ID (A) ea 280tok K is =0.5 ar ) is DS(on th in ax R ion y m at er d b Op ite Lim 100 0.2 0.1 10 10 100s 0.05 -1 0.02 1 Tj= 175 C Tc= 25 C 1ms Sinlge pulse 10ms Zth=k Rthj-c =tp/ t 0.01 Single pulse tp t 0.1 0.1 -2 10 1 10 -5 10 V DS(V) 10 V GS=10V 10 -1 tp (s) V DS = 2V 350 8V 300 7V 250 10 -2 AM14735v1 ID (A) AM14734v1 300 -3 Figure 5: Transfer characteristics Figure 4: Output characteristics ID (A) 10 -4 250 200 200 150 150 100 6V 100 50 50 5V 0 0 2 4 6 8 0 V DS(V) Figure 6: Gate charge vs gate-source voltage 0 4 5 6 7 8 V GS(V) AM15431v1 V GS=10V 2.20 8 2.15 6 4 2.10 2 2.05 2 0 0 6/19 3 R DS(on) (m) 2.25 V DD=50V ID=180 A 10 2 Figure 7: Static drain-source on-resistance AM14736v1 V GS (V) 1 50 100 150 Q g(nC) DocID024040 Rev 3 0 40 80 120 160 ID(A) STH310N10F7-2, STH310N10F7-6 Electrical characteristics Figure 9: Capacitance variations Figure 8: Normalized V(BR)DSS vs temperature AM14738v1 C (pF) AM14742v1 V (BR)DSS (norm) 14000 ID = 1m A Ciss 1.04 12000 1.02 10000 1.00 8000 6000 0.98 4000 0.96 Crss 2000 Coss 0.94 -75 -25 25 75 125 0 T J(C) 20 40 60 80 100 V DS(V) Figure 11: Normalized gate threshold voltage vs temperature Figure 10: Source-drain diode forward characteristics AM14741v1 V GS(th) (norm) AM14739v1 V SD (V) 0 ID = 250 A 1.05 1.0 T J=-50C 0.95 0.90 0.85 T J=25C 0.75 0.80 0.65 0.45 0.70 T J=150C 0.55 0 40 80 160 120 0.60 -75 ISD(A) -25 0 25 75 125 T J(C) Figure 12: Normalized on-resistance vs temperature AM14740v1 R DS(on) (norm) 2.0 ID = 60A 1.6 1.2 0.8 0.4 -75 -25 0 25 75 DocID024040 Rev 3 125 T J(C) 7/19 Test circuits 3 STH310N10F7-2, STH310N10F7-6 Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit VDD 47 k 12 V 1 k 100 nF I G = CONST Vi V GS 100 D.U.T. VG 2.7 k 2200 F 47 k PW 1 k AM01469v 1 Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform t on V(BR)DSS t d(on) VD t off tr t d(off) tf 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 8/19 DocID024040 Rev 3 0 10% VDS 90% AM01473v 1 STH310N10F7-2, STH310N10F7-6 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of (R) (R) ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. (R) ECOPACK is an ST trademark. DocID024040 Rev 3 9/19 Package information 4.1 STH310N10F7-2, STH310N10F7-6 2 H PAK-2 package information Figure 19: HPAK-2 outline 8159712_D 10/19 DocID024040 Rev 3 STH310N10F7-2, STH310N10F7-6 Package information Table 8: HPAK-2 mechanical data mm Dim. Min. Typ. Max. A 4.30 4.80 A1 0.03 0.20 C 1.17 1.37 e 4.98 5.18 E 0.50 0.90 F 0.78 0.85 H 10.00 10.40 H1 7.40 L 15.30 L1 1.27 1.40 L2 4.93 5.23 L3 6.85 7.25 L4 1.5 1.7 M 2.6 2.9 R 0.20 0.60 V 0 8 DocID024040 Rev 3 - 7.80 15.80 11/19 Package information STH310N10F7-2, STH310N10F7-6 Figure 20: HPAK-2 recommended footprint 8159712_D 12/19 DocID024040 Rev 3 STH310N10F7-2, STH310N10F7-6 4.2 Package information 2 H PAK-6 package information Figure 21: HPAK-6 outline 8159693_Rev_F DocID024040 Rev 3 13/19 Package information STH310N10F7-2, STH310N10F7-6 Table 9: HPAK-6 mechanical data mm Dim. Min. 14/19 Typ. Max. A 4.30 4.80 A1 0.03 0.20 C 1.17 1.37 e 2.34 2.74 e1 4.88 5.28 e2 7.42 7.82 E 0.45 0.60 F 0.50 0.70 H 10.00 H1 7.40 L 14.75 15.25 L1 1.27 1.40 L2 4.35 4.95 L3 6.85 7.25 L4 1.5 1.75 M 1.90 2.50 R 0.20 0.60 V 0 8 DocID024040 Rev 3 - 10.40 7.80 STH310N10F7-2, STH310N10F7-6 Package information Figure 22: HPAK-6 recommended footprint footprint_Rev_F Dimensions are in mm. DocID024040 Rev 3 15/19 Package information 4.3 STH310N10F7-2, STH310N10F7-6 Packing information Figure 23: Tape outline Figure 24: Reel outline T REE L DIMENS IONS 40 mm min. Acc ess hole At slot location B D C N A Tape slot In core for Full radius At hub Tape start 16/19 G measured DocID024040 Rev 3 STH310N10F7-2, STH310N10F7-6 Package information Table 10: Tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID024040 Rev 3 Min. Max. 330 13.2 26.4 30.4 17/19 Revision history 5 STH310N10F7-2, STH310N10F7-6 Revision history Table 11: Document revision history Date Revision 10-Dec-2012 1 Changes Initial release. Part number(s) previously included in datasheet ID02287 23-Jul-2013 27-Nov-2014 18/19 2 3 Document status promoted from preliminary to production data Modified: IDSS and VGS value in table 4 Added: EAS value in table 2 Minor text changes Updated: H PAK-6 package information. Updated the title, features and description. Minor text changes. 2 DocID024040 Rev 3 STH310N10F7-2, STH310N10F7-6 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2014 STMicroelectronics - All rights reserved DocID024040 Rev 3 19/19 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: STMicroelectronics: STH310N10F7-2 STH310N10F7-6