AD5255BRUZ25 - Analog Devices

3-Channel Digital Potentiometer with

Nonvolatile Memory

AD5255

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

3 channels

Dual 512 position

Single 128 position

25 kΩ or 250 kΩ full-scale resistance

Low temperature coefficient

Potentiometer divider 15 ppm/°C

Rheostat mode 35 ppm/°C

Nonvolatile memory retains wiper settings

Permanent memory write protection

Linear increment/decrement

±6 dB increment/decrement

I2C-compatible serial interface

2.7 V to 5.5 V single-supply operation

±2.25 V to ±2.75 V dual-supply operation

Power-on reset time

256 bytes general-purpose user EEPROM

11 bytes RDAC user EEPROM

GBIC and SFP compliant EEPROM

100-year typical data retention at TA = 55°C

APPLICATIONS

Mechanical potentiometer replacement

RGB LED backlight controls

White LED brightness adjustment

Programmable gain and offset controls

Programmable filters

FUNCTIONAL BLOCK DIAGRAM

RDAC0

RDAC1

RDAC2

9-BIT

RDAC1

9-BIT

RDAC2

7-BIT

DATA

CONTROL

COMMAND

DECODE

LOGIC

ADDRESS

DECODE

LOGIC

DECODE

LOGIC

POWER-ON

RESET

SERIAL

INTERFACE

32 BYTES

RDAC

EEPROM

256 BYTES

USER

EEPROM

GND

SCL

SDA

A0_RDAC

A1_RDAC

A0_E

A1_E

04555-0-001

Figure 1.

GENERAL DESCRIPTION

The AD5255 provides a dual 512 position and a single 128

position digitally controlled variable resistors1 (VR) in a TSSOP

package. This device performs the same electronic adjustment

function as a potentiometer, trimmer, or VR. Each VR offers a

completely programmable value of resistance between the A

terminal and the wiper or the B terminal and the wiper. The

fixed A-to-B terminal resistance of 25 kΩ or 250 kΩ has a 1%

channel-to-channel matching tolerance and a nominal

temperature coefficient of 35 ppm/°C.

Wiper position programming, EEPROM2 reading, and EEPROM

writing is conducted via the standard 2-wire I2C interface. Pre-

vious/default wiper position settings can be stored in memory

and refreshed upon system power-up.

Additional features of the AD5255 include preprogrammed

linear and logarithmic increment/decrement wiper changing.

The actual resistor tolerances are stored in EEPROM, so the

actual end-to-end resistance is known, which is valuable for

calibration in precision applications.

The AD5255 is available in a 24-lead TSSOP. All parts are

guaranteed to operate over the extended industrial temperature

range of −40°C to +85°C

1 The terms programmable resistor, variable resistor, RDAC, and digital

potentiometer are used interchangeably.

2 The terms nonvolatile memory, EEMEM, and EEPROM are used

interchangeably.

AD5255

Rev. A | Page 2 of 20

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Interface Descriptions.................................................................... 10

I2C Interface ................................................................................ 10

EEPROM Interface..................................................................... 11

RDAC I2C Interface.................................................................... 12

Theory of Operation ...................................................................... 15

Linear Increment and Decrement Commands ...................... 15

Logarithmic Taper Mode Adjustment (±6 dB/step) .............. 15

Using Additional Internal Nonvolatile EEPROM.................. 16

Digital Input/Output Configuration........................................ 16

Multiple Devices on One Bus ................................................... 16

Level Shift for Bidirectional Communication ........................ 16

Terminal Voltage Operation Range ......................................... 16

Power-Up Sequence ................................................................... 17

Layout and Power Supply Biasing............................................ 17

RDAC Structure.......................................................................... 17

Calculating the Programmable Resistance ............................. 17

Programming the Potentiometer Divider............................... 18

Applications..................................................................................... 19

Laser Diode Driver (LDD) Calibration................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

11/05—Rev. 0 to Rev. A

Added Figure 2.....................................................................................4

Changes to Figure 3 and Table 4........................................................7

7/04—Revision 0: Initial Version

AD5255

Rev. A | Page 3 of 20

ELECTRICAL CHARACTERISTICS

Single supply: VDD = 2.7 V to 5.5 V and −40°C < TA < +85°C, unless otherwise noted.

Dual supply: VDD = +2.25 V or +2.75 V, VSS = −2.25 V or −2.75 V, and −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS,

RHEOSTAT MODE

Resistor Differential Nonlinearity2

R-DNL RWB, 7-bit channels −0.7

+0.7

LSB

RWB, 9-bit channels −2.5 +2.5 LSB

Resistor Integral Nonlinearity2

R-INL RWB, 7-bit channels −0.5 +0.5 LSB

R-INL RWB, 9-bit channels, VDD = 5.5 V −2.0 +2.0 LSB

R-INL RWB, 9-bit channels, VDD = 2.7 V −4.0 +4.0 LSB

Resistance Temperature Coefficent (∆RWB/RWB)/∆T × 107

35 ppm/°C

Wiper Resistance RW V

DD = 5 V, IW = 1 V/RWB 100 150 Ω

VDD = 3 V, IW = 1 V/RWB 250 400 Ω

Channel Resistance Matching ∆RAB1/∆RAB2 Ch 1 and 2 RWB, Dx = 0x1FF 0.1 %

Nominal Resistor Tolerance ∆RAB/RAB Dx = 0x3FF −15 +15 %

DC CHARACTERISTICS,

POTENTIOMETER DIVIDER MODE

Differential Nonlinearity3

DNL 7-bit channels −0.5

+0.5 LSB

DNL 9-bit channels −2.0

+2.0 LSB

Integral Nonlinearity3

INL 7-bit channels −0.5

+0.5 LSB

INL 9-bit channels −2.0

+2.0 LSB

Voltage Divider Temperature Coefficent (∆VW/VW)/∆T × 107Code = half scale 15 ppm/°C

Full-Scale Error VWFSE 7-bit channels/9-bit channels,

code = full scale

−1/−2.75 0/0 LSB

Zero-Scale Error VWZSE 7-bit channels/9-bit channels,

code = zero scale

0/0 1/2.0 LSB

RESISTOR TERMINALS

Terminal Voltage Range4VA, VB, VW VSS VDD V

Capacitance5 Ax, Bx CA,B f = 1 kHz, measured to GND,

code = half scale

85 pF

Capacitance5 Wx CW f = 1 kHz, measured to GND,

code = half scale

95 pF

Common-Mode Leakage Current 5, 6ICM V

W = VDD/2 0.01 1 μA

AD5255

Rev. A | Page 4 of 20

Parameter Symbol Conditions Min Typ1Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V

DD = 5 V, VSS = 0 V 2.4 V

VDD/VSS = +2.7 V/0 V or

VDD/VSS = ±2.5 V

2.1 V

Input Logic Low VIL V

DD = 5 V, VSS = 0 V 0.8 V

VDD/VSS = +2.7 V/0 V or

VDD/VSS = ±2.5 V

0.6 V

Output Logic High (SDA) VOH RPULL-UP = 2.2 kΩ to VDD = 5 V,

VSS = 0 V

4.9 V

Output Logic Low VOL RPULL-UP = 2.2 kΩ to VDD = 5 V,

VSS = 0 V

0.4 V

WP Leakage Current IWP WP = VDD 9 μA

A0 Leakage Current IA0 A0 = GND 3 μA

Input Leakage Current (Excluding WPand A0) II V

IN = 0 V or VDD ±1 μA

Input Capacitance5CI

5 pF

POWER SUPPLIES

Single-Supply Power Range VDD V

SS = 0 V 2.7 5.5 V

Dual-Supply Power Range VDD/VSS ±2.2

±2.7

Positive Supply Current IDD V

IH = VDD or VIL = GND, VSS = 0 V 5 15 μA

Negative Supply Current ISS VIH = VDD or VIL = GND,

VDD = 2.5 V, VSS = −2.5 V

−5 −15 μA

EEMEM Data Storing Mode Current IDD_STORE V

IH = VDD or VIL = GND 35 mA

EEMEM Data Restoring Mode Current IDD_RESTORE V

IH = VDD or VIL = GND 2.5 mA

Power Dissipation7PDISS V

IH = VDD = 5 V or VIL = GND 25 75 μW

Power Supply Sensitivity5PSS ∆VDD = 5 V ± 10% 0.01 0.025 %/%

1 Typical represents average readings at 25°C, VDD = 5 V.

2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.

4 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

5 Guaranteed by design and not subject to production test.

6 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

04555-0-015

PS S

SCL

Figure 2. I2C Timing Diagram

AD5255

Rev. A | Page 5 of 20

Single supply: VDD = 3 V to 5.5 V and −40°C < TA < +85°C, unless otherwise noted.

Dual supply: VDD = 2.25 V or 2.75 V, VSS = −2.25 V or −2.75 V, and −40°C < TA < + 85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1Max Unit

DYNAMIC CHARACTERISTICS2, 3

Bandwidth −3 dB BW VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ 125/12 kHz

Total Harmonic Distortion THDW V

A = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

VW Settling Time tS VA = VDD, VB = 0 V,

VW = 0.50% error band,

code 0x000 to 0x100, RAB = 25 kΩ/250 kΩ

4/36 μs

Resistor Noise Spectral Density eN_WB R

AB = 25 kΩ/250 kΩ, TA = 25°C 14/45 nV√Hz

Digital Crosstalk CT VA = VDD, VB = 0 V, measure VW with

adjacent RDAC making full-scale change

−80 dB

Analog Crosstalk CAT Signal input at A0 and measure output at

W1, f = 1 kHz

−72 dB

INTERFACE TIMING CHARACTERISTICS

(APPLY TO ALL PARTS)4, 5

SCL Clock Frequency fSCL 400 kHz

tBUF Bus Free Time Between Stop

and Start

t1 1.3 μs

tHD;STA Hold Time (Repeated)

Start Condition

t2 After this period the first clock pulse is

generated

600 ns

tLOW Low Period of SCL Clock t3 1.3 μs

tHIGH High Period of SCL Clock t4 0.6 50 μs

tSU;STA Setup Time for Repeated

Start Condition

t5 600 ns

tHD;DAT Data Hold Time t6 900 ns

tSU;DAT Data Setup Time t7 100 ns

tR Rise Time of Both SDA and SCL

Signals

t8 300 ns

tF Fall Time of Both SDA and SCL

Signals

t9 300 ns

tSU;STO Setup Time for Stop Condition t10 600 ns

EEMEM Data Storing Time tEEMEM_STORE 26 ms

EEMEM Data Restoring Time

at Power-On

tEEMEM_RESTORE1 360 μs

EEMEM Data Restoring Time

on Restore Command or

Reset Operation

tEEMEM_RESTORE2 360 μs

EEMEM Data Rewritable Time tEEMEM_REWRITE 540 μs

FLASH/EE MEMORY RELIABILITY

Endurance6 100 kcycles

Data Retention7 55°C 100 years

1 Typical represents average readings at 25°C, VDD = 5 V.

2 Guaranteed by design and not subject to production test.

3 All dynamic characteristics use VDD = 5 V.

4 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

5 See the timing diagram for location of measured values.

6 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.

7 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature.

AD5255

Rev. A | Page 6 of 20

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V, +7 V

VSS to GND +0.3 V, −7 V

VDD to VSS 7 V

VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V

IA, IB, IW

Pulsed1 ±20 mA

Continuous ±2 mA

Digital Inputs and Output Voltage to GND −0.3 V, VDD + 0.3 V

Operating Temperature Range2 −40°C to +85°C

Maximum Junction Temperature (TJ max) 150°C

Storage Temperature −65°C to +150°C

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Thermal Resistance Junction-to-Ambient

θJA, TSSOP-24

143°C/W

1 Includes programming of nonvolatile memory.

2 Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

Stresses greater than those listed under Absolute Maximum

Ratings may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD5255

Rev. A | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

A1_RDAC

A0_RDAC

SDA

SCL

A0_EE

TEST0 (NC)

TEST1 (NC)

TEST2 (NC)

TEST3 (NC)

DGND

A1_EE

AD5255

TOP VIEW

(Not to Scale)

04555-0-034

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 A0_EE I2C Device Address 0 for EEMEM.

2 A1_RDAC I2C Device Address 1 for RDAC.

3 A0_RDAC I2C Device Address 0 for RDAC.

4 RS Resets the scratchpad register with current contents of the EEMEM register. Factory defaults to midscale before

any programming.

5 WP Write Protect. When active low, WP prevents any changes to the present register contents, except that RESET

and Command 1 and Command 8 still refresh the RDAC register from EEMEM.

6 SCL Serial Input Register Clock. Shifts in one bit at a time on the positive clock edges.

7 SDA Serial Data Input. Shifts in one bit at a time on the positive clock edges. The MSB is loaded first.

8 DGND Ground. Logic ground reference.

9 VSS Negative Supply. Connect to 0 V for single-supply applications.

10 A2 A terminal of RDAC2.

11 W2 Wiper terminal of RDAC2.

12 B2 B terminal of RDAC2.

13 A1 A terminal of RDAC1.

14 W1 Wiper terminal of RDAC1.

15 B1 B terminal of RDAC1.

16 B0 B terminal of RDAC0.

17 W0 Wiper terminal of RDAC0.

18 A0 A terminal of RDAC0.

19 VDD Positive Power Supply.

20 TEST3 (NC) Test Pin 3. Do not connect.

21 TEST2 (NC) Test Pin 2. Do not connect.

22 TEST1 (NC) Test Pin 1. Do not connect.

23 TEST0 (NC) Test Pin 0. Do not connect.

24 A1_EE I2C Device Address 1 for EEMEM.

AD5255

Rev. A | Page 8 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

INL (LSB)

25619264 1280 320 384 448 512

CODE (DECIMAL)

04555-0-002

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 4. INL—9-Bit RDAC

–1.50

–1.00

–0.50

–0.75

–1.25

–0.25

DNL (LSB)

0.50

0.25

1.00

0.75

1.50

1.25

25619264 1280 320 384 448 512

CODE (DECIMAL)

04555-0-003

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 5. DNL—9-Bit RDAC

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

R-INL (LSB)

25619264 1280 320 384 448 512

CODE (DECIMAL)

04555-0-004

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 6. R-INL—9-Bit RDAC

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

R-DNL (LSB)

25619264 1280 320 384 448 512

CODE (DECIMAL)

04555-0-005

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 7. R-DNL—9-Bit RDAC

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

INL (LSB)

644816 320 80 96 112 128

CODE (DECIMAL)

04555-0-006

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 8. INL—7-Bit RDAC

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

DNL (LSB)

644816 320 80 96 112 128

CODE (DECIMAL)

04555-0-007

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 9. DNL—7-Bit RDAC

AD5255

Rev. A | Page 9 of 20

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

R-INL (LSB)

644816 320 80 96 112 128

CODE (DECIMAL)

04555-0-008

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 10. R-INL—7-Bit RDAC

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

R-DNL (LSB)

644816 320 80 96 112 128

CODE (DECIMAL)

04555-0-009

= –40°C, +25°C, +85°C SUPERIMPOSED

= 5V

Figure 11. R-DNL—7-Bit RDAC

RHEOSTAT MODE TEMPCO (ppm/°C)

25619264 1280 320 384 448 512

CODE (DECIMAL)

04555-0-010

= –40°C, +85°C

= 5V

= V

= 0V

Figure 12. Temperature Coefficient (Rheostat Mode)

POTENTIOMETER MODE TEMPCO (ppm/°C)

25619264 1280 320 384 448 512

CODE (DECIMAL)

04555-0-011

= –40°C, +85°C

= 5V

= V

= 0V

Figure 13. Temperature Coefficient (Potentiometer Mode)

–10

–8

–6

–4

–2

SUPPLY CURRENT (mA)

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

04555-0-012

IDD: VDD = 5.5V

IDD: VDD = 2.7V

IS: VDD = 2.7V, VSS = 2.7V

Figure 14. Supply Current vs. Temperature

(mA)

100

110

CLOCK FREQUENCY (Hz)

04555-0-013

= 25°C

= 5.5V

= 2.7V

Figure 15. Supply Current vs. Clock Frequency

AD5255

Rev. A | Page 10 of 20

INTERFACE DESCRIPTIONS

I2C INTERFACE

All control and access to both EEPROM memory and the

RDAC registers are conducted via a standard 2-wire I2C interface.

Figure 2 shows the timing characteristics of the I2C bus.

Figure 16 and Figure 17 illustrate standard transmit and receive

bus signals in the I2C interface.

These figures use the following legend:

From master to slave

From slave to master

S = Start condition

P = Stop condition

A = Acknowledge (SDA low)

A = Not acknowledge (SDA high)

R/W = Read enable at high and write enable at low

SLAVE ADDRESSS

0 = WRITE

A DATA A

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

DATA A/A P

04555-0-016

R/W

Figure 16. I2C—Master Transmitting Data to Slave

SLAVE ADDRESSS

1 = WRITE

A DATA A

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE

DATA A P

04555-0-017

R/W

Figure 17. I2C—Master Reading Data from Slave

SLAVE ADDRESSS

READ OR WRITE

A DATA

(N BYT E S + ACKNOWL EDGE)

A/A P

04555-0-018

R/W SL AV E ADDRES SS

READ OR WRITE

REPEATED START

A DATA

(N BYTES + ACKNO WLE DGE)

A/A

R/W

DIRECTION OF TRANSFER MAY

CHANGE AT THIS P OINT

Figure 18. Combined Transmit/Read

AD5255

Rev. A | Page 11 of 20

EEPROM INTERFACE

MEMORY ADDRESS MEMORY DATA MEMORY DATASAAAAA00

01 EE

0011P

04555-0-019

0 WRITE (N BYTES + ACKNOWLEDGE)EEPROM SLAVE ADDRESS

A/A

Figure 19. EEPROM Write

MEMORY DATA MEMORY DATASAAAA00

01 EE

0011P

04555-0-020

1 READ (N BYTES + ACKNOWLEDGE)EEPROM SLAVE ADDRESS

Figure 20. EEPROM Current Read

SLAVE ADDRESS MEMORY ADDRESSS

0 WRIT E

AA P

04555-0-021

WSLAVE ADDRESS MEMORY DATASR

1 READ

REPEATED START

(N BYT ES + ACKNO W LEDG E)

A/A

Figure 21. EEPROM Random Read

The 256 bytes of EEPROM memory provided in the AD5255

are organized into 16 pages of 16 bytes each. The word size of

each memory location is one byte wide.

The I2C slave address of the EEPROM is 10100(A1E)(A0E),

where A1E and A0E are external pin-programmable address

bits. The 2-pin programmable address bits allow a total of four

AD5255 devices to be controlled by a single I2C master bus,

each having its own EEPROM.

An internal 8-bit address counter for the EEPROM is

automatically incremented following each read or write

operation. For read operations, the address counter is

incremented after each byte is read, and the counter rolls

over from Address 255 to 0.

For write operations, the address counter is incremented after

each byte is written. The counter rolls over from the highest

address of the current page to the lowest address of the current

page. For example, writing two bytes beginning at Address 31

causes the counter to roll back to Address 16 after the first byte

is written; then the address increments to 17 after the second

byte is written.

EEPROM Write

Each write operation issued to the EEPROM programs between

1 byte and 16 bytes (1 page) of memory. Figure 19 shows the

EEPROM write interface. The number of bytes of data, N, that

the user wants to send to the EEPROM is unrestricted. If more

than 16 bytes of data are sent in a single write operation, the

address counter rolls back to the beginning address, and the

previously sent data is overwritten.

EEPROM Write-Acknowledge Polling

After each write operation, an internal EEPROM write cycle

begins. During the EEPROM internal write cycle, the I2C

interface of the device is disabled. It is necessary to determine

if the internal write cycle is complete and whether the I2C

interface is enabled. To do so, execute I2C interface polling

by sending a start condition followed by the EEPROM slave

address plus the desired R/W bit. If the AD5255 I2C interface

responds with an ACK, the write cycle is complete, and the

interface is ready to proceed with further operations. Other-

wise, the I2C interface must be polled again to determine

whether the write cycle has been completed.

EEPROM Read

The AD5255 EEPROM provides two different read operations,

shown in Figure 20 and Figure 21. The number of bytes, N, read

from the EEPROM in a single operation is unrestricted. If more

than 256 bytes are read, the address counter rolls back to the

start address, and data previously read is read again.

Figure 20 shows the EEPROM current read operation. This

operation does not allow an address location to be specified,

and reads data beginning at the current address location stored

in the internal address counter.

AD5255

Rev. A | Page 12 of 20

A random read operation is shown in Figure 21. This operation

changes the address counter to the specified memory address

by performing a dummy write and then performing a read

operation beginning at the new address counter location.

EEPROM Write Protection

Setting the WP pin to a logic low protects the EEPROM mem-

ory from future write operations. In this mode, EEPROM read

operations and RDAC register loading operate normally.

RDAC I2C INTERFACE

DATA DATASA AAAA10 0

01 R

EE/

RDAC A

CMD/

REG

1100P

04555-0-022

0 WRITE (N BYTES + ACKNOWLEDGE)RDAC ADDRESSRDAC SLAVE ADDRESS

A/A

Figure 22. RDAC Write

SAAA11

01 R

ARDAC EEPROM OR REGISTER DATA RDAC EEPROM OR REGISTER DATA

1100P

04555-0-023

1 READ (N BYTES + ACKNOWLEDGE)RDAC SLAVE ADDRESS

Figure 23. RDAC Current Read

SLAVE ADDRESS RDAC ADDRESSS

0 WRIT E

AA P

04555-0-024

WSLAVE ADDRESS RDAC D ATASR

1 READ

REPEATED START

(N BYT ES + ACKNO W LEDG E)

A/A

Figure 24. RDAC Random Read

SAAA10

01 R

CMD/

REG

1100P

04555-0-025

0 WRITE 1 CMD

RDAC SLAVE ADDRESS

Figure 25. RDAC Shortcut Command

Table 5. RDAC Register Addresses (CMD/REG = 0, EE/RDAC = 0)

A4 A3 A2 A1 A0 RDAC Byte Description

0 0 0 0 0 RDAC0 (D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC0 8 LSBs

0 0 0 0 1 RDAC0 (X)(X)(X)(X)(X)(X)(X)(D8) – RDAC0 MSB

0 0 0 1 0 RDAC1 (D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC1 8 LSBs

0 0 0 1 1 RDAC1 (X)(X)(X)(X)(X)(X)(X)(D8) – RDAC1 MSB

0 0 1 0 0 RDAC2 (X)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC2 7 bits

0 0 1 0 1 Reserved

. . . to . . .

1 1 1 1 1

AD5255

Rev. A | Page 13 of 20

Table 6. RDAC R/W EEPROM Addresses (CMD/REG = 0, EE/RDAC = 1)

A4 A3 A2 A1 A0 Byte Description

0 0 0 0 0 RDAC0 8 LSBs

0 0 0 0 1 RDAC0 MSB

0 0 0 1 0 RDAC1 8 LSBs

0 0 0 1 1 RDAC1 MSB

0 0 1 0 0 RDAC2 7 bits

0 0 1 0 1 11 bytes RDAC User EEPROM

. . . to . . .

0 1 1 1 1

Table 7. RDAC Command Table (CMD/REG = 1)

C3 C2 C1 C0 Command Description

0 0 0 0 NOP

0 0 0 1 Restore EEPROM to RDAC1

0 0 1 0 Store RDAC to EEPROM2

0 0 1 1 Decrement RDAC 6 dB

0 1 0 0 Decrement All RDACs 6 dB

0 1 0 1 Decrement RDAC 1 Step

0 1 1 0 Decrement All RDACs 1 Step

0 1 1 1 Reset; Restore EEPROM to all RDACs2

1 0 0 0 Increment RDACs 6 dB

1 0 0 1 Increment All RDACs 6 dB

1 0 1 0 Increment RDAC 1 Step

1 0 1 1 Increment All RDAC 1 Step

1 1 0 0 Reserved

. . . to . . .

1 1 1 1

1 Command leaves the device in the EEPROM read power state. Issue the NOP command to return the device to the idle state.

2 Command requires acknowledge polling after execution.

RDAC Interface Operation

Each programmable resistor wiper setting is controlled by

specific RDAC registers, as shown in Table 5. Each RDAC

which provides nonvolatile wiper storage functionality.

RDAC registers and their corresponding EEPROM memory

locations are programmed and read independently from each

other. The RDAC register is refreshed by the EEPROM locations

either with a hardware reset via Pin 1, or by issuing one of the

various RDAC register load commands shown in the Table 7.

RDAC Write

Setting the wiper position requires an RDAC write operation,

shown in Figure 22. RDAC write operations follow a format

similar to the EEPROM write interface. The only difference

between an RDAC write and an EEPROM write operation

is the use of an RDAC address byte in place of the memory

address used in the EEPROM write operation. The RDAC

address byte is described in detail in Table 5 and Table 6.

As with the EEPROM write operation, any RDAC EEPROM

(Shortcut Command 2) write operation disables the I2C inter-

face during the internal write cycle. Acknowledge polling, as

described in the EEPROM Interface section, is required to

determine whether the write cycle is complete.

RDAC Read

The AD5255 provides two RDAC read operations. The first,

shown in Figure 23, reads the contents of the current RDAC

address counter. Figure 24 illustrates the second read operation,

which allows users to specify which RDAC register to read by

first issuing a dummy write command to change the RDAC

address pointer, and then proceeding with the RDAC read

operation at the new address location.

The read-only RDAC EEPROM memory locations can also be

read by using the address and bits specified in Table 6.

AD5255

Rev. A | Page 14 of 20

RDAC Shortcut Commands

Eleven shortcut commands are provided for easy manipulation of

RDAC registers and their corresponding EEPROM memory

locations. These commands are shown in Table 9 . A more

detailed discussion about the RDAC shortcut commands can

be found in the Theory of Operation section.

The interface for issuing an RDAC shortcut command is shown

in Figure 25. All shortcut commands require acknowledge poll-

ing to determine whether the command has finished executing.

RDAC Resistor Tolerance

The end-to-end resistance tolerance for each RDAC channel

is stored in read-only memory during factory production.

This information is read by using the address and bits speci-

fied in Table 8.

Tolerance values are stored in percentage form. Figure 26 shows

the format of the tolerance data stored in memory. Each stored

tolerance uses two memory locations. The first location stores

the integer portion, while the second location stores the decimal

portion.

The resistance tolerance is stored in sign-magnitude format.

The MSB of the first memory location designates the sign

(0 = +, 1 = −) and the remaining seven LSBs are designated for

the integer portion of the tolerance. All eight bits of the second

memory location represent the decimal portion of the tolerance

value.

Table 8. Addresses for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)

A4 A3 A2 A1 A0 Data Byte Description

1 1 0 0 0 Sign and 7-Bit Integer Values of RDAC0 Tolerance (Read-Only)

1 1 0 0 1 8-Bit Decimal Value of RDAC0 Tolerance (Read-Only)

1 1 0 1 0 Sign and 7-Bit Integer Values of RDAC1 Tolerance (Read-Only)

1 1 0 1 1 8-Bit Decimal Value of RDAC1 Tolerance (Read-Only)

1 1 1 0 0 Sign and 7-Bit Integer Values of RDAC2 Tolerance (Read-Only)

1 1 1 0 1 8-Bit Decimal Value of RDAC2 Tolerance (Read-Only)

7 BITS FOR INTEGER NUMBERSIGN

SIGN 2

A AD6 D5 D4 D3 D2 D1 D0D7

–2

–1

–3

–4

–5

–6

–7

–8

AD6 D5 D4 D3 D2 D1 D0D7

8 BITS FOR DECIMAL NUMBER

04555-0-026

Figure 26. Format of Stored Tolerance in Sign Magnitude with Bit Positions Descriptions Unit is in %. Only Data Bytes Shown.

AD5255

Rev. A | Page 15 of 20

THEORY OF OPERATION

The AD5255 digital potentiometer operates as a true variable

resistor. The RDAC register contents determine the resistor

wiper position. The RDAC register acts like a scratchpad

interface. See the RDAC I2C Interface section for the format of

the data-words and commands to program the RDAC registers.

Each RDAC register has a corresponding EEPROM memory

location, which provides nonvolatile storage of resistor wiper

position settings. The AD5255 provides commands to store the

RDAC register contents to their respective EEPROM memory

locations. During subsequent power-on sequences, the RDAC

registers are automatically loaded with the stored values.

Saving data from an RDAC register to EEPROM memory takes

approximately 25 ms and consumes 35 mA.

In addition to moving data between RDAC registers and

EEPROM memory, the AD5255 provides other shortcut

commands.

Table 9. AD5255 Shortcut Commands

No. Function

1 Restore EEPROM setting to RDAC1

2. Store RDAC register contents to EEPROM2

3 Decrement RDAC 6 dB (shift data bits right)

4 Decrement all RDACs 6 dB (shift all data bits right)

5 Decrement RDAC 1 step

6 Decrement all RDACs 1 step

7 Reset EEPROM setting to RDAC2

8 Increment RDAC 6 dB (shift data bits left)

9 Increment all RDACs 6 dB (shift all data bits left)

10 Increment RDAC 1 step

11 Increment all RDACs 1 step

1 Command leaves the device in the EEPROM read power state. Issue the NOP

command to return the device to the idle state.

2 Command requires acknowledge polling after execution.

LINEAR INCREMENT AND DECREMENT

COMMANDS

The increment and decrement commands (Command 10,

Command 11, Command 5, and Command 6) are useful for

linear step adjustment applications. These commands simplify

microcontroller software coding by allowing the controller to

send only an increment or decrement command to the AD5255.

The adjustment can be directed to an individual RDAC or to all

three RDACs.

LOGARITHMIC TAPER MODE ADJUSTMENT

(±6 dB/STEP)

The AD5255 accommodates logarithmic taper adjustment of

the RDAC wiper position(s) by shifting the register contents

left/right for increment/decrement operations. Command 8,

Command 9, Command 3, and Command 4 are used to

logarithmically increment or decrement the wiper positions

individually or change all three channel settings at the same time.

Incrementing the wiper position by +6 dB doubles the RDAC

the AD5255 uses a shift register to shift the bits left and right to

achieve a logarithmic increment or decrement.

Nonideal ±6 dB step adjustment occurs under certain conditions.

Table 10 illustrates how the shifting function affects the data

bits of an individual RDAC. Each line going down the table

represents a successive shift operation. Note: The left-shift

commands (Command 10 and Command 11) were modified

such that if the data in the RDAC register equals 0 and the data

is shifted, the RDAC register is set to Code 1. Similarly, if the

data in the RDAC register is greater than or equal to midscale

and the data is left shifted, the data in the RDAC register is

automatically set to full scale. This makes the left-shift function

as close as possible to a logarithmic adjustment.

The right-shift commands (Command 3 and Command 4) are

ideal only if the LSB is a 0 (ideal logarithmic = no error). If the

LSB is 1, the right-shift function generates a linear half

LSB error.

Table 10. RDAC Register Contents after ±6 dB Step Adjustments

Left Shift (+6 dB/Step) Right Shift (−6 dB/Step)

0 0000 0000 1 1111 1111

0 0000 0001 0 1111 1111

0 0000 0010 0 0111 1111

0 0000 0100 0 0011 1111

0 0000 1000 0 0001 1111

0 0001 0000 0 0000 1111

0 0010 0000 0 0000 0111

0 0100 0000 0 0000 0011

0 1000 0000 0 0000 0001

1 0000 0000 0 0000 0000

1 1111 1111 0 0000 0000

1 1111 1111

Actual conformance to a logarithmic curve between the data

contents in the RDAC register and the wiper position for each

right-shift command (Command 3 and Command 4) execution

contains an error only for odd numbers of bits. Even numbers

of bits are ideal.

AD5255

Rev. A | Page 16 of 20

USING ADDITIONAL INTERNAL

NONVOLATILE EEPROM

The AD5255 contains additional internal user EEPROM for

saving constants and other data. The user EEPROM I2C data-

word follows the same format as the general-purpose EEPROM

memory shown in Figure 19 and Figure 20. User EEPROM

memory addresses are shown in Table 6.

To support the use of multiple EEPROM modules on a single

I2C bus, the AD5255 features two external addressing pins,

Pin 21 and Pin 22 (A1_EE and A0_EE), to manually set the

address of the EEPROM included with the AD5255. This

feature ensures the correct EEPROM memory is accessed

when using multiple memory modules on a single I2C bus.

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD protected. Digital inputs are high

impedance and can be driven directly from most digital sources.

The RESET digital input pin does not have an internal pull-up

resistor. Therefore, the user should place a pull-up resistor from

RESET to VDD if the function is not used. The WP pin has an

internal pull-down resistor. If not driven by an external source,

the AD5255 defaults to a write-protected state. ESD protection

of the digital inputs is shown in Figure 27.

INPUTS

GND

04555-0-027

Figure 27. Equivalent WP ESD Protection

MULTIPLE DEVICES ON ONE BUS

Figure 28 shows four AD5255 devices on the same serial bus.

Each has a different slave address since the state of their AD0

pin and AD1 pin are different. This allows independent reading

and writing to each RDAC within each device.

MASTER SDA

SDA

AD1

AD0

SCL SDA

AD1

AD0

SCL SDA

AD1

AD0

SCL SDA

AD1

AD0

SCL

04555-0-028

Figure 28. Multiple AD5255 Devices on a Single Bus

LEVEL SHIFT FOR BIDIRECTIONAL

COMMUNICATION

While most legacy systems operate at one voltage, adding a new

component might require a different voltage. When two sys-

tems transmit the same signal at two different voltages, use a

level shifter to allow the systems to communicate.

For example, a 3.3 V microcontroller (MCU) can be used along

with a 5 V digital potentiometer. A level shifter is required to

enable bidirectional communication.

Figure 29 shows one of many possible techniques to properly

level-shift signals between two devices. M1 and M2 are

N-channel FETs (2N7002). If VDD falls below 2.5 V, use low

threshold N-channel FETs (FDV301N) for M1 and M2.

DD1

= 3.3V V

DD2

= 5V

DA1

SCL1

SDA2

SCL2

3.3V

MCU 5V

AD5255

04555-0-029

Figure 29. Level Shifting for Different Voltage Devices on an I2C Bus

TERMINAL VOLTAGE OPERATION RANGE

The AD5255 positive VDD and negative VSS power supply inputs

define the boundary conditions for proper 2-terminal program-

mable resistance operation. Supply signals on terminals W and

B that exceed VDD or VSS are clamped by the internal forward-

biased diodes of the AD5255.

04555-0-030

Figure 30. Maximum Terminal Voltages Set by VDD and VSS

The ground pin of the AD5255 is used as a digital ground

reference and needs to be tied to the common ground of the

PCB. Reference the digital input control signals to the AD5255

ground pin and satisfy the logic levels defined in the Digital

Inputs and Outputs parameters in Table 1.

AD5255

Rev. A | Page 17 of 20

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance

at the A, B, and W terminals (Figure 30), it is important to

power VDD/VSS before applying any voltage to the A, B, and W

terminals. Otherwise, the diode is forward-biased such that

VDD/VSS are powered unintentionally, which affects the rest of

the circuit. The ideal power-up sequence is as follows: GND,

VDD, VSS, digital inputs, and VA/VB/VW. The order of powering

VA, VB, VW, and the digital inputs is not important as long as

they are powered after VDD/VSS.

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to use compact, minimum lead

length layout design. Make the leads to the input as direct as

possible with a minimum conductor length. Make sure the

ground paths have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies

with quality capacitors. Use low equivalent series resistance

(ESR) 1 μF to 10 μF tantalum or electrolytic capacitors at the

supplies to minimize any transient disturbance and filter low

frequency ripple. Figure 31 illustrates the basic supply-

bypassing configuration for the AD5255.

GND

AD5255

10μF

0.1μF

04555-0-031

Figure 31. Power Supply Bypassing

RDAC STRUCTURE

The patent pending RDAC contains a string of equal resistor

segments, with an array of analog switches. The switches act

as the wiper connection.

The AD5255 has two RDACs with 512 connection points

allowing it to provide better than 0.2% set-ability resolution.

The AD5255 also contains a third RDAC with 128-step

resolution.

Figure 32 shows an equivalent structure of the connections

between the two terminals that make up one channel of the

RDAC. The SWB switch is always on, while one of the switches,

SW(0) to SW(2N − 1), may or may not be on at any given time

depending on the resistance position decoded from the data bits

in the RDAC register.

Since the switches are nonideal, there is a 100 Ω wiper resis-

tance, RW. Wiper resistance is a function of supply voltage and

temperature; lower supply voltages and higher temperatures

result in higher wiper resistances. Consideration of wiper

resistance dynamics is important in applications in which

accurate prediction of output resistance is required.

04555-0-032

RDAC

WIPER

AND

DECODER

DIGITAL

CIRCUITRY

OMITTED FOR

CLARITY

= R

SW(0)

SW(1)

SW(2

–1)

SW(2

–2)

Figure 32. Equivalent RDAC Structure

CALCULATING THE PROGRAMMABLE RESISTANCE

The nominal resistance of the RDAC between the A and B

terminals is available in 25 kΩ or 250 kΩ. The final two or

three digits of the part number determine the nominal

resistance value, for example, 25 kΩ = 25 and 250 kΩ = 250.

The following discussion describes the calculation of resistance

RWB(D) at different codes of a 25 kΩ part for RDAC0. The 9-bit

data-word in the RDAC latch is decoded to select one of the 512

possible settings.

The first wiper connection starts at the B terminal for data 0x000.

RWB(0) is 100 Ω of the wiper resistance and it is independent of

the full-scale resistance. The second connection is the first tap

point where RWB(1) becomes 48.8 Ω + 100 = 148.8 Ω for data

0x001. The third connection is the next tap point representing

RWB(2) = 97.6 + 100 = 197.6 Ω for data 0x002, and so on. Each

LSB data-value increase moves the wiper up the resistor ladder

until the last tap point is reached at RWB(511) = 25051 Ω.

See Figure 32 for a simplified diagram of the equivalent

RDAC circuit.

These general equations determine the programmed output

resistance between W and B.

AD5255

Rev. A | Page 18 of 20

For RDAC0 and RDAC1:

()

WB RR

DR +×= 512 (1)

For RDAC2:

()

WB RR

DR +×= 128 (2)

where D is the decimal equivalent of the data contained in the

RDAC register, and RW is the wiper resistance.

The output resistance values in Tabl e 1 1 are set for the given

RDAC latch codes with VDD = 5 V, which applies to RAB = 25 kΩ

digital potentiometers.

Table 11. RWB at Selected Codes for RWB_FS = 25 kΩ

D (Dec) RWB(D) (Ω) Output State

511 25051 Full scale

256 12600 Midscale

1 148.8 1 LSB

0 100 Zero scale (wiper contact resistance)

Note that in the zero-scale condition, a finite wiper resistance of

100 Ω is present. To avoid degradation or possible destruction

of the internal switches, care should be taken to limit the current

flow between W and B to no more than 20 mA intermittently

or 2 mA continuously.

Channel-to-channel RWB matching is better than 0.1%. The

change in RWB with temperature has a 35 ppm/°C temperature

coefficient.

Like the mechanical potentiometer that the RDAC replaces, the

AD5255 parts are totally symmetrical. The resistance between

the W wiper and the A terminal also produces a digitally

controlled complementary resistance, RWA . When RWA is used,

the B terminal can be floating or tied to the wiper. Setting the

resistance value for RWA starts at a maximum value of resistance

and decreases as the data loaded in the latch is increased in

value. The general transfer equations for this operation are as

follows.

For RDAC0 and RDAC1:

()

WB RR

DR +×

−

=512

512 (3)

For RDAC2:

()

WB RR

DR +×

−

=128

128 (4)

For example, the following RDAC latch codes set the

corresponding output resistance values, which apply

to RAB = 25 kΩ digital potentiometers.

Table 12. RWA(D) at Selected Codes for RAB = 25 kΩ

D (DEC) RWA(D) (Ω) Output State

511 148.8 Full scale

256 12600 Midscale

1 25051 1 LSB

0 25100 Zero scale

The typical distribution of RAB from channel-to-channel is

±0.1% within the same package. Device-to-device matching

is process lot-dependent, with a worst-case variation of ±15%.

RAB temperature coefficient is 35 ppm/°C.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer can be configured to generate an

output voltage at the wiper terminal that is proportional to the

input voltages applied to the A and B terminals. Connecting the

A terminal to 5 V and the B terminal to ground produces an

output voltage at the wiper that can vary between 0 V to 5 V.

Each LSB of voltage is equal to the voltage applied across the

A and B terminals divided by the 2N position resolution of the

potentiometer divider.

Since the AD5255 can operate from dual supplies, the general

equations defining the output voltage at VW with respect to

ground for any given input voltages applied to the A and B

terminals are as follows.

For RDAC0 and RDAC1:

()

WVV

DV +×= 512 (5)

For RDAC2:

()

WVV

DV +×= 128 (6)

Equation 5 assumes that VW is buffered; therefore, the effect of

wiper resistance is nulled. Operation of the digital potentiometer

in the divider mode results in more accurate operation over

temperature. In this mode, the output voltage is dependent

on the ratio of the internal resistors, not on the absolute value;

therefore, the drift improves to 15 ppm/°C. There is no voltage

polarity restriction between the A, B, and W terminals as long

as the terminal voltage (VTERM) stays within VSS < VTERM < VDD.

AD5255

Rev. A | Page 19 of 20

APPLICATIONS

LASER DIODE DRIVER (LDD) CALIBRATION

The AD5255 can be used with any laser diode driver. Its high

resolution, compact footprint, and superior temperature drift

characteristics make it ideal for optical parameter setting.

The ADN2841 is a 2.7 Gbps laser diode driver that uses a

unique control algorithm to manage both the laser average

power and extinction ratio after initial factory calibration.

It stabilizes the laser data transmission by continuously

monitoring its optical power and by correcting the variations

caused by temperature and the laser degradation over time.

In the ADN2841, the IMPD monitors the laser diode current.

Through its dual-loop power and extinction ratio control,

calibrated by the AD5255, the internal driver controls the

bias current IBIAS and consequently the average power. It also

regulates the modulation current, IMODP, by changing the

modulation current linearly with slope efficiency.

Any changes in the laser threshold current or slope efficiency

are, therefore, compensated. As a result, this optical supervisory

system minimizes the laser characterization efforts, enabling

designers to apply comparable lasers from multiple sources.

AD5255

ADN2841

SDA

SCL

PSET

ERSET

ASET

04555-0-033

Figure 33. Optical Supervisory System

AD5255

Rev. A | Page 20 of 20

OUTLINE DIMENSIONS

24 13

121

6.40 BSC

4.50

4.40

4.30

PIN 1

7.90

7.80

7.70

0.15

0.05

0.30

0.19

0.65

BSC 1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AD

Figure 34. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature

Range Package Description Package Option

Ordering

Quantity RAB (kΩ)

AD5255BRU25 −40°C to +85°C Thin Shrink Small Outline Package RU-24 62 25

AD5255BRUZ251−40°C to +85°C Thin Shrink Small Outline Package RU-24 62 25

AD5255BRU25-RL7 −40°C to +85°C Thin Shrink Small Outline Package RU-24 1,000 25

AD5255BRU250 −40°C to +85°C Thin Shrink Small Outline Package RU-24 62 250

AD5255BRUZ2501−40°C to +85°C Thin Shrink Small Outline Package RU-24 62 250

AD5255BRU250-RL7 −40°C to +85°C Thin Shrink Small Outline Package RU-24 1,000 250

1 Z = Pb-free part.

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent

Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D04555–0–11/05(A)