Data Sheet Rev.1.1 24.05.2011 2048MB DDR3 - SDRAM UDIMM 240 Pin UDIMM Features: SGU02G64A1BD1MT-xxR 2GByte in FBGA Technology RoHS compliant Options: Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC Module Density 2048MB with 8 dies and 1 rank Standard Grade Grade W (TA) (TC) (TA) (TC) 0C to 70C 0C to 85C -40C to 85C -40C to 95C *) The refresh rate has to be doubled when 85C<TC<95C Environmental Requirements: Operating temperature (ambient) Standard Grade 0C to 70C Grade W -40C to 85C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55C to 100C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50C 240-pin 64-bit DDR3 unbuffered Dual-In-Line Double Data Rate Synchronous DRAM module Module organization: single rank 256M x 64 VDD = 1.5V 0.075V, VDDQ 1.5V 0.075V 1.5V I/O ( SSTL_15 compatible) Fly-by-bus with termination for C/A & CLK bus Serial presence-detect (SPD) EEPROM Gold-contact pads This module is fully pin and functional compatible to the JEDEC PC3-10600 spec. and JEDEC- Standard MO-268. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR3 - SDRAM component Micron MT41J256M8HX-15E DIE-Rev.D 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package 8-bit prefetch architecture Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type. On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh. Self Refresh and Power Down Modes. ZQ Calibration for output driver and ODT. System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Figure: mechanical dimensions 1 1 if no tolerances specified 0.15mm Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 14 Data Sheet Rev.1.1 24.05.2011 This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module (UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving "power-down" mode. All inputs and all full drive-strength outputs are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM 2 using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module's organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR3 SDRAMs used Row Addr. Device Bank Addr. Col. Addr. Refresh Module Bank Select 256M x 64bit 8 x 256M x 8bit (2048Mbit) 15 BA0, BA1, BA2 10 8k S0# Module Dimensions in mm 133.35 (long) x 30(high) x 2.70[max] (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SGU02G64A1BD1MT-BB[W]R 2048 MB 8.5 GB/s 1.87ns/1066MT/s 7-7-7 SGU02G64A1BD1MT-CC[W]R 2048 MB 10.6 GB/s 1.5ns/1333MT/s 9-9-9 Pin Name A0-9, A11 - A14 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0, BA1, BA2 Bank Address Inputs DQ0 - DQ63 Data Input / Output DM0-DM7 Input Data Mask RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0 Clock Enable CK0 Clock Inputs, positive line CK0# Clock Inputs, negative line DQS0 - DQS7 Data Strobe, positive line DQS0# - DQS7# Data Strobe, negative line (only used when differential data strobe mode is enabled) S0#, S1# Chip Select Event# Temperature event: The EVENT# pin is asserted by the temperature sensor when critical Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 14 Data Sheet Rev.1.1 VDD Supply Voltage (1.5V 0.075V) VREFDQ Reference voltage: DQ, DM (VDD/2) VREFCA Reference voltage: Control, command, and address (VDD/2) VSS Ground VTT Termination voltage: Used for control, command, and address (VDD/2). VDDSPD Serial EEPROM Positive Power Supply SCL Serial Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 - SA2 Presence Detect Address Inputs ODT0 On-Die Termination NC No Connection 24.05.2011 Pin Configuration Frontside PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol VREFDQ VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS PIN 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Symbol NC CKE0 VDD BA2 NC(Err_Out#) VDD A11 A7 VDD A5 A4 VDD A2 VDD CK1 CK1# VDD VDD VREFCA NC(Par_In) VDD A10/ AP BA0 VDD WE# CAS# PIN 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VDD NC(S1#) NC(RSVD/ODT1) VDD NC(S2#) VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 PIN 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Signals in brackets (...) may be connected at the DIMM socket, but are not used on the DIMM Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 14 Data Sheet Rev.1.1 24.05.2011 Backside PIN 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Symbol VSS DQ4 DQ5 VSS DM0/DQS9 NC(DQS9#) VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 NC(DQS10#) VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 NC(DQS11#) VSS DQ22 PIN 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 NC(DQS12#) VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8/DQS17 NC(DQS17#) VSS CB6 CB7 VSS NC(TEST) NC(RESET#) PIN 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 Symbol NC(CKE1) VDD NC(A15) A14 VDD A12/BC# A9 VDD A8 A6 VDD A3 A1 VDD VDD CK0 CK0# VDD NC(EVENT#) A0 VDD BA1 VDD RAS# S0# VDD PIN 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 Symbol ODT0 A13 VDD NC(S3#) VSS DQ36 DQ37 VSS DM4/DQS13 NC(DQS13#) VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 NC(DQS14#) VSS DQ46 DQ47 VSS DQ52 DQ53 VSS PIN 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol DM6/DQS15 NC(DQS15#) VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC(DQS16#) VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT Signals in brackets (...) may be connected at the DIMM socket, but are not used on the DIMM Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 14 Data Sheet Rev.1.1 24.05.2011 FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM UDIMM, 1 RANK AND 8 COMPONENTS S0 DQS4 DQS4 DM4 DQS0 DQS0 DM0 DM DQ0 DQ1 DQ2 I/O 0 I/O 1 I/O 2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D0 ZQ I/O 0 I/O 1 I/O 2 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 I/O 0 I/O 1 I/O 2 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 I/O 0 I/O 1 I/O 2 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 I/O 0 I/O 1 I/O 2 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DQS5 DQS5 DM5 DQS1 DQS1 DM1 DM DQ8 DQ9 DQ10 I/O 0 I/O 1 I/O 2 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D1 ZQ CS DQS DQS D5 ZQ DQS6 DQS6 DM6 DQS2 DQS2 DM2 DM DQ16 DQ17 DQ18 I/O 0 I/O 1 I/O 2 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D2 ZQ CS DQS DQS D6 ZQ DQS7 DQS7 DM7 DQS3 DQS3 DM3 DM BA0-BA2 A0-A14 RAS CAS WE ODT0 CKE0 CK0 CK0 RESET DQ32 DQ33 DQ34 DQ24 DQ25 DQ26 I/O 0 I/O 1 I/O 2 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D3 ZQ BA0-BA2: SDRAM D0-D7 A0-A14: SDRAM D0-D7 RAS: SDRAM D0-D7 CAS: SDRAM D0-D7 WE: SDRAM D0-D7 ODT: SDRAM D0-D7 CKE: SDRAM D0-D7 CK: SDRAM D0-D7 CK: SDRAM D0-D7 RESET: SDRAM D0-D7 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen DM DQS DQS VDDSPD SPD VDD/VDDQ D0-D7 VREFDQ D0-D7 VREFCA D0-D7 VSS D0-D7 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 CS DQS DQS D7 ZQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of the JEDED document. 5. For each DRAM, a unique ZQ resistor is connected to GND. The ZQ resistor is 2401%. 6. Refer to associated figure for SPD details. www.swissbit.com eMail: info@swissbit.com Page 5 of 14 Data Sheet Rev.1.1 24.05.2011 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VDDL VIN, VOUT Any input 0V VIN VDD, VREF pin 0V VIN 0.95V (All other pins not under test = 0V) MIN -0.4 -0.4 -0.4 -0.4 MAX 1.975 1.975 1.975 1.975 II UNITS V V V V A Command/Address -16 16 IOZ -16 -2 -5 16 2 5 A IVREF -8 8 A RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ's and ODT are disabled; 0V VOUT VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL MIN VDD 1.425 VDDQ 1.425 VDDL 1.425 VREF 0.49 x VDDQ VTT 0.49 x VDDQ-20mV VIH (DC) VREF + 0.1 VIL (DC) -0.3 NOM 1.5 1.5 1.5 0.50 x VDDQ 0.50 x VDDQ MAX 1.575 1.575 1.575 0.51x VDDQ 0.51x VDDQ+20mV VDDQ + 0.3 VREF - 0.1 UNITS V V V V V V V AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.175 - MAX VREF - 0.175 UNITS V V CAPACITANCE At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 6 of 14 Data Sheet Rev.1.1 24.05.2011 IDD Specifications and Conditions (0C TCASE + 85C, VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W Fast Exit PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit Address bus inputs are not changing; DQ's are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ's are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle ACTIVE POWER-DOWN CURRENT: All device banks open; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ's are floating at VREF (always fast exit) ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Symbol max. Unit 10600-999 8500-777 IDD0 680 600 mA IDD1 800 760 mA IDD2P 240 200 mA 96 96 IDD2Q 280 240 mA IDD2N 296 256 mA IDD3P 280 240 mA IDD3N 320 280 mA IDD4R 1280 1120 mA www.swissbit.com eMail: info@swissbit.com Page 7 of 14 Data Sheet Parameter & Test Condition OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE 0.2V; All other Control and Address bus inputs are floating at VREF; DQ's are floating at VREF OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Rev.1.1 Symbol max. 24.05.2011 Unit 10600-999 8500-777 IDD4W 1320 1160 mA IDD5 1600 1520 mA IDD6 96 96 mA IDD7 3080 2680 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 10600-999 8500-777 9 7 CL (IDD) 13.5 13.125 tRCD (IDD) 49.5 50.625 tRC (IDD) 6 7.5 tRRD (IDD) 1.5 1.87 tCK (IDD) 36 37.5 tRAS MIN (IDD) 70'200 70'200 tRAS MAX (IDD) 13.5 13.125 tRP (IDD) 160 160 tRFC (IDD) Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Unit tCK ns ns ns ns ns ns ns ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 8 of 14 Data Sheet Rev.1.1 24.05.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0C TCASE, + 85C, VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) AC CHARACTERISTICS PARAMETER Clock cycle time CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 CK high-level width CK low-level width Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS SYMBOL tCK (10) tCK (9) tCK (8) tCK (7) tCK (6) tCK (5) tCH tCL tHZ tLZ 10600-999 MIN MAX 1.5 <1.875 1.5 <1.875 1.875 <2.5 1.875 <2.5 2.5 3.3 8500-777 MIN MAX 1.875 <2.5 2.5 3.3 0.47 0.47 0.53 0.53 0.25 0.47 0.47 0.53 0.53 0.3 Unit ns ns ns ns ns ns tCK tCK ns -0.5 0.25 -0.6 0.3 ns tDS(Base) 30 25 ps DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS VREF=1V/ns tDH(Base) 65 100 ps tDS1V 180 200 ps DQ and DM input hold time relative to DQS VREF=1V/ns DQ and DM input pulse width ( for each input ) DQS, DQS# to DQ skew, per access DQ-DQS hold, DQS to first DQ to go non-valid, per access DQS input high pulse width DQS input low pulse width DQS, DQS# rising to/from CK, CK# DQS, DQS# rising to/from CK, CK# when DLL disabled DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time DQS read preamble DQS read postamble DQS write preamble DQS write postamble Positive DQS latching edge to associated clock edge Address and control input pulse width ( for each input ) CTRL, CMD, Addr setup to CK, CK# CTRL, CMD, Addr setup to CK, CK# VREF @ 1V/ns tDH1V 165 200 ps tDIPW 0.4 0.49 ns 1 2 125 tDQSQ 0.38 tQH 150 0.38 ps tCK (AVG) tDQSH tDQSL tDQSCK 0.45 0.45 -255 0.55 0.55 +255 0.45 0.45 -300 0.55 0.55 300 tCK tCK ps tDQSCK 1 10 1 10 ns DLL_DIS tDSS 0.2 0.2 tCK tDSH 0.2 0.2 tCK tRPRE tRPST tWPRE tWPST tDQSS 0.9 0.3 0.9 0.3 - 0.25 Note1 Note2 + 0.25 0.9 0.3 0.9 0.3 - 0.25 Note1 Note2 + 0.25 tCK tCK tCK tCK tCK tIPW 620 780 ps tIS(Base) 65 125 ps tIS(1V) 240 300 ps The maximum preamble is bound by tLZDQS (MAX) The maximum postamble is bound by tHZDQS (MAX) Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 9 of 14 Data Sheet Rev.1.1 24.05.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0C TCASE + 85C ; VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) AC CHARACTERISTICS PARAMETER SYMBOL CTRL, CMD, Addr hold to CK, tIH(Base) CK# CTRL, CMD, Addr hold to CK, tIH(1V) CK# VREF @ 1V/ns CAS# to CAS# command delay tCCD ACTIVE to ACTIVE (same bank) tRC command period ACTIVE bank a to ACTIVE bank tRRD b command ACTIVE to READ or WRITE tRCD delay Four bank 1K Page size tFAW Activate period 2K Page size ACTIVE to PRECHARGE tRAS command Internal READ to precharge tRTP command delay Write recovery time tWR Auto precharge write recovery + tDAL precharge time Internal WRITE to READ tWTR command delay PRECHARGE command period tRP LOAD MODE command cycle tMRD time REFRESH to ACTIVE or REFRESH to REFRESH tRFC command interval Average periodic refresh interval 0 C TCASE 85C 85 C < TCASE 95C RTT turn-on from ODTL on reference RTT turn-on from ODTL off reference Asynchronous RTT turn-on delay (power Down with DLL off) Asynchronous RTT turn-off delay (power Down with DLL off) RTT dynamic change skew Exit self refresh to commands not requiring a locked DLL Write levelling setup from rising CK, CK# crossing to rising DQS, DQS# crossing Write levelling setup from rising DQS, DQS# crossing to rising CK, CK# crossing First DQS, DQS# rising edge DQS, DQS# delay Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen 10600-999 MIN MAX 8500-777 MIN MAX 140 200 ps 240 300 ps 4 4 tCK 49.5 50.625 ns 6 7.5 ns 13.5 13.125 ns 30 45 37.5 50 ns 36 70'200 37.5 70'200 Unit ns 7.5 7.5 ns 15 15 tWR + tRP/tCK ns 7.5 7.5 ns 15 13.125 ns 4 4 tCK tWR + tRP/tCK 160 70'200 160 ns 70'200 tREFI 7.8 7.8 tREFI (IT) 3.9 3.9 ns s tAON -250 250 -300 300 ps tAOF 0.3 0.7 0.3 0.7 tCK tAONPD 1 9 1 9 ns tAOFPD 1 9 1 9 ns tADC 0.3 0.7 0.3 0.7 tCK tXS 120 120 ns tWLS 195 245 ps tWLH 195 245 ps tWLMRD tWLDQSEN 40 25 40 25 tCK tCK Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 10 of 14 Data Sheet Rev.1.1 24.05.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0C TCASE + 85C ; VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) AC CHARACTERISTICS PARAMETER Exit reset from CKE HIGH to a valid command Begin power supply ramp to power supplies stable RESET# LOW to power supplies stable RESET# LOW to I/O and RTT High-Z Exit precharge power-down to any non-READ command CKE minimum high/low time 10600-999 MIN MAX 120 8500-777 MIN MAX 120 Unit ns tVDDPR 200 200 ms tRPS 200 200 ms tIOz 20 20 ns SYMBOL tXPR tXP 6 7.5 ns tCKE 5.625 5.625 tCK Serial Presence-Detect EEPROM SCL SDA WP/ EVENT R2 0 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen SA0 SA1 SA2 SA0 SA1 SA2 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 11 of 14 Data Sheet Rev.1.1 24.05.2011 SERIAL PRESENCE-DETECT MATRIX Byte Byte Description 10600-999 8500-777 0 CRC RANGE, EEPROM BYTES, BYTES USED 0x92 1 SPD REVISON 0x10 2 DRAM DEVICE TYPE 0x0B 3 MODULE TYPE (FORM FACTOR) 0x02 4 SDRAM DEVICE DENSITY & BANKS 0x03 5 SDRAM DEVICE ROW & COLUMN COUNT 0x19 6 BYTE 6 RESERVED 0x00 7 MODULE RANKS & DEVICE DQ COUNT 0x01 8 ECC TAG & MODULE MEMORY BUS WIDTH 0x03 9 FINE TIMEBASE DIVIDEND/DIVISOR 0x52 10 MEDIUM TIMEBASE DIVIDEND 0x01 11 MEDIUM TIMEBASE DIVISOR 0x08 12 MIN SDRAM CYCLE TIME (tCK MIN) 13 BYTE 13 RESERVED 14 CAS LATENCIES SUPPORTED (CL4 => CL11) 15 CAS LATENCIES SUPPORTED (CL12 => CL18) 16 MIN CAS LATENCY TIME (tAA MIN) 17 MIN WRITE RECOVERY TIME (tWR MIN) 18 MIN RAS# TO CAS# DELAY (tRCD MIN) 0x69 0x69 19 MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN) 0x30 0x3C 20 MIN ROW PRECHARGE DELAY (tRP MIN) 0x69 0x69 21 UPPER NIBBLE FOR tRAS & tRC 22 MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN) 0x20 0x2C 23 MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN) 0x89 0x95 24 MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB 0x00 25 MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB 0x05 26 MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN) 0x3C 27 MIN INTERNAL READ TO PRECHARGE CMD DELAY (tRTP MIN) 0x3C 28 MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB 0x00 0x01 29 MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB 0xF0 0x2C 30 SDRAM DEVICE OUTPUT DRIVERS SUPPORTED 0x82 31 SDRAM DEVICE THERMAL & REFRESH OPTIONS 0x05 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen 0x0C 0x0F 0x00 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 0x7E 0x1E 0x00 0x69 0x69 0x78 0x11 www.swissbit.com eMail: info@swissbit.com Page 12 of 14 Data Sheet Byte 32-59 Rev.1.1 Byte Description 10600-999 24.05.2011 8500-777 BYTES 32-59 RESERVED 0x00 60 MODULE HEIGHT (NOMINAL) 0x0F 61 MODULE THICKNESS (MAX) 0x01 62 REFERENCE RAW CARD ID 0x00 63 ADDRESS MAPPING EDGE CONECTOR TO DRAM 0x00 BYTES 64-116 RESEVED 0x00 117 MODULE MFR ID (LSB) 0x83 118 MODULE MFR ID (MSB) 0xDA 119 MODULE MFR LOCATION ID 0x01 (Switzerland) 0x02 (Germany) 0x03 (USA) 120 MODULE MFR YEAR X 121 MODULE MFR WEEK X 122-125 MODULE SERIAL NUMBER X 126-127 CRC 128-145 MODULE PART NUMBER 64-116 0x8BB7 0x281F "SGU02G64A1BD1MT-xx" 146 MODULE DIE REV X 147 MODULE PCB REV X 148 DRAM DEVICE MFR ID (LSB) 0x80 149 DRAM DEVICE MFR (MSB) 0x2C 150-175 MFR RESERVED BYTES 150-175 0x00 176-255 CUSTOMER RESERVED BYTES 176-255 0xFF Part Number Code S G U 02G 64 A1 B D 1 MT 1 2 3 4 5 6 7 8 9 10 - CC * R 11 12 13 *RoHs compl. DDR3-1333MT/s Swissbit AG SDRAM DDR3 240 Pin DIMM 1.5V Depth (2GB) Width PCB-Type (B63URCA 0.71) Chip Vendor (Micron) 1 Module Rank Chip Rev. D Chip organisation x8 * optional / additional information Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 13 of 14 Data Sheet Rev.1.1 24.05.2011 Locations Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D - 12681 Berlin Germany Phone: +49 (0)30 93 69 54 - 0 Fax: +49 (0)30 93 69 54 - 55 _____________________________ Swissbit NA, Inc. 14 Willett Avenue, Suite 301A Port Chester, NY 10573 USA Phone: +1 914 935 1400 Fax: +1 914 935 9865 _____________________________ Swissbit NA, Inc. 3913 Todd Lane, Suite - 307 Austin, TX 78744 USA Phone: +1 512 302 9001 Fax: +1 512 302 4808 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 14 of 14