SGUO2G64A1BD1MT-BBR - Swissbit

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 1

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

2048MB DDR3 – SDRAM UDIMM

240 Pin UDIMM

SGU02G64A1BD1MT-xxR

2GByte in FBGA Technology

RoHS compliant

*) The refresh rate has to be doubled when 85°C<TC<95°C

Environmental Requirements:

 Operating temperature (ambient)

Standard Grade 0°C to 70°C

Grade W -40°C to 85°C

 Operating Humidity

10% to 90% relative humidity, noncondensing

 Operating Pressure

105 to 69 kPa (up to 10000 ft.)

 Storage Temperature

-55°C to 100°C

 Storage Humidity

5% to 95% relative humidity, noncondensing

 Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:

 Data Rate / Latency Marking

DDR3 1066 MT/s CL7 -BB

DDR3 1333 MT/s CL9 -CC

 Module Density

2048MB with 8 dies and 1 rank

Standard Grade (TA) 0°C to 70°C

(TC) 0°C to 85°C

Grade W (TA) -40°C to 85°C

(TC) -40°C to 95°C

Figure: mechanical dimensions1

Features:

 240-pin 64-bit DDR3 unbuffered Dual-In-Line Double Data

Rate Synchronous DRAM module

 Module organization: single rank 256M x 64

 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V

 1.5V I/O ( SSTL_15 compatible)

 Fly-by-bus with termination for C/A & CLK bus

 Serial presence-detect (SPD) EEPROM

 Gold-contact pads

 This module is fully pin and functional compatible to the

JEDEC PC3-10600 spec. and JEDEC- Standard MO-268.

(see www.jedec.org)

 The pcb and all components are manufactured according

to the RoHS compliance specification [EU Directive

2002/95/EC Restriction of Hazardous Substances (RoHS)]

 DDR3 - SDRAM component Micron

MT41J256M8HX-15E DIE-Rev.D

 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package

 8-bit prefetch architecture

 Programmable CAS Latency, CAS Write Latency, Additive

Latency, Burst Length and Burst Type.

 On-Die-Termination (ODT) and Dynamic ODT for improved

signal integrity.

 Refresh. Self Refresh and Power Down Modes.

 ZQ Calibration for output driver and ODT.

 System Level Timing Calibration Support via Write Leveling

and Multi Purpose Register (MPR) Read Pattern.

1if no tolerances specified ± 0.15mm

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module

(UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured

octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed

operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses

to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An

auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst

access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is

providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All

inputs and all full drive-strength outputs are SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM

using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are

utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several

timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Organization

DDR3 SDRAMs used

Row

Addr.

Device Bank

Addr.

Col.

Addr.

Refresh

Module

Bank Select

256M x 64bit

8 x 256M x 8bit (2048Mbit)

15

BA0, BA1, BA2

10

8k

S0#

Module Dimensions

in mm

133.35 (long) x 30(high) x 2.70[max] (thickness)

Timing Parameters

Part Number

Module Density

Transfer Rate

Clock Cycle/Data bit rate

Latency

SGU02G64A1BD1MT-BB[W]R

2048 MB

8.5 GB/s

1.87ns/1066MT/s

7-7-7

SGU02G64A1BD1MT-CC[W]R

2048 MB

10.6 GB/s

1.5ns/1333MT/s

9-9-9

Pin Name

A0-9, A11 – A14

Address Inputs

A10/AP

Address Input / Autoprecharge Bit

BA0, BA1, BA2

Bank Address Inputs

DQ0 – DQ63

Data Input / Output

DM0-DM7

Input Data Mask

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CKE0

Clock Enable

CK0

Clock Inputs, positive line

CK0#

Clock Inputs, negative line

DQS0 - DQS7

Data Strobe, positive line

DQS0# - DQS7#

Data Strobe, negative line (only used when differential data strobe mode is enabled)

S0#, S1#

Chip Select

Event#

Temperature event: The EVENT# pin is asserted by the temperature sensor when critical

Figure 1: Mechanical Dimensions

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 3

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

VDD

Supply Voltage (1.5V± 0.075V)

VREFDQ

Reference voltage: DQ, DM (VDD/2)

VREFCA

Reference voltage: Control, command, and address (VDD/2)

VSS

Ground

VTT

Termination voltage: Used for control, command, and address (VDD/2).

VDDSPD

Serial EEPROM Positive Power Supply

SCL

Serial Clock for Presence Detect

SDA

Serial Data Out for Presence Detect

SA0 – SA2

Presence Detect Address Inputs

ODT0

On-Die Termination

NC

No Connection

Pin Configuration

Frontside

Symbol

1

VREFDQ

27

DQ18

49

NC

75

VDD

101

VSS

2

VSS

28

DQ19

50

CKE0

76

NC(S1#)

102

DQS6#

3

DQ0

29

VSS

51

VDD

77

NC(RSVD/ODT1)

103

DQS6

4

DQ1

30

DQ24

52

BA2

78

VDD

104

VSS

5

VSS

31

DQ25

53

NC(Err_Out#)

79

NC(S2#)

105

DQ50

6

DQS0#

32

VSS

54

VDD

80

VSS

106

DQ51

7

DQS0

33

DQS3#

55

A11

81

DQ32

107

VSS

8

VSS

34

DQS3

56

A7

82

DQ33

108

DQ56

9

DQ2

35

VSS

57

VDD

83

VSS

109

DQ57

10

DQ3

36

DQ26

58

A5

84

DQS4#

110

VSS

11

VSS

37

DQ27

59

A4

85

DQS4

111

DQS7#

12

DQ8

38

VSS

60

VDD

86

VSS

112

DQS7

13

DQ9

39

CB0

61

A2

87

DQ34

113

VSS

14

VSS

40

CB1

62

VDD

88

DQ35

114

DQ58

15

DQS1#

41

VSS

63

CK1

89

VSS

115

DQ59

16

DQS1

42

DQS8#

64

CK1#

90

DQ40

116

VSS

17

VSS

43

DQS8

65

VDD

91

DQ41

117

SA0

18

DQ10

44

VSS

66

VDD

92

VSS

118

SCL

19

DQ11

45

CB2

67

VREFCA

93

DQS5#

119

SA2

20

VSS

46

CB3

68

NC(Par_In)

94

DQS5

120

VTT

21

DQ16

47

VSS

69

VDD

95

VSS

22

DQ17

48

NC

70

A10/ AP

96

DQ42

23

VSS

71

BA0

97

DQ43

24

DQS2#

72

VDD

98

VSS

25

DQS2

73

WE#

99

DQ48

26

VSS

74

CAS#

100

DQ49

Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 4

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

Backside

Symbol

121

VSS

147

DQ23

169

NC(CKE1)

195

ODT0

221

DM6/DQS15

122

DQ4

148

VSS

170

VDD

196

A13

222

NC(DQS15#)

123

DQ5

149

DQ28

171

NC(A15)

197

VDD

223

VSS

124

VSS

150

DQ29

172

A14

198

NC(S3#)

224

DQ54

125

DM0/DQS9

151

VSS

173

VDD

199

VSS

225

DQ55

126

NC(DQS9#)

152

DM3/DQS12

174

A12/BC#

200

DQ36

226

VSS

127

VSS

153

NC(DQS12#)

175

A9

201

DQ37

227

DQ60

128

DQ6

154

VSS

176

VDD

202

VSS

228

DQ61

129

DQ7

155

DQ30

177

A8

203

DM4/DQS13

229

VSS

130

VSS

156

DQ31

178

A6

204

NC(DQS13#)

230

DM7/DQS16

131

DQ12

157

VSS

179

VDD

205

VSS

231

NC(DQS16#)

132

DQ13

158

CB4

180

A3

206

DQ38

232

VSS

133

VSS

159

CB5

181

A1

207

DQ39

233

DQ62

134

DM1/DQS10

160

VSS

182

VDD

208

VSS

234

DQ63

135

NC(DQS10#)

161

DM8/DQS17

183

VDD

209

DQ44

235

VSS

136

VSS

162

NC(DQS17#)

184

CK0

210

DQ45

236

VDDSPD

137

DQ14

163

VSS

185

CK0#

211

VSS

237

SA1

138

DQ15

164

CB6

186

VDD

212

DM5/DQS14

238

SDA

139

VSS

165

CB7

187

NC(EVENT#)

213

NC(DQS14#)

239

VSS

140

DQ20

166

VSS

188

A0

214

VSS

240

VTT

141

DQ21

167

NC(TEST)

189

VDD

215

DQ46

142

VSS

168

NC(RESET#)

190

BA1

216

DQ47

143

DM2/DQS11

191

VDD

217

VSS

144

NC(DQS11#)

192

RAS#

218

DQ52

145

VSS

193

S0#

219

DQ53

146

DQ22

194

VDD

220

VSS

Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 5

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM UDIMM,

1 RANK AND 8 COMPONENTS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D0

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D1

DQSCS

DQ0

DQ1

DQ2

DQ3

DQ5

DQ4

DQ6

DQ7

S0

DQS0

DM0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ13

DQ12

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D2

DQSCS

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ21

DQ20

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D3

DQSCS

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D4

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D5

DQSCS

DQ32

DQ33

DQ34

DQ35

DQ37

DQ36

DQ38

DQ39

DQS4

DM4

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ45

DQ44

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D6

DQSCS

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ53

DQ52

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D7

DQSCS

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ61

DQ60

DQ62

DQ63

VDDSPD SPD

VDD/VDDQ D0-D7

VREFDQ

VREFCA

D0-D7

VSS

BA0-BA2 BA0-BA2: SDRAM D0-D7

A0-A14 A0-A14: SDRAM D0-D7

RAS RAS: SDRAM D0-D7

CAS CAS: SDRAM D0-D7

WE WE: SDRAM D0-D7

ODT0 ODT: SDRAM D0-D7

CKE0 CKE: SDRAM D0-D7

CK0 CK: SDRAM D0-D7

RESET RESET: SDRAM D0-D7

Notes:

1. DQ-to-I/O wiring is shown as recommended but may

be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be

maintained as shown.

3. DQ, DM, DQS/DQS resistors: Refer to associated

topology diagram.

4. Refer to the appropriate clock wiring topology under

the DIMM wiring details section of the JEDED document.

5. For each DRAM, a unique ZQ resistor is connected to

GND. The ZQ resistor is 240Ω±1%.

6. Refer to associated figure for SPD details.

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 6

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

MAXIMUM ELECTRICAL DC CHARACTERISTICS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Supply Voltage

VDD

-0.4

1.975

V

I/O Supply Voltage

VDDQ

-0.4

1.975

V

VDDL Supply Voltage

VDDL

-0.4

1.975

V

Voltage on any pin relative to VSS

VIN, VOUT

-0.4

1.975

V

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V

(All other pins not under test = 0V)

II

µA

Command/Address

RAS#, CAS#, WE#, S#, CKE

-16

16

CK, CK#

-16

16

DM

-2

2

OUTPUT LEAKAGE CURRENT

(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

-5

5

µA

DQ, DQS, DQS#

VREF LEAKAGE CURRENT ; VREF is on a valid level

IVREF

-8

8

µA

DC OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

NOM

MAX

UNITS

Supply Voltage

VDD

1.425

1.5

1.575

V

I/O Supply Voltage

VDDQ

1.425

1.5

1.575

V

VDDL Supply Voltage

VDDL

1.425

1.5

1.575

V

I/O Reference Voltage

VREF

0.49 x VDDQ

0.50 x VDDQ

0.51x VDDQ

V

I/O Termination Voltage (system)

VTT

0.49 x VDDQ-20mV

0.50 x VDDQ

0.51x VDDQ+20mV

V

Input High (Logic 1) Voltage

VIH (DC)

VREF + 0.1

VDDQ + 0.3

V

Input Low (Logic 0) Voltage

VIL (DC)

-0.3

VREF – 0.1

V

AC INPUT OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Input High (Logic 1) Voltage

VIH (AC)

VREF + 0.175

-

V

Input Low (Logic 0) Voltage

VIL (AC)

-

VREF - 0.175

V

CAPACITANCE

At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.

When inductance and delay parameters associated with trace lengths are used in simulations, they are

significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then

render a considerably more accurate result. JEDEC modules are now designed by using simulations to close

timing budgets.

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 7

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

IDD Specifications and Conditions

(0°C ≤ TCASE ≤ + 85°C°, VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

Parameter

& Test Condition

Symbol

max.

Unit

10600-999

8500-777

OPERATING CURRENT *) :

One device bank Active-Precharge;

tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

IDD0

680

600

mA

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between

valid commands; Address inputs changing once every

two clock cycles; Data Pattern is same as IDD4W

IDD1

800

760

mA

PRECHARGE POWER-DOWN

CURRENT:

All device banks idle; Power-down mode;

tCK = tCK (IDD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at VREF

Fast Exit

IDD2P

240

200

mA

Slow Exit

96

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at VREF

IDD2Q

280

240

mA

PRECHARGE STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD2N

296

256

mA

ACTIVE POWER-DOWN CURRENT:

All device banks open; tCK = tCK (IDD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at VREF (always fast exit)

IDD3P

280

240

mA

ACTIVE STANDBY CURRENT:

All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD3N

320

280

mA

OPERATING READ CURRENT:

All device banks open, Continuous burst reads; One

module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

IDD4R

1280

1120

mA

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 8

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

Parameter

& Test Condition

Symbol

max.

Unit

10600-999

8500-777

OPERATING WRITE CURRENT:

All device banks open, Continuous burst writes; One

module rank active; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are changing once every two clock

cycles; DQ inputs changing once per clock cycle

IDD4W

1320

1160

mA

BURST REFRESH CURRENT:

tCK = tCK (IDD); refresh command at every tRFC (IDD)

interval, CKE is HIGH, CS# is HIGH between valid

commands; All other Control and Address bus inputs

are changing once every two clock cycles; DQ inputs

changing once per clock cycle

IDD5

1600

1520

mA

SELF REFRESH CURRENT:

CK and CK# at 0V; CKE ≤ 0.2V; All other Control and

Address bus inputs are floating at VREF; DQ’s are

floating at VREF

IDD6

96

mA

OPERATING CURRENT*) :

Four device bank interleaving READs, IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK

(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are not changing during

DESELECT; DQ inputs changing once per clock cycle

IDD7

3080

2680

mA

*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)

mode.

TIMING VALUES USED FOR IDD MEASUREMENT

IDD MEASUREMENT CONDITIONS

SYMBOL

10600-999

8500-777

Unit

CL (IDD)

9

7

tCK

tRCD (IDD)

13.5

13.125

ns

tRC (IDD)

49.5

50.625

ns

tRRD (IDD)

6

7.5

ns

tCK (IDD)

1.5

1.87

ns

tRAS MIN (IDD)

36

37.5

ns

tRAS MAX (IDD)

70’200

ns

tRP (IDD)

13.5

13.125

ns

tRFC (IDD)

160

ns

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 9

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

(0°C ≤ TCASE, ≤ + 85°C°, VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

10600-999

8500-777

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

Clock cycle time

CL = 10

tCK (10)

1.5

<1.875

-

ns

CL = 9

tCK (9)

1.5

<1.875

-

ns

CL = 8

tCK (8)

1.875

<2.5

-

ns

CL = 7

tCK (7)

1.875

<2.5

1.875

<2.5

ns

CL = 6

tCK (6)

2.5

3.3

2.5

3.3

ns

CL = 5

tCK (5)

ns

CK high-level width

tCH

0.47

0.53

0.47

0.53

tCK

CK low-level width

tCL

0.47

0.53

0.47

0.53

tCK

Data-out high-impedance

window from CK/CK#

tHZ

0.25

0.3

ns

Data-out low-impedance window

from CK/CK#

tLZ

-0.5

0.25

-0.6

0.3

ns

DQ and DM input setup time

relative to DQS

tDS(Base)

30

25

ps

DQ and DM input hold time

relative to DQS

tDH(Base)

65

100

ps

DQ and DM input setup time

relative to DQS VREF=1V/ns

tDS1V

180

200

ps

DQ and DM input hold time

relative to DQS VREF=1V/ns

tDH1V

165

200

ps

DQ and DM input pulse width

( for each input )

tDIPW

0.4

0.49

ns

DQS, DQS# to DQ skew, per

access

tDQSQ

125

150

ps

DQ-DQS hold, DQS to first DQ

to go non-valid, per access

tQH

0.38

tCK

(AVG)

DQS input high pulse width

tDQSH

0.45

0.55

0.45

0.55

tCK

DQS input low pulse width

tDQSL

0.45

0.55

0.45

0.55

tCK

DQS, DQS# rising to/from CK,

CK#

tDQSCK

-255

+255

-300

300

ps

DQS, DQS# rising to/from CK,

CK# when DLL disabled

tDQSCK

DLL_DIS

1

10

1

10

ns

DQS falling edge to CK rising

- setup time

tDSS

0.2

tCK

DQS falling edge from CK rising

- hold time

tDSH

0.2

tCK

DQS read preamble

tRPRE

0.9

Note1

0.9

Note1

tCK

DQS read postamble

tRPST

0.3

Note2

0.3

Note2

tCK

DQS write preamble

tWPRE

0.9

tCK

DQS write postamble

tWPST

0.3

tCK

Positive DQS latching edge to

associated clock edge

tDQSS

- 0.25

+ 0.25

- 0.25

+ 0.25

tCK

Address and control input pulse

width ( for each input )

tIPW

620

780

ps

CTRL, CMD, Addr setup to CK,

CK#

tIS(Base)

65

125

ps

CTRL, CMD, Addr setup to CK,

CK# VREF @ 1V/ns

tIS(1V)

240

300

ps

1 The maximum preamble is bound by tLZDQS (MAX)

2 The maximum postamble is bound by tHZDQS (MAX)

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 10

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

10600-999

8500-777

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

CTRL, CMD, Addr hold to CK,

CK#

tIH(Base)

140

200

ps

CTRL, CMD, Addr hold to CK,

CK# VREF @ 1V/ns

tIH(1V)

240

300

ps

CAS# to CAS# command delay

tCCD

4

tCK

ACTIVE to ACTIVE (same bank)

command period

tRC

49.5

50.625

ns

ACTIVE bank a to ACTIVE bank

b command

tRRD

6

7.5

ns

ACTIVE to READ or WRITE

delay

tRCD

13.5

13.125

ns

Four bank

Activate period

1K Page size

tFAW

30

37.5

ns

2K Page size

45

50

ACTIVE to PRECHARGE

command

tRAS

36

70’200

37.5

70’200

ns

Internal READ to precharge

command delay

tRTP

7.5

ns

Write recovery time

tWR

15

ns

Auto precharge write recovery +

precharge time

tDAL

tWR + tRP/tCK

tWR +

tRP/tCK

ns

Internal WRITE to READ

command delay

tWTR

7.5

ns

PRECHARGE command period

tRP

15

13.125

ns

LOAD MODE command cycle

time

tMRD

4

tCK

REFRESH to ACTIVE or

REFRESH to REFRESH

command interval

tRFC

160

70’200

160

70’200

ns

Average periodic refresh interval

0 °C ≤ TCASE ≤ 85°C

tREFI

7.8

µs

85 °C < TCASE ≤ 95°C

tREFI (IT)

3.9

RTT turn-on from ODTL on

reference

tAON

-250

250

-300

300

ps

RTT turn-on from ODTL off

reference

tAOF

0.3

0.7

0.3

0.7

tCK

Asynchronous RTT turn-on

delay (power Down with DLL off)

tAONPD

1

9

1

9

ns

Asynchronous RTT turn-off

delay (power Down with DLL off)

tAOFPD

1

9

1

9

ns

RTT dynamic change skew

tADC

0.3

0.7

0.3

0.7

tCK

Exit self refresh to commands

not requiring a locked DLL

tXS

120

ns

Write levelling setup from rising

CK, CK# crossing to rising DQS,

DQS# crossing

tWLS

195

245

ps

Write levelling setup from rising

DQS, DQS# crossing to rising

CK, CK# crossing

tWLH

195

245

ps

First DQS, DQS# rising edge

tWLMRD

40

tCK

DQS, DQS# delay

tWLDQSEN

25

tCK

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 11

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

10600-999

8500-777

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

Exit reset from CKE HIGH to a

valid command

tXPR

120

ns

Begin power supply ramp to

power supplies stable

tVDDPR

200

ms

RESET# LOW to power supplies

stable

tRPS

200

ms

RESET# LOW to I/O and RTT

High-Z

tIOz

20

ns

Exit precharge power-down to

any non-READ command

tXP

6

7.5

ns

CKE minimum high/low time

tCKE

5.625

tCK

Serial Presence-Detect EEPROM

SCL SDA

SA2

SA1

SA0

EVENT

WP/

R2

0Ω

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 12

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

SERIAL PRESENCE-DETECT MATRIX

Byte

Byte Description

10600-999

8500-777

0

CRC RANGE, EEPROM BYTES, BYTES USED

0x92

1

SPD REVISON

0x10

2

DRAM DEVICE TYPE

0x0B

3

MODULE TYPE (FORM FACTOR)

0x02

4

SDRAM DEVICE DENSITY & BANKS

0x03

5

SDRAM DEVICE ROW & COLUMN COUNT

0x19

6

BYTE 6 RESERVED

0x00

7

MODULE RANKS & DEVICE DQ COUNT

0x01

8

ECC TAG & MODULE MEMORY BUS WIDTH

0x03

9

FINE TIMEBASE DIVIDEND/DIVISOR

0x52

10

MEDIUM TIMEBASE DIVIDEND

0x01

11

MEDIUM TIMEBASE DIVISOR

0x08

12

MIN SDRAM CYCLE TIME (tCK MIN)

0x0C

0x0F

13

BYTE 13 RESERVED

0x00

14

CAS LATENCIES SUPPORTED (CL4 => CL11)

0x7E

0x1E

15

CAS LATENCIES SUPPORTED (CL12 => CL18)

0x00

16

MIN CAS LATENCY TIME (tAA MIN)

0x69

17

MIN WRITE RECOVERY TIME (tWR MIN)

0x78

18

MIN RAS# TO CAS# DELAY (tRCD MIN)

0x69

19

MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)

0x30

0x3C

20

MIN ROW PRECHARGE DELAY (tRP MIN)

0x69

21

UPPER NIBBLE FOR tRAS & tRC

0x11

22

MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)

0x20

0x2C

23

MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)

0x89

0x95

24

MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB

0x00

25

MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB

0x05

26

MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)

0x3C

27

MIN INTERNAL READ TO PRECHARGE CMD DELAY

(tRTP MIN)

0x3C

28

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB

0x00

0x01

29

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB

0xF0

0x2C

30

SDRAM DEVICE OUTPUT DRIVERS SUPPORTED

0x82

31

SDRAM DEVICE THERMAL & REFRESH OPTIONS

0x05

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 13

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

Byte

Byte Description

10600-999

8500-777

32-59

BYTES 32-59 RESERVED

0x00

60

MODULE HEIGHT (NOMINAL)

0x0F

61

MODULE THICKNESS (MAX)

0x01

62

REFERENCE RAW CARD ID

0x00

63

ADDRESS MAPPING EDGE CONECTOR TO DRAM

0x00

64-116

BYTES 64-116 RESEVED

0x00

117

MODULE MFR ID (LSB)

0x83

118

MODULE MFR ID (MSB)

0xDA

119

MODULE MFR LOCATION ID

0x01 (Switzerland)

0x02 (Germany)

0x03 (USA)

120

MODULE MFR YEAR

X

121

MODULE MFR WEEK

X

122-125

MODULE SERIAL NUMBER

X

126-127

CRC

0x8BB7

0x281F

128-145

MODULE PART NUMBER

"SGU02G64A1BD1MT-xx"

146

MODULE DIE REV

X

147

MODULE PCB REV

X

148

DRAM DEVICE MFR ID (LSB)

0x80

149

DRAM DEVICE MFR (MSB)

0x2C

150-175

MFR RESERVED BYTES 150-175

0x00

176-255

CUSTOMER RESERVED BYTES 176-255

0xFF

Part Number Code

S

G

U

02G

64

A1

B

D

1

MT

-

CC

*

R

1

2

3

4

5

6

7

8

9

10

11

12

13

*RoHs compl.

Swissbit AG

DDR3-1333MT/s

SDRAM DDR3

240 Pin DIMM 1.5V

Chip Vendor (Micron)

Depth (2GB)

1 Module Rank

Width

Chip Rev. D

PCB-Type (B63URCA 0.71)

Chip organisation x8

* optional / additional information

Data Sheet Rev.1.1 24.05.2011

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 14

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

Locations

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Switzerland

Phone: +41 (0)71 913 03 03

Fax: +41 (0)71 913 03 15

_____________________________

Swissbit Germany GmbH

Wolfener Strasse 36

D – 12681 Berlin

Germany

Phone: +49 (0)30 93 69 54 – 0

Fax: +49 (0)30 93 69 54 – 55

_____________________________

Swissbit NA, Inc.

14 Willett Avenue, Suite 301A

Port Chester, NY 10573

USA

Phone: +1 914 935 1400

Fax: +1 914 935 9865

_____________________________

Swissbit NA, Inc.

3913 Todd Lane, Suite – 307

Austin, TX 78744

USA

Phone: +1 512 302 9001

Fax: +1 512 302 4808