© Semiconductor Components Industries, LLC, 2015
June, 2018 − Rev. 26
1Publication Order Number:
CAT25010/D
CAT25010, CAT25020,
CAT25040
EEPROM Serial 1/2/4-Kb SPI
Description
The CAT25010/20/40 are a EEPROM Serial 1/2/4−Kb SPI devices
internally organized as 128x8/256x8/512x8 bits. They feature a
16−byte page write buffer and support the Serial Peripheral Interface
(SPI) protocol. The device is enabled through a Chip Select (CS)
input. In addition, the required bus signals are a clock input (SCK),
data input (SI) and data output (SO) lines. The HOLD input may be
used to pause any serial communication with the CAT25010/20/40
device. These devices feature software and hardware write protection,
including partial as well as full array protection.
Features
•20 MHz (5 V) SPI Compatible
•1.8 V to 5.5 V Supply Voltage Range
•SPI Modes (0,0) & (1,1)
•16−byte Page Write Buffer
•Self−timed Write Cycle
•Hardware and Software Protection
•Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•Industrial and Extended Temperature Range
•PDIP, SOIC, TSSOP 8−Lead and UDFN 8−Pad Packages
•These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SI
SO
CAT25010
CAT25020
CAT25040
SCK
VSS
VCC
CS
WP
HOLD
Figure 1. Functional Symbol
www.onsemi.com
PIN CONFIGURATION
SI
HOLD
VCC
VSS
WP
SO
CS 1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC−8
V SUFFIX
CASE 751BD
SCK
SOIC (V), TSSOP (Y), UDFN (HU4)
TSSOP−8
Y SUFFIX
CASE 948AL
Chip SelectCS
Serial Data OutputSO
Write ProtectWP
GroundVSS
Serial Data InputSI
Serial ClockSCK
FunctionPin Name
PIN FUNCTION
Hold Transmission InputHOLD
Power SupplyVCC
UDFN−8
HU4 SUFFIX
CASE 517AZ
For the location of Pin 1, please consult the
corresponding package drawing.
CAT25010, CAT25020, CAT25040
www.onsemi.com
2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to VCC + 0.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICC Supply Current Read, Write, VCC = 5.0 V,
SO open
10 MHz / −40°C to 85°C 2 mA
5 MHz / −40°C to 125°C 2 mA
ISB1 Standby Current VIN = GND or VCC, CS = VCC,
WP = VCC, VCC = 5.0 V
2mA
ISB2 Standby Current VIN = GND or VCC, CS = VCC,
WP = GND, VCC = 5.0 V
TA = −40°C to +85°C 4 mA
TA = −40°C to +125°C 5 mA
ILInput Leakage Current VIN = GND or VCC −2 2 mA
ILO Output Leakage
Current
CS = VCC,
VOUT = GND or VCC
TA = −40°C to +85°C−1 1 mA
TA = −40°C to +125°C−1 2 mA
VIL Input Low Voltage −0.5 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC + 0.5 V
VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V
VOH1 Output High Voltage VCC > 2.5 V, IOH = −1.6 mA VCC − 0.8 V V
VOL2 Output Low Voltage VCC > 1.8 V, IOL = 150 mA0.2 V
VOH2 Output High Voltage VCC > 1.8 V, IOH = −100 mAVCC − 0.2 V V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN CAPACITANCE (Note 2) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol Test Conditions Min Typ Max Units
COUT Output Capacitance (SO) VOUT = 0 V 8 pF
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
CAT25010, CAT25020, CAT25040
www.onsemi.com
3
Table 5. A.C. CHARACTERISTICS − Mature Product
(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended).) (Notes 4, 8)
Symbol Parameter
VCC = 1.8 V − 5.5 V / −405C to +855C
VCC = 2.5 V − 5.5 V / −405C to +1255C
VCC = 2.5 V − 5.5 V
−405C to +855C
Units
Min Max Min Max
fSCK Clock Frequency DC 5 DC 10 MHz
tSU Data Setup Time 40 20 ns
tHData Hold Time 40 20 ns
tWH SCK High Time 75 40 ns
tWL SCK Low Time 75 40 ns
tLZ HOLD to Output Low Z 50 25 ns
tRI (Note 5) Input Rise Time 2 2 ms
tFI (Note 5) Input Fall Time 2 2 ms
tHD HOLD Setup Time 0 0 ns
tCD HOLD Hold Time 10 10 ns
tVOutput Valid from Clock Low 75 40 ns
tHO Output Hold Time 0 0 ns
tDIS Output Disable Time 50 20 ns
tHZ HOLD to Output High Z 100 25 ns
tCS CS High Time 140 70 ns
tCSS CS Setup Time 30 15 ns
tCSH CS Hold Time 30 15 ns
tCNS CS Inactive Setup Time 20 15 ns
tCNH CS Inactive Hold Time 20 15 ns
tWPS WP Setup Time 10 10 ns
tWPH WP Hold Time 10 10 ns
tWC (Note 7) Write Cycle Time 5 5 ms
Table 6. POWER−UP TIMING (Notes 5, 6)
Symbol Parameter Max Units
tPUR Power−up to Read Operation 1 ms
tPUW Power−up to Write Operation 1 ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
8. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For
previous product revision (Rev. C) the tCSH is defined relative to the negative clock edge (please refer to data sheet Doc. No.
MD−1006 Rev. U)
CAT25010, CAT25020, CAT25040
www.onsemi.com
4
Table 7. A.C. CHARACTERISTICS – New Product (Rev E)
(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended), unless otherwise specified.) (Note 9)
Symbol Parameter
VCC = 1.8 V − 5.5 V
−405C to +855C
VCC = 2.5 V − 5.5 V
−405C to +1255C
VCC = 4.5 V − 5.5 V
−405C to +855C
Units
Min Max Min Max Min Max
fSCK Clock Frequency DC 5 DC 10 DC 20 MHz
tSU Data Setup Time 20 10 5 ns
tHData Hold Time 20 10 5 ns
tWH SCK High Time 75 40 20 ns
tWL SCK Low Time 75 40 20 ns
tLZ HOLD to Output Low Z 50 25 25 ns
tRI (Note 10) Input Rise Time 2 2 2 ms
tFI (Note 10) Input Fall Time 2 2 2 ms
tHD HOLD Setup Time 0 0 0 ns
tCD HOLD Hold Time 10 10 5 ns
tVOutput Valid from Clock Low 70 35 20 ns
tHO Output Hold Time 0 0 0 ns
tDIS Output Disable Time 50 20 20 ns
tHZ HOLD to Output High Z 100 25 25 ns
tCS CS High Time 80 40 20 ns
tCSS CS Setup Time 30 30 15 ns
tCSH CS Hold Time 30 30 20 ns
tCNS CS Inactive Setup Time 20 20 15 ns
tCNH CS Inactive Hold Time 20 20 15 ns
tWPS WP Setup Time 10 10 10 ns
tWPH WP Hold Time 10 10 10 ns
tWC (Note 12) Write Cycle Time 5 5 5 ms
Table 8. POWER−UP TIMING (Notes 10, 11)
Symbol Parameter Min Max Units
tPUR Power−up to Read Operation 0.1 1 ms
tPUW Power−up to Write Operation 0.1 1 ms
9. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF
10.This parameter is tested initially and after a design or process change that affects the parameter.
11. tPUR and tPUW are the delays required from the time VCC is stable at the operating voltage until the specified operation can be initiated.
12.tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
CAT25010, CAT25020, CAT25040
www.onsemi.com
5
Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25010/20/40.
CS: The chip select input pin is used to enable/disable the
CAT25010/20/40. When CS is high, the SO output is
tri−stated (high impedance) and the device is in Standby
Mode (unless an internal write operation is in progress).
Every communication session between host and
CAT25010/20/40 must be preceded by a high to low transition
and concluded with a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25010/20/40, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
to VCC, either directly or through a resistor.
Functional Description
The CAT25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0) and
(1,1). The device contains an 8−bit instruction register. The
instruction set and associated op−codes are listed in Table 9.
Reading data stored in the CAT25010/20/40 is
accomplished by simply providing the READ command and
an address. Writing to the CAT25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits in
a Status Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25010/20/40 will accept any one of the six instruction
op−codes listed in Table 9 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 9. INSTRUCTION SET (Note 13)
Instruction Opcode Operation
WREN 0000 0110 Enable Write Operations
WRDI 0000 0100 Disable Write Operations
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 X011 Read Data from Memory
WRITE 0000 X010 Write Data to Memory
13.X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 2. Synchronous Data Timing
CS
SCK
SI
SO
tCNH
tCSS tWH tWL
tSU
tH
HI−Z
VALID
IN
VALID
OUT
tCSH
tRI
tFI
tVtV
tHO
tCNS
tCS
HI−Z
tDIS
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read−only.
CAT25010, CAT25020, CAT25040
www.onsemi.com
6
Table 10. STATUS REGISTER
7 6 5 4 3 2 1 0
1 1 1 1 BP1 BP0 WEL RDY
Table 11. BLOCK PROTECTION BITS
Status Register Bits
Array Address Protected Protection
BP1 BP0
0 0 None No Protection
0 1 CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF Quarter Array Protection
1 0 CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF Half Array Protection
1 1 CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF Full Array Protection
WRITE OPERATIONS
The CAT25010/20/40 device powers up into a write
disable state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1 bits
from the status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25010/20/40. Care must be taken to
take the CS input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly set.
WREN timing is illustrated in Figure 3. The WREN
instruction must be sent prior to any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Figure 3. WREN Timing
SCK
SI
SO
00000 110
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
Figure 4. WRDI Timing
SCK
SI
SO
00000 100
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
CAT25010, CAT25020, CAT25040
www.onsemi.com
7
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 8−bit address
and data as shown in Figure 5. For the CAT25040, bit 3 of
the write instruction opcode contains A8 address bit.
Internal programming will start after the low to high CS
transition. During an internal write cycle, all commands,
except for RDSR (Read Status Register) will be ignored.
The RDY bit will indicate if the internal write cycle is in
progress (RDY high), or the device is ready to accept
commands (RDY low).
Page Write
After sending the first data byte to the CAT25010/20/40,
the host may continue sending data, up to a total of 16 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the
CAT25010/20/40 is automatically returned to the write
disable state.
Figure 5. Byte WRITE Timing
SCK
SI
SO
0 0 0 0 X* 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0
012345678
OPCODE DATA IN
HIGH IMPEDANCE
BYTE ADDRESS
13 14 15 16 17 18 19 20 21 22 23
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
CS
A0
A7
Figure 6. Page WRITE Timing
SCK
SI
SO
0000 X*0 10
BYTEADDRESS
Data
Byte 1
012345678 131415
16−23 24−31
Data Byte N
OPCODE
7..1 0
16+(N−1)x8−1..16+(N−1)x8
16+Nx8−1
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
CS
A7A0
Data
Byte 3
Data
Byte 2
CAT25010, CAT25020, CAT25040
www.onsemi.com
8
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2 and 3 can be written using the WRSR command.
Write Protection
When WP input is low all write operations to the memory
array and Status Register are inhibited. WP going low while
CS is still low will interrupt a write operation. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the Status Register
or memory array. The WP input timing is shown in Figure 8.
Figure 7. WRSR Timing
0123 45678 10911121314
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
7 6 5 4 3 2 10
0000000 1
OPCODE
Dashed Line = mode (1, 1)
CS
Figure 8. WP Timing
SCK
WP
Dashed Line = mode (1, 1)
WP
CS
tWPH
tWPS
CAT25010, CAT25020, CAT25040
www.onsemi.com
9
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 8−bit address (for the CAT25040, bit 3 of the
read instruction opcode contains A8 address bit).
After receiving the last address bit, the CAT25010/20/40
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25010/20/40 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the full content of the status register
(New product, Rev. E) or the RDY (Ready) bit only (i.e.,
data out = FFh) for previous product revisions C, D (Mature
product). For easy detection of the internal write cycle
completion, both during writing to the memory array and to
the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.
Figure 9. READ Timing
SCK
SI
SO
BYTE ADDRESS
0123456789
D7 D6 D5 D4 D3 D2 D1 D0
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
1312 14 15 16 17 18 19 20 21 22
00 00X*0 11
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
A0
A7
CS
Figure 10. RDSR Timing
012345678 10911121314
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO 7 6 54 3 2 1 0
00000 1 01
Dashed Line = mode (1, 1)
CS
CAT25010, CAT25020, CAT25040
www.onsemi.com
10
Hold Operation
The HOLD input can be used to pause communication
between host and CAT25010/20/40. To pause, HOLD must
be taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
The CAT25010/20/40 devices incorporate Power−On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state. The device will
power up into Standby mode after VCC exceeds the POR
trigger level and will power down into Reset mode when
VCC drops below the POR trigger level. This bi−directional
POR behavior protects the device against ‘brown−out’
failure following a temporary loss of power.
The CAT25010/20/40 device powers up in a write disable
state and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Figure 11. HOLD Timing
SCK
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
tLZ
CS
HOLD
tCD
tHD
tHD
tCD
tHZ
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
(Note 14) Package Type Temperature Range Lead Finish Shipping†
CAT25010HU4I−GT3 S0U UDFN8−EP −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25010VI−GT3 25010E SOIC−8, JEDEC −40°C to +125°C NiPdAu 3,000 Units / Tape & Reel
CAT25010YI−GT3 S01E TSSOP−8−40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25020HU4I−GT3 S1U UDFN8−EP −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25020VI−GT3 25020E SOIC−8, JEDEC −40°C to +125°C NiPdAu 3,000 Units / Tape & Reel
CAT25020YI−GT3 S02E TSSOP−8−40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040HU4I−GT3 S2U UDFN8−EP −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040VI−GT3 25040E SOIC−8, JEDEC −40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
CAT25040YI−GT3 S04E TSSOP−8−40°C to +85°C NiPdAu 3,000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifi-
cations Brochure, BRD8011/D.
14.Specific Device Marking shows the first row top marking for new product (Revision E).
15.All packages are RoHS−compliant (Lead−free, Halogen−free).
16.The standard lead finish is NiPdAu.
17.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A DATE 23 MAR 201
5
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇ
ÇÇ
ÇÇ
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.08 A1 SEATING
PLANE
NOTE 3
b
8X
0.10 C
0.05 C
AB
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
b0.20 0.30
D2.00 BSC
D2 1.35 1.45
E3.00 BSC
E2 1.25 1.35
e0.50 BSC
L0.25 0.35
14
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.45 3.40
1
DIMENSIONS: MILLIMETERS
1
NOTE 4
0.30
8X
DET AIL A
A3 0.13 REF
A3
A
DETAIL B
L1 DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
L1 −−− 0.15
e
RECOMMENDED
5
1.56
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXX
AWLYWG
1
M
M
0.68
C0.10
8X
ÉÉ
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON42552E
ON SEMICONDUCTOR STANDARD
UDFN8, 2X3 EXTENDED PAD
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON42552E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #UDFN8−046−01 TO ON SEMICON-
DUCTOR. REQ. BY B. BERGMAN. 23 JUL 2009
AREDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD.
REQ. BY B. BECKER. 23 MAR 2015
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. A Case Outline Number
:
517AZ
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
DATE 19 DEC 2008
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34272E
ON SEMICONDUCTOR STANDARD
SOIC 8, 150 MILS
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON34272E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 01O
Case Outline Number:
751BD
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
DATE 19 DEC 2008
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34428E
ON SEMICONDUCTOR STANDARD
TSSOP8, 4.4X3
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON34428E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #TSSOP8−004−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 01O
Case Outline Number:
948AL
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor ’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
◊
