Philips Semiconductors Silicon N-channel dual-gate MOS-FETs FEATURES e Short channel transistor with high forward transfer admittance to input capacitance ratio e Low noise gain controlled amplifier up to 1 GHz. APPLICATIONS e VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment. DESCRIPTION Depletion type field effect transistor in a plastic microminiature SOT143 or SOT143R package with source and substrate interconnected. The transistors are protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. Product specification BF998; BF998R s,b Top view MAMO39 Marking code: MOp. Fig.1 Simplified outline (GOT143) and symbol; BF998. CAUTION (PE The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. PINNING 1 | |e PIN DESCRIPTION Top view MAMO40 source drain gate 2 gate 1 PkwOoOnM = Marking code: MOp. Fig.2 Simplified outline (SOT143R) and symbol; BF998R. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYP. UNIT Vos drain-source valtage Ip drain current Prot total power dissipation lyse forward transfer admittance Cigt-s input capacitance at gate 1 Cw reverse transfer capacitance f= 1 MHz F noise figure f = 800 MHz operating junction temperature 7 450 1996 Aug 01 346Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Vos drain-source voltage - 12 Vv Ip drain current - 30 mA te gate 1 current - 10 mA tlee gate 2 current - 10 mA Prot total power dissipation; BF998 | up to Tamp = 60 C; see Fig.3; note 1 | - 200 mw UP to Tamb = 50 C; see Fig.3; note 2 | - 200 mw Prot total power dissipation; BF998R | up to Tamp = 50 C; see Fig.4; note 1 | - 200 mw Tetg storage temperature ~65 +150 C Tj operating junction temperature - 150 C Notes 1. Device mounted on a ceramic substrate, 8 mm x 10 mm x 0.7 mm. 2. Device mounted on a printed-circuit board. MLAI98 MGA002 200 Prot max (mW) 100 Tamb (C) (1) Ceramic substrate. (2) Printed-circuit board. 200 Fig.3 Power derating curves; BF998. 200 Ptot max (mW) 100 Tamb (C) Fig.4 Power derating curve; BF998R. 1996 Aug 01 347Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS |; VALUE UNIT Rin j-a thermal resistance from junction to ambient in free air; BF998 | note 1 460 KAW note 2 500 KAW Rih j-a thermal resistance from junction to ambient in free air; BF998R | note 1 500 K/AV Notes 1. Device mounted on a ceramic substrate, 8 mm x 10 mm x 0.7 mm. 2. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. | MAX. | UNIT tVsrjai-ss | gate 1-source breakdown voltage Vee-s = Vos = 0; Ia1-sg = +10 MA 6 20 Vv +V(pR)G2-ss_| gate 2-source breakdown voltage Veat-s = Vos = 0; Igo-sg = 10 MA 6 20 Vv ~Vpyai-s gate 1-source cut-off voltage Veo-s = 4 Vi Vos = 8 V3 Ip = 20 pA - 2.0 Vv ~Vipye2-s gate 2-source cut-off voltage Vat-s = 0; Vos = 8 V3 Ip = 20 A - 1.5 Vv lbss drain-source current Vao.5 = 4 Vi Vos = 8 V; Vgi-s = 0; note 1 | 2 18 mA +le1-ss gate 1 cut-off current Vae2-5 = Vos = 0; Va1-5 = +5 V - 50 nA +lgo-ss gate 2 cut-off current Vat-s = Vos = 0; Vaa-g = +5 V ~ 50 nA Note 1. Measured under pulse condition. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; Vos = 8 V; Vao-s = 4 V; Ip = 10 mA. SYMBOL PARAMETER CONDITIONS MIN. | TYP. | MAX. | UNIT lyis! forward transfer admittance | f= 1 kHz 2i 24 | - mS Cigt-s input capacitance at gate 1 f= 1 MHz - 2.1 2.5 pF Cigo-s input capacitance at gate 2 f=1 MHz - 1.2 - pF Cogs output capacitance f= 1 MHz - 1.05 |- pF Cis reverse transfer capacitance | f= 1 MHz ~ 25 - fF F noise figure f = 200 MHz; Gs = 2 mS; Bg = Beopt - 0.6 - dB f = 800 MHz; Gs = 3.3 mS; Bs = Bgopt_ | 1.0 - dB 1996 Aug 01 348Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGE813 i, 24 D = (mA) VG1-S= 20 0.4V 03V 16 02V 12 01V ov 8 -0.1V -02V 4 -0.3V ~0.4V -05V 0 0 2 4 6 8 10 Vps (V) Ve2s = 4 V3 Tamb = 25 C. Fig.5 Output characteristics; typical values. MGE@15 3V =4V 2V -1 0 Ver WV) Vos = 8 V; Tamp = 25 C. Fig.6 Transfer characteristics; typical values. MGE614 24 Us) (mA) max / | typ 20 0 ~1600 1200 -800 400 0 400 Ver (mv) Vos = 8 V; Vgo.5 = 4 V; Tam = 25 C. Fig.7 Drain current as a function of gate 1 voltage; typical values. MGE811 30 4v lytgl 3V (mS) 2Vv 24 1V 18 12 0 4 8 12 16 20 Ip (mA) Vos = 8 V; Tamp = 25 C. Fig.8 Forward transfer admittance as a function of drain current; typical values. 1996 Aug 01 349Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGEaI2 30 Weg! (ms) 24 Ver) Vpg = 8 V: Tamb = 25 C. Fig.8 Forward transfer admittance as a function of gate 1 voltage; typical values. MGE8t0 15 Cos (pF) 1.4 Vao-g = 4V; f= 1 MHZ; Tamb = 25 C. Fig.10 Output capacitance as a function of drain-source voltage; typical values. MGE809 2.3 Cig (pF) 24 17 Vet1-s ) Vos = 8 V: Vao.g = 4 V; f= 1 MHZ: Tamp = 25 C. Fig.11 Gate 1 input capacitance as a function of gate 1-source voltage; typical values. MBH479 24 Cig (pF) 2.3 2.2 2.4 2.0 0 Vaa2_s (V) Vos = 8 V; Vei-g = 0 V; f= 1 MHz; Tamp = 25 C. Fig.12 Gate 1 input capacitance as a function of gate 2-source voltage; typical values. 1996 Aug 01 350Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGC466 Yis (m8) 1071 107? 10 102 f (MHz) 103 Vps = 8 V; Va2-s = 4 V; Ip = 10 MA; Tamp = 25 C. Fig.13 Input admittance as a function of the frequency; typical values. MGC467 103 -108 \Yrs| V5 (8) (deg) 102 -10? 10 -10 1 -1 10 10 f (MHz) 103 Vos = 8 V; Va2-s = 4 V; Ip = 10 MA; Tamp = 25 C. Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. MGC468 102 -10? l fs] Pts (mS) (deg) 10 -10 10 10? 108 f (MHz) Vos = 8 V; Veo-5 = 4 Vi Ip = 10 MA; Tamp = 25 C. Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. MGC46S Yos (mS) 1071 10-2 10 10? f (MHz) 10% Vos = 8 V; Vaa-s = 4 Vi Ip = 10 MA: Tamp = 25 C. Fig.16 Output admittance as a function of the frequency; typical values. 1996 Aug 01 351Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R 500 output AT KQ 50Q input 360 2 10 pF vi D2 oD : t BB405 | | 330 kQ TA BB405 | | 330 kQ 1nF , 1nF Viun Viun input output MGEs0z Vop = 12 V; Gg = 2 mS; G, = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately haff a turn from the cold side, to adjust G_ = 0.5 mS. C1 adjusted for Gg = 2 mS. Fig.17 Gain control test circuit at f = 200 MHz. 1996 Aug 01 352Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R Vpp Vage Yop tnF tnF 140k2 Y4 +E 100 ka nF Ek 270 kn L4 Li 1nF \ ig nF 502 SHEE an rt output nF 2 4h 42 input otF GH tnF 7 08 to "7 ito 40 pF xc x c2 meee 2to18pF | 0.5to 3.5 pF 77. 7, 18kQ 3602 MGE801 Vpp Vop = 12 V; Gs = 3.3 mS; G_ = 1 mS. L1 =L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 =2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2m, silvered 0.5 mm copper wire, 4 mm above ground plane. Fig.18 Gain control test circuit at f = 800 MHz. 1996 Aug 01 353Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R 0 MGE808 MGE807 AGir AG (dB) (dB) 10 -10 40 -40 -50 -50 i) 2 4 6 8 10 Vage (V) Vage (VY) Vpp = 12 V; f= 200 MHZ: Tamp = 25 C. Vop = 12 V; f= 800 MHz; Tamp = 25 C. Fig.19 Automatic gain control characteristics Fig.20 Automatic gain control characteristics measured in circuit of Fig.17. measured in circuit of Fig. 18. 1996 Aug 01 354