EiceDRIVER TM 2EDN752x / 2EDN852x Dual Channel 5A, High-Speed, Low-Side Gate Driver With High Negative Input Voltage Capability and Advanced Revers Current Robustness EiceDRIVERTM Fast Dual Channel Low-Side Gate Driver Data Sheet Revision 2.0, 2015-07-22 Power Management and Multimarket EiceDRIVERTM 2EDN752x / 2EDN852x Revision History , Revision 2.0, 2015-07-22 Page/ Item Subjects (major changes since previous revision) Responsible Date updated from version 1.1 all Complete revision Data Sheet Tobias Gerber 2015/07/22 2 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Fast Dual Channel 5 A Low-Side Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 1.1 1.2 1.3 Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Undervoltage Lockout Versions 6 Logic Versions 7 Package Versions 7 2 Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 4.1 4.2 4.3 4.4 4.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction 13 Supply Voltage 13 Input Configurations 13 Driver Outputs 13 Undervoltage Lockout (UVLO) 14 5 5.1 5.2 5.3 5.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute Maximum Ratings 15 Thermal Characteristics 15 Operating Range 17 Electrical Characteristics 17 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data Sheet 3 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Fast Dual Channel 5 A Low-Side Gate Driver Main Features * * * * * * * * * * * Industry-Standard Pinout Two Independent Low-Side Gate Drivers 5 A Peak Sink/Source Output Driver at VDD = 12 V -10 Vdc Negative Input Capability against GND-Bouncing Enhanced operating robustness due to High Reverse Current Capability (5 A Peak) True Low-Impedance Rail-To-Rail Output (0.7 and 0.55 ) Very Low Propagation Delay (19 ns) Typ. 1 ns Channel to Channel Delay Matching Wide Input and Output Voltage Range up to 20 V Active Low Output Driver even on Low Power or Disabled Driver High Flexibility through Different Logic Input Configurations (LVTTL and CMOS 3.3 V) * PG-DSO-8, PG-WSON-8 and PG-TSSOP-8 Package * * Extended Operation from -40 C to 150 C (Junction Temperature) Particularly Well-Suited for Driving Standard, Superjunction MOSFETs, IGBTs and GaN Power Devices PG-DSO-8 Typical Applications * SMPS * Single / interleave PFC * Synchronous rectification * Isolated gate driving via pulse transformer's * Local direct gate drive for high performanc SMPS * DC-to-DC Converters * Bricks * Power Tools * Industrial Applications PG-WSON-8 PG-TSSOP-8 Data Sheet 4 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Description From Controller The Fast Dual Channel 5A Low-Side Gate Driver is an advanced dual-channel driver optimized for driving both Standard MOSFETs and Superjunction MOSFETs (OptiMOSTM, CoolMOSTM), as well as GaN Power devices, in all applications in which they are commonly used. The input signals are LVTTL compatible (CMOS 3.3V) with an input voltage range from 3V to +20V. The ability to operate with -10VDC at the input pins protects the device against ground bounce conditions. Each of the two outputs is able to sink and source a 5 A current utilizing a true rail-to-rail stage, that ensures very low impedances of 0.7 up to the positive and 0.55 down to the negative rail respectively. Very low channel to channel delay matching, typ. 1 ns, enables the double source and sink capability of 10 A, by paralleling both channels. Advanced Reverse Current Robustness, demonstrated with over 5 A feedback current, sourced by MOSFET ringing or inductive feedbacks, gives more safety margin and robustness in application. Different logic input/output configurations guarantee high flexibility in all applications; e.g. with two paralleled switches in a boost configuration (see Figure below). The gate driver is available in the three package options: A standard PG-DSO-8, a thin PG-WSON-8 and PG-TSSOP8 (small size DSO 8 package). 1 ENA ENB 88 2 INA OUTA 7 33 GND VDD 66 44 INB Load1 VDD 2EDN752x / 2EDN852x Load2 M1 Rg1 Rg2 M2 OUTB 55 CVDD Figure 0-1 Typical Application Data Sheet 5 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Product Versions 1 Product Versions The 2EDN752x / 2EDN852x is available in 2 different logic, 2 different undervoltage lockout and 3 package versions. Table 1-1 Product Versions Part Number Description Package Order Code IC Topside Marking Code 2EDN7524F standard input. standard UVLO PG-DSO-8 SP001339264 2N7524AF EiceDRIV XXHYYWW 2EDN7524R standard input, standard UVLO PG-TSSOP-8 SP001391096 2N7524 AR_XXX HYYWW 2EDN8524R standard input, super junction PG-TSSOP-8 UVLO SP001391100 2N8524 AR_XXX HYYWW 2EDN7523F inverted input, standard UVLO PG-DSO-8 SP001358244 2N7523AF EiceDRIV XXHYYWW 2EDN7524G standard input, standard UVLO PG-WSON-8 SP001391108 2N7524 AG_XXX HYYWW 2EDN7523R inverted input. standard UVLO PG-TSSOP-8 SP001391098 2N7523 AR_XXX HYYWW 2EDN8523R inverted input. super junction UVLO PG-TSSOP-8 SP001391102 2N8523 AR_XXX HYYWW 2EDN7523G inverted input. standard UVLO PG-WSON-8 SP001391114 2N7523 AG_XXX HYYWW 1.1 Undervoltage Lockout Versions The two Undervoltage Lockout versions are indicated by the variable x in the product version 2EDNy52x: * y=7: lower voltage level (4.2V) * y=8: higher voltage level (8.0V) Please go to the functional description section for more details in Chapter 4 Undervoltage Lockout (UVLO). Data Sheet 6 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Product Versions 1.2 Logic Versions The 2 logic versions are indicated by the variable y in the product version 2EDNy52x: * x=3: inverting * x=4: standard (non-inverting) The logic relations between inputs, enable pins and outputs are given in Table 1-2 for the inverting and standard version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective input, if the enable inputs ENA and ENB are high (or left open). A logic "low" at an enable input or an undervoltage lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal. Table 1-2 Logic Table Inputs Output Inverting ENA ENB INA INB UVLO x x x x L L x H L H 1) Output non-inverting OUTA OUTB OUTA OUTB active L L L L x inactive L L L L L x inactive H L L L L H x inactive L L H L L H x L inactive L H L L L H x H inactive L L L H H H L L inactive H H L L H H H L inactive L H H L H H L H inactive H L L H H H H H inactive L L H H 1) Active means that Vcc is above UVLO threshold voltage and release logic to control output stage. Inactive means that UVLO disabel active the output stage. 1.3 Package Versions Most of the logic versions and UVLO versions are available in 3 different packages. * * * a standard PG-DSO-8 (designated by "F") a leadless PG-WSON-8 (designated by "G") a small PG-TSSOP-8 (designated by "R") Drawings can be viewed in Chapter 8 Outline Dimensions. Data Sheet 7 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Pin Configuration and Description 2 Pin Configuration and Description The pin configuration for the inverting and standard input version of 2EDN7524F and 2EDN7523F in the PGDSO-8 package is shown in Figure 2-1. 1 ENA 2 INA 3 GND 4 INB ENB 8 OUTA 7 VDD 6 OUTB 5 Figure 2-1 Pin Configuration PG-DSO-8, Top View Table 2-1 Pin Configuration 2EDN7524F and 2EDN7523F in the PG-DSO-8 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (inverting or non-inverting) 3 GND Ground 4 INB Input signal channel B Logic input, controlling OUTB (inverting or non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 to 20V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low Data Sheet 8 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Pin Configuration and Description The pin configuration for standard input version of 2EDN7524R, 2EDN8524R, 2EDN7523R and 2EDN8523R in the PG-TSSOP-8 package is shown in Figure 2-2. 1 ENA 2 INA 3 GND 4 INB Heat Sink ENB 8 OUTA 7 VDD 6 OUTB 5 Figure 2-2 Pin Configuration PG-TSSOP-8, Top View Table 2-2 Pin Configuration 2EDN7524R, 2EDN8524R, 2EDN7523R and 2EDN8523R in the PG-TSSOP-8 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (non-inverting) 3 GND Ground 4 INB Input signal channel B Logic input, controlling OUTB (non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 to 20V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low Heat sink of PG-TSSOP-8 packages has to be connected to GND pin. Data Sheet 9 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Pin Configuration and Description The pin configuration for standard input version of 2EDN7524G and 2EDN7523G. In the PG-WSON-8 package is shown in Figure 2-3. ENA 1 INA 2 GND INB 8 ENB 7 OUTA 3 6 VDD 4 5 OUTB Heat Sink Figure 2-3 Pin Configuration PG-WSON-8, Top View Table 2-3 Pin Configuration 2EDN7524G and 2EDN7523Gin the PG-WSON-8 Package Pin Symbol Description 1 ENA Enable input channel A Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low 2 INA Input signal channel A Logic input, controlling OUTA (non-inverting) 3 GND Ground 4 INB Input signal channel B Logic input, controlling OUTB (non-inverting) 5 OUTB Driver output channel B Low-impedance output with source and sink capability 6 VDD Positive supply voltage Operating range 4.5 to 20V 7 OUTA Driver output channel A Low-impedance output with source and sink capability 8 ENB Enable input channel B Logic Input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low Heat sink of PG-WSON-8 packages has to be connected to GND pin. Data Sheet 10 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Block Diagram 3 Block Diagram A simplified functional block diagram for the non-inverted version is given in Figure 3-1 VDD VDD 6 UVLO VDD 400k ENA 1 Logic A INA 7 OUTA 5 OUTB 2 100k GND GND VDD VDD 400k ENB 8 Logic B INB 4 100k GND GND 3 GND Figure 3-1 Block Diagram, standard input, pull-up/pull-down resistor configuration Data Sheet 11 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Block Diagram A simplified functional block diagram for the inverted version is given in Figure 3-2. VDD VDD 6 UVLO VDD 400k ENA 1 VDD Logic A 7 OUTA 5 OUTB 400k INA 2 GND VDD VDD VDD 400k 400k ENB 8 Logic B INB 4 GND GND 3 GND Figure 3-2 Block Diagram, inverting input, pull-up/pull-down resistor configuration Data Sheet 12 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Functional Description 4 Functional Description 4.1 Introduction The 2EDN752x / 2EDN852x is a fast dual-channel driver for low-side switches. Two true rail-to-rail output stages with very low output impedance and high current capability are chosen to ensure highest flexibility and cover a high variety of applications. The focus on robustness at input and output side gives this device even a safety margin on critical abnormal situations. An extended negative voltage range protects input pins against ground shifts. No current flows over the ESD structure of the IC during a negative input level. All outputs are robust against reverse current. The interaction with the power MOSFET, even reverse reflected power can be covered by the strong internal output stage. All inputs are compatible with LVTTL signal levels. The threshold voltages with a typical hysteresis of 1V are kept constant over the supply voltage range. Since the 2EDN752x / 2EDN852x aims particularly at fast-switching applications, signal delays and rise/fall times have been minimized. Special effort has been made towards minimizing delay differences between the 2 channels to very low values of typically 1ns. 4.2 Supply Voltage The maximum supply voltage is 20V. This high voltage can be valuable in order to exploit the full current capability of 2EDN752x / 2EDN852x when driving very large MOSFETs. The minimum operating supply voltage is set by the undervoltage lockout function to a typical default value of 4.2V or of 8V. This lockout function protects power MOSFET from running into linear mode with high power dissipation. 4.3 Input Configurations As described in Chapter 1, 2EDN752x / 2EDN852x is available in 2 different configurations with respect to the logic configuration of the 4 input pins (input plus enable). The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left open. The standard PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event during power up and a not driven input condition. Version with inverted PWM input have a internal pull up resistor to prevent unwanted switch-on. All inputs are compatible with LVTTL levels and provide a hysteresis of 1V typ. It is independent of the supply voltage. All input pins have a negative extended voltage range. This prevents cross current over single wires during GND shifts between signal source (controller) and driver input. 4.4 Driver Outputs The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical 5A of sourcing and sinking current. This output stage has a shoot through protection and current limiting behavior. The on-resistance is very low with a typical value below 0.7 for the sourcing p-channel MOS and 0.5 for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving real rail-to-rail behaviour and not suffering from a source follower's voltage drop. Data Sheet 13 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Functional Description Gate Drive Outputs held active low in case of floating inputs ENx, INx or during startup or power down once UVLO is not exceeded. Under any situation, startup, UVLO or shutdown, outputs are held under defined conditions. 4.5 Undervoltage Lockout (UVLO) The Undervoltage Lockout function ensures that the output can be switched to its high level only, if the supply voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not operated if the driving voltage is too low to completely switch it on, thereby avoiding excessive power dissipation. The default UVLO level is set to a typical value of 4.2V / 8V (with some hysteresis). UVLO of 4.2V is normally used for low voltage and TTL based MOSFETs. For higher level, like high voltage super junction MOSFETS, an active voltage of minimum 8V version is available. Data Sheet 14 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Characteristics 5 Characteristics The absolute maximum ratings are listed in Table 5-1. Stresses beyond these values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.1 Absolute Maximum Ratings Table 5-1 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Positive supply voltage VVDD -0.3 22 V Voltage at pins INA, INB, ENA, ENB VIN -10 22 V Voltage at pins OUTA, OUTB VOUT -0.3 VVDD+0.3 V Note1) Reverse current peak at pins OUTA, OUTB ISNK_rev ISRC_rev -5 5 Apk < 500ns2) Junction temperature TJ -40 150 C Storage temperature TS -55 150 C ESD capability VESD 1.5 kV Charged Device Mode (CDM) 3) 2.5 kV Human Body Model (HBM) 4) 1) Voltage spikes resulting from reverse current peaks are allowed. 2) ISNK_rev < -2A or ISRC_rev > 2 A may reduce life time; No limitation by design; Parameter verified by design, not 100% tested in production; max. power dissipation must be observed (see Figure 7-8) 3) According to JESD22-C101 4) According to JESD22-A114 5.2 Thermal Characteristics Table 5-2 Thermal Characteristics Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Thermal resistance junctionambient 1) RthJA25 125 K/W PG-DSO-8, Tamb=25C Thermal resistance junctioncase (top) 2) RthJC25 66 K/W PG-DSO-8, Tamb=25C Thermal resistance junctionboard 3) RthJB25 62 K/W PG-DSO-8, Tamb=25C Characterization parameter junction-top 4) thJC25 16 K/W PG-DSO-8, Tamb=25C Data Sheet 15 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Characteristics Table 5-2 Thermal Characteristics Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Characterization parameter junction-board 5) thJB25 55 K/W PG-DSO-8, Tamb=25C Thermal resistance junctionambient 1) RthJA25 64 K/W PG-TSSOP-8, Tamb=25C Thermal resistance junctioncase (top) 2) RthJP25 56 K/W PG-TSSOP-8, Tamb=25C Thermal resistance junctionboard 3) RthJB25 55 K/W PG-TSSOP-8, Tamb=25C Characterization parameter junction-top 4) thJC25 9 K/W PG-TSSOP-8, Tamb=25C Characterization parameter junction-board 5) thJB25 13 K/W PG-TSSOP-8, Tamb=25C Thermal resistance junctionambient 1) RthJA25 61 K/W PG-WSON-8, Tamb=25C Thermal resistance junctioncase (top) 2) RthJP25 54 K/W PG-WSON-8, Tamb=25C Thermal resistance junctionboard 3) RthJB25 52 K/W PG-WSON-8, Tamb=25C Characterization parameter junction-top 4) thJC25 8 K/W PG-WSON-8, Tamb=25C Characterization parameter junction-board 5) thJB25 11 K/W PG-WSON-8, Tamb=25C 1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDECstandard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). 5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). Data Sheet 16 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Characteristics 5.3 Operating Range Table 5-3 Operating Range Parameter Symbol Values Min. Typ. Unit Note or Test Condition Min defined by UVLO Max. Supply voltage VVDD 4.5 20 V Logic input voltage VIN -5 20 V Junction temperature TJ -40 150 C 1) 1) Continuous operation above 125 C may reduce life time. 5.4 Electrical Characteristics Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They are valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at TJ=25C. Table 5-4 Power Supply Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition VDD quiescent current IVDDqu1 0.5 0.7 1.2 mA OUT = high, VVDD= 12 V VDD quiescent current IVDDqu2 0.3 0.48 0.7 mA OUT = low, VVDD= 12 V Unit Note or Test Condition Table 5-5 Undervoltage Lockout Standard MOSFET Version Parameter Symbol Values Min. Typ. Max. Undervoltage Lockout (UVLO) UVLOon turn on threshold 3.9 4.2 4.5 V Undervoltage Lockout (UVLO) UVLOoff turn off threshold 3.6 3.9 4.2 V UVLO threshold hysteresis Table 5-6 0.3 UVLOhys V Undervoltage Lockout Superjunction MOSFET Version Parameter Symbol Values Unit Min. Typ. Max. Undervoltage Lockout (UVLO) UVLOon turn on threshold 7.4 8.0 8.6 V Undervoltage Lockout (UVLO) UVLOoff turn off threshold 6.5 7.0 7.5 V UVLO threshold hysteresis -- 1.0 -- V Data Sheet UVLOhys 17 Note or Test Condition Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Characteristics Table 5-7 Logic Inputs INA, INB, ENA, ENB Parameter Symbol Values Unit Min. Typ. Max. Input voltage threshold for transition LH VINH 1.9 2.1 2.3 V Input voltage threshold for transition HL VINL 0.8 1.0 1.2 V Input pull up resistor1) RIN H 400 k RIN L 100 k 2) Input pull down resistor Note or Test Condition 1) Inputs with initial high logic level 2) Inputs with initial low logic level Table 5-8 Static Output Caracteristics (see Figure 6-2) Parameter Symbol High Level (Sourcing) Output Resistance Ron_SNK High Level (Sourcing) Output Current ISNK_peak Low Level (Sinking) Output Resistance Ron_SRC High Level (Sinking) Output Current ISRC_Peak Values Unit Note or Test Condition ISNK = 50mA Min. Typ. Max. 0.35 0.7 1.2 5.0 1) A 0.55 1.0 -5.0 2) A 0.28 ISRC = 50mA 1) Active limited by design at apox. 6.5Apk, parameter is not subject to production test - verified by design / characterization, max. power dissipation must be observed 2) Active limited by design at apox. -6.5Apk, parameter is not subject to production test - verified by design / characterization, max. power dissipation must be observed Data Sheet 18 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Characteristics Table 5-9 Dynamic Characteristics (see Figure 6-1, Figure 6-2, Figure 6-3 and Figure 6-4) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Input/Enable to output propagation delay TPDON 15 19 25 ns CLOAD= 1.8 nF, VVDD= 12 V Input/Enable to output propagation delay TPDOFF 15 19 25 ns CLOAD= 1.8 nF, VVDD= 12 V Input/Enable to output propagation delay mismatch between channels DtPD 1 4 ns Rise Time TRISE 5.3 101) ns CLOAD= 1.8 nF, VVDD= 12 V 1) ns CLOAD= 1.8 nF, VVDD= 12 V ns CLOAD= 1.8 nF, VVDD= 12 V -- Fall Time TFAll -- 4.5 10 Minimum input pulse width that changes output state TPW -- 10 20 1) Parameter verified by design, not 100% tested in production. Data Sheet 19 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Timing Diagrams 6 Timing Diagrams Figure 6-1 shows the definition of rise, fall and delay times for the inputs of the non-inverting version (with Enable pin high or open). ENx (high) VIN H VINL VIN H VINL INx 90% OUT 10% TPDON TRIS E TPDOF F TFAL L Figure 6-1 Propagation delay, rise and fall time, non-inverted Figure 6-2 shows the definition of rise, fall and delay times for the inputs of the inverting version (with enable pins high or open). ENx (high) VINH VIN L INx VINH VINL 90% OUT 10% TPDON TRIS E TPDOF F TFAL L Figure 6-2 Propagation delay, rise and fall Time, inverted Figure 6-3 illustrates the undervoltage lockout function. UVLOon UVLOoff VDD OUT Figure 6-3 UVLO behaviour, input ENx and INx drives OUT normally high Data Sheet 20 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Timing Diagrams Figure 6-4 illustrates the minimum input pulse width that changes output state. ENx (high) VIN H VINL VIN H INx VINL TPW 90% OUT Figure 6-4 TPW, minimum input pulse width that changes output state Data Sheet 21 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Typical Characteristics 7 Typical Characteristics UVLO_ON vs TEMPERATURE 4,5 UVLO_HYS vs TEMPERATURE 0,6 on value off value 4,3 UVLO hys [V] UVLO on [V] 0,4 4,1 0,2 3,9 VDD=12V VDD=12V 0 3,7 -50 0 50 100 T junction [C] -50 150 0 50 100 T junction [C] 150 Figure 7-1 Undervoltage lockout VINL / VINH INx to OUTx vs TEMPERATURE 2,7 VIN_HYS ENx vs TEMPERATURE 1,2 typ VINH typ VINL 2,3 Vin_hys ENx [V] VIN [V] 1,1 1,9 1,5 1 1,1 VDD=12V VDD=12V 0,9 0,7 -50 0 50 100 T junction [C] -50 150 0 50 100 T junction [C] 150 Figure 7-2 Input (INx) characteristic Data Sheet 22 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Typical Characteristics VINL / VINH ENx to OUTx vs TEMPERATURE 2,7 VIN_HYS ENx vs TEMPERATURE 1,2 typ VENH typ VENL 2,3 Vin_hys ENx [V] VIN ENx [V] 1,1 1,9 1,5 1 1,1 VDD=12V VDD=12V 0,9 0,7 -50 0 50 100 T junction [C] -50 150 0 50 100 T junction [C] 150 Figure 7-3 Input (ENx) characteristic VINx to OUTx Propagation Delay vs TEMPERATURE 25 VINx to OUTx Propagation Delay vs TEMPERATURE 25 typ T PD_ON typ T PD_OFF typ T PD_OFF 22,5 T PD_ON [ns] 22,5 T PD_ON [ns] typ T PD_ON 20 17,5 20 17,5 VDD=12V Input 5V VDD=12V Input 3.3V 15 15 -50 0 50 100 T junction [C] 150 -50 0 50 100 T junction [C] 150 Figure 7-4 Propagation delay (INx) on different input logic levels (see Figure 6-1) Data Sheet 23 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Typical Characteristics VENx to OUTx Propagation Delay vs TEMPERATURE 25 VENx to OUTx Propagation Delay vs TEMPERATURE 25 typ T PD_ON typ T PD_OFF typ T PD_OFF 22,5 T PD_ON [ns] 22,5 T PD_ON [ns] typ T PD_ON 20 17,5 20 17,5 VDD=12V Enable 5V VDD=12V Enable 3.3V 15 15 -50 0 50 100 T junction [C] 150 -50 0 50 100 T junction [C] 150 Figure 7-5 Propagation delay (ENx) on different input logic levels (see Figure 6-1) OUTx Rise /Fall Time 10% - 90% vs TEMPERATURE 6,5 typ T Rrise 6 typ T Fall T PD_ON [ns] 5,5 5 4,5 VDD=12V OUTx with 1.8nF load 4 3,5 -50 0 50 100 T junction [C] 150 Figure 7-6 Rise / fall times with load on output (see Figure 6-1) Data Sheet 24 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Typical Characteristics Power Consumption vs VDD Supply Voltage Power Consumption vs TEMPERATURE 0,80 OUTx High OUTx Low 0,65 Idd [mA] Idd [mA] 0,8 0,6 0,4 0,50 OUTx High 0,35 OUTx Low VDD=12V ENx NC both channel in Tj=25C 0,2 0,20 0 10 -50 20 Vdd [V] 50 100 T junction [C] 150 Power Consumption vs Frequency 50 Tamb 25C Input 50%@3.3V Device self-heating Load 1.8nF serial 40 I DD [mA] 0 VDD 4,5V 30 VDD 12V VDD 20V 20 10 0 0 250 500 750 Frequency [kHz] 1000 Figure 7-7 Power consumption related to temperature, supply voltage and frequency Data Sheet 25 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Typical Characteristics Reverse Current at OUTx with High Side Active Reverse Current at OUTx with Low Side Active -1,5 7,5 Test Conditions: Tj = 25C, 1s positive Pulse fsw = 1kHz -3,0 2.5 W 10 W I OUT [A] I OUT [A] 6,0 Test Conditions: Tj = 25C, 1s negative Pulse fsw = 1kHz 4,5 7.5 W 3,0 5W -4,5 5W 7.5 W -6,0 10 W 2.5 W 1,5 0,0 -7,5 0,8 1,0 1,3 1,5 U OUT [V] 1,8 -2,3 2,0 -2,0 -1,8 -1,5 U OUT [V] -1,3 -1,0 Figure 7-8 Output OUTx with reverse current and resulting power dissipation Data Sheet 26 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Outline Dimensions 8 Outline Dimensions Figure 8-1 PG-DSO-8 Data Sheet 27 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Outline Dimensions Figure 8-2 PG-TSSOP-8 (see notes) Data Sheet 28 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Outline Dimensions Figure 8-3 PG-TSSOP-8 Data Sheet 29 Revision 2.0, 2015-07-22 EiceDRIVERTM 2EDN752x / 2EDN852x Outline Dimensions Notes 1. For further information on package types, recommendation for board assembly, please go to: http://www.infineon.com/cms/en/product/technology/packages/. Data Sheet 30 Revision 2.0, 2015-07-22 Trademarks of Infineon Technologies AG AURIXTM, C166TM, CanPAKTM, CIPOSTM, CIPURSETM, CoolMOSTM, CoolSETTM, CORECONTROLTM, CROSSAVETM, DAVETM, DI-POLTM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPIMTM, EconoPACKTM, EiceDRIVERTM, eupecTM, FCOSTM, HITFETTM, HybridPACKTM, I2RFTM, ISOFACETM, IsoPACKTM, MIPAQTM, ModSTACKTM, mydTM, NovalithICTM, OptiMOSTM, ORIGATM, POWERCODETM, PRIMARIONTM, PrimePACKTM, PrimeSTACKTM, PRO-SILTM, PROFETTM, RASICTM, ReverSaveTM, SatRICTM, SIEGETTM, SINDRIONTM, SIPMOSTM, SmartLEWISTM, SOLID FLASHTM, TEMPFETTM, thinQ!TM, TRENCHSTOPTM, TriCoreTM. Other Trademarks Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM, ARMTM, MULTI-ICETM, KEILTM, PRIMECELLTM, REALVIEWTM, THUMBTM, VisionTM of ARM Limited, UK. AUTOSARTM is licensed by AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM, FirstGPSTM of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft Corporation. FlexRayTM is licensed by FlexRay Consortium. HYPERTERMINALTM of Hilgraeve Incorporated. IECTM of Commission Electrotechnique Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM, NUCLEUSTM of Mentor Graphics Corporation. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies, Inc. OpenwaveTM Openwave Systems Inc. RED HATTM Red Hat, Inc. RFMDTM RF Micro Devices, Inc. SIRIUSTM of Sirius Satellite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM, PALLADIUMTM of Cadence Design Systems, Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM, WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 www.infineon.com Edition 2015-07-22 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2014 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Doc_Number Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. 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