EiceDRIVER ™
2EDN752x / 2EDN852x
Dual Channel 5A, High-Speed, Low-Side Gate Driver With High
Negative Input Voltage Capability and Advanced Revers
Current Robustness
EiceDRIVER™
Fast Dual Channel Low-Side Gate Driver
Power Management and Multimarket
Data Sheet
Revision 2.0, 2015-07-22
Data Sheet 2 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Revision History ,
Revision 2.0, 2015-07-22
Page/
Item
Subjects (major changes since previous revision) Responsible Date
updated from version 1.1
all Complete revision Tobias Gerber 2015/07/22
EiceDRIVER™
2EDN752x / 2EDN852x
Data Sheet 3 Revision 2.0, 2015-07-22
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Fast Dual Channel 5 A Low-Side Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1 Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Undervoltage Lockout Versions 6
1.2 Logic Versions 7
1.3 Package Versions 7
2 Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Introduction 13
4.2 Supply Voltage 13
4.3 Input Configurations 13
4.4 Driver Outputs 13
4.5 Undervoltage Lockout (UVLO) 14
5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Absolute Maximum Ratings 15
5.2 Thermal Characteristics 15
5.3 Operating Range 17
5.4 Electrical Characteristics 17
6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table of Contents
EiceDRIVER™ 2EDN752x / 2EDN852x
PG-DSO-8
PG-WSON-8
PG-TSSOP-8
Data Sheet 4 Revision 2.0, 2015-07-22
Fast Dual Channel 5 A Low-Side Gate Driver
Main Features
• Industry-Standard Pinout
• Two Independent Low-Side Gate Drivers
• 5 A Peak Sink/Source Output Driver at VDD = 12 V
• -10 Vdc Negative Input Capability against GND-Bouncing
• Enhanced operating robustness due to High Reverse Current
Capability (5 A Peak)
• True Low-Impedance Rail-To-Rail Output (0.7 Ω and 0.55 Ω)
• Very Low Propagation Delay (19 ns)
• Typ. 1 ns Channel to Channel Delay Matching
• Wide Input and Output Voltage Range up to 20 V
• Active Low Output Driver even on Low Power or Disabled Driver
• High Flexibility through Different Logic Input Configurations
(LVTTL and CMOS 3.3 V)
• PG-DSO-8, PG-WSON-8 and PG-TSSOP-8 Package
• Extended Operation from -40 °C to 150 °C (Junction Temperature)
• Particularly Well-Suited for Driving Standard, Superjunction
MOSFETs, IGBTs and GaN Power Devices
Typical Applications
•SMPS
• Single / interleave PFC
• Synchronous rectification
• Isolated gate driving via pulse transformer’s
• Local direct gate drive for high performanc SMPS
• DC-to-DC Converters
•Bricks
• Power Tools
• Industrial Applications
Data Sheet 5 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Description
The Fast Dual Channel 5A Low-Side Gate Driver is an advanced dual-channel driver optimized for driving both
Standard MOSFETs and Superjunction MOSFETs (OptiMOSTM, CoolMOSTM), as well as GaN Power devices, in all
applications in which they are commonly used. The input signals are LVTTL compatible (CMOS 3.3V) with an
input voltage range from 3V to +20V. The ability to operate with -10VDC at the input pins protects the device
against ground bounce conditions. Each of the two outputs is able to sink and source a 5 A current utilizing a
true rail-to-rail stage, that ensures very low impedances of 0.7 Ω up to the positive and 0.55 Ω down to the
negative rail respectively. Very low channel to channel delay matching, typ. 1 ns, enables the double source
and sink capability of 10 A, by paralleling both channels. Advanced Reverse Current Robustness,
demonstrated with over 5 A feedback current, sourced by MOSFET ringing or inductive feedbacks, gives more
safety margin and robustness in application. Different logic input/output configurations guarantee high
flexibility in all applications; e.g. with two paralleled switches in a boost configuration (see Figure below). The
gate driver is available in the three package options: A standard PG-DSO-8, a thin PG-WSON-8 and PG-TSSOP-
8 (small size DSO 8 package).
Figure 0-1 Typical Application
INB
INA
From Controller
2EDN752x /
2EDN852x
GND VDD
OUTA
CVDD
ENB
OUTB
VDD
ENA
Load1 Load2
1
2
3
45
6
7
8
2
3
4
8
7
6
5
R
g1
R
g2
M
1
M
2
Data Sheet 6 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1 Product Versions
The 2EDN752x / 2EDN852x is available in 2 different logic, 2 different undervoltage lockout and 3 package
versions.
1.1 Undervoltage Lockout Versions
The two Undervoltage Lockout versions are indicated by the variable x in the product version 2EDNy52x:
• y=7: lower voltage level (4.2V)
• y=8: higher voltage level (8.0V)
Please go to the functional description section for more details in Chapter 4 Undervoltage Lockout (UVLO).
Table 1-1 Product Versions
Part Number Description Package Order Code IC Topside
Marking Code
2EDN7524F standard input. standard UVLO PG-DSO-8 SP001339264 2N7524AF
EiceDRIV
XXHYYWW
2EDN7524R standard input, standard UVLO PG-TSSOP-8 SP001391096 2N7524
AR_XXX
HYYWW
2EDN8524R standard input, super junction
UVLO
PG-TSSOP-8 SP001391100 2N8524
AR_XXX
HYYWW
2EDN7523F inverted input, standard UVLO PG-DSO-8 SP001358244 2N7523AF
EiceDRIV
XXHYYWW
2EDN7524G standard input, standard UVLO PG-WSON-8 SP001391108 2N7524
AG_XXX
HYYWW
2EDN7523R inverted input. standard UVLO PG-TSSOP-8 SP001391098 2N7523
AR_XXX
HYYWW
2EDN8523R inverted input. super junction
UVLO
PG-TSSOP-8 SP001391102 2N8523
AR_XXX
HYYWW
2EDN7523G inverted input. standard UVLO PG-WSON-8 SP001391114 2N7523
AG_XXX
HYYWW
Data Sheet 7 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1.2 Logic Versions
The 2 logic versions are indicated by the variable y in the product version 2EDNy52x:
• x=3: inverting
• x=4: standard (non-inverting)
The logic relations between inputs, enable pins and outputs are given in Table 1-2 for the inverting and
standard version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the
respective input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or
an undervoltage lockout event, due to low voltage at VDD, causes the respective output to be low too,
regardless of the input signal.
1.3 Package Versions
Most of the logic versions and UVLO versions are available in 3 different packages.
• a standard PG-DSO-8 (designated by “F”)
• a leadless PG-WSON-8 (designated by “G”)
• a small PG-TSSOP-8 (designated by “R”)
Drawings can be viewed in Chapter 8 Outline Dimensions.
Table 1-2 Logic Table
Inputs Output Inverting Output non-inverting
ENA ENB INA INB UVLO1)
1) Active means that Vcc is above UVLO threshold voltage and release logic to control output stage.
Inactive means that UVLO disabel active the output stage.
OUTA OUTB OUTA OUTB
xxxxactiveL LL L
LLxxinactiveL L L L
HL L xinactiveH L L L
HLHxinactiveL L H L
LHx LinactiveL H L L
LHxHinactiveL L L H
HH L LinactiveH H L L
HHH LinactiveL H H L
HH LHinactiveH L L H
HHHHinactiveL L H H
Data Sheet 8 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
2 Pin Configuration and Description
The pin configuration for the inverting and standard input version of 2EDN7524F and 2EDN7523F in the PG-
DSO-8 package is shown in Figure 2-1.
Figure 2-1 Pin Configuration PG-DSO-8, Top View
Table 2-1 Pin Configuration 2EDN7524F and 2EDN7523F in the PG-DSO-8 Package
Pin Symbol Description
1 ENA Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2 INA Input signal channel A
Logic input, controlling OUTA (inverting or non-inverting)
3 GND Ground
4 INB Input signal channel B
Logic input, controlling OUTB (inverting or non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD Positive supply voltage
Operating range 4.5 to 20V
7 OUTA Driver output channel A
Low-impedance output with source and sink capability
8 ENB Enable input channel B
Logic Input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
1
2
3
4
8
7
6
5
ENA
INA
GND
INB
ENB
OUTA
VDD
OUTB
Data Sheet 9 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for standard input version of 2EDN7524R, 2EDN8524R, 2EDN7523R and 2EDN8523R in
the PG-TSSOP-8 package is shown in Figure 2-2.
Figure 2-2 Pin Configuration PG-TSSOP-8, Top View
Heat sink of PG-TSSOP-8 packages has to be connected to GND pin.
Table 2-2 Pin Configuration 2EDN7524R, 2EDN8524R, 2EDN7523R and 2EDN8523R in the PG-TSSOP-8
Package
Pin Symbol Description
1 ENA Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2 INA Input signal channel A
Logic input, controlling OUTA (non-inverting)
3 GND Ground
4 INB Input signal channel B
Logic input, controlling OUTB (non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD Positive supply voltage
Operating range 4.5 to 20V
7 OUTA Driver output channel A
Low-impedance output with source and sink capability
8 ENB Enable input channel B
Logic Input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
1
2
3
4
8
7
6
5
ENB
OUTA
VDD
OUTB
GND
ENA
INA
INB
Heat
Sink
Data Sheet 10 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for standard input version of 2EDN7524G and 2EDN7523G. In the PG-WSON-8 package
is shown in Figure 2-3.
Figure 2-3 Pin Configuration PG-WSON-8, Top View
Heat sink of PG-WSON-8 packages has to be connected to GND pin.
Table 2-3 Pin Configuration 2EDN7524G and 2EDN7523Gin the PG-WSON-8 Package
Pin Symbol Description
1 ENA Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2 INA Input signal channel A
Logic input, controlling OUTA (non-inverting)
3 GND Ground
4 INB Input signal channel B
Logic input, controlling OUTB (non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD Positive supply voltage
Operating range 4.5 to 20V
7 OUTA Driver output channel A
Low-impedance output with source and sink capability
8 ENB Enable input channel B
Logic Input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
8
7
6
5
ENB
OUTA
VDD
OUTB
GND
ENA
INA
INB
Heat
Sink
2
3
4
1
Data Sheet 11 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Block Diagram
3 Block Diagram
A simplified functional block diagram for the non-inverted version is given in Figure 3-1
Figure 3-1 Block Diagram, standard input, pull-up/pull-down resistor configuration
INA
1
2
6
7OUTA
UVLO
Logic A
ENA
VDD
INB
8
4
5
Logic B
ENB
3
GND
OUTB
GND
VDD
VDD
VDD
VDD
GND
GND
GND
40 0k
40 0k
10 0k
10 0k
Data Sheet 12 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Block Diagram
A simplified functional block diagram for the inverted version is given in Figure 3-2.
Figure 3-2 Block Diagram, inverting input, pull-up/pull-down resistor configuration
INA
1
2
6
7OUTA
UVLO
Logic A
ENA
VDD
INB
8
4
5
Logic B
ENB
3
GND
OUTB
VDD
VDD
VDD
VDD
GND
GND
GND
VDD
VDD
40 0k
40 0k
40 0k 40 0k
Data Sheet 13 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
4 Functional Description
4.1 Introduction
The 2EDN752x / 2EDN852x is a fast dual-channel driver for low-side switches. Two true rail-to-rail output
stages with very low output impedance and high current capability are chosen to ensure highest flexibility and
cover a high variety of applications.
The focus on robustness at input and output side gives this device even a safety margin on critical abnormal
situations. An extended negative voltage range protects input pins against ground shifts. No current flows
over the ESD structure of the IC during a negative input level. All outputs are robust against reverse current.
The interaction with the power MOSFET, even reverse reflected power can be covered by the strong internal
output stage.
All inputs are compatible with LVTTL signal levels. The threshold voltages with a typical hysteresis of 1V are
kept constant over the supply voltage range.
Since the 2EDN752x / 2EDN852x aims particularly at fast-switching applications, signal delays and rise/fall
times have been minimized. Special effort has been made towards minimizing delay differences between the
2 channels to very low values of typically 1ns.
4.2 Supply Voltage
The maximum supply voltage is 20V. This high voltage can be valuable in order to exploit the full current
capability of 2EDN752x / 2EDN852x when driving very large MOSFETs. The minimum operating supply voltage
is set by the undervoltage lockout function to a typical default value of 4.2V or of 8V. This lockout function
protects power MOSFET from running into linear mode with high power dissipation.
4.3 Input Configurations
As described in Chapter 1, 2EDN752x / 2EDN852x is available in 2 different configurations with respect to the
logic configuration of the 4 input pins (input plus enable).
The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left
open. The standard PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on
event during power up and a not driven input condition. Version with inverted PWM input have a internal pull
up resistor to prevent unwanted switch-on.
All inputs are compatible with LVTTL levels and provide a hysteresis of 1V typ. It is independent of the supply
voltage.
All input pins have a negative extended voltage range. This prevents cross current over single wires during
GND shifts between signal source (controller) and driver input.
4.4 Driver Outputs
The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical
5A of sourcing and sinking current. This output stage has a shoot through protection and current limiting
behavior. The on-resistance is very low with a typical value below 0.7 Ω for the sourcing p-channel MOS and
0.5 Ω for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for
achieving real rail-to-rail behaviour and not suffering from a source follower’s voltage drop.
Data Sheet 14 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
Gate Drive Outputs held active low in case of floating inputs ENx, INx or during startup or power down once
UVLO is not exceeded. Under any situation, startup, UVLO or shutdown, outputs are held under defined
conditions.
4.5 Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the output can be switched to its high level only, if the supply
voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not
operated if the driving voltage is too low to completely switch it on, thereby avoiding excessive power
dissipation.
The default UVLO level is set to a typical value of 4.2V / 8V (with some hysteresis). UVLO of 4.2V is normally used
for low voltage and TTL based MOSFETs. For higher level, like high voltage super junction MOSFETS, an active
voltage of minimum 8V version is available.
Data Sheet 15 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
5 Characteristics
The absolute maximum ratings are listed in Table 5-1. Stresses beyond these values may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
5.1 Absolute Maximum Ratings
5.2 Thermal Characteristics
Table 5-1 Absolute Maximum Ratings
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Positive supply voltage VVDD -0.3 22 V
Voltage at pins INA, INB, ENA,
ENB
VIN -10 22 V
Voltage at pins OUTA, OUTB VOUT -0.3 VVDD+0.3 V Note1)
1) Voltage spikes resulting from reverse current peaks are allowed.
Reverse current peak at pins
OUTA, OUTB
ISNK_rev
ISRC_rev
-5
5
Apk < 500ns2)
2) ISNK_rev < -2A or ISRC_rev > 2 A may reduce life time; No limitation by design; Parameter verified by design, not 100%
tested in production; max. power dissipation must be observed (see Figure 7-8)
Junction temperature TJ-40 150 °C
Storage temperature TS-55 150 °C
ESD capability VESD 1.5 kV Charged Device Mode
(CDM) 3)
3) According to JESD22-C101
2.5 kV Human Body Model
(HBM) 4)
4) According to JESD22-A114
Table 5-2 Thermal Characteristics
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Thermal resistance junction-
ambient 1)
RthJA25 125 K/W PG-DSO-8, Tamb=25°C
Thermal resistance junction-
case (top) 2)
RthJC25 66 K/W PG-DSO-8, Tamb=25°C
Thermal resistance junction-
board 3)
RthJB25 62 K/W PG-DSO-8, Tamb=25°C
Characterization parameter
junction-top 4)
ΨthJC25 16 K/W PG-DSO-8, Tamb=25°C
Data Sheet 16 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Characterization parameter
junction-board 5)
ΨthJB25 55 K/W PG-DSO-8, Tamb=25°C
Thermal resistance junction-
ambient 1)
RthJA25 64 K/W PG-TSSOP-8, Tamb=25°C
Thermal resistance junction-
case (top) 2)
RthJP25 56 K/W PG-TSSOP-8, Tamb=25°C
Thermal resistance junction-
board 3)
RthJB25 55 K/W PG-TSSOP-8, Tamb=25°C
Characterization parameter
junction-top 4)
ΨthJC25 9 K/W PG-TSSOP-8, Tamb=25°C
Characterization parameter
junction-board 5)
ΨthJB25 13 K/W PG-TSSOP-8, Tamb=25°C
Thermal resistance junction-
ambient 1)
RthJA25 61 K/W PG-WSON-8, Tamb=25°C
Thermal resistance junction-
case (top) 2)
RthJP25 54 K/W PG-WSON-8, Tamb=25°C
Thermal resistance junction-
board 3)
RthJB25 52 K/W PG-WSON-8, Tamb=25°C
Characterization parameter
junction-top 4)
ΨthJC25 8 K/W PG-WSON-8, Tamb=25°C
Characterization parameter
junction-board 5)
ΨthJB25 11 K/W PG-WSON-8, Tamb=25°C
1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-
standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No
specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to
control the PCB temperature, as described in JESD51-8.
4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and
is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
Table 5-2 Thermal Characteristics
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Data Sheet 17 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
5.3 Operating Range
5.4 Electrical Characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They
are valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at TJ=25°C.
Table 5-3 Operating Range
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Supply voltage VVDD 4.5 20 V Min defined by UVLO
Logic input voltage VIN -5 20 V
Junction temperature TJ-40 150 °C 1)
1) Continuous operation above 125 °C may reduce life time.
Table 5-4 Power Supply
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
VDD quiescent current IVDDqu1 0.5 0.7 1.2 mA OUT = high, VVDD=12V
VDD quiescent current IVDDqu2 0.3 0.48 0.7 mA OUT = low, VVDD=12V
Table 5-5 Undervoltage Lockout Standard MOSFET Version
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO)
turn on threshold
UVLOon 3.9 4.2 4.5 V
Undervoltage Lockout (UVLO)
turn off threshold
UVLOoff 3.6 3.9 4.2 V
UVLO threshold hysteresis UVLOhys 0.3 V
Table 5-6 Undervoltage Lockout Superjunction MOSFET Version
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Undervoltage Lockout (UVLO)
turn on threshold
UVLOon 7.4 8.0 8.6 V
Undervoltage Lockout (UVLO)
turn off threshold
UVLOoff 6.5 7.0 7.5 V
UVLO threshold hysteresis UVLOhys —1.0—V
Data Sheet 18 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 5-7 Logic Inputs INA, INB, ENA, ENB
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input voltage threshold for
transition LH
VINH 1.9 2.1 2.3 V
Input voltage threshold for
transition HL
VINL 0.8 1.0 1.2 V
Input pull up resistor1)
1) Inputs with initial high logic level
RIN H 400 kΩ
Input pull down resistor2)
2) Inputs with initial low logic level
RIN L 100 kΩ
Table 5-8 Static Output Caracteristics (see Figure 6-2)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
High Level (Sourcing) Output
Resistance
Ron_SNK 0.35 0.7 1.2 Ω I
SNK = 50mA
High Level (Sourcing) Output
Current
ISNK_peak 5.0 1)
1) Active limited by design at apox. 6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
A
Low Level (Sinking) Output
Resistance
Ron_SRC 0.28 0.55 1.0 Ω I
SRC = 50mA
High Level (Sinking) Output
Current
ISRC_Peak -5.0 2)
2) Active limited by design at apox. -6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
A
Data Sheet 19 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 5-9 Dynamic Characteristics (see Figure 6-1, Figure 6-2, Figure 6-3 and Figure 6-4)
Parameter Symbol Values Unit Note or Test Condition
Min. Typ. Max.
Input/Enable to output
propagation delay
TPDON 15 19 25 ns CLOAD= 1.8 nF, VVDD=12V
Input/Enable to output
propagation delay
TPDOFF 15 19 25 ns CLOAD= 1.8 nF, VVDD=12V
Input/Enable to output
propagation delay mismatch
between channels
DtPD 14ns
Rise Time TRISE —5.310
1)
1) Parameter verified by design, not 100% tested in production.
ns CLOAD= 1.8 nF, VVDD=12V
Fall Time TFAll —4.510
1) ns CLOAD= 1.8 nF, VVDD=12V
Minimum input pulse width
that changes output state
TPW —1020nsC
LOAD= 1.8 nF, VVDD=12V
Data Sheet 20 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Timing Diagrams
6 Timing Diagrams
Figure 6-1 shows the definition of rise, fall and delay times for the inputs of the non-inverting version (with
Enable pin high or open).
Figure 6-1 Propagation delay, rise and fall time, non-inverted
Figure 6-2 shows the definition of rise, fall and delay times for the inputs of the inverting version (with enable
pins high or open).
Figure 6-2 Propagation delay, rise and fall Time, inverted
Figure 6-3 illustrates the undervoltage lockout function.
Figure 6-3 UVLO behaviour, input ENx and INx drives OUT normally high
INx
OUT
T
PDON
V
IN H
90%
T
PDOFF
T
RISE
T
FAL L
10%
V
IN L
ENx
V
IN H
V
IN L
(high)
INx
VINH
VINL
OUT
T
PDON
T
PDOFF
T
RISE
T
FAL L
ENx
V
IN H
V
IN L
90%
10%
(high)
OUT
VDD
UVLO
on
UVLO
off
Data Sheet 22 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
7 Typical Characteristics
Figure 7-1 Undervoltage lockout
Figure 7-2 Input (INx) characteristic
3,7
3,9
4,1
4,3
4,5
-50 0 50 100 150
UVLO on [V]
T junction [°C]
UVLO_ON
vs
TEMPERATURE
on value
off value
VDD=12V
0
0,2
0,4
0,6
-50 0 50 100 150
UVLO hys [V]
T junction [°C]
UVLO_HYS
vs
TEMPERATURE
VDD=12V
0,7
1,1
1,5
1,9
2,3
2,7
-50 0 50 100 150
VIN [V]
T junction [°C]
VINL / VINH INx to OUTx
vs
TEMPERATURE
typ VINH
typ VINL
VDD=12V
0,9
1
1,1
1,2
-50 0 50 100 150
Vin_hys ENx [V]
T junction [°C]
VIN_HYS ENx
vs
TEMPERATURE
VDD=12V
Data Sheet 23 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
Figure 7-3 Input (ENx) characteristic
Figure 7-4 Propagation delay (INx) on different input logic levels (see Figure 6-1)
0,7
1,1
1,5
1,9
2,3
2,7
-50 0 50 100 150
VIN ENx [V]
T junction [°C]
VINL / VINH ENx to OUTx
vs
TEMPERATURE
typ VENH
typ VENL
VDD=12V
0,9
1
1,1
1,2
-50 0 50 100 150
Vin_hys ENx [V]
T junction [°C]
VIN_HYS ENx
vs
TEMPERATURE
VDD=12V
15
17,5
20
22,5
25
-50 0 50 100 150
T PD_ON [ns]
T junction [°C]
VINx to OUTx Propagation Delay
vs
TEMPERATURE
typ T PD_ON
typ T PD_OFF
VDD=12V
Input 3.3V
15
17,5
20
22,5
25
-50 0 50 100 150
T PD_ON [ns]
T junction [°C]
VINx to OUTx Propagation Delay
vs
TEMPERATURE
typ T PD_ON
typ T PD_OFF
VDD=12V
Input 5V
Data Sheet 24 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
Figure 7-5 Propagation delay (ENx) on different input logic levels (see Figure 6-1)
Figure 7-6 Rise / fall times with load on output (see Figure 6-1)
15
17,5
20
22,5
25
-50 0 50 100 150
T PD_ON [ns]
T junction [°C]
VENx to OUTx Propagation Delay
vs
TEMPERATURE
typ T PD_ON
typ T PD_OFF
VDD=12V
Enable 3.3V
15
17,5
20
22,5
25
-50 0 50 100 150
T PD_ON [ns]
T junction [°C]
VENx to OUTx Propagation Delay
vs
TEMPERATURE
typ T PD_ON
typ T PD_OFF
VDD=12V
Enable 5V
VDD=12V
Enable 5V
3,5
4
4,5
5
5,5
6
6,5
-50 0 50 100 150
T PD_ON [ns]
T junction [°C]
OUTx Rise /Fall Time 10% - 90%
vs
TEMPERATURE
typ T Rrise
typ T Fall
VDD=12V
OUTx with 1.8nF load
Data Sheet 25 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
Figure 7-7 Power consumption related to temperature, supply voltage and frequency
0,2
0,4
0,6
0,8
01020
Idd [mA]
Vdd [V]
Power Consumption
vs
VDD Supply Voltage
OUTx High
OUTx Low
Tj=25°C
0,20
0,35
0,50
0,65
0,80
-50 0 50 100 150
Idd [mA]
T junction [°C]
Power Consumption
vs
TEMPERATURE
OUTx High
OUTx Low
VDD=12V
ENx NC
both channel in
0
10
20
30
40
50
0 250 500 750 1000
I DD [mA]
Frequency [kHz]
Power Consumption
vs
Frequency
VDD 4,5V
VDD 12V
VDD 20V
Tamb 25°C
Input 50%@3.3V
Device self-heating
Load 1.8nF serial
Data Sheet 26 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
Figure 7-8 Output OUTx with reverse current and resulting power dissipation
0,0
1,5
3,0
4,5
6,0
7,5
0,8 1,0 1,3 1,5 1,8 2,0
I OUT [A ]
U OUT [V]
Reverse Current
at OUTx
with High Side Active
10 W
7.5 W
5 W
2.5 W
Test Conditions:
Tj = 25°C,
1µs positive Pulse
fsw = 1kHz
-7,5
-6,0
-4,5
-3,0
-1,5
-2,3 -2,0 -1,8 -1,5 -1,3 -1,0
I OUT [A ]
U OUT [V]
Reverse Current
at OUTx
with Low Side Active
10 W
7.5 W
5 W
2.5 W
Test Conditions:
Tj = 25°C,
1µs negative Pulse
fsw = 1kHz
Data Sheet 27 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
8 Outline Dimensions
Figure 8-1 PG-DSO-8
Data Sheet 28 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Figure 8-2 PG-TSSOP-8 (see notes)
Data Sheet 29 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Figure 8-3 PG-TSSOP-8
Data Sheet 30 Revision 2.0, 2015-07-22
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Notes
1. For further information on package types, recommendation for board assembly, please go to:
http://www.infineon.com/cms/en/product/technology/packages/.
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I2RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-
d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™,
SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,
UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of
Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay
Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association
Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave
Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of
Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
Edition 2015-07-22
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG.
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