DDATA SHEET
Product specification June 2001
DISCRETE SEMICONDUCTORS
BT136X series E
Triacs
sensitive gate
NXP Semiconductors Product specification
Triacs BT136X series E
sensitive gate
GENERAL DESCRIPTION QUICK REFERENCE DATA
Passivated, sensitive gate triacs in a SYMBOL PARAMETER MAX. MAX. UNIT
full pack plastic envelope, intended for
use in general purpose bidirectional BT136X- 600E 800E
switching and phase control VDRM Repetitive peak off-state 600 800 V
applications, where high sensitivity is voltages
required in all four quadrants. IT(RMS) RMS on-state current 4 4 A
ITSM Non-repetitive peak on-state 25 25 A
current
PINNING - SOT186A PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 main terminal 1
2 main terminal 2
3 gate
case isolated
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
-600 -800
VDRM Repetitive peak off-state - 6001800 V
voltages
IT(RMS) RMS on-state current full sine wave; Ths 92 ˚C - 4 A
ITSM Non-repetitive peak full sine wave; Tj = 25 ˚C prior to
on-state current surge
t = 20 ms - 25 A
t = 16.7 ms - 27 A
I2tI
2t for fusing t = 10 ms - 3.1 A2s
dIT/dt Repetitive rate of rise of ITM = 6 A; IG = 0.2 A;
on-state current after dIG/dt = 0.2 A/μs
triggering T2+ G+ - 50 A/μs
T2+ G- - 50 A/μs
T2- G- - 50 A/μs
T2- G+ - 10 A/μs
IGM Peak gate current - 2 A
VGM Peak gate voltage - 5 V
PGM Peak gate power - 5 W
PG(AV) Average gate power over any 20 ms period - 0.5 W
Tstg Storage temperature -40 150 ˚C
TjOperating junction - 125 ˚C
temperature
T1T2
G
123
case
1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may
switch to the on-state. The rate of rise of current should not exceed 3 A/μs.
June 2001 1 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Visol R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - - 2500 V
three terminals to external waveform;
heatsink R.H. 65% ; clean and dustfree
Cisol Capacitance from T2 to external f = 1 MHz - 10 - pF
heatsink
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-hs Thermal resistance full or half cycle
junction to heatsink with heatsink compound - - 5.5 K/W
without heatsink compound - - 7.2 K/W
Rth j-a Thermal resistance in free air - 55 - K/W
junction to ambient
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IGT Gate trigger current VD = 12 V; IT = 0.1 A
T2+ G+ - 2.5 10 mA
T2+ G- - 4.0 10 mA
T2- G- - 5.0 10 mA
T2- G+ - 11 25 mA
ILLatching current VD = 12 V; IGT = 0.1 A
T2+ G+ - 3.0 15 mA
T2+ G- - 10 20 mA
T2- G- - 2.5 15 mA
T2- G+ - 4.0 20 mA
IHHolding current VD = 12 V; IGT = 0.1 A - 2.2 15 mA
VTOn-state voltage IT = 5 A - 1.4 1.70 V
VGT Gate trigger voltage VD = 12 V; IT = 0.1 A - 0.7 1.5 V
VD = 400 V; IT = 0.1 A; Tj = 125 ˚C 0.25 0.4 - V
IDOff-state leakage current VD = VDRM(max); Tj = 125 ˚C - 0.1 0.5 mA
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
dVD/dt Critical rate of rise of VDM = 67% VDRM(max); Tj = 125 ˚C; - 50 - V/μs
off-state voltage exponential waveform; gate open circuit
tgt Gate controlled turn-on ITM = 6 A; VD = VDRM(max); IG = 0.1 A; - 2 - μs
time dIG/dt = 5 A/μs
June 2001 2 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
Fig.1. Maximum on-state dissipation, Ptot, versus rms
on-state current, IT(RMS), where α = conduction angle.
Fig.2. Maximum permissible non-repetitive peak
on-state current ITSM, versus pulse width tp, for
sinusoidal currents, tp 20ms.
Fig.3. Maximum permissible non-repetitive peak
on-state current ITSM, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
Fig.4. Maximum permissible rms current IT(RMS) ,
versus heatsink temperature Ths.
Fig.5. Maximum permissible repetitive rms on-state
current IT(RMS), versus surge duration, for sinusoidal
currents, f = 50 Hz; Ths 92˚C.
Fig.6. Normalised gate trigger voltage
VGT(Tj)/ VGT(25˚C), versus junction temperature Tj.
012345
0
1
2
3
4
5
6
7
8
= 180
120
90
60
30
IT(RMS) / A
Ptot / W Ths(max) / C
125
119.5
114
108.5
103
97.5
92
86.5
81
1
-50 0 50 100 150
0
1
2
3
4
5BT136X
92 C
Ths / C
IT(RMS) / A
10us 100us 1ms 10ms 100ms
10
100
1000
T / s
ITSM / A
TITSM
time
I
Tj initial = 25 C max
T
dI /dt limit
T
T2- G+ quadrant
0.01 0.1 1 10
0
2
4
6
8
10
12
surge duration / s
IT(RMS) / A
1 10 100 1000
0
5
10
15
20
25
30 BT136
Number of cycles at 50Hz
ITSM / A
TITSM
time
I
Tj initial = 25 C max
T
-50 0 50 100 150
0.4
0.6
0.8
1
1.2
1.4
1.6
Tj / C
VGT(Tj)
VGT(25 C)
June 2001 3 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
Fig.7. Normalised gate trigger current
IGT(Tj)/ IGT(25˚C), versus junction temperature Tj.
Fig.8. Normalised latching current IL(Tj)/ IL(25˚C),
versus junction temperature Tj.
Fig.9. Normalised holding current IH(Tj)/ IH(25˚C),
versus junction temperature Tj.
Fig.10. Typical and maximum on-state characteristic.
Fig.11. Transient thermal impedance Zth j-hs, versus
pulse width tp.
Fig.12. Typical, critical rate of rise of off-state voltage,
dVD/dt versus junction temperature Tj.
-50 0 50 100 150
0
0.5
1
1.5
2
2.5
3
Tj / C
IGT(Tj)
IGT(25 C)
T2+ G+
T2+ G-
T2- G-
T2- G+
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
12
VT / V
IT / A
Tj = 125 C
Tj = 25 C typ max
Vo = 1.27 V
Rs = 0.091 ohms
-50 0 50 100 150
0
0.5
1
1.5
2
2.5
3
Tj / C
IL(Tj)
IL(25 C)
10us 0.1ms 1ms 10ms 0.1s 1s 10s
0.01
0.1
1
10
tp / s
Zth j-hs (K/W)
tp
P
t
D
unidirectional
with heatsink compound
without heatsink compound
bidirectional
-50 0 50 100 150
0
0.5
1
1.5
2
2.5
3
Tj / C
IH(Tj)
IH(25C)
0 50 100 150
1
10
100
1000
Tj / C
dVD/dt (V/us)
June 2001 4 Rev 1.400
1;3 Semiconductors Product specification
Triacs BT136X series E
sensitive gate
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Fig.13. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Refer to mounting instructions for F-pack envelopes.
2. Epoxy meets UL94 V0 at 1/8".
10.3
max
3.2
3.0
4.6
max
2.9 max
2.8
seating
plane
6.4
15.8
max
0.6
2.5
2.54
5.08
123
3 max.
not tinned
3
0.5
2.5
0.9
0.7
M
0.4
15.8
max. 19
max.
13.5
min.
Recesses (2x)
2.5
0.8 max. depth
1.0 (2x)
1.3
June 2001 5 Rev 1.400
NXP Semiconductors
Legal information
DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
DEFINITIONS
Product specification The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer , unless NXP
Semiconductors and customer have exp licitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
DISCLAIMERS
Limited warranty and liability Information in this
document is believed to be a ccur ate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, specia l or co nsequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards custo m er for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product d escr iptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-cri tical or safety-critic al systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to res ult in personal inj ur y, de ath or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductor s pr od ucts in such equipment or
application s an d therefore suc h inc lusion and/or use is at
the customer’s own risk.
Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is su itable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimi ze the risks
associated with their applicatio ns an d products.
NXP Semiconductors
Legal information
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is b ased
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is respon sible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in orde r to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stre ss ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommende d
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreemen t. In cas e an
individual agreement is concluded only the terms and
conditions of the respective a greement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors prod ucts by customer.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the gran t, conveyance or
implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the p roduct data giv en in the Limiting values an d
Characteristics sections of this document, and as such is
not complete, exhaustive or leg ally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified prod uc ts in au t omo tive equipment or
applications.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such au tomo tive applications, use and
specifications, and (b) whenever customer uses the
product for automotive app lications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liab ility, damages or failed
product clai ms r esult ing fr om cus to mer d esign and use o f
the product for automotive applications beyond NXP
Semiconductors’ standard wa rranty and NXP
Semiconductors’ product specifications.
Contact information
For additional inf ormation please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
Customer notification
This data sheet was changed to reflect the ne w company name NXP Semiconductors, including new legal defin itions
and disclaimers. No changes were made to the content, except for the legal defin itions and disclaimers.
© NXP B.V. 2011
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information prese nted in this docu ment doe s not form p art of any qu otation or co ntract, is belie ved to be accurat e and re liable and may be chan ged without
notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellect ual property rights.
Printed in The Netherlands