DISCRETE SEMICONDUCTORS DATA SHEET BT136X series E Triacs sensitive gate Product specification June 2001 NXP Semiconductors Product specification Triacs sensitive gate GENERAL DESCRIPTION Passivated, sensitive gate triacs in a full pack plastic envelope, intended for use in general purpose bidirectional switching and phase control applications, where high sensitivity is required in all four quadrants. PINNING - SOT186A PIN BT136X series E QUICK REFERENCE DATA SYMBOL VDRM IT(RMS) ITSM PARAMETER MAX. MAX. UNIT BT136XRepetitive peak off-state voltages RMS on-state current Non-repetitive peak on-state current 600E 600 800E 800 V 4 25 4 25 A A PIN CONFIGURATION SYMBOL DESCRIPTION case 1 main terminal 1 2 main terminal 2 3 gate T2 T1 G 1 2 3 case isolated LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER VDRM Repetitive peak off-state voltages IT(RMS) ITSM RMS on-state current Non-repetitive peak on-state current I2t dIT/dt IGM VGM PGM PG(AV) Tstg Tj I2t for fusing Repetitive rate of rise of on-state current after triggering Peak gate current Peak gate voltage Peak gate power Average gate power Storage temperature Operating junction temperature CONDITIONS MIN. - full sine wave; Ths 92 C full sine wave; Tj = 25 C prior to surge t = 20 ms t = 16.7 ms t = 10 ms ITM = 6 A; IG = 0.2 A; dIG/dt = 0.2 A/s T2+ G+ T2+ GT2- GT2- G+ over any 20 ms period MAX. -600 6001 UNIT -800 800 V - 4 A - 25 27 3.1 A A A2s -40 - 50 50 50 10 2 5 5 0.5 150 125 A/s A/s A/s A/s A V W W C C 1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may switch to the on-state. The rate of rise of current should not exceed 3 A/s. June 2001 1 Rev 1.400 1;3 Semiconductors Product specification Triacs sensitive gate BT136X series E ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Visol R.M.S. isolation voltage from all three terminals to external heatsink f = 50-60 Hz; sinusoidal waveform; R.H. 65% ; clean and dustfree - - 2500 V Cisol Capacitance from T2 to external f = 1 MHz heatsink - 10 - pF MIN. TYP. MAX. UNIT - 55 5.5 7.2 - K/W K/W K/W MIN. TYP. MAX. UNIT T2+ G+ T2+ GT2- GT2- G+ - 2.5 4.0 5.0 11 10 10 10 25 mA mA mA mA T2+ G+ T2+ GT2- GT2- G+ VD = 12 V; IGT = 0.1 A IT = 5 A VD = 12 V; IT = 0.1 A VD = 400 V; IT = 0.1 A; Tj = 125 C VD = VDRM(max); Tj = 125 C 0.25 - 3.0 10 2.5 4.0 2.2 1.4 0.7 0.4 0.1 15 20 15 20 15 1.70 1.5 0.5 mA mA mA mA mA V V V mA MIN. TYP. MAX. UNIT - 50 - V/s - 2 - s THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Rth j-a Thermal resistance junction to ambient full or half cycle with heatsink compound without heatsink compound in free air STATIC CHARACTERISTICS Tj = 25 C unless otherwise stated SYMBOL PARAMETER CONDITIONS IGT Gate trigger current VD = 12 V; IT = 0.1 A IL Latching current IH VT VGT Holding current On-state voltage Gate trigger voltage ID Off-state leakage current VD = 12 V; IGT = 0.1 A DYNAMIC CHARACTERISTICS Tj = 25 C unless otherwise stated SYMBOL PARAMETER CONDITIONS dVD/dt Critical rate of rise of off-state voltage Gate controlled turn-on time VDM = 67% VDRM(max); Tj = 125 C; exponential waveform; gate open circuit ITM = 6 A; VD = VDRM(max); IG = 0.1 A; dIG/dt = 5 A/s tgt June 2001 2 Rev 1.400 1;3 Semiconductors Product specification Triacs sensitive gate 8 BT136X series E Ptot / W Ths(max) / C 5 81 IT(RMS) / A BT136X 86.5 7 6 = 180 1 92 C 4 92 120 5 97.5 90 60 4 3 103 30 3 108.5 2 114 1 119.5 2 1 0 0 1 2 3 IT(RMS) / A 125 5 4 0 -50 50 Ths / C 100 150 Fig.4. Maximum permissible rms current IT(RMS) , versus heatsink temperature Ths. Fig.1. Maximum on-state dissipation, Ptot, versus rms on-state current, IT(RMS), where = conduction angle. 1000 0 ITSM / A 12 IT(RMS) / A ITSM IT 10 T time 8 Tj initial = 25 C max 100 6 dIT /dt limit 4 T2- G+ quadrant 2 10 10us 100us 1ms T/s 10ms 0 0.01 100ms Fig.2. Maximum permissible non-repetitive peak on-state current ITSM, versus pulse width tp, for sinusoidal currents, tp 20ms. 30 ITSM / A BT136 T 1.4 time Tj initial = 25 C max 1.2 15 1 10 0.8 5 0.6 0 1 10 100 Number of cycles at 50Hz 0.4 -50 1000 Fig.3. Maximum permissible non-repetitive peak on-state current ITSM, versus number of cycles, for sinusoidal currents, f = 50 Hz. June 2001 VGT(Tj) VGT(25 C) I TSM IT 20 10 Fig.5. Maximum permissible repetitive rms on-state current IT(RMS), versus surge duration, for sinusoidal currents, f = 50 Hz; Ths 92C. 1.6 25 0.1 1 surge duration / s 0 50 Tj / C 100 150 Fig.6. Normalised gate trigger voltage VGT(Tj)/ VGT(25C), versus junction temperature Tj. 3 Rev 1.400 1;3 Semiconductors Product specification Triacs sensitive gate BT136X series E 3 IGT(Tj) IGT(25 C) 12 Tj = 125 C Tj = 25 C T2+ G+ T2+ GT2- GT2- G+ 2.5 IT / A typ 10 max Vo = 1.27 V Rs = 0.091 ohms 8 2 6 1.5 4 1 2 0.5 0 -50 0 50 Tj / C 100 0 150 0.5 1 1.5 VT / V 2 2.5 3 Fig.10. Typical and maximum on-state characteristic. Fig.7. Normalised gate trigger current IGT(Tj)/ IGT(25C), versus junction temperature Tj. 3 0 IL(Tj) IL(25 C) 10 Zth j-hs (K/W) with heatsink compound without heatsink compound 2.5 unidirectional 1 bidirectional 2 1.5 0.1 1 P D tp t 0.5 0 -50 0 50 Tj / C 100 0.01 10us 150 1ms 10ms 0.1s 1s 10s tp / s Fig.11. Transient thermal impedance Zth j-hs, versus pulse width tp. Fig.8. Normalised latching current IL(Tj)/ IL(25C), versus junction temperature Tj. 3 0.1ms IH(Tj) IH(25C) 1000 dVD/dt (V/us) 2.5 100 2 1.5 10 1 0.5 0 -50 0 50 Tj / C 100 1 150 50 100 150 Tj / C Fig.9. Normalised holding current IH(Tj)/ IH(25C), versus junction temperature Tj. June 2001 0 Fig.12. Typical, critical rate of rise of off-state voltage, dVD/dt versus junction temperature Tj. 4 Rev 1.400 1;3 Semiconductors Product specification Triacs sensitive gate BT136X series E MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 4.6 max 3.2 3.0 2.9 max 2.8 Recesses (2x) 2.5 0.8 max. depth 6.4 15.8 max. 19 max. 15.8 max seating plane 3 max. not tinned 3 2.5 13.5 min. 1 0.4 2 3 M 1.0 (2x) 0.6 2.54 0.9 0.7 0.5 2.5 5.08 1.3 Fig.13. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Refer to mounting instructions for F-pack envelopes. 2. Epoxy meets UL94 V0 at 1/8". June 2001 5 Rev 1.400 NXP Semiconductors Legal information DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. 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