WIZ810MJ Datasheet
(Ver. 1.3)
© 2013 WIZnet Co., Ltd. All Rights Reserved.
For more information, visit our website at www.wiznet.co.kr
WIZ810MJ Datasheet
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Document History Information
Revision
Data
Description
Ver. 1.0
September , 2007
Release with WIZ810MJ Launching
Ver. 1.1
February, 2008
Hardware revision(ver.1.1).
Modified the SPI_EN signal description (P.8)
Modified the Schematic & Partlist : R10 is mounted
as SPI_EN pull-down resistor. (P.15~16)
Ver. 1.2
January, 2009
Added temperature specification
Ver. 1.3
January, 2013
Hardware revision(ver.1.2)
Changed operation temperature range(P.5)
Changed Partlist and schematic
WIZ810MJ Datasheet
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WIZnet’s Online Technical Support
If you have something to ask about WIZnet Products, Write down your question
on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an
answer as soon as possible.
WIZ810MJ Datasheet
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Table of Contents
1. Introduction .............................................................................. 5
1.1. Features ............................................................................. 5
1.2. Block Diagram ...................................................................... 5
2. Pin Assignments & descriptions ................................................... 6
2.1. Pin Assignments ................................................................... 6
2.2. Power & Ground ................................................................... 6
2.3. MCU Interfaces ..................................................................... 7
2.4. Network status & LEDs ........................................................... 8
2.5. Miscellaneous Signals ............................................................ 8
3. Timing Diagrams ....................................................................... 9
3.1. Reset Timing ...................................................................... 9
3.2. Register/Memory READ Timing ............................................... 10
3.3. Register/Memory WRITE Timing .............................................. 11
3.4. SPI Timing......................................................................... 12
4. Dimensions ............................................................................. 13
5. Connector Specification ............................................................ 14
6. Schematic .............................................................................. 15
7. Partlists .................................................................................. 16
WIZ810MJ Datasheet
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1. Introduction
WIZ810MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY),
MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and no
effort is required to interface W5100 and Transformer. The WIZ810MJ is an ideal option for users
who want to develop their Internet enabling systems rapidly.
For the detailed information on implementation of Hardware TCP/IP, refer to the W5100
Datasheet.
WIZ810MJ consists of W5100 and MAG-JACK.
TCP/IP, MAC protocol layer: W5100
Physical layer: Included in W5100
Connector: MAG-JACK(RJ45 with Transformer)
1.1. Features
Supports 10/100 Base TX
Supports half/full duplex operation
Supports auto-negotiation and auto crossover detection
IEEE 802.3/802.3u Complaints
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 4 independent connections simultaneously
Supports MCU bus Interface and SPI Interface
Supports Direct/Indirect mode bus access
Supports Socket API for easy application programming
Interfaces with Two 2.0mm pitch 2 * 14 header pin
Temperature :
[PCB rev1.0] : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage)
[PCB rev1.1] : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage)
[PCB rev1.2] : -40 ~ 85℃ (Operation), -40 ~ 85℃ (Storage)
1.2. Block Diagram
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2. Pin Assignments & descriptions
2.1. Pin Assignments
I : Input O : Output
I/O : Bi-directional Input and output P : Power
2.2. Power & Ground
Symbol
Type
Pin No.
Description
VCC
P
JP1:1 , JP2:24
Power : 3.3 V power supply
GND
P
JP1:8, JP1:13, JP1:24,
JP2:1, JP2:4, JP2:7
JP2:13, JP2:14, JP2:23
Ground
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2.3. MCU Interfaces
Type
Pin No.
Description
I
JP1:7
ADDRESS PIN OR SCLK(Serial Clock)
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI Clock signal Pin.
I
JP1:10
ADDRESS PIN or /SCS (Slave Select) *
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI Slave Select signal Pin. In only SPI Mode,
this pin is active low
I
JP1:9
ADDRESS PIN or MOSI (Master Out Slave In) *
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI MOSI signal pin.
I/O
JP1:12
ADDRESS PIN or MISO (Master In Slave Out) *
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI MISO signal pin.
I
JP1:11, JP1:14
JP1:15
Address
Used as Address[10-8] pin
I
JP1:16 ~ JP1:23
Address
Used as Address[7-0] pin
I/O
JP2:21, JP2:22
JP2:19, JP2:20
JP2:17, JP2:18
JP2:15, JP2:16
Data
8 bit-wide data bus
I
JP1:5
Module Select : Active low.
/CS of W5100
I
JP1:4
Read Enable : Active low.
/RD of W5100
I
JP1:3
Write Enable : Active low
/WR of W5100
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O
JP1:2
Interrupt : Active low
After reception or transmission it indicates that
the W5100 requires MCU attention.
By writing values to the Interrupt Status Register
of W5100 the interrupt will be cleared.
All interrupts can be masked by writing values to
the IMR of W5100 (Interrupt Mask Register).
For more details refer to the W5100 Datasheet
2.4. Network status & LEDs
You can observe the network status using MAG-JACK LEDs. LED interface can be extended to
the LED of the main board.
Symbol
Type
Pin No.
Description
COL_LED
O
JP2:6
Collision LED : Active low when collisions occur.
TX_LED
O
JP2:8
Transmit activity LED : Active low indicates the
presence of transmitting activity.
RX_LED
O
JP2:10
Receive activity LED : Active low indicates the
presence of receiving activity.
FDX_LED
O
JP2:11
Full Duplex LED : Active low when in full duplex
operation. Active high when in half duplex
operation.
LINK_LED
O
JP2:12
Link LED : Active low in link state indicates a
good status for 10/100M.
It is always ON when the link is OK and it flashes
while in a TX or RX state.
2.5. Miscellaneous Signals
Symbol
Type
Pin No.
Description
/RESET
I
JP2:2
Reset : This pin is active low input to
initialize or re-initialize W5100.
By asserting this pin low for at least 2us,
all internal registers will be re-initialized
to their default states.
SPI_EN
I
JP2:9
SPI Enable : This pin selects
Enable/Disable W5100 SPI Mode.
Low = SPI Mode Disable
High = SPI Mode Enable
A pull-down resistor(R10) sets to the
default of SPI Mode Disable.
H/W ver.1.0 : R10 is not mounted
H/W ver.1.1 : R10 is mounted
NC
-
JP1 : 6, 25, 26, 27, 28
JP2 : 3, 5, 25, 26, 27, 28
Not Connect
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3. Timing Diagrams
WIZ810MJ provides following interfaces of W5100.
-. Direct/Indirect mode bus access
-. SPI access
3.1. Reset Timing
Description
Min
Max
1
Reset Cycle Time
2 us
-
2
/RESET to internal PLOCK
-
10 ms
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3.2. Register/Memory READ Timing
Description
Min
Max
1
Read Cycle Time
80 ns
-
2
Valid Address to /CS low time
8 ns
-
3
/CS low to /RD low time
-
1 ns
4
/RD high to /CS high time
-
1 ns
5
/RD low to Valid Data Output time
-
80 ns
6
/RD high to Data High-Z Output time
-
1 ns
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3.3. Register/Memory WRITE Timing
Description
Min
Max
1
Write Cycle Time
70 ns
-
2
Valid Address to /CS low time
7 ns
-
3
/CS low to /WR high time
70 ns
-
4
/CS low to /WR low time
-
1 ns
5
/WR high to /CS high time
-
1 ns
6
/WR low to Valid Data time
-
14 ns
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3.4. SPI Timing
Description
Mode
Min
Max
1 /SS low to SCLK
Slave
21 ns
-
2 Input setup time
Slave
7 ns
-
3 Input hold time
Slave
28 ns
-
4 Output setup time
Slave
7 ns
14 ns
5 Output hold time
Slave
21 ns
-
6 SCLK time
Slave
70 ns
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4. Dimensions
Symbols
Dimensions (mm)
A
48.0
B
3.5
C
25.0
D
22.4
E
18.4
F
1.0
G
2.0
H
2.0
I
16.0
J
13.5
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5. Connector Specification
UNIT:mm
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6. Schematic
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.2
WIZ810MJ
B1 1Friday, January 25, 2013
D3
D2
D4
D5
LOGO
CON1
1
CHGND
D7
D6
1V8D
R1
1M
XTLP
Y1
25MHz (SMD)
C2 15pF
C1 15pF
XTLP
R7
300 (1%)
R6
12K (1%)
XTLN
XTLN
3V3D VCC
RSET_BG
LINK_LED
FDX_LED
/CS
A6
/WR
A14_SCLK
1V8D
A8
A12_MOSI
A10
/INT
A4
A2
A0
/RD
A7
A11_MISO
A9
A1
A13_/SCS
A3
A5
COL_LED
RX_LED
FDX_LED LINK_LED
TX_LED
3V3D
D7
SPI_EN
D5
/RESET
D1 D2
D0
D6
3V3D
1V8D
D3 D4
JP1
HEADER 14X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
JP2
HEADER 14X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
3V3D
1V8D
3V3A
/RESET
1V8D
RXIP
C12
0.1uF
3V3A
RXIN
R2
49.9
R3
49.9
C3
0.1uF
C4
0.1uF
R8
49.9
R9
49.9
C5
0.1uF
TXOP
R4
200
R5
200
TXON
SPI_EN
C13
0.1uF
SCLK
C14
0.1uF
MOSI
/SCS 1V8A
C6
0.1uF
C10
0.1uF
CHGND
CHGND
MISO
/RD
/WR
1V8A
/INT
/CS
C17
3.3uF/16V C18
10uF/16V
A0
A1
1V8_OUT
A2
TX_LED
C19
10uF/16V
A3
A4
C20
0.1uF C21
0.1uF
A5
RX_LED
A6
C23
0.1uF
C22
0.1uF C24
0.1uF C25
0.1uF
TXON
TXOP
RXIP
A7
RXIN
1V8D
COL_LED
A8
U1
W5100
RSET_BG
1
VCC3V3A
2
NC
3
GNDA
4
RXIP
5
RXIN
6
VCC1V8A
7
TXOP
8
TXON
9
GNDA
10
1V8_OUT
11
VCC3V3D
12
GNDD
13
GNDD
14
VCC1V8D
15
VCC1V8D
16
GNDD
17
VCC3V3D
18
DATA7
19
DATA6
20
DATA5
21
DATA4
22
DATA3
23
DATA2
24
DATA1
25
DATA0
26
MISO
27
MOSI
28
/SCS
29
SCLK
30
SEN
31
GNDD
32
VCC1V8D
33
TEST_MODE3
34
TEST_MODE2
35
TEST_MODE1
36
TEST_MODE0
37
ADDR14
38
ADDR13
39
ADDR12
40
ADDR11 41
ADDR10 42
GNDD 43
VCC3V3D 44
ADDR9 45
ADDR8 46
ADDR7 47
ADDR6 48
ADDR5 49
ADDR4 50
ADDR3 51
ADDR2 52
ADDR1 53
ADDR0 54
/CS 55
/INT 56
/WR 57
/RD 58
/RESET 59
NC 60
NC 61
NC 62
OPMODE0 63
OPMODE1 64
OPMODE2 65
LINKLED 66
SPDLED 67
GNDD 68
VCC1V8D 69
FDXLED 70
COLLED 71
RXLED 72
TXLED 73
VCC1V8A 74
XTLN 75
XTLP 76
GNDA 77
NC 78
NC 79
NC 80
A9
FDX_LED
A12
A13
SCLK
A14
MISO
MOSI
/SCS
A11
R10
4.7K
U2
BS-RB10005
TD+
1
TD-
2
TCT
3
NC1
4
NC2
5
NC3
6
RD+
7
RD-
8
L1+
12 L2-
11 L3+
10 L4-
9
CH_GND1
13
CH_GND2
14
SPI_EN
U3
SN74CB3Q3257
S1
1B1
2
1B2
3
1A 4
2B1
5
2B2
62A 7
GND 8
3A 9
3B2
10 3B1
11 4A 12
4B2
13 4B1
14 /OE 15
VCC 16
3V3D
3V3D
A11_MISO
A12_MOSI
A13_/SCS
A14_SCLK
LINK_LED
1V8_OUT
A10
3V3D
3V3A
A11
A12
A13
A14
FB2 1uH 1V8A
C11
10uF/16V
C7
10uF/16V C9
0.01uF
FB1 1uH
3V3A3V3D
1V8A
D0
D1
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7. Partlists
Item
Q.ty
Reference
Part
Tech. Characteristics
Package
1
2
C1,C2
15pF
50V-20% Ceramic
CASE 0603
2
14
C3,C4,C5,C6,C10,
C12,C13,C14,C20,
C21,C22,C23,C24,C25
0.1uF
50V-20% Ceramic
CASE 0603
3
4
C7,C11,C18,C19
10uF/16V
16Vmin 10%
EIA/IECQ 3216
4
1
C9
0.01uF
50V-20% Ceramic
CASE 0603
5
2
FB1,FB2
1uH Chip Ferrite Inductor
CASE 0805
6
2
JP1,JP2
2X14 28PIN 2mm DIP
STRAIGHT Header
2 X 14 2mm pitch
7
1
R1
1M
1/10W-5% SMD
CASE 0603
8
4
R2,R3,R8,R9
49.9
1/10W-1% SMD
CASE 0603
9
2
R5,R4
200
1/10W-5% SMD
CASE 0603
10
1
R6
12K
1/10W-1% SMD
CASE 0603
11
1
R7
300
1/10W-1% SMD
CASE 0603
12
1
R10
4.7K
1/10W-5% SMD
CASE 0603
13
1
U1
W5100
WIZnet Hardware TCP/IP
LQFP80
14
1
U2
BS-RB10005
Transformer + RJ45
15
1
U3
SN74CB3Q3257
Bus Switch(vendor : TI)
TSSOP
16
1
Y1
25MHz (SMD)
SMD Type, CL=18pF,
Industrial.
SX-1
17
1
PCB
WIZ810MJ REV1.2 1.6T
4LAYER
FR4, OSP