CX23885 PCI Express Video and Broadcast Audio Decoder Data Sheet DSH-201010p2 February 2009 Ordering Information Model Number Description CX23885* PCI Express Video and Broadcast Audio Decoder Package 128-pin ETQFP (lead-free) *Lead-free (Pb Free) and RoHS compliant Revision History Revision Date p1 June 27, 2008 p2 February 4, 2009 Description Preliminary release. P2 release *Added Section 1.14, Crystal Oscillator. (c) 2008, 2009, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to this document at any time, without notice. Conexant advises all customers to ensure that they have the latest version of this document and to verify, before placing orders, that information being relied on is current and complete. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: Conexant(R) and the Conexant C symbol. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant's Legal Information posted at www.conexant.com which is incorporated by reference. Conexant Lead-free products are China RoHS Compliant: Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to conexant.tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer. 2 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. CX23885 PCI Express Video and Broadcast Audio Decoder Distinguishing Features The CX23885 brings Conexant Systems' long heritage of audio and video capture solutions to systems that enable PCI ExpressTM bus architectures. The family of devices integrates all the functions required to perform television and external A/V capture on personal computers or consumer electronic devices. The integrated worldwide video decoder and audio decoder can be used for a high performance, cost effective, basic analog television capture, or can be used as the base for more complex multiple tuner configurations. The devices can support capture of two simultaneous digital television transport streams, two simultaneous analog streams, or a combination of analog and digital capture. This latest generation of devices further integrates components found on a typical video capture card such as video ADC anti-alias filter components, and analog to digital converters for stereo audio capture. Quality video is accomplished by using 10-bit video ADCs and a full 10-bit video data path. For high-quality audio, a minimum of 16-bit audio resolution through the entire audio data path ensures high fidelity audio, whether it comes from the integrated broadcast audio decoder, the sigma-delta ADCs, or from an external serial audio source. The device are packaged in a 14x14 mm, lead-free 128-pin ETQFP. DSH-201010p2 2/4/09 PCI Express 1.0a compliant Worldwide audio and video decoding Automatic video and broadcast audio standard detection and configuration Flexible video input mux supporting composite, S-Video, and component inputs with integrated anti-alias filtering Integrated sigma-delta stereo audio ADCs with 4:2 mux Audio sample rate converters on all inputs and outputs Two MPEG transport stream ports--parallel and serial Two I2C master ports Macrovision 1.0 detection compliant Programmable VBI data slicer for data services such as closed caption, WSS, and program guides Infrared transmitter and receiver logic Auxiliary/Audio Phase Locked Loop (PLL) clock for general use Support for MPEG-2 encoding when used with the CX23417 Conexant Preliminary Information/Conexant Proprietary and Confidential 3 Functional Block Diagram 3 CVBS or Luma Inputs 3 2 3 CVBS, Luma, Chroma, SIF, or Pb Inputs 2 CVBS, Luma, Chroma, SIF, or Pr Inputs L/R 1 Audio In L/R 2 Audio In 4 Analog Front End CH 1 Clock, Data, Start, Valid Clock, Data[7:0], Start, Valid Clock, Data, Start, Valid Serial TS/PS Input Port or BT.656/VIP1.1 Input or Output Parallel TS/PS Input Port or BT.656/VIP1.1 Input or Output Serial TS/PS Input Port Color Space Converter and Formatter Analog Front End CH 2 Analog Front End CH 3 18-Bit Audio ADCs Video Decoder NTSC/PAL/ SECAM 10-Bit Video ADC 10-Bit Video/SIF ADC Audio Decoder BTSC/EIAJ/ A2/NICAM/ AM GPIO UART GPIO x24 RS232 Baseband Audio Vol/Tone/ Balance/Mute Color Space Converter and Formatter I2C Master 1 SCL{1} SDA{1} I2C Master 2 SCL{2} SDA{2} RISC Engine and DMA Controller PCI Express SRAM Butters TL DLL MAC x1 PCI Express PHY I/F System PLL Aux/Audio PLL Serial Audio In/Out Crystal Amplifier Video PLL 16 to 24-Bit 32, 44.1, 48, 96 kHz Single Crystal Frequency Conexant Preliminary Information/Conexant Proprietary and Confidential x1 PCI Express Audio Master Clock DSH-201010p2 2/4/09 Contents Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 Analog Video Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Integrated Clamping and Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Flexible Decoder Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High Performance Luma and Chroma Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Video Processing Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High Quality Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pixel Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Vertical Blanking Interval Slicing and Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stereo Broadcast Audio Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCI Express Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Communication and General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1 3.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory Mapped Registers: Application Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.1 Device Control #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.2 PCI Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.3 PCI Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.4 PCI Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.5 Video A Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.6 Video A Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.7 Video A Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.8 Video A Interrupt Set Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.9 Video B Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.10 Video B Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.11 Video B Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.12 Video B Interrupt Set Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.13 Video C Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.14 Video C Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 5 CX23885 Data Sheet 3.3 3.4 3.5 3.6 6 3.2.15 Video C Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.16 Video C Interrupt Set Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.17 Audio Internal Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.18 Audio Internal Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.19 Audio Internal Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.20 Audio Internal Interrupt Set Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.21 Audio External Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.22 Audio External Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.23 Audio External Interrupt Masked Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.24 Audio External Interrupt Set Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Memory Mapped Registers: DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.1 APB DMAC Current Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.2 APB DMAC Current Table Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.3 APB DMAC Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.4 APB DMAC Table Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Memory Mapped Registers: Miscellaneous Utilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.1 Timer Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.2 Timer Limit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.3 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.4 GPIO Interrupts Sensitivity Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.5 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.6 GPIO (417 Microcontroller Interface) RW Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.7 GPIO (417 Microcontroller) Output Enable, Low Active. . . . . . . . . . . . . . . . . . . . . . . 61 3.4.8 GPIO (417 Microcontroller) Output Enable, Low Active. . . . . . . . . . . . . . . . . . . . . . . 62 3.4.9 Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.4.10 Pad Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Memory Mapped Registers: Video A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.5.1 Video A General Purpose Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.5.2 Video A General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.5.3 Video A DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.5.4 Video A VIP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.5.5 Video A Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.5.6 Video A VBI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Memory Mapped Registers: Video B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.6.1 Video B General Purpose Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.6.2 Video B General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.6.3 Video B DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.6.4 Video B Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.6.5 Video B TS Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.6.6 Video B TS HW SOP Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.6.7 Video B TS General Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.6.8 Video B TS Bad Packet Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.6.9 Video B TS SOP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.6.10 Video B TS Fifo Overflow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.11 Video B TS Valid Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.6.12 Video B TS Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.6.13 Video B VIP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.6.14 Video B Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.7 Memory Mapped Registers: Video C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.7.1 Video C General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.7.2 Video C General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.7.3 Video C DMA Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.7.4 Video C TS Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.7.5 Video C TS HW SOP Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.7.6 Video C TS General Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.7.7 Video C TS Bad Packet Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.7.8 Video C TS SOP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.7.9 Video C TS Fifo Overflow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.7.10 Video C TS Valid Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.7.11 Video C TS Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.8 Memory Mapped Registers: Internal Audio Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.8.1 Audio Internal General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.8.2 Audio Internal General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.8.3 Audio Internal DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.8.4 Audio Internal Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.8.5 Audio Internal Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.9 Memory Mapped Registers: External Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.9.1 Audio External DMA Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.9.2 Audio External General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.9.3 Audio External General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.9.4 Audio External DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.9.5 Audio External Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.9.6 Audio External Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.10 Memory Mapped Registers: I2C Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.10.1 I2C Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.10.2 I2C Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.10.3 I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.10.4 I2C Read Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.10.5 I2C Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.11 Memory Mapped Registers: UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.1 UART TxD/RxD Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.2 UART Baud Rate Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.3 UART Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.11.4 UART FIFO Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.12 Rider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.12.1 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.12.2 Accessing PCI Express Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.12.3 Accessing Rider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.12.4 Register Access Exception - Vital Product Data (VPD) . . . . . . . . . . . . . . . . . . . . . . 98 3.12.5 Register Type Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.12.6 Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.12.7 Read-Write Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.12.8 Read-Only; Write-1-to-Clear Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.12.9 Sticky Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.12.10 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 7 CX23885 Data Sheet 3.12.11 3.12.12 3.12.13 3.12.14 3.12.15 3.12.16 3.12.17 3.12.18 3.12.19 3.12.20 3.12.21 3.12.22 3.12.23 3.12.24 3.12.25 3.12.26 3.12.27 3.12.28 3.12.29 3.12.30 3.12.31 3.12.32 3.12.33 3.12.34 3.12.35 3.12.36 3.12.37 3.12.38 3.12.39 3.12.40 3.12.41 3.12.42 3.12.43 3.12.44 3.12.45 3.12.46 3.12.47 3.12.48 3.12.49 3.12.50 3.12.51 3.12.52 3.12.53 3.12.54 3.12.55 3.12.56 8 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PCI Express Registers - PCI Compatible Header . . . . . . . . . . . . . . . . . . . . . . . . . 99 PCI Device and Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PCI Status and Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PCI Class Code and Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PCI Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 PCI Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 PCI Subsystem and Subsystem Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PCI Express Registers: Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PCI Express Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PCI Express Device Status and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PCI Express Link Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PCI Express Link Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Power Management Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Power Management Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Vital Product Data Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 VPD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Message Signaled Interrupt Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MSI Address Lower 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 MSI Address Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 MSI Data Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PCI Express Registers: Extended Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 111 AER Uncorrectable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 AER Uncorrectable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 AER Uncorrectable Error Severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 AER Correctable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 AER Correctable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 AER Capability and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 AER Header Log 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 AER Header Log 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 AER Header Log 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 AER Header Log 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Port VC Capability Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Port VC Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 VC Resource 0 Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 VC Resource 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 VC Resource 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 VC Resource 1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 VC Resource 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 VC Resource 2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 VC Resource 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 VC Resource 3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VC Arbitration Table Entries 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VC Arbitration Table Entries 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VC Arbitration Table Entries 16-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.13 3.14 3.15 3.16 3.17 3.18 3.12.57 VC Arbitration Table Entries 24-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.12.58 VC Arbitration Table Entries 32-39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.12.59 VC Arbitration Table Entries 40-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.12.60 VC Arbitration Table Entries 48-55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.12.61 VC Arbitration Table Entries 56-63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Rider Registers - Global. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.13.1 Rider Status 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.13.2 Rider Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.13.3 Rider Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Rider Registers: Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.14.1 Transaction Layer Status 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.14.2 TL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.14.3 Transmit Queue Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.14.4 AL Request Root Complex Lower Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.14.5 AL Request Root Complex Upper Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.14.6 AL Request Endpoint Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.14.7 AL Request Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.14.8 AL Request Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.14.9 Transaction Layer Test Control (Flow Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.14.10 Receive Buffer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 3.14.11 Virtual Channel Resources 0 and 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 3.14.12 Virtual Channel Resources 2 and 3 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.14.13 Virtual Channel Resource 0 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . 133 3.14.14 Virtual Channel Resource 2 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . 134 3.14.15 Virtual Channel Resource 3 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . 134 Rider Registers: Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.15.1 Data Link Layer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.15.2 Replay Timeout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.15.3 ACK Latency Timeout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Rider Registers: MAC Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.16.1 MAC Layer Status 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.16.2 MAC Layer Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.16.3 MAC Layer Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.16.4 MAC Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.16.5 MAC Loopback Master Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.16.6 MAC L0s Exit Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Audio and Video Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.17.1 Serial Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.17.1.1 Host Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.17.1.2 Host Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 3.17.1.3 Host Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Chip Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.18.1 Baseband Analog Front End and General Chip Configuration Registers . . . . . . . 143 3.18.1.1 Chip Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.18.1.2 Baseband AFE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 3.18.1.3 Video PLL Integer/Post Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 3.18.1.4 Video PLL Fractional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 9 CX23885 Data Sheet 3.18.1.5 Auxiliary PLL Integer/Post Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.18.1.6 Auxiliary PLL Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.18.1.7 System PLL Integer/Post Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 3.18.1.8 System PLL Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 3.18.1.9 Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.18.1.10 Audio I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 3.18.1.11 Audio Lock Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 3.18.1.12 Audio Lock Control 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 3.18.1.13 Power-Down Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.18.1.14 AFE Diagnostic Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 3.18.1.15 AFE Diagnostics Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.18.1.16 PLL Diagnostic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.18.1.17 AFE Clock Out Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.18.1.18 DLL1 Diagnostic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.18.1.19 GPIO[23:19] Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.18.1.20 GPIO [23:19] Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 3.18.1.21 IFADC Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 3.19 IR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 3.19.1 Infrared Remote registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 3.19.1.1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 3.19.1.2 Transmit Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3.19.1.3 Receive Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3.19.1.4 Transmit Carrier Duty Cycle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 3.19.1.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 3.19.1.6 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 3.19.1.7 Low Pass Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 3.19.1.8 FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 3.20 Video Decoder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 3.20.1 Basic Video Decoder Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 3.20.1.1 Output Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.20.1.2 Output Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.20.1.3 General Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 3.20.1.4 Interrupt Status and Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 3.20.1.5 Luma Data Path Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.20.1.6 Horizontal Scaling Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 3.20.1.7 Vertical Scaling Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 3.20.1.8 Chroma Data Path Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 3.20.1.9 VBI Line Data Type Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 3.20.1.10 VBI Line Data Type Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 3.20.1.11 VBI Line Data Type Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 3.20.1.12 VBI Line Data Type Control 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 3.20.1.13 VBI Line Data Type Control 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 3.20.1.14 VBI Frame Code Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 3.20.1.15 VBI Miscellaneous Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 3.20.1.16 VBI Miscellaneous Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.20.1.17 VBI Payload 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 3.20.1.18 VBI Payload 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.20.1.19 VBI Custom Mode 1, Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 3.20.1.20 VBI Custom Mode 1, Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 3.20.1.21 VBI Custom Mode 1, Config3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.20.1.22 VBI Custom Mode 2, Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 3.20.1.23 VBI Custom Mode 2, Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.20.1.24 VBI Custom Mode 2, Config3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.20.1.25 VBI Custom Mode 3, Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 3.20.1.26 VBI Custom Mode 3, Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 3.20.1.27 VBI Custom Mode 3, Config3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 3.20.1.28 Horizontal Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 3.20.1.29 Vertical Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 3.20.1.30 Sample Rate Convert and Comb Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 3.20.1.31 Chroma Config and VBI Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.20.1.32 Field Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.20.1.33 Miscellaneous Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 3.20.1.34 DFE Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 3.20.1.35 DFE Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 3.20.1.36 DFE Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 3.20.1.37 PLL Loop Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 3.20.1.38 Horizontal Timing Loop Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.20.1.39 White Crush Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.20.1.40 Soft Reset Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.20.1.41 Version ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 3.20.1.42 VBI Passthrough Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 3.21 Audio Decoder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 3.21.1 8051 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 3.21.2 Format Detection and Subcarrier Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 3.21.3 User Preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 3.21.4 8051 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 3.21.5 General Control/Interrupt Control/Rev Number/Soft Reset . . . . . . . . . . . . . . . . . . 214 3.21.6 Audio Analog AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 3.21.7 Phase Fix/Dematrix/Analog Demod Source Select/Prescaler . . . . . . . . . . . . . . . . 216 3.21.8 Path 1 Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 3.21.9 Path 1 Volume/Balance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 3.21.10 Path 1 Equalizer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 3.21.11 Path 1 Soft Clip Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 3.21.12 Path 2 Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 3.21.13 Path 2 Volume/Balance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 3.21.14 Path 2 Equalizer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 3.21.15 Path 2 Soft Clip Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 3.21.16 Sample Rate Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 3.21.17 Sample Rate Converter Loop Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . 226 3.21.18 SRC1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 3.21.19 SRC2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 3.21.20 SRC3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 3.21.21 SRC4 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 11 CX23885 Data Sheet 3.21.22 SRC5 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 3.21.23 SRC6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 3.21.24 Output Selects/Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 3.21.25 I2S Input Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 3.21.26 I2S Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 3.21.27 Autoconfiguration Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 3.22 Audio ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 3.22.1 Delta-Sigma ADC Miscellaneous Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 3.22.2 Delta-Sigma ADC Miscellaneous Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 3.22.3 Chopper Clocks Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 3.22.4 Chopper Clock Reference and Bandgap Divide Settings . . . . . . . . . . . . . . . . . . . 235 3.22.5 Chopper Clock S2D Divide Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 3.22.6 Bandgap Testing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 3.22.7 SD2 MUX Control for Right Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 3.22.8 SD2 MUX Control for Left Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 3.22.9 S2D Bias and Startup Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 3.22.10 Delta-Sigma ADC Amplifier Bias Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 3.22.11 Miscellaneous Testing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 3.22.12 Power Down Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 3.22.13 DS and S2D Stability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 3.22.14 Dynamic Dither Amplitude Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 3.22.15 Digital Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 3.22.16 Digital Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 3.22.17 I2S_TX_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 4 Thermal/Mechanical Information. 243 4.1 4.2 4.3 5 Electrical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 5.1 5.2 6 DC Electrical Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Connecting the CX23885 to the CX23417. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 6.1 12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Center Pad Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Mechanical Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 CX23885 and CX23417 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. DSH-201010p2 2/4/09 Fundamental Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Overtone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CFG Block, Device Core, and Transaction Layer Interfaces . . . . . . . . . . . . . . . . . . . . . 96 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 128-Pin ETQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Exposed Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Conexant Preliminary Information/Conexant Proprietary and Confidential 13 CX23885 Data Sheet 14 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. DSH-201010p2 2/4/09 External Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 External Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Control Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 CX23885 and CX23417 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Conexant Preliminary Information/Conexant Proprietary and Confidential 15 CX23885 Data Sheet 16 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 1 Functional Overview The CX23885 brings Conexant Systems' fifth generation of video decoding technology to PCI Express-enabled personal computers. Third generation broadcast audio decoding is integrated on chip to provide high fidelity TV stereo. The product is ideally suited for products that need to capture audio and video from analog or digital sources and deliver that data over PCI Express. 1.1 Analog Video Inputs The CX23885 integrates two high-performance 10-bit ADCs and provides a full 10-bit data path through the video decoder to maintain optimum end-to-end video quality. Eight analog inputs are provided with flexible analog muxing that can be configured for one or a combination of the following audio and video inputs: Eight composite inputs Four Y/C inputs Two composite with one Y/C, one YPbPr, and one sound IF Four composite with four sound IF One composite with two YPbPr and one sound IF Time multiplexing the various inputs to the chroma and sound ADC allows for the simultaneous digitalization of Pb and Pr inputs in component mode, or chroma with sound-IF for supporting Y/C sources with broadcast audio. All video inputs have integrated anti-alias filters, eliminating the need for external filter components. 1.2 Integrated Clamping and Automatic Gain Control DC restoration and Automatic Gain Control (AGC) are provided to compensate for sources with differing average picture levels. Manual gain control is also supported. Gain values can be read from and written to the device, allowing for the calibration of each input and facilitating fast switching from one source to another. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 17 Functional Overview 1.3 CX23885 Data Sheet Flexible Decoder Rates The video data path includes a sample rate converter to enable multiple pixel rates and to track any timing fluctuations that may be present within the video source. With the sample rate converter, the user can program the device to decode video at output pixel rates of either 13.5 MHz for an ITU-R BT.656 compliant output stream or at 12.27 MHz and 14.75 MHz for NTSC and PAL/SECAM square pixel rates, respectively. The sample rate converter with internal FIFO monitors the horizontal timing of the input source to create a fixed number of samples per line. It controls a PLL to slowly adjust the FIFO level such that short-term jitter in the input source is filtered out of the digitized video stream. This provides stable video data and output clocks, even with sources like VCRs that can have inherently unstable timing. 1.4 High Performance Luma and Chroma Separation Luma/chroma separation of composite video sources is accomplished through a 5-line adaptive chroma comb filter for NTSC and PAL standards. The adaptive comb filter looks across five lines of incoming video and determines which of the five lines are appropriately correlated enough to average together. Depending on the amount of correlation among the lines, two or three lines are averaged together to form the resulting combed filtered line. In the case where no correlation exists between lines, the decoder automatically falls back to chroma band-pass and luma notch filtering. The output of the chroma comb filter is also remodulated and fed back into the luma channel. The result is a high- quality image with reduced cross-chrominance and cross-luminance artifacts--such as dot crawl, hanging dots, rainbow effects--that restore full bandwidth to luminance data from composite sources. Additionally, we have a SECAM "Bell" filter to improve SECAM luminance and chroma separation. This is because SECAM uses an FM modulated signal carrier that is always present, regardless of whether or not there is color information being broadcast. This results in a visible artifact in the luminance at the carrier frequency. To eliminate this effect, an "Inverse Bell" filter is applied at the encoder to attenuate color frequencies near the Dr and Db carriers. Thus, if little or no color information is present in the signal, the carriers will be reduced in amplitude. 1.5 Video Processing Functions Back-end video processing functions include contrast, brightness, hue, saturation, and scaling. In addition, the luma data path provides white crush compensation for sources that exceed sync tip to white level ratios. The decoder also provides four sets of selectable peaking filters for sharpening the image. The luma data output range is selectable so that luma codes can be limited to the nominal ITU-R BT.656 code range, or can support values below black level, or can use the entire 10-bit range of values where 0 is black level, and 1023 is nominal white. Additional chroma functions include AGC to compensate for attenuated color subcarriers, a color killer for true black and white sources, and coring for limiting low-level chroma noise. 18 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 1.6 Functional Overview High Quality Scaling Arbitrary horizontal and vertical scaling is available, from full resolution down to an 8:1 ratio (icon size).To maintain a high-quality scaled image, multi-tap polyphase interpolation is used. The horizontal luma scaler uses 6-tap, 63-phase FIR interpolation between horizontal source samples, while the horizontal chroma scaler uses 4-tap, 63-phase interpolation. Line store memory is integrated into the decoder so that the vertical scaler--depending on the horizontal scaling ratio--can use from 2tap to 5-tap, seven-phase interpolation between lines. 1.7 Pixel Formatting Two pixel formatting engines are available for converting video samples into the following formats: YUY2 RGB24 RGB32 RGB555 1.8 Vertical Blanking Interval Slicing and Decoding An integrated VBI data slicer supports a variety of data standards: WST, Closed Caption, WSS, VITC, as well as programming guide information like Gemstar 1x, Gemstar 2x, and VPS. Decoded data for closed caption, WSS, and Gemstar services is available through either a register read or can be inserted as ancillary data within the ITU-R BT.656 data stream. For high-bit rate services such as WST, NABTS, VPS, and VITC, data is provided on the pixel output port and can be inserted as ancillary data as well. There is independent control of what data service is to be sliced/decoded for every line of each field in the vertical interval. Programmability is also provided such that custom data slicing can be accomplished for data services that do not comply with one of the standards already supported. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 19 Functional Overview 1.9 CX23885 Data Sheet Stereo Broadcast Audio Decoding The CX23885 integrates a stereo broadcast audio decoder capable of demodulating all of the worldwide audio standards: BTSC, EIAJ, A2, NICAM, FM (standard and highdeviation modes), and AM. The sound IF output from the tuner interfaces directly with the CX23885, eliminating the need for external sound demodulation chips. Dual language, subchannel, and Secondary Audio Formats (SAP) are also supported for broadcasts that transmit multilingual capability. Simultaneous dual language can be supported with different languages on each channel of the stereo left/right pair. The audio decoder has automatic standard detection and configuration through an onboard microprocessor so that no user intervention is necessary to set up the decoder for the various standards. This is especially useful in geographic regions where different audio standards may be received on a channel-by-channel basis. 1.10 Audio Interfaces Demodulated broadcast audio is available through two interfaces, serial audio output or embedded in the ITU-R BT.656/VIP pixel port as ancillary data. The serial audio output port can supply audio samples from the broadcast decoder or from the serial audio input port. An internal sample rate converter allows for selection of 32 kHz, 44.1 kHz, 48 kHz, or 96 kHz sample rate for easy system integration. This sample rate conversion is available for both the serial audio (input and output) and BT.656/VIP interfaces, independent of one another. In the BT.656/VIP mode, audio samples are embedded into the video stream and are tagged as ancillary data during the horizontal blanking interval. This allows for the capture of audio samples on systems that do not provide serial audio interfaces. The serial audio interfaces support programmable master/slave modes and 16- to 32-bit sample widths. The CX23885 features baseband analog audio input integrating a stereo 16-bit deltasigma analog to digital converter including multi-stage decimation filter. It supports up to 192 kHz internal sample rate, minimum 88 dB SNR, 17.6 kHz bandwidth, and 0.1 dB passband ripple. One of two stereo 2.0 Vrms full-scale inputs can be selected via register control. This audio is routed through the audio processing block to be output I2S or DMA'd over PCI Express. 20 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 1.11 Functional Overview Audio Processing In addition to the demodulation of broadcast audio in the CX23885, premium functions such as three-band equalization, volume, balance, mute, and automatic volume control are independently available on both the broadcast audio and serial audio data streams. The audio samples can also be locked to the incoming video stream to ensure that the audio samples are rate-matched to the video, eliminating the need for MPEG encoders to drop or repeat frames in order to keep the video and audio in sync. The entire audio data path is a minimum of 16 bits wide to maintain CD quality performance levels throughout the audio signal chain. 1.12 PCI Express Bus The CX23885 features a PCI Express single lane (x1) link compliant to base Specification 1.0a. This PCI Express single-function endpoint offers a dual simplex 2.5 Gbps upstream port supporting 8 upstream channels on VC0/TC0-TC7. The bidirectional, point-to-point, packet-based high throughput is implemented through a layered architecture. The physical layer is composed of an internally PIPE compliant, logical subblock consisting of the Media Access Layer (MAC) and the Physical Coding Sublayer (PCS), and the electrical subblock consisting of the Physical Media Attachment Layer (PMA). Physical Layer Packets (PLPs) originate at the transmitter (Tx) and terminate at the receiver (Rx). Above the Physical Layer is the Data Link Layer (DLL) processing DLLPs which facilitate link initialization and training, link power management, TLP flow control, and the acknowledgement of successful TLP delivery across the link. Above the DLL is the Transaction Layer (TL) processing splittransaction protocol based link traffic consisting of up to 128 byte TLPs. Above the TL is the Application Layer (AL) supporting the DMA streaming infrastructure, Tx/Rx buffering, decode, and execution of RISC instructions, register and memory access, interrupts, and overall QoS management balancing traffic priorities, latencies, and bandwidth. 1.13 Communication and General Features A hardware interrupt pin is available along with a maskable interrupt status register so that the device can notify the system when internal events occur without the need to implement polling schemes. Other convenient features consist of the following: Programmable infrared transmitter/receiver logic, able to modulate or demodulate low data rate consumer remote control protocols General purpose I/O pins Power-down pin or register-controlled power-down levels 1.2 V, 1.8 V, 3.3 V power supply configuration available with an external pass transistor PLL output for either supplying a video locked 256x/384x oversample audio clock or a general purpose user programmable clock for minimizing PCB component count Small package size: a 128-pin, 14x14 mm ETQFP Lead-free package DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 21 Functional Overview 1.14 CX23885 Data Sheet Crystal Oscillator The AFE contains a crystal oscillator circuit to produce a low-jitter clock reference for the audio/video decoder. Three crystal frequencies are supported: 28.636MHz for operation without IF sampling feature, and 49.920MHz and 56.010MHz for IF sampling. The clock reference is used for the ADC sample clocks and the reference clock for the PLLs. This clock reference is also used by the front-end digital logic that directly interfaces to the ADC modules. The crystal oscillator has a dedicated power supply pin, VAA_XTAL, which should be carefully decoupled to the VSS_XTAL pin in order to minimize board noise from coupling into the reference clock. Either a passive crystal circuit can be connected to XTI and XTO or a square wave clock signal can be fed into XTI through an AC coupling capacitor of 10nF, XTO being grounded through another similar capacitor. Figures 1 through 3 illustrate the crystal configuration connections: third overtone, fundamental crystals, and single-ended inputs. Table 1 lists the crystal specifications, and Table 2 lists the external component specifications for operation at different frequencies. Table 1. External Crystal Specifications Frequency 28.636 MHz 49.920 MHz 56.010 MHz Tolerance 25 ppm (CL = 27 and 33 pF) 25 ppm 25 ppm Temperature stability 25 ppm (0 C to 70 C) 25 ppm (0 C to 70 C) 25 ppm (0 C to 70 C) Aging stability 15 ppm / 4 yrs 15 ppm / 4 yrs 15 ppm / 4 yrs Oscillator Mode Fundamental Third overtone Third overtone Calibration Mode Parallel resonant Parallel resonant Parallel resonant Load Capacitance 20 pF, nom 18 pF, max 18 pF, max Shunt Capacitance 7 pF, max 7 pF, max 7 pF, max Series Resistance 80 max @ 500 W drive level 80 max @ 500 W drive level 80 max @ 500 W drive level Operating Temperature 0 C to 70 C 0 C to 70 C 0 C to 70 C 22 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Functional Overview Figure 1. Fundamental Mode XTI XTO C4 R1 C1 C2 Figure 2. Overtone Mode XTI XTO C4 R1 L1 C1 C2 C3 Figure 3. External Drive XTI XTO 10 nF 10 nF Sig DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 23 Functional Overview CX23885 Data Sheet Table 2. External Component Specifications Frequency 28.636 MHz 49.920 MHz 56.010 MHz C1 27 pF 15 pF 12 pF C2 33 pF 15 pF 12 pF C3 Not populated 10 nF 10 nF C4 120 pF 120 pF 120 pF L1 Not populated 0.82 H 0.68 H R1 50 50 50 24 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 2 Pin Descriptions Table 3 lists the pins and their functions. Figure 4 provides a pinout diagram. Table 3. Pin List (1 of 10) Pin Name Pin Number VIN3 1 VAA_CH1 2 VIN4 3 VSS_CH1 4 VIN5 5 IREF 6 DSH-201010p2 2/4/09 Dir I Type Description As Composite or Luma signal input to ADC1. The signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into ADC1. Unused inputs should not be connected. Ap Analog channel 1 (clamp, single-to-diff, VGA, filter) power. VAA_CH1 = 3.3 V nominal. As Chroma, Sound IF, or Pb signal input to ADC2 or Luma, Composite signal input to ADC1. This signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In color component (Pb, Pr) input mode, the Pb component should be connected to one of these pins, and the Pr component should be connected to the Pr pins (VIN7, VIN8). Unused inputs should not be connected. Ap Analog channel 1 (clamp, single-to-diff, VGA, filter) ground I As Chroma, Sound IF, or Pb signal input to ADC2 or Luma, Composite signal input to ADC1. This signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In color component (Pb, Pr) input mode, the Pb component should be connected to one of these pins, and the Pr component should be connected to the Pr pins (VIN7, VIN8). Unused inputs should not be connected. O Ar Current reference pin. Connect 30 k, 1% precision resistor to ground. I Conexant Preliminary Information/Conexant Proprietary and Confidential 25 Pin Descriptions CX23885 Data Sheet Table 3. Pin List (2 of 10) Pin Name Pin Number VIN6 7 SD2_NEG2 8 VIN7 9 VAA_CH2 10 VIN8 11 VSS_CH2 Dir Description As Chroma, Sound IF, or Pb signal input to ADC2 or Luma, Composite signal input to ADC1. This signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In color component (Pb, Pr) input mode, the Pb component should be connected to one of these pins, and the Pr component should be connected to the Pr pins (VIN7, VIN8). Unused inputs should not be connected. Ar Negative input of single-to-differential converter. Tie to analog ground through AC coupling capacitor for common mode noise rejection. The capacitor should match the value used on the analog inputs. As Chroma, Sound IF or Pr signal input to ADC2 or Luma, Composite signal input to ADC1. This signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In color component (Pb, Pr) input mode, the Pr component should be connected to this pin, and the Pb should be connected to a Pb pin (VIN4, VIN5, VIN6). Unused inputs should not be connected. Ap Analog channel 2 (clamp, single-to-diff, VGA, filter) power. VAA_CH2 = 3.3 V nominal. As Chroma, Sound IF, or Pr signal input to ADC2 or Luma, Composite signal input to ADC1. This signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In color component (Pb, Pr) input mode, the Pr component should be connected to this pin, and the Pb should be connected to a Pb pin (VIN4, VIN5, VIN6). Unused inputs should not be connected. 12 Ap Analog channel 2 (clamp, single-to-diff, VGA, filter) ground VSS_XTAL 13 Ap Crystal oscillator ground. Connect to analog ground. XTI 14 I As 28.63636 or MHz crystal oscillator input, or singleended clock oscillator input. Used for PLL clock reference and ADC sample clock. IC master clock for whole chip. XTO 15 I/O As Crystal buffer return, or DC reference input for singleended clock oscillator mode. VAA_XTAL 16 Ap Crystal oscillator power. VAA_XTAL = 3.3 V nominal. Connect to VAA. 26 I Type I I Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Pin Descriptions Table 3. Pin List (3 of 10) Pin Name Pin Number Dir Type Description VAA_DS1 17 Ap Delta-sigma audio ADC power. VSS_DS1 18 Ap Delta-sigma audio ADC ground VREFP_DS 19 O Ar Delta-sigma audio ADC positive reference voltage VREFM_DS 20 O Ar Delta-sigma audio ADC negative reference voltage ASUB_DS 21 Ap Delta-sigma audio ADC substrate tie VR1 22 I As Right channel audio input 1 VR_NEG 23 I As Right channel negative input VR2 24 I As Right channel audio input 2 VL1 25 I As Left channel audio input 1 VL_NEG 26 I As Left channel negative input VL2 27 I As Left channel audio input 2 VSS_DS2 28 Ap Delta-sigma audio ADC ground VAA_DS2 29 Ap Delta-sigma audio ADC power VOUT_REG 30 O Ar Internal regulator output signal. Connect to base of NPN transistor (q2n4401). VIN_REG 31 I Ar Internal regulator input signal. Connect to emitter of NPN transistor (q2n4401). VAA_REG 32 Ap Power for PCI Express internal voltage regulator VDDA 33 Ap PCI Express receiver power supply. Connect to analog 1.2 V. RXP 34 D PCI Express receiver differential pair. Connect to PERp0. VSSA 35 Ap PCI Express receiver ground. RXM 36 D PCI Express receiver differential pair. Connect to PERn0. VDDA 37 Ap PCI Express receiver power supply. Connect to analog 1.2 V. REF_RES 38 O Ar Reference resistor for internal bias voltage generation. Connect to 3.0 k 1% resistor to ground. ATEST 39 O D Reserved VDDRO 40 Ap PCI Express power. Connect to 1.8 V. VSSRO 41 Ap PCI Express ground. Connect to ground. DSH-201010p2 2/4/09 I I Conexant Preliminary Information/Conexant Proprietary and Confidential 27 Pin Descriptions CX23885 Data Sheet Table 3. Pin List (4 of 10) Pin Name Pin Number Dir Type Description VDDTO 42 Ap PCI Express transmitter oscillator power supply. Connect to analog 1.8 V. VSSTO 43 Ap PCI Express transmitter oscillator ground. Connect to ground. VDDT 44 Ap PCI Express transmitter driver power supply. Connect to 1.8 V. TXP 45 D PCI Express transmitter differential pair. Connect to PETp0. VSST 46 Ap PCI Express transmitter driver ground. Connect to ground. TXM 47 D PCI Express receiver differential pair. Connect to PETn0. VDDT 48 Ap PCI Express transmitter driver power supply. Connect to 1.8 V. VSSTA 49 Ap PCI Express transmitter driver ground. Connect to ground. VDDTA 50 Ap PCI Express analog PLL power. Connect to 1.2 V. REFCLKP 51 I D PCI Express differential pair reference clock. Connect to REFCLK+. REFCLKM 52 I D PCI Express differential pair reference clock. Connect to REFCLK-. GPIO[15] 53 I/O D General Purpose I/O Configurable multifunction status/control pin VDD 54 Dp Digital core logic power TEST 55 I D Puts chip in test mode for ATE/Debug testing. Activehigh. PERST_N 56 I D PCI Express reset input, active low RESET_OUT_N 57 O D Buffered output PERST_N combined with internal POR, soft reset, and hot PCI reset VDD 58 Dp Digital core logic power GPIO[14] 59 D General Purpose I/O Configurable multifunction status/control pin 28 O O I/O Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Pin Descriptions Table 3. Pin List (5 of 10) Pin Name Pin Number Dir Type Description IRQ_N (GPIO[16]) 60 I/O D When UART_GPIO_EN bit is cleared in the MC417_GPIO_CTL register: This is an Interrupt input, active-low (external A/V decoder), or output from AV_CORE. When UART_GPIO_EN bit is set in the MC417_GPIO_CTL register: This is a General Purpose I/O Configurable multifunction status/control pin. URX(GPIO[17]) 61 I/O D When UART_GPIO_EN bit is cleared in the MC417_GPIO_CTL register: UART receive input When UART_GPIO_EN bit is set in the MC417_GPIO_CTL register: This is a General Purpose I/O Configurable multifunction status/control pin. UTX(GPIO[18] 62 I/O D When UART_GPIO_EN bit is cleared in the MC417_GPIO_CTL register: UART transmit output When UART_GPIO_EN bit is set in the MC417_GPIO_CTL register: This is a General Purpose I/O Configurable multifunction status/control pin. VDDIO 63 Dp Digital I/O pad power GPIO[13] 64 I/O D General Purpose I/O Configurable multifunction status/control pin GPIO[12] 65 I/0 D General Purpose I/O Configurable multifunction status/control pin VDD 66 Dp Digital core logic power GPIO[11] 67 I/O TS2_SOP 68 I/O D Start of packet indicator input or Data Request output TS2_VAL 69 I D Valid indicator for TS2. TS2_CLK 70 I D Transport stream input clock. All other TS2 signals sampled at rising edge of TS2_CLK TS2_DAT 71 I D Transport stream input serial data TS1_SOP 72 I/O D TS input mode: Start of packet indicator input or Data Request Output TS1_VAL 73 I D Valid indicator for TS1. DSH-201010p2 2/4/09 General Purpose I/O Configurable multifunction status/control pin Conexant Preliminary Information/Conexant Proprietary and Confidential 29 Pin Descriptions CX23885 Data Sheet Table 3. Pin List (6 of 10) Pin Name Pin Number TS1_CLK 74 VDD 75 GPIO[10] 76 TS1_DAT[0] 77 Dir I/O Type Description D Transport stream input clock. All other TS1 signals sampled at rising edge of TS1_CLK Dp Digital core logic power I/O D General Purpose I/O Configurable multifunction status/control pin I/O D Multiplexed pin function. 1. TS input mode: This can be a serial transport/ program stream data bit or a parallel transport/ program stream data bit[0]. 2. Video input mode: Data bit[0] of ITU-656 or VIP source 3. Video output mode: Data bit[0] of internally decoded video TS1_DAT[1] 78 I/O D Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[1] 2. Video input mode: Data bit[1] of ITU-656 or VIP source 3. Video output mode: Data bit[1] of internally decoded video TS1_DAT[2] 79 I/O D Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[2] 2. Video input mode: Data bit[2] of ITU-656 or VIP source 3. Video output mode: Data bit[2] of internally decoded video TS1_DAT[3] 80 I/O D Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[3] 2. Video input mode: Data bit[3] of ITU-656 or VIP source 3. Video output mode: Data bit[3] of internally decoded video TS1_DAT[4] 81 I/O D Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[4] 2. Video input mode: Data bit[4] of ITU-656 or VIP source 3. Video output mode: Data bit[4] of internally decoded video 30 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Pin Descriptions Table 3. Pin List (7 of 10) Pin Name TS1_DAT[5] Pin Number 82 Dir I/O Type D Description Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[5] 2. Video input mode: Data bit[5] of ITU-656 or VIP source 3. Video output mode: Data bit[5] of internally decoded video TS1_DAT[6] 83 I/O D Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[6] 2. Video input mode: Data bit[6] of ITU-656 or VIP source 3. Video output mode: Data bit[6] of internally decoded video TS1_DAT[7] 84 I/O D Multiplexed pin function. 1. TS input mode: Parallel transport or program stream data bit[7] 2. Video input mode: Data bit[7] of ITU-656 or VIP source 3. Video output mode: Data bit[7] of internally decoded video VDDIO 85 Dp Digital I/O pad power GPIO[9] 86 I/O D General Purpose I/O Configurable multifunction status/control pin GPIO[8] 87 I/O D General Purpose I/O Configurable multifunction status/control pin VDD 88 Dp Digital core logic power GPIO[0] 89 I/O D General Purpose I/O Configurable multi-function status/control pin GPIO[1] 90 I/O D General Purpose I/O Configurable multi-function status/control pin GPIO[2] 91 I/O D General Purpose I/O Configurable multi-function status/control pin GPIO[3] 92 I/O D General Purpose I/O Configurable multi-function status/control pin SDA1 93 O D I2C-compatible serial data SCL1 94 I/O D I2C-compatible serial clock output GPIO[4] 95 I/O D General Purpose I/O Configurable multifunction status/control pin DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 31 Pin Descriptions CX23885 Data Sheet Table 3. Pin List (8 of 10) Pin Name Pin Number VDD 96 SDA2 97 SCL2 98 VDDIO 99 GPIO[5] 100 GPIO[6] 101 VDD 102 I2S_BCLK(GPIO[23]) 103 I2S_WCLK (GPIO[22]) Dir Type Description Dp Digital core logic power O D I2C-compatible serial data I/O D I2C-compatible serial clock output Dp Digital I/O pad power I/O D General Purpose I/O Configurable multifunction status/control pin I/O D General Purpose I/O Configurable multifunction status/control pin Dp Digital core logic power I/O D When GPIO2_OUT_ENABLE_N bit is set in the GPIO2_OUT_EN_REG register: I2S bit clock for sampling serial data When GPIO2_OUT_ENABLE_N bit is cleared in the GPIO2_OUT_EN_REG register: This is a General Purpose I/O Configurable multifunction status/control pin. 104 I/O D When GPIO2_OUT_ENABLE_N bit is set in the GPIO2_OUT_EN_REG register: I2S word clock to frame data word boundaries When GPIO2_OUT_ENABLE_N bit is cleared in the GPIO2_OUT_EN_REG register: This is a General Purpose I/O Configurable multifunction status/control pin. I2S_SDAT(GPIO[21]) 105 I/O D When GPIO2_OUT_ENABLE_N bit is set in the GPIO2_OUT_EN_REG register: I2S serial data When GPIO2_OUT_ENABLE_N bit is cleared in the GPIO2_OUT_EN_REG register: This is a General Purpose I/O Configurable multifunction status/control pin. IR_RX (GPIO[19]) 106 I/O D When GPIO2_OUT_ENABLE_N bit is set in the GPIO2_OUT_EN_REG register: Infrared remote control receiver input When GPIO2_OUT_ENABLE_N bit is cleared in the GPIO2_OUT_EN_REG register: This is a General Purpose I/O Configurable multifunction status/control pin. 32 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Pin Descriptions Table 3. Pin List (9 of 10) Pin Name Pin Number Dir I/O Type D Description IR_TX (GPIO[20]) 107 When GPIO2_OUT_ENABLE_N bit is set in the GPIO2_OUT_EN_REG register: Infrared transmitter output When GPIO2_OUT_ENABLE_N bit is cleared in the GPIO2_OUT_EN_REG register: This is a General Purpose I/O Configurable multifunction status/control pin. Reserved 108 Reserved pin. Not connected. Reserved 109 Reserved pin. Not connected. VDD 110 GPIO[7] 111 VDDO_PLL 112 AUX_PLL_CLK 113 VSSO_PLL Dp Digital I/O pad power D General Purpose I/O Configurable multifunction status/control pin Ap Isolated Aux PLL output pad power D Aux PLL output 114 Ap Isolated Aux PLL output pad ground VSS_PLL 115 Ap Analog PLL ground VAA_PLL 116 Ap Analog PLL power Reserved 117 Reserved pin. Should not be connected. Reserved 118 Reserved pin. Should not be connected. Reserved 119 Reserved pin. Should not be connected. Reserved 120 Reserved pin. Should not be connected. VAA_ADC2 121 Ap ADC core power. VAA_ADC = 3.3 V nominal. VSS_ADC2 122 Ap ADC core ground VSS_ADC1 123 Ap ADC core ground VAA_ADC1 124 Ap ADC core power. VAA_ADC = 3.3 V nominal. ASUB 125 Ap ADC core substrate ground VIN1 126 I As Composite or Luma signal input to ADC1. The signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into ADC1. Unused inputs should not be connected. S2D_NEG1 127 I Ar Negative input of single-to-differential converter. Tie to analog ground through AC coupling capacitor for common mode noise rejection. The capacitor should match the value used on the analog inputs. DSH-201010p2 2/4/09 I/O O Conexant Preliminary Information/Conexant Proprietary and Confidential 33 Pin Descriptions CX23885 Data Sheet Table 3. Pin List (10 of 10) Pin Name Pin Number Dir Type Description VIN2 128 I As Composite or Luma signal input to ADC1. The signal passes through on-chip analog multiplexers before passing through a gain stage, an anti-alias filter stage, and into ADC1. Unused inputs should not be connected. Exposed Pad -- -- -- Tie to digital ground (must be connected). R Od As Ap Dp Ar D Active resistive pullup Open-drain pads with glitch filters Analog signal Analog power or ground Digital power or ground Analog reference, for connection to external component Digital signal Legend for Pin Type 34 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Pin Descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RESERVED RESERVED RESERVED RESERVED VAA_PLL VSS_PLL VSSO_PLL AUX_PLL_CLK VDDO_PLL GPIO[7] VDD Reserved Reserved IR_TX(GPIO[20]) IR_RX(GPIO[19]) I2S_SDAT(GPIO[21]) I2S_WCLK(GPIO[22]) I2S_BCLK(GPIO[23]) VDD GPIO[6] GPIO[5] VDDIO SCL_2 SDA_2 CX23885 128-pin ETQFP 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDD GPIO[4] SCL_1 SDA_1 GPIO[3] GPIO[2] GPIO[1] GPIO[0] VDD GPIO[8] GPIO[9] VDDIO TS1_DAT[7] TS1_DAT[6] TS1_DAT[5] TS1_DAT[4] TS1_DAT[3] TS1_DAT[2] TS1_DAT[1] TS1_DAT[0] GPIO[10] VDD TS1_CLK TS1_VAL TS1_SOP TS2_DAT TS2_CLK TS2_VAL TS2_SOP GPIO[11] VDD GPIO[12] VDDA RXP VSSA RXM VDDA REF_RES Reserved VDDRO VSSRO VDDTO VSSTO VDDT TXP VSST TXM VDDT VSSTA VDDTA REFCLKP REFCLKM GPIO[15] VDD TEST PERST_N RESET_OUT_N VDD GPIO[14] IRQ_N(GPIO[16]) URX(GPIO[17]) UTX(GPIO[18]) VDDIO GPIO[13] 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VIN3 VAA_CH1 VIN4 VSS_CH1 VIN5 IREF VIN6 SD2_NEG2 VIN7 VAA_CH2 VIN8 VSS_CH2 VSS_XTAL XTI XTO VAA_XTAL VAA_DS1 VSS_DS1 VREFP_DS VREFM_DS ASUB_DS VR1 VR_NEG VR2 VL1 VL_NEG VL2 VSS_DS2 VAA_DS2 VOUT_REG VIN_REG VAA_REG 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 VIN2 S2D_NEG1 VIN1 ASUB VAA_ADC1 VSS_ADC1 VSS_ADC2 VAA_ADC2 Figure 4. Pinout Diagram 102740_002 DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 35 Pin Descriptions 36 CX23885 Data Sheet Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 3 3.1 Registers Register Map Table 4. Register Map Register Type Description RO Read-only WO Write-only RW Read/Write RW* Read/Write, but data may not be same as written at a later time. RR Same as RW, but writing a 1 resets corresponding bit location, writing 0 has no effect. RWp Read-only, Write-only shared port, data written cannot be read. Only accessible by DMAC. Rp Read-only port. Only accessible by DMAC. Wd Write-only, operates on other data entering register. GENERAL NOTE: 1. Unused register bits will read back 0. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 37 Registers CX23885 Data Sheet 3.2 Memory Mapped Registers: Application Layer 3.2.1 Device Control #2 Register: DEV_CNTRL2 Bits Type Default [31:6] RO 26'b0 [5] WO 1'b0 [4:0] RO 5'b0 3.2.2 Address: 0x0004000 Name Description Reserved RUN_RISC A value of 1 enables the RISC controller. A value of 0 holds the RISC controller in a reset state. Reserved PCI Interrupt Mask Register: PCI_INT_MSK Bits Type Address: 0x00040010 Default Name Description [31:28] RO 4'b0 [27] RW 1'b0 AV_CORE_MSK Set when AV_CORE interrupt condition occurs. Cleared by clearing interrupt bits in AV_CORE interrupt status register. A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [26] RW 1'b0 UART_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [25] RW 1'b0 IRQN_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. 38 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [24] RW 1'b0 GPIO1_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [23] RW 1'b0 GPIO0_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [22] RW 1'b0 TM_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [21] RW 1'b0 I2C_3_RACK_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [20] RW 1'b0 I2C_3_MSK Set when an I2C #3 read or write operation has completed. [19] RW 1'b0 I2C_2_RACK_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [18] RW 1'b0 I2C_2_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [17] RW 1'b0 I2C_1_RACK_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 39 Registers CX23885 Data Sheet [16] RW 1'b0 [15:3] RW 3'b0 [12] RW 1'b0 APB_DMA_BERR_M SK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [11] RW 1'b0 AL_WR_BERR_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [10] RW 1'b0 AL_RD_BERR_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [9] RW 1'b0 RISC_WR_BERR_MS K A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [8] RW 1'b0 RISC_RD_BERR_MS K A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [7] RW 1'b0 RESERVED [6] RW 1'b0 RESERVED [5] RW 1'b0 RESERVED [4] RW 1'b0 40 I2C_1_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. Reserved AUD_EXT_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [3] RW 1'b0 AUD_INT_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [2] RW 1'b0 VID_C_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [1] RW 1'b0 VID_B_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. [0] RW 1'b0 VID_A_MSK A value of 1 enables the corresponding interrupt bit location in the PCI_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 41 Registers 3.2.3 CX23885 Data Sheet PCI Interrupt Status Register: PCI_INT_STAT Bits Type Address: 0x00040014 Default Name Description [31:28] RO 4'h0 [27] RO 1'b0 AV_CORE_INT Set when AV_CORE interrupt condition occurs. Cleared by clearing interrupt bits in AV_CORE interrupt status register. [26] RO 1'b0 UART_INT Set when UART interrupt condition occurs. Cleared by clearing interrupt bits in UART_ISR. [25] RR 1'b0 IRQN_INT Set when GPIO interrupt condition occurs on pin IRQN pin, also called GPIO[4]. [24] RR 1'b0 GPIO1_INT Set when GPIO interrupt condition occurs on pin GPIO[23]. [23] RR 1'b0 GPIO0_INT Set when GPIO interrupt condition occurs on pin GPIO[22]. [22] RR 1'b0 TM_INT Set when timer TM_CNT reaches its limit TM_LMT. [21] RR 1'b0 I2C_3_RACK Set when an I2C #3 read or write operation has completed successfully. Latched on rising edge of I2C_2_INT. Intended for status only. Typically masked off. [20] RR 1'b0 I2C_3_INT Set when an I2C #3 read or write operation has completed. [19] RR 1'b0 I2C_2_RACK Set when an I2C #2 read or write operation has completed successfully. Latched on rising edge of I2C_3_INT. Intended for status only. Typically masked off. [18] RR 1'b0 I2C_2_INT Set when an I2C #2 read or write operation has completed. [17] RR 1'b0 I2C_1_RACK Set when an I2C #1 read or write operation has completed successfully. Latched on rising edge of I2C_1_INT. Intended for status only. Typically masked off. [16] RR 1'b0 I2C_1_INT Set when an I2C #1 read or write operation has completed. [15:13] RO 3'b0 [12] RR 1'b0 42 Reserved Reserved APB_DMA_BERR_INT Set when the BERR signal is asserted to the ASB master during an APB DMA. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [11] RR 1'b0 AL_WR_BERR_INT Set when the BERR signal is asserted to the AL ASB master during a write transfer. [10] RR 1'b0 AL_RD_BERR_INT Set when the BERR signal is asserted to the AL ASB master during a read transfer. [9] RR 1'b0 RISC_WR_BERR_INT Set when the BERR signal is asserted to the RISC controller during a write transfer. [8] RR 1'b0 RISC_RD_BERR_INT Set when the BERR signal is asserted to the RISC controller during a read transfer. [7] RO 1'b0 Reserved [6] RO 1'b0 Reserved [5] RO 1'b0 Reserved [4] RO 1'b0 AUD_EXT_INT Set when an external audio interrupt condition occurs. Cleared by clearing the bits of the Audio EXT Interrupt Status register. [3] RO 1'b0 AUD_INT_INT Set when an internal audio interrupt condition occurs. Cleared by clearing the bits of the Audio INT Interrupt Status register. [2] RO 1'b0 VID_C_INT Set when a Video C interrupt condition occurs. Cleared by clearing the bits of the Video C Interrupt Status register. [1] RO 1'b0 VID_B_INT Set when a Video B interrupt condition occurs. Cleared by clearing the bits of the Video B Interrupt Status register. [0] RO 1'b0 VID_A_INT Set when a Video A interrupt condition occurs. Cleared by clearing the bits of the Video A Interrupt Status register. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 43 Registers 3.2.4 CX23885 Data Sheet PCI Interrupt Masked Status Register: PCI_INT_MSTAT Bits Type Address: 0x00040018 Default Name Description [31:28] RO 4'b0 [27] RO 1'b0 AV_CORE_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [26] RO 1'b0 UART_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [25] RO 1'b0 IRQN_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [24] RO 1'b0 GPIO1_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [23] RO 1'b0 GPIO0_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [22] RO 1'b0 TM_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [21] RO 1'b0 I2C_3_RACK_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [20] RO 1'b0 I2C_3_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [19] RO 1'b0 I2C_2_RACK_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [18] RO 1'b0 I2C_2_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [17] RO 1'b0 I2C_1_RACK_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [16] RO 1'b0 I2C_1_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [15:13] RO 3'b0 44 Reserved RESERVED Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [12] RO 1'b0 [11] RO 1'b0 AL_WR_BERR_MSTA T These bits are the logical AND of the corresponding bits in the status and mask registers. [10] RO 1'b0 AL_RD_BERR_MSTA T These bits are the logical AND of the corresponding bits in the status and mask registers. [9] RO 1'b0 RISC_WR_BERR_MS TAT These bits are the logical AND of the corresponding bits in the status and mask registers. [8] RO 1'b0 RISC_RD_BERR_MS TAT These bits are the logical AND of the corresponding bits in the status and mask registers. [7] RO 1'b0 RESERVED [6] RO 1'b0 RESERVED [5] RO 1'b0 RESERVED [4] RO 1'b0 AUD_EXT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [3] RO 1'b0 AUD_INT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [2] RO 1'b0 VID_C_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [1] RO 1'b0 VID_B_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. [0] RO 1'b0 VID_A_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. DSH-201010p2 2/4/09 APB_DMA_BERR_MST These bits are the logical AND of the AT corresponding bits in the status and mask registers. Conexant Preliminary Information/Conexant Proprietary and Confidential 45 Registers 3.2.5 CX23885 Data Sheet Video A Interrupt Mask Register: VID_A_INT_MSK Bits Type Default [31:18] RO 14'b0 [17:0] RW 18'b0 3.2.6 Address: 0x00040020 Name Description Reserved VID_A_INT_MSK A value of 1 enables the corresponding interrupt bit location in the VID_A_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. Video A Interrupt Status Register VID_A_INT_STAT Bits Type Default Address: 0x00040024 Name Description [31:18] RO 14'b0 [17] RR 1'b0 VBI_A_OPC_ERR Set when the RISC controller detects a reserved/unused opcode in the VBI A instruction sequence. [16] RR 1'b0 VID_A_OPC_ERR Set when the RISC controller detects a reserved/unused opcode in the video A instruction sequence. [15:14] RO 2'b0 [13] RR 1'b0 VBI_A_SYNC Set when number of lines or bytes do not match the VBI A RISC program expectations. [12] RR 1'b0 VID_A_SYNC Set when number of lines or bytes do not match the video A RISC program expectations. [11:10] RO 2'b0 [9] RR 1'b0 VBI_A_OF Set when VBI A FIFO overflow condition is being handled. [8] RR 1'b0 VID_A_OF Set when video A FIFO overflow condition is being handled. [7:6] RO 2'b0 [5] RR 1'b0 46 Reserved Reserved Reserved Reserved VBI_A_RISCI2 Set when the IRQ2 bit in a VBI A RISC instruction is set. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [4] RR 1'b0 [3:2] RO 2'b0 [1] RR 1'b0 VBI_A_RISCI1 Set when the IRQ1 bit in a VBI A RISC instruction is set. [0] RR 1'b0 VID_A_RISCI1 Set when the IRQ1 bit in a video A RISC instruction is set. 3.2.7 VID_A_RISCI2 Set when the IRQ2 bit in a video A RISC instruction is set. Reserved Video A Interrupt Masked Status Register: VID_A_INT_MSTAT Bits Type Default [31:18] RO 14'b0 [17:0] RO 18'b0 3.2.8 Address: 0x00040028 Name Description Reserved VID_A_INT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. Video A Interrupt Set Status Register VID_A_INT_SSTAT Bits Type Default [31:18] RO 14'b0 [17:0] WO 18'b0 3.2.9 Address: 0x0004002C Name Description Reserved VID_INT_SSTAT Writing a 1 to these bits will set the corresponding bits in the status register. Video B Interrupt Mask Register: VID_B_INT_MSK Bits Type Default [31:21] RO 11'b0 [20:0] RW 21'b0 DSH-201010p2 2/4/09 Address: 0x00040030 Name Description Reserved VID_B_INT_MSK A value of 1 enables the corresponding interrupt bit location in the VID_B_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. Conexant Preliminary Information/Conexant Proprietary and Confidential 47 Registers CX23885 Data Sheet 3.2.10 Video B Interrupt Status Register: VID_B_INT_STAT Bits Type Default Address: 0x00040034 Name Description [31:21] RO 11'b0 [20] RR 1'b0 [19:18] RO 2'b0 [17] RR 1'b0 VBI_B_OPC_ERR Set when the RISC controller detects a reserved/ unused opcode in the VBI B instruction sequence. [16] RR 1'b0 VID_B_OPC_ERR Set when the RISC controller detects a reserved/ unused opcode in the video B instruction sequence. [15:14] RO 2'b0 [13] RR 1'b0 VBI_B_SYNC Set when number of lines or bytes do not match the VBI B RISC program expectations. [12] RR 1'b0 VID_B_SYNC Set when number of lines or bytes do not match the video B RISC program expectations. [11:10] RO 2'b0 [9] RR 1'b0 VBI_B_OF Set when VBI B FIFO overflow condition is being handled. [8] RR 1'b0 VID_B_OF Set when video B FIFO overflow condition is being handled. [7:6] RO 2'b0 [5] RR 1'b0 VBI_B_RISCI2 Set when the IRQ2 bit in a VBI B RISC instruction is set. [4] RR 1'b0 VID_B_RISCI2 Set when the IRQ2 bit in a video B RISC instruction is set. [3:2] RO 2'b0 [1] RR 1'b0 VBI_B_RISCI1 Set when the IRQ1 bit in a VBI B RISC instruction is set. [0] RR 1'b0 VID_B_RISCI1 Set when the IRQ1 bit in a video B RISC instruction is set. 48 Reserved TS_BAD_PCKT Set when the MPEG transport stream interface detects an error (either of the three status check bits are set and the appropriate error condition is detected). Reserved Reserved Reserved Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.2.11 Video B Interrupt Masked Status Register: VID_B_INT_MSTAT Bits Type Default [31:21] RO 11'b0 [20:0] RO 21'b0 Address: 0x00040038 Name Description Reserved VID_B_INT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. 3.2.12 Video B Interrupt Set Status Register: VID_B_INT_SSTAT Bits Type Default [31:18] RO 14'b0 [17:0] WO 18'b0 Address: 0x0004003C Name Description Reserved VID_INT_SSTAT Writing a 1 to these bits will set the corresponding bits in the status register. 3.2.13 Video C Interrupt Mask Register: VID_C_INT_MSK Bits Type [31:21] RO 11'b0 [20:0] RW 21'b0 DSH-201010p2 2/4/09 Default Address: 0x00040040 Name Description Reserved VID_C_INT_MSK A value of 1 enables the corresponding interrupt bit location in the VID_C_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. Conexant Preliminary Information/Conexant Proprietary and Confidential 49 Registers CX23885 Data Sheet 3.2.14 Video C Interrupt Status Register: VID_C_INT_STAT Bits Type Default [31:21] RO 11'b0 [20] RR 1'b0 [19:17] RO 3'b0 [16] RR 1'b0 [15:13] RO 3'b0 [12] RR 1'b0 [11:9] RO 3'b0 [8] RR 1'b0 [7:5] RO 3'b0 [4] RR 1'b0 [3:1] RO 3'b0 [0] RR 1'b0 Address: 0x00040044 Name Description Reserved TS_BAD_PCKT Set when the MPEG transport stream interface detects an error (either of the three status check bits are set and the appropriate error condition is detected). Reserved VID_C_OPC_ERR Set when the RISC controller detects a reserved/ unused opcode in the instruction sequence. Reserved VID_C_SYNC Set when number of lines or bytes do not match the video RISC program expectations. Reserved VID_C_OF Set when video FIFO overflow condition is being handled. Reserved VID_C_RISCI2 Set when the IRQ2 bit in a video RISC instruction is set. Reserved VID_C_RISCI1 Set when the IRQ1 bit in a video RISC instruction is set. 3.2.15 Video C Interrupt Masked Status Register: VID_C_INT_MSTAT Bits Type [31:21] RO 11'b0 [20:0] RO 21'b0 50 Default Address: 0x00040048 Name Description Reserved VID_C_INT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.2.16 Video C Interrupt Set Status Register: VID_C_INT_SSTAT Bits Type Default [31:17] RO 15'b0 [16:0] WO 17'b0 Address: 0x0004004C Name Description Reserved VID_C_INT_SSTAT Writing a 1 to these bits will set the corresponding bits in the status register. 3.2.17 Audio Internal Interrupt Mask Register: AUDIO_INT_INT_MSK Bits Type Default [31:18] RO 14'b0 [17:0] RW 18'b0 Address: 0x00040050 Name Description Reserved AUD_INT_INT_MSK A value of 1 enables the corresponding interrupt bit location in the AUD_INT_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. 3.2.18 Audio Internal Interrupt Status Register: AUD_INT_INT_STAT Bits Type [31:18] RO 14'b0 [17] RR 1'b0 AUD_INT_B_OPC_ERR Set when the RISC controller detects a reserved/unused opcode in the internal audio B instruction sequence. [16] RR 1'b0 AUD_INT_A_OPC_ERR Set when the RISC controller detects a reserved/unused opcode in the internal audio A instruction sequence. [15:14] RO 2'b0 [13] RR 1'b0 DSH-201010p2 2/4/09 Default Address: 0x00040054 Name Description Reserved Reserved AUD_INT_B_SYNC Set when number of lines or bytes do not match the internal audio B RISC program expectations. Conexant Preliminary Information/Conexant Proprietary and Confidential 51 Registers CX23885 Data Sheet [12] RR 1'b0 AUD_INT_A_SYNC Set when number of lines or bytes do not match the internal audio A RISC program expectations. [11:10] RO 2'b0 [9] RR 1'b0 AUD_INT_B_OF Set when internal audio B FIFO overflow condition is being handled. [8] RR 1'b0 AUD_INT_A_OF Set when internal audio A FIFO overflow condition is being handled. [7:6] RO 2'b0 [5] RR 1'b0 AUD_INT_B_RISCI2 Set when the IRQ2 bit in an internal audio B RISC instruction is set. [4] RR 1'b0 AUD_INT_A_RISCI2 Set when the IRQ2 bit in an internal audio A RISC instruction is set. [3:2] RO 2'b0 [1] RR 1'b0 AUD_INT_B_RISCI1 Set when the IRQ1 bit in an internal audio B RISC instruction is set. [0] RR 1'b0 AUD_INT_A_RISCI1 Set when the IRQ1 bit in an internal audio A RISC instruction is set. Reserved Reserved Reserved 3.2.19 Audio Internal Interrupt Masked Status Register: AUD_INT_INT_MSTAT Bits Type Default [31:18] RO 14'b0 [17:0] RO 18'b0 Address: 0x00040058 Name Description Reserved AUD_INT_INT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. 3.2.20 Audio Internal Interrupt Set Status Register: AUD_INT_INT_SSTAT Bits Type Default [31:18] RO 14'b0 [17:0] WO 18'b0 52 Address: 0x0004005C Name Description Reserved AUD_INT_INT_SSTAT Writing a 1 to these bits will set the corresponding bits in the status register. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.2.21 Audio External Interrupt Mask Register: AUDIO_EXT_INT_MSK Bits Type Default [31:17] RO 15'b0 [16:0] RW 17'b0 Address: 0x00040060 Name Description Reserved AUD_EXT_INT_MSK A value of 1 enables the corresponding interrupt bit location in the AUD_EXT_INT_STAT register. Unmasking a bit may generate an interrupt immediately due to a previously pending condition. The interrupt remains asserted until the device driver clears or masks the pending request. 3.2.22 Audio External Interrupt Status Register: AUD_EXT_INT_STAT Bits Type Default [31:17] RO 15'b0 [16] RR 1'b0 [15:13] RO 3'b0 [12] RR 1'b0 [11:9] RO 3'b0 [8] RR 1'b0 [7:5] RO 3'b0 [4] RR 1'b0 [3:1] RO 3'b0 [0] RR 1'b0 DSH-201010p2 2/4/09 Address: 0x00040064 Name Description Reserved AUD_EXT_OPC_ERR Set when the RISC controller detects a reserved/unused opcode in the external audio instruction sequence. Reserved AUD_EXT_SYNC Set when number of lines or bytes do not match the external audio RISC program expectations. Reserved AUD_EXT_OF Set when external audio FIFO overflow condition is being handled. Reserved AUD_EXT_RISCI2 Set when the IRQ2 bit in an external audio RISC instruction is set. Reserved AUD_EXT_RISCI1 Set when the IRQ1 bit in an external audio RISC instruction is set. Conexant Preliminary Information/Conexant Proprietary and Confidential 53 Registers CX23885 Data Sheet 3.2.23 Audio External Interrupt Masked Status Register: AUD_EXT_INT_MSTAT Bits Type Default [31:17] RO 15'b0 [16:0] RO 17'b0 Address: 0x00040068 Name Description Reserved AUD_EXT_INT_MSTAT These bits are the logical AND of the corresponding bits in the status and mask registers. 3.2.24 Audio External Interrupt Set Status Register: AUD_EXT_INT_SSTAT Bits Type [31:17] RO 15'b0 [16:0] WO 17'b0 54 Default Address: 0x0004006C Name Description Reserved AUD_EXT_INT_SSTAT Writing a 1 to these bits will set the corresponding bits in the status register. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.3 Memory Mapped Registers: DMAC 3.3.1 APB DMAC Current Buffer Pointer Register: DMA1_PTR1 (qword) Address: 0x00100000 Register: DMA2_PTR1 (qword) Address: 0x00100004 Register: DMA3_PTR1 (qword) Address: 0x00100008 Register: DMA4_PTR1 (qword) Address: 0x0010000C Register: DMA5_PTR1 (qword) Address: 0x00100010 Register: DMA6_PTR1 (dword) Address: 0x00100014 Register: DMA7_PTR1 (dword) Address: 0x00100018 Register: DMA8_PTR1 (dword) Address: 0x0010001C Bits Type [31:24] RO 8'b0 [23:2] RO 22'hxxxxxx [1:0] RO 2'b00 DSH-201010p2 2/4/09 Default Name Description Reserved DMA{x}_PTR1 Current DMA qword or dword address pointer. Points to next qword or qword transfer location within source or destination buffer. Always dword-aligned. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 55 Registers 3.3.2 CX23885 Data Sheet APB DMAC Current Table Pointer Register: DMA1_PTR2 Address: 0x00100040 Register: DMA2_PTR2 Address: 0x00100044 Register: DMA3_PTR2 Address: 0x00100048 Register: DMA4_PTR2 Address: 0x0010004C Register: DMA5_PTR2 Address: 0x00100050 Register: DMA6_PTR2 Address: 0x00100054 Register: DMA7_PTR2 Address: 0x00100058 Register: DMA8_PTR2 Address: 0x0010005C Bits Type Default [31:24] RO 8'b0 [23:2] RW* 22'hxxxxxx [1:0] RO 2'b00 56 Name Description Reserved DMA{x}_PTR2 Current DMA CDT address pointer. Points to current CDT entry. Always dword-aligned. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.3.3 Registers APB DMAC Buffer Limit Register: DMA1_CNT1 (oword) Address: 0x00100080 Register: DMA2_CNT1 (oword) Address: 0x00100084 Register: DMA3_CNT1 (oword) Address: 0x00100088 Register: DMA4_CNT1 (oword) Address: 0x0010008C Register: DMA5_CNT1 (oword) Address: 0x00100090 Register: DMA6_CNT1 (qword) Address: 0x00100094 Register: DMA7_CNT1 (qword) Address: 0x00100098 Register: DMA8_CNT1 (qword) Address: 0x0010009C Bits Type Default [31:11] RO 21'b0 [10:0] RW* 11'hxxx DSH-201010p2 2/4/09 Name Description Reserved DMA{x}_CNT1 Initialize to DMA buffer size in # of owords or qwords. Increments during DMA data transfers and reloads when next CDT pointer is fetched. Conexant Preliminary Information/Conexant Proprietary and Confidential 57 Registers 3.3.4 CX23885 Data Sheet APB DMAC Table Size Register: DMA1_CNT2 Address: 0x001000C0 Register: DMA2_CNT2 Address: 0x001000C4 Register: DMA3_CNT2 Address: 0x001000C8 Register: DMA4_CNT2 Address: 0x001000CC Register: DMA5_CNT2 Address: 0x001000D0 Register: DMA6_CNT2 Address: 0x001000D4 Register: DMA7_CNT2 Address: 0x001000D8 Register: DMA8_CNT2 Address: 0x001000DC Bits Type [31:11 ] RO [10:0] RW* 58 Default Name 21'b0 11'hxxx Description Reserved DMA{x}_CNT2 Initialize to DMA CDT size in # of qwords. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.4 Memory Mapped Registers: Miscellaneous Utilities 3.4.1 Timer Counters Register: TM_CNT_LDW Bits [31:0] Type RO Address: 0x00110000 Default 32'b0 Name TM_CNT_LDW Description Lower dword of timer. The timer increments every 96 ns, from 0 to the limit value, then resets to 0 and counts again. The maximum value provides for ~312 days. The upper 16-bits of the timer are captured for reading at the TM_CNT_UW register whenever the TM_CNT_LDW register is read. Register: TM_CNT_UW Bits Type Default [31:16] RO 16'b0 [15:0] RO 16'b0 3.4.2 Address: 0x00110004 Name Description Reserved TM_CNT_UW Upper 16-bits of the 48-bit timer, captured at the time the lower 32-bits were read. The timer increments every 96 ns, from 0 to the limit value, then resets to 0 and counts again. The maximum value provides for ~312 days. Timer Limit Values Register: TM_LMT_LDW Bits [31:0] Type RW Address: 0x00110008 Default 32'b0 Name TM_LMT_LDW Description When the current count value of the timer reaches the limit value, an interrupt TM_INT is set. The periodic timer interrupt event rate is = 10.4 MHz / (TM_LMT + 1). If TM_LMT is set to 0, TM_CNT remains reset. Register: TM_LMT_UW Bits Type Default [31:16] RO 16'b0 [15:0] RW 16'b0 DSH-201010p2 2/4/09 Address: 0x0011000C Name Description Reserved TM_LMT_UW When the current count value of the timer reaches the limit value, an interrupt TM_INT is set. The periodic timer interrupt event rate is = 10.4 MHz / (TM_LMT + 1). If TM_LMT is set to 0, TM_CNT remains reset. TM_CNT is reset whenever TM_LMT_UW is written. Conexant Preliminary Information/Conexant Proprietary and Confidential 59 Registers 3.4.3 CX23885 Data Sheet GPIO Register: GP0_IO Bits Address: 0x00110010 Type Default Name Description [31:24] RO 8'h00 [23:16] RW 8'h00 GP_OE A value of 1 enables corresponding GP_IO bit to be output on the GPIO pin. A value of 0 enables corresponding GP_IO bit to be input on the GPIO pin. [15:8] RO 8'h00 GP_IN The values from the GPIO pins. [7:0] RW* 8'h00 GP_OUT The values to drive out on the GPIO pin. This is a don't-care if GP_OE is set to 0. 3.4.4 Reserved GPIO Interrupts Sensitivity Mode Register: GPIO_ISM Bits Address: 0x00110014 Type Default Name Description [6:4] WO 3'b000 GP_ISM_SNS Sensitivity mode for interrupt inputs GPIO[TBD]. 0 = level-sensitive 1 = edge-sensitive [2:0] WO 3'b000 GP_ISM_POL Polarity control for interrupt inputs GPIO[TBD]. 1 = active-hi or posedge 0 = active-lo or negedge Note this control inverted from SPIPE for active low interrupts default. 3.4.5 Soft Reset Register: SOFT_RESET Bits Type Default [31:1] R0 31'b0 [0] RW 1'b0 60 Address: 0x0011001C Name Description Reserved SOFT_RESET Software reset register bit, writing this bit to 1 will generate reset pulse that reset whole Pecos except PCI-Express Physical layer. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.4.6 Registers GPIO (417 Microcontroller Interface) RW Data Register: MC417_RWD Bits Type Default [31:16] RO 16'b 0 [15:0] RW* 16'b 0 3.4.7 Address: 0x0011002 Name Description Reserved MC417_GPIO_RWD Read/Write data register. The values to drive out on the MC417 GPIO[18:3] pin. When the RD/WR register is read, each bit reads back either the PAD input value if the pad is configured as an input or the latched output value if it is configured as an output. MC417 GPIO[18:3] is mapped to pads {UTX, URX, IRQ_N, GPIO[15:4], select one of GPIO[3:0] by MC417_GPIO_SEL} GPIO (417 Microcontroller) Output Enable, Low Active Register: MC417_OEN Bits Type Address: 0x00110024 Default [31:16] RO 16'b 0 [15:0] RW* 16'h FFFF DSH-201010p2 2/4/09 Name Description Reserved MC417_GPIO_OEN Output Enable of GPIO[18:3] pins When MC417 GPIO Mode is activated, GPIO[18:3] is mapped to {UTX, URX, IRQ_N, GPIO[15:4], select one of GPIO[3:0] by MC417_GPIO_SEL} Conexant Preliminary Information/Conexant Proprietary and Confidential 61 Registers 3.4.8 CX23885 Data Sheet GPIO (417 Microcontroller) Output Enable, Low Active Register: MC417_CTL Bits Type Address: 0x00110028 Default Name Description [31:6] RO 26'b 0 [5:4] RW 2'b 11 [3] RO 1'b 0 [2:1] RW 2'b 11 MC417_GPIO_SEL Select one of 4 GPIO[3:0] pins as MC417 I/F pin, default is 2'b11 indicating GPIO[3] is selected as MC417 GPIO I/F MC417_GPIO_SEL[1:0] = 2'b11: GPIO[3] is selected for MC417 I/F pin MC417_GPIO_SEL[1:0] = 2'b10: GPIO[2] is selected for MC417 I/F pin MC417_GPIO_SEL[1:0] = 2'b01: GPIO[1] is selected for MC417 I/F pin MC417_GPIO_SEL[1:0] = 2'b00: GPIO[0] is selected for MC417 I/F pin [0] RW 1'b 0 UART_GPIO_EN A value of 1 will enable the GPIO[18:16] pins & GPIO[11] pin for microcontroller interface 62 Reserved MC417_SPD_CTL Pad drive strength (or speed) for GPIO[18:4] pins to be used for 417 microcontroller interface 00 = medium 01 = slow 1x = fast Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.4.9 Registers Clock Delay Register: CLK_DELAY Address: 0x00110048 Bits Type [31:20] RO 12'h000 [19:16] RW 4'h0 JTCK_DLY_SEL Select programmable delay for JTCK from 0 buffer delay (4'h0) to 15 buffers delay (4'hF). [15:12] RW 4'h0 PCLK_DLY_SEL Select programmable delay for 62.5 MHz pclk from 0 buffer delay (4'h0) to 15 buffers delay (4'hF). [11:8] RW 4'h1 BCLK_N_DLY_SEL Select programmable delay for 125 MHz bclk_n from 0 buffer delay (4'h0) to 15 buffers delay (4'hF). [7:4] RW 4'h1 BCLK_DLY_SEL Select programmable delay for 125 MHz bclk from 0 buffer delay (4'h0) to 15 buffers delay (4'hF). [3:0] RW 4'h2 MCLK_DLY_SEL Select programmable delay for 250 MHz mclk from 0 buffer delay (4'h0) to 15 buffers delay (4'hF). DSH-201010p2 2/4/09 Default Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 63 Registers CX23885 Data Sheet 3.4.10 Pad Control Register: PAD_CTRL Bits Type Address: 0x0011004C Default Name Description [31:26] RO 6'b000000 [25:24] RW 2'b00 MISC_SPD Pad drive strength (or speed) for miscellaneous pins, RESET_OUT_N and TEST, PERST_N (these are input only for now and not testable): 00 = medium 01 = slow 1x = fast [23:22] RW 2'b01 GPIO_SPD Pad drive strength (or speed) for GPIO, IRQN pins: 00 = medium 01 = slow 1x = fast [21:20] RW 2'b01 UART_SPD Pad drive strength (or speed) for UART interface pins, UTX, URX: 00 = medium 01 = slow 1x = fast [19:18] RW 2'b00 TS2_SPD Pad drive strength (or speed) for TS2 interface pins, TS2_SOP, TS2_DATA, TS2_VAL, and TS2_CLK: 00 = medium 01 = slow 1x = fast [17:16] RW 2'b00 TS1_SPD Pad drive strength (or speed) for TS1 interface pins, TS1_DATA, TS1_VAL, TS1_CLK, and TS1_SOP: 00 = medium 01 = slow 1x = fast [15:10] RO 6'b000000 [9] RW 1'b1 64 Reserved Reserved I2C2_MODE Puts I2C#2 SCL and SDA pads into I2C mode. 0 = I2C2_SDA, I2C2_SCL pads in generalpurpose I/O mode 1 = I2C2_SDA, I2C2_SCL pads in I2C mode Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [8] RW 1'b1 [7:3] RO 5'b00000 [2] RW 1'b0 TS2_SOP_OE When set, enables the output driver for the TS2_SOP pin, the Transport Stream 2 start-ofpacket pin. 0 = TS2_SOP in input mode 1 = TS2_SOP in output mode [1] RW 1'b0 TS1_SOP_OE When set, enables the output driver for the TS1_SOP pin, the Transport Stream 1 start-ofpacket pin. 0 = TS1_SOP in input mode 1 = TS1_SOP in output mode [0] RW 1'b0 TS1_OE When set, enables the output driver for the followingTS1 (Transport Stream 1) data, clock, and valid pins: * TS1_VAL * TS1_CLK * TS1_DATA[7:0] To summarize: 0 ts1 pins in input mode 1 ts1 pins in output mode DSH-201010p2 2/4/09 I2C1_MODE Puts I2C#1 SCL and SDA pads into I2C mode. 2 = I2C1_SDA, I2C1_SCL pads in generalpurpose I/O mode 3 = I2C1_SDA, I2C1_SCL pads in I2C mode Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 65 Registers CX23885 Data Sheet 3.5 Memory Mapped Registers: Video A Interface 3.5.1 Video A General Purpose Counter Register: VID_A_GPCNT Address: 0x00130020 Register: VBI_A_GPCNT Address: 0x00130024 Bits Type [31:16] RO 16'b0 [15:0] RO 16'b0 3.5.2 Default Name Description Reserved {x}_GP_CNT General purpose counter used by RISC program. Video A General Purpose Counter Control Register: VID_A_GPCNT_CTL Address: 0x00130030 Register: VBI_A_GPCNT_CTL Address: 0x00130034 Bits [1:0] 3.5.3 Type WO Default 2'b00 Name {x}_GPCTL Description General purpose counter control used by RISC program: 00 = no change 01 = increment 10 = reserved 11 = reset to 0 Video A DMA Control Register: VID_A_DMA_CTL Bits Type Default Address: 0x00130040 Name Description [7:6] RO 2'b0 [5] RW 1'b0 VBI_A_RISC_EN VBI RISC controller enable. [4] RW 1'b0 VID_A_RISC_EN Video RISC controller enable. [3:2] RO 2'b0 [1] RW 1'b0 VBI_A_FIFO_EN VBI FIFO enable. [0] RW 1'b0 VID_A_FIFO_EN Video FIFO enable. 66 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.5.4 Registers Video A VIP Control Register: VID_A_VIP_CTRL Bits Type Default [31:1] RO 31'h00000000 [0] RW 1'b0 3.5.5 Address: 0x00130080 Name Description Reserved VIP_MODE This bit is used to specify the format of the input data, vip 1.1 or vip 2.0. 1'b0 = VIP 1.1 1'b1 = VIP 2.0 Video A Pixel Format Register: VID_A_PIXEL_FRMT Bits Type Default Address: 0x00130084 Name Description [31:5] RO 28'h0000000 [4] RW 1'b0 VID_A_GAMMA_FACT OR Gamma Correction removal factor selection for video channel A. 1'b0 = 2.2 factor (NTSC) 1'b1 = 2.8 factor (PAL & SECAM) [3] RW 1'b1 VID_A_GAMMA_DIS A value of 0 enables gamma correction removal for Video channel A. The inverse gamma correction factor of 2.2 or 2.8 is determined by the vid_a_gamma_factor register bit. 1'b0 = enables gamma correction removal 1'b1 = disables gamma correction removal [2:0] RW 3'b000 VID_A_FORMAT Video A Color Format 000 = RGB32 001 = RGB24 010 = RGB16 011 = RGB15 100 = YUV2 4:2:2 101 = BtYUV 4:1:1 110 = Y8 (Gray scale) 111 = Y210 (10-bit YCrCb 4:2:2) DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 67 Registers 3.5.6 CX23885 Data Sheet Video A VBI Control Register: VID_A_VBI_CTRL Bits Type Default [31:2] RO 30'h00000000 [1:0] RW 2'b00 68 Address: 0x00130088 Name Description Reserved VID_A_VIP_EXT VBI select extension enable This field determines which lines get captured as vbi data independent of the lines that are captured for the video data. 2'b00 = DMA buffer for VBI data will contain VBLANK number of lines 2'b01 = DMA buffer for VBI data will contains (VBLANK +1) number of lines 2'b10 = DMA buffer for VBI data will contains (VBLANK +2) number of lines 2'b01 = DMA buffer for VBI data will contains (VBLANK +3) number of lines Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.6 Registers Memory Mapped Registers: Video B Interface Register: VID_B_DMA Address: 0x00130100 Register: VBI_B_DMA Address: 0x00130108 Bits [63:0] 3.6.1 Type RW Default 64'bx Name Description {x}_DMA qword port for DMA destination access. Video B General Purpose Counter Register: VID_B_GPCNT Address: 0x00130120 Register: VBI_B_GPCNT Address: 0x00130124 Bits Type [31:16] RO 16'b0 [15:0] RO 16'b0 3.6.2 Default Name Description Reserved {x}_GP_CNT General purpose counter used by RISC program. Video B General Purpose Counter Control Register: VID_B_GPCNT_CTL Address: 0x00130134 Register: VBI_B_GPCNT_CTL Address: 0x00130138 Bits [1:0] Type WO DSH-201010p2 2/4/09 Default 2'b00 Name {x}_GPCTL Description General purpose counter control used by RISC program: 00 = no change 01 = increment 10 = reserved 11 = reset to 0 Conexant Preliminary Information/Conexant Proprietary and Confidential 69 Registers 3.6.3 CX23885 Data Sheet Video B DMA Control Register: VID_B_DMA_CTL Bits Type Address: 0x00130140 Default Name Description [7:6] RO 2'b0 [5] RW 1'b0 VBI_B_RISC_EN VBI RISC controller enable [4] RW 1'b0 VID_B_RISC_EN Video RISC controller enable [3:2] RO 2'b0 [1] RW 1'b0 VBI_B_FIFO_EN VBI FIFO enable [0] RW 1'b0 VID_B_FIFO_EN Video FIFO enable 3.6.4 Reserved Reserved Video B Source Select Register: VID_B_SRC_SEL Bits Type Default [31:1] RO 31'b0 [0] RW 1'b0 3.6.5 Address: 0x00130144 Name Description Reserved VID_B_SRC_SEL Video B source select 0 = External 656 Video 1 = Parallel MPEG Video Video B TS Line Length Register: VID_B_LNGTH Bits Type Default [31:12] RO 20'b0 [11:0] RW 12'b0 70 Address: 0x00130150 Name Description Reserved VID_B_LN_LNGTH Transport stream line length in bytes. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.6.6 Registers Video B TS HW SOP Control Register: VID_B_HW_SOP_CTL Bits Type Default Address: 0x00130154 Name Description [31:24] RO 8'b0 [23:16] RW 8'd47 APB_STRT_BYTE Byte start pattern that is searched for in the mpeg transport stream that signals start of transport stream. This is issued every mpeg packet. [15:4] RW 12'd188 APB_PKT_LNGTH Used to sync/mark detect SOP [3] RW 1'b0 APB_CAP_ALL A value of 1 allows all data of a punctured clock stream to be captured. A value of 0 will result in the first two packets to be lost. This bit must only be set to 1 when in punctured clock mode. [2] RW 1'b0 APB_AUTO_SOP A value of 1 eliminates the need for an external start of packet in punctured clock mode. It must only be used with APB_SOP_SEL = 00. A value of 0 allows all other start of packet modes to be used. [1:0] RW 2'b00 APB_STRT_FLTR_CNT Defines the number of apb_strt_bytes that need to be detected before the mpeg fec interface is declared as being in sync. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 71 Registers 3.6.7 CX23885 Data Sheet Video B TS General Control Register: VID_B_GEN_CTL Bits Type Default Address: 0x00130158 Name Description [31:9] RO 23'b0 [8] RW 1'b0 APB_DREQ_POL Polarity of Data Request output signal. 0 = The polarity is active high. Data Request will be high when the TSCLK_EN register bit that drives it is high. 1 = The polarity is active low. Data Request will be low when the TS_CLK_EN register bit that drives it is high. [7] WO 1'b0 APB_STAT_CLR Active-High reset for stat registers. [6] WO 1'b0 APB_SW_RST Active-High Software reset. Writing a 1 to this bit causes the MPEG TS logic to be held in reset for 128 pclk cycles. [5] RW 1'b0 APB_ERR_ACK Determines whether the interface is in an error ack mode. This is only valid while APB_PUNC_CLK is active. [4] RW 1'b0 APB_BIT_RVRS This reverses each byte-wide input one byte at a time. [3] RW 1'b1 APB_SMODE Input Mode Select. 0 - Parallel Mode 1 - Serial Mode [2] RW 1'b0 APB_PUNC_CLK Determines whether the TS interface is operating in punctured clock mode. [1] RW 1'b0 APB_MCLK_POL Polarity of MPEG generated MCLK. Default means TS inputs are negedge driven. When asserted high TS inputs are negedge sampled and assumed posedge driven. [0] RO 1'b0 MPEG_IN_SYNC Active-high "in sync" indicator for MPEG. 72 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.6.8 Registers Video B TS Bad Packet Status Register: VID_B_BD_PKT_STATUS Bits Type Address: 0x0013015C Default Name Description [31:13] RO 19'b0 [12] RW 1'b0 APB_BAD_PKT_CHK Enables bad pkt status and mpeg_bad_pkt interrupt [11:0] RO 12'h000 MPG_BAD_PKT_STAT Bad pkt counter status. When enabled, counter output is incremented every time a packet number of bytes received is less than or greater than the expected programmed number of bytes. Counter status is updated at the falling edge of TS_BAD_PKT interrupt, generated by the internal mpeg_ts. 3.6.9 Reserved Video B TS SOP Status Register: VID_B_SOP_STATUS Bits Type Default Address: 0x00130160 Name Description [31:17] RO 15'b0 [16] RW 1'b0 APB_TSSOP_POL Polarity select 0 - Active High (default) 1 - Active Low [15:14] RW 2'b00 APB_SOP_SEL SOP Format. 00-- detects rising edge of TSSOP input 01-- detects rising edge of TSVALERR input 10-- detects rise and fall edge of TSSOP input 11 - detects start byte in data stream [13] RW 1'b0 APB_SOP_BYTEWIDE SOP width select. Byte wide is only an option in serial mode. 0 - Bit width 1 - Byte width [12] RW 1'b0 APB_SOP_SYNC_CHK Enables bad sop status and mpeg_bad_pkt interrupt [11:0] RO 12'h000 MPG_BAD_SOP_STAT Bad SOP counter status. When enabled, counter output is incremented every time there is a SOP mis-compare. Counter status is updated at the falling edge of TS_BAD_PKT interrupt, generated by the internal mpeg_ts. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 73 Registers CX23885 Data Sheet 3.6.10 Video B TS Fifo Overflow Status Register: VID_B_FIFO_OVFL_STAT Bits Type Default Address: 0x00130164 Name Description [31:13] RO 19'b0 Reserved [12] RW 1'b0 APB_FIFO_OVFL_CHK Enables FIFO overflow status and mpeg_bad_pkt [11:0] RO 12'h000 MPG_FIFO_OVFL_STAT When enabled the counter output is incremented every time the mpeg TS FIFO overflows. Counter status is updated at the falling edge of TS_BAD_PKT interrupt, generated by the internal mpeg_ts. 3.6.11 Video B TS Valid Miscellaneous Register: VID_B_VLD_MISC Bits Type Default Address: 0x00130168 Name Description [31:14] RO 18'b0 [13] RW 1'b0 APB_TSVALERR_POL Control for polarity of tsvalerr input. 0 - Active-High (Default) 1 - Active-Low [12] RW 1'b0 APB_VAL_SEL Selects whether tsvalerr is active. 0-- selects the external tsvalerr (default) 1-- internally generated valid [11:0] RW 12'h000 APB_VAL_LNGTH Programmable valid length. Used when mode requires TS to be terminated after a count vs. the input valid (tsvalerr) 74 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.6.12 Video B TS Clock Enable Register: VIDB_TS_CLK_EN Bits Type Default [31:1] RO 31'b0 [0] RW 1'b1 Address: 0x0013016C Name Description Reserved VID_TS_CLK_EN TS_CLK enable for TS1 0 = disable TS_CLK 1 = enable TS_CLK This register bit will also drive the Data Request output signal to the device that is the source of the MPEG TS. The Data Request signal will share a pin with the Start Of Packet input signal, as they are not needed simultaneously. 3.6.13 Video B VIP Control Register: VID_B_VIP_CTRL Bits Type Default [31:1] RO 31'h00000000 [0] RW 1'b0 DSH-201010p2 2/4/09 Address: 0x00130180 Name Description Reserved VID_B_VIP_MODE This bit is used to specify the format of the input data, vip 1.1 or vip 2.0. 1'b0 = VIP 1.1 1'b1 = VIP 2.0 Conexant Preliminary Information/Conexant Proprietary and Confidential 75 Registers CX23885 Data Sheet 3.6.14 Video B Pixel Format Register: VID_B_PIXEL_FRMT Bits Type Default Address: 0x00130184 Name Description [31:5] RO 28"h0000000 [4] RW 1'b0 VID_B_GAMMA_FACT OR Gamma Correction removal factor selection for video channel B. 1'b0 = 2.2 factor (NTSC) 1'b1 = 2.8 factor (PAL & SECAM) [3] RW 1'b1 VID_B_GAMMA_DIS A value of 0 enables gamma correction removal for Video channel B. The inverse gamma correction factor of 2.2 or 2.8 is determined by the vid_a_gamma_factor register bit. 1'b0 = enables gamma correction removal 1'b1 = disables gamma correction removal [2:0] RW 3'b000 VID_B_FORMAT Video B Color Format 000 = RGB32 001 = RGB24 010 = RGB16 011 = RGB15 100 = YUV2 4:2:2 101 = BtYUV 4:1:1 110 = Y8 (Gray scale) 111 = Y210 (10-bit YCrCb 4:2:2) 76 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.7 Memory Mapped Registers: Video C Interface 3.7.1 Video C General Purpose Counter Register: VID_C_GPCNT Bits Type Default [31:16] RO 16'b0 [15:0] RO 16'b0 3.7.2 Address: 0x00130220 Name Description Reserved {x}_GP_CNT General purpose counter used by RISC program. Video C General Purpose Counter Control Register: VID_C_GPCNT_CTL Bits [1:0] 3.7.3 Type WO Default 2'b00 Address: 0x00130230 Name {x}_GPCTL Description General purpose counter control used by RISC program: 00 = no change 01 = increment 10 = reserved 11 = reset to 0 Video C DMA Control Register: VID_C_DMA_CTL Bits Type Default [7:5] RO 3'b0 [4] RW 1'b0 [3:1] RO 3'b0 [0] RW 1'b0 DSH-201010p2 2/4/09 Address: 0x00130240 Name Description Reserved VID_C_RISC_EN Video RISC controller enable Reserved VID_C_FIFO_EN Video FIFO enable Conexant Preliminary Information/Conexant Proprietary and Confidential 77 Registers 3.7.4 CX23885 Data Sheet Video C TS Line Length Register: VID_C_LNGTH Bits Type Default [31:12] RO 20'b0 [11:0] RW 12'b0 3.7.5 Address: 0x00130250 Name Description Reserved VID_C_LN_LNGTH Transport stream line length in bytes Video C TS HW SOP Control Register: VID_C_HW_SOP_CTL Bits Type Default Address: 0x00130254 Name Description [31:24] RO 8'b0 [23:16] RW 8'h47 APB_STRT_BYTE Byte start pattern that is searched for in the mpeg transport stream that signals start of transport stream. This is issued every mpeg packet. [15:4] RW 12'hBC APB_PKT_LNGTH Used to sync/mark detect SOP [3] RW 1'b0 APB_CAP_ALL A value of 1 allows all data of a punctured clock stream to be captured. A value of 0 will result in the first two packets to be lost. This bit must only be set to 1 when in punctured clock mode. [2] RW 1'b0 APB_AUTO_SOP A value of 1 eliminates the need for an external start of packet in punctured clock mode. It must only be used with APB_SOP_SEL = 00. A value of 0 allows all other start of packet modes to be used. [1:0] RW 2'b00 APB_STRT_FLTR_CNT Defines the number of apb_strt_bytes that need to be detected before the mpeg fec interface is declared as being in sync. 78 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.7.6 Registers Video C TS General Control Register: VID_C_GEN_CTL Bits Type Default Address: 0x00130258 Name Description [31:9] RO 23'b0 [8] RW 1'b0 APB_DREQ_POL Polarity of Data Request output signal. 0 = the polarity is active high. Data Request will be high when the TS_CLK_EN register bit that drives it is high. 1 = the polarity is active low. Data Request will be low when the TS_CLK_EN register bit that drives it is high. [7] WO 1'b0 APB_STAT_CLR Active-High reset for stat registers. [6] WO 1'b0 APB_SW_RST Active-High Software reset. Writing a 1 to this bit causes the MPEG TS logic to be held in reset for 128 pclk cycles. [5] RW 1'b0 APB_ERR_ACK Determines whether the interface is in an error ack mode. This is only valid while APB_PUNC_CLK is active. [4] RW 1'b0 APB_BIT_RVRS This reverses each byte-wide input one byte at a time. [3] RW 1'b1 APB_SMODE Input Mode Select. 0 - Parallel Mode 1 - Serial Mode [2] RW 1'b0 APB_PUNC_CLK Determines whether the TS interface is operating in punctured clock mode. [1] RW 1'b0 APB_MCLK_POL Polarity of MPEG generated MCLK. Default means TS inputs are negedge driven. When asserted high TS inputs are negedge sampled and assumed posedge driven. [0] RO 1'b0 MPEG_IN_SYNC Active-high "in sync" indicator for MPEG. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 79 Registers 3.7.7 CX23885 Data Sheet Video C TS Bad Packet Status Register: VID_C_BD_PKT_STATUS Bits Type Default Address: 0x0013025C Name Description [31:13] RO 19'b0 [12] RW 1'b0 APB_BAD_PKT_CHK Enables bad pkt status and mpeg_bad_pkt interrupt [11:0] RO 12'h000 MPG_BAD_PKT_STAT Bad pkt counter status. When enabled, counter output is incremented every time a packet number of bytes received is less than or greater than the expected programmed number of bytes. Counter status is updated at the falling edge of TS_BAD_PKT interrupt, generated by the internal mpeg_ts. 3.7.8 Reserved Video C TS SOP Status Register: VID_C_SOP_STATUS Bits Type Default Address: 0x00130260 Name Description [31:17] RO 15'b0 [16] RW 1'b0 APB_TSSOP_POL Polarity select 0 = Active High (default) 1 = Active Low [15:14] RW 2'b00 APB_SOP_SEL SOP Format. 00 = detects rising edge of TSSOP input 01 = detects rising edge of TSVALERR input 10 = detects rise and fall edge of TSSOP input 11 = detects start byte in data stream [13] RW 1'b0 APB_SOP_BYTEWIDE SOP width select. Byte wide is only an option in serial mode. 0 = Bit width 1 = Byte width [12] RW 1'b0 APB_SOP_SYNC_CHK Enables bad sop status and mpeg_bad_pkt interrupt [11:0] RO 12'h000 MPG_BAD_SOP_STAT Bad SOP counter status. When enabled, counter output is incremented every time there is a SOP mis-compare. Counter status is updated at the falling edge of TS_BAD_PKT interrupt, generated by the internal mpeg_ts. 80 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.7.9 Registers Video C TS Fifo Overflow Status Register: VID_C_FIFO_OVFL_STAT Default Address: 0x00130264 Bits Type Name Description [31:13] RO 19'b0 [12] RW 1'b0 APB_FIFO_OVFL_CHK Enables FIFO overflow status and mpeg_bad_pkt. [11:0] RO 12'h000 MPG_FIFO_OVFL_STAT When enabled the counter output is incremented every time the mpeg TS FIFO overflows. Counter status is updated at the falling edge of TS_BAD_PKT interrupt, generated by the internal mpeg_ts. Reserved 3.7.10 Video C TS Valid Miscellaneous Register: VID_C_VLD_MISC Bits Type [31:14] RO 18'b0 [13] RW 1'b0 APB_TSVALERR_POL Control for polarity of tsvalerr input. 0 = Active-High (Default) 1 = Active-Low [12] RW 1'b0 APB_VAL_SEL Selects whether tsvalerr is active. 0 = selects the external tsvalerr (default) 1 = internally generated valid [11:0] RW 12'h000 APB_VAL_LNGTH Programmable valid length. Used when mode requires TS to be terminated after a count vs. the input valid (tsvalerr) DSH-201010p2 2/4/09 Default Address: 0x00130268 Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 81 Registers CX23885 Data Sheet 3.7.11 Video C TS Clock Enable Register: VIDC_TS_CLK_EN Bits Type Default Address: 0x0013026C Name Description [31:1] RO 31'b0 [0] RW 1'b0 VIDC_TS_CLK_EN TS_CLK_enable for TS2 0 =disable TS_CLK 1 = enable TS_CLK This register bit will also drive the Data Request output signal to the device that is the source of the MPEG TS. The Data Request signal will share a pin with the Start Of Packet input signal, as they are not needed simultaneously. [12] RW 1'b0 APB_VAL_SEL Selects whether tsvalerr is active. 0 = selects the external tsvalerr (default) 1 = internally generated valid [11:0] RW 12'h000 APB_VAL_LNGTH Programmable valid length. Used when mode requires TS to be terminated after a count vs. the input valid (tsvalerr) 82 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.8 Memory Mapped Registers: Internal Audio Interface 3.8.1 Audio Internal General Purpose Counter Register: AUD_INT_A_GPCNT Address: 0x00140020 Register: AUD_INT_B_ GPCNT Address: 0x00140024 Bits Type Default [31:16] RO 16'b0 [15:0] RO 16'b0 3.8.2 Name Description Reserved {x}_GP_CNT General purpose counter used by RISC program. Audio Internal General Purpose Counter Control Register: AUD_INT_A_GPCNT_CTL Address: 0x00140030 Register: AUD_INT_B_GPCNT_CTL Address: 0x00140034 Bits [1:0] 3.8.3 Type WO Default 2'b00 Name {x}_GPCTL Description General purpose counter control used by RISC program: 00 = no change 01 = increment 10 = reserved 11 = reset to 0 Audio Internal DMA Control Register: AUD_INT_DMA_CTL Bits Type Default Address: 0x00140040 Name Description [7:6] RO 2'b0 [5] RW 1'b0 AUD_INT_B_RISC_EN Internal audio B RISC controller enable [4] RW 1'b0 AUD_INT_A_RISC_EN Internal audio A RISC controller enable [3:2] RO 2'b0 [1] RW 1'b0 AUD_INT_B_FIFO_EN Internal audio B FIFO enable [0] RW 1'b0 AUD_INT_A_FIFO_EN Internal audio A FIFO enable DSH-201010p2 2/4/09 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 83 Registers 3.8.4 CX23885 Data Sheet Audio Internal Line Length Register: AUD_INT_A_LNGTH Address: 0x00140050 Register: AUD_INT_B_LNGTH Address: 0x00140054 Bits Type Default [31:12] RO 20'b0 [11:0] RW 12'b0 3.8.5 Name Description Reserved AUD{x}_LNGTH Internal audio line length in bytes Audio Internal Mode Selection Register: AUD_INT_A_MODE Address: 0x00140058 Register: AUD_INT_B_MODE Address: 0x0014005C Bits Type Default [31:1] RO 20'b0 [0] RW 1'b0 84 Name Description Reserved AUD{x}_MODE Internal audio mode: 1 = 32 bits input mode (16 bits L/R) 0 = 48 bits input mode (24 bits L/R) Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.9 Memory Mapped Registers: External Audio Interface 3.9.1 Audio External DMA Port Register: AUD_EXT_DMA Bits [63:0] 3.9.2 Type RW p Address: 0x00140100 Default 64'bx Name {x}_DMA Description qword port for DMA destination access Audio External General Purpose Counter Register: AUD_EXT_GPCNT Bits Type Default [31:16] RO 16'b0 [15:0] RO 16'b0 3.9.3 Address: 0x00140120 Name Description Reserved {x}_GP_CNT General purpose counter used by RISC program Audio External General Purpose Counter Control Register: AUD_EXT_GPCNT_CTL Bits [1:0] Type WO DSH-201010p2 2/4/09 Default 2'b00 Address: 0x00140130 Name {x}_GPCTL Description General purpose counter control used by RISC program: 00 = no change 01 = increment 10 = reserved 11 = reset to 0 Conexant Preliminary Information/Conexant Proprietary and Confidential 85 Registers 3.9.4 CX23885 Data Sheet Audio External DMA Control Register: AUD_EXT_DMA_CTL Bits Type Default [7:5] RO 3'b0 [4] RW 1'b0 [3:1] RO 3'b0 [0] RW 1'b0 3.9.5 Address: 0x00140140 Name Description Reserved AUD_EXT_RISC_EN External audio RISC controller enable Reserved AUD_EXT_FIFO_EN External audio FIFO enable Audio External Line Length Register: AUD_EXT_LNGTH Bits Type [31:12] RO 20'b0 [11:0] RW 12'b0 3.9.6 Default Address: 0x00140150 Name Description Reserved AUD_EXT_LN_LNGTH External audio line length in bytes Audio External Mode Selection Register: AUD_EXT_A_MODE Bits Type Default [31:1] RO 20'b0 [0] RW 1'b0 86 Address: 0x00140158 Name Description Reserved AUD_EXT_MODE External audio input mode: 1 = 32 bits input mode (16 bits L/R) 0 = 48 bits input mode (24 bits L/R) Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.10 Registers Memory Mapped Registers: I2C Master The I2C protocol defines a method to send and receive a variable number of bytes via a serial bus that interconnects several IC's. Corona contains an I2C master than can drive this bus, and the registers below provide the programmable interface to three I2C masters. There are three sets of registers, one for each I2C master. First, some background is useful on the basic I2C protocol. The basic I2C protocol for writes: 1. Send Start sequence (SDA falls while SCL is high) 2. Send 7-bit Device Address 3. Send R/W bit, set to 0 4. Check for Slave Ack, and if received, continue 5. Send variable number of bytes, checking for Ack after each byte 6. Optionally send Stop (SDA rises while SCL is high) The basic I2C protocol for reads: 1. Send Start (SDA falls while SCL is high) 2. Send 7-bit Device Address 3. Send R/W bit, set to 1 4. Check for Slave Ack, and if received, turnaround bus to let slave drive bus 5. Receive variable number of bytes, send Ack after each byte until done 6. Optionally send stop (SDA rises while SCL is high) The Stop condition is not important for most slaves, since the next Start (or repeated Start) will re-initialize its state the same as a Stop would. The Stop is important for multi-master systems, and as it's a way for a master to relinquish control of the bus. But while I2C defines only this simple mechanism of transmitting or receiving a variable number of bytes to/from a specific device address, it is customary for devices to define the first N bytes of a write (one to three bytes have been observed) as a subaddress. This subaddress typically functions as an index into a register map. Also, it is typical for slave devices to support the concept that the byte transmitted after this subaddress goes to the location specified by that subaddress, and each subsequent byte goes to an auto incrementing address from the initial point. Reads work in a similar manner, but since reads cycles do not have a means to send a subaddress, the convention is that reads come from the last subaddress sent on a write transaction. Thus, a read of a specific subaddress is often accomplished by transmitting the subaddress bytes through a write, followed by a read transaction. Each byte from the read is assumed to come from auto incrementing addresses, starting at the subaddress sent by the write. The idea of the programmable register interface described in the following sections is to allow software to flexibly execute the basic I2C protocol, while providing some convenience features for devices that conform to a typical subaddress model. The hardware provides three methods for software to interface to the I2C bus: 1. Software Mode. Directly toggle the SCL and SDA lines, thereby implementing the protocol through software. (All other modes are hardware mode.) 2. Simple Mode. For writes, specify the Device Address, the number of bytes to send (0 to 4), and the data bytes themselves. For reads, specify the Device Address, the number of bytes to receive, and read the received bytes from a register. I2C_SADDR_LEN is set to 0 for this mode. The I2C_DATA_LEN specifies the number of bytes to send or receive. 3. Subaddress Mode. This supports directly the subaddress model. For writes, the hardware automatically inserts a subaddress before the data bytes. The number of subaddress bytes to insert is controlled by I2C_SADDR_LEN, which can be 1 to 3. For reads, the hardware will automatically insert a subaddress write before receiving data bytes. This mode provides a couple of features for software. First, because the subaddress field has an auto increment feature, software need not DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 87 Registers CX23885 Data Sheet re-write this field each time if is doing multiple write or read transactions to sequential addresses. Second, the hardware knows which bytes to send to set the subaddress before issuing a read transaction. Thus, an important feature is the ability to specify both the number of address bytes, and the number of data bytes in any given I2C cycle. The hardware also provides some additional features to optimize hardware mode operation: 1. Extend mode. This allows software to generate any length I2C transaction by repeatedly accessing the register set. This eliminates the inefficiency of resending the device address and subaddress bytes. By setting I2C_EXTEND, each time an I2C transaction is triggered, the hardware will just continue the previous transaction, transmitting or receiving the number of bytes specified in I2C_DATA_LEN. No Stop or Start transitions will be generated. The current I2C transaction will be extended until the I2C_EXTEND bit is disabled. 2. Simple read mode. The hardware can support a subaddress field on writes, but disable the feature that sends an I2C write transaction to set subaddress field prior to reads. This prevents unnecessary write transactions if the slave device is keeping track of the subaddress anyway. Set I2C_READ_SA to 0 for simple read mode. To trigger a hardware mode I2C cycle, simple write to the I2C{X}_CNTRL dword. For writes, software should have already written the I2C{X}_DATA and I2C{X}_ADDR registers. Software can launch another I2C operation after the I2C_XFER_RDY bit is set. For reads, software should write the I2C{X}_ADDR register before initiating the read with a write to the I2C{X}_CNTRL dword. After the I2C_XFER_RDY bit is set, the read data will be available in the I2C{X}_DATA register. 88 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.10.1 I2C Address This DWORD contains address information. Note that the R/W bit, normally bundled with the I2C Device Address, is not included here, but is specified in the control word. A write must be performed to the I2C{x}_CTRL register to initiate an I2C transaction. Register: I2C1_ADDR Address: 0x00180000 Register: I2C2_ADDR Address: 0x00190000 Register: I2C3_ADDR Address: 0x001A0000 Bits Type [31:25] RW 7'h00 [24] RO 1'b0 [23:0] RW 1'b1 DSH-201010p2 2/4/09 Default Name Description I2C_DADDR I2C Device Address. These 7 bits contain the device address. Note that the 7 bits are left justified within the byte. These bits are transmitted for every transaction, after the Start transition is generated. Reserved I2C_SADDR I2C subaddress. For I2C Writes only, these bytes are sent after the device address is sent. The I2C_SADDR_LEN field determines how many bytes are sent, which can be 0 to 3. The subaddress is right-justified within the three-byte field, such that if only one byte is transmitted, it will come from I2C_SADDR[7:0]. The address will be incremented with each I2C byte transaction, if I2C_SADDR_INC is set. Conexant Preliminary Information/Conexant Proprietary and Confidential 89 Registers CX23885 Data Sheet 3.10.2 I2C Write Data This register contains the data bytes to send in a write transaction. If I2C_SADDR_LEN is set to something other than zero, then these bytes will come after the subaddress field is transmitted. Otherwise, these bytes define all of the bytes that are sent. The number of bytes sent depends on the I2C_DATA_LEN parameter, which can be 0 to 4. The counting and transmitting starts at the least-significant byte (I2C_WDATA[7:0]). A write must be performed to the I2C{x}_CTRL register to initiate an I2C transaction. Register: I2C1_WDATA Address: 0x00180004 Register: I2C2_WDATA Address: 0x00190004 Register: I2C3_WDATA Address: 0x001A0004 Bits [31:0] Type RW Default Name 0x0 Description I2C_WDATA I2C Write Data. Write data is transmitted leastsignificant byte first. 3.10.3 I2C Control Writing to this register will trigger an I2C read or write operation based on the I2C_READ_WRN bit. Register: I2C1_CTRL Address: 0x00180008 Register: I2C2_CTRL Address: 0x00190008 Register: I2C3_CTRL Address: 0x001A0008 Bits Type [31:24] RW 8'h9D, 8'h27, 8'h27 [23:22] RO 2'b0 90 Default Name Description I2C_PERIOD Period of I2C Clock For 12C1_CTRL: I2C_PERIOD = Period (ns) / 16 (pclk period) * 4 - 1 Default is set for 99.5 kHz operation (to be less than or equal to 100 kHz). For 12C1_CTRL: I2C_PERIOD = Period (ns) / 16 (pclk period) * 4 - 1 Default is set for 391 kHz operation (to be less than or equal to 400 kHz) For 12C1_CTRL: I2C_PERIOD = Period (ns) / 16 (pclk period) * 4 Default is set for 1.95 MHz operation (to be less than 2.0 MHz) Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [21] RO 1'b1 I2C_SCL_IN Reading this bit provides access to the buffered SCL input pin. [20] RO 1'b1 I2C_SDA_IN Reading this bit provides access to the buffered SDA input pin. [19:18] RO 2'b0 [17] RW 1'b1 I2C_SCL_OUT A value of 1 releases the SCL output, and a 0 forces the SCL output low. This override is for direct software control of the bus. Set I2C_SOFT to 1 to enable this bit. [16] RW 1'b1 I2C_SDA_OUT A value of 1 releases the SDA output, and a 0 forces the SDA output low. This override is for direct software control of the bus. Set I2C_SOFT to 1 to enable this bit. [15] RO 1'b0 [14:12] RW 3'b001 I2C_DATA_LEN Data Length in Bytes. Determines number of bytes to send from I2C_DATA after subaddress field. The I2C engine begins transmitting with I2C_WDATA[7:0] and proceeds to the MSB for writes. Similarly, for reads, the I2C engine stores read data first in I2C_RDATA[7:0] and proceeds to the MSB. For writes, the action is as follows: 0 = send no data bytes 1 = write I2C_WDATA[7:0] 2 = write I2C_WDATA[15:0] 3 = write I2C_WDATA[23:0] 4 = write I2C_WDATA[31:0] 5-7 = reserved For writes, the action is as follows: 0 = read no data bytes 1 = read to I2C_RDATA[7:0] 2 = read to I2C_RDATA[15:0] 3 = read to I2C_RDATA[23:0] 4 = read to I2C_RDATA[31:0] 5-7 = reserved If the logic automatically generates a write to set the subaddress for a read operation, then this field is a don't-care for the write, and should be set based on the number of bytes to read. [11] RW 1'b1 I2C_SADDR_INC Address Auto Increment. When set, the subaddress field in I2C_SADDR[23:0] is automatically incremented. [10] RO 1'b0 DSH-201010p2 2/4/09 Reserved Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 91 Registers CX23885 Data Sheet [9:8] RW 2'b10 [7:6] RO 2'b00 [5] RW 1'b0 I2C_SOFT I2C mode. When set, software drives the SDA and SCL directly through the I2C_SDA and I2C_SCL register bits. 0 = hardware. 1 = software. [4] RW 1'b0 I2C_NOSTOP I2C stop mode. 0 = transmit stop at end of transaction. 1 = do not transmit stop at end of transaction. Hold SCL low. [3] RW 1'b0 I2C_EXTEND I2C Extend Mode. 0 = each transaction ends with a STOP (unless I2C_NOSTOP is set) and returns to idle. 1 = Transaction does end with a STOP, and does not go back to IDLE. The SCL signal remains low. The next transaction will result in data transmission or reception only according to I2C_READ_WRN and I2C_DATA_LEN, without START or device address transmission. Note: do not change the I2C_READ_WRN bit while in Extend mode. To exit extend mode, send last data transaction without I2C_EXTEND mode = 0. [2] RW 1'b0 I2C_SYNC I2C synchronization. 0 = disallows the slave to insert wait states. 1 = allows the slave to insert bit-level clock wait states. [1] RW 1'b0 I2C_READ_SA I2C Read with subaddress. When set, I2C read transaction is preceded with I2C write transaction that sets subaddress field. This can be used to avoid unnecessary writes if the I2C slave already has an internal subaddress register set. 0 = I2C read operations result in a single I2C read transaction to the Device Address 1 = I2C read operations results in an I2C write transaction to set the subaddress field, followed by a read transaction. [0] RW 1'b0 I2C_READ_WRN I2C Read/Write bit. 0 = Issue I2C Write transaction 1 = Issue I2C Read operation subject to I2C_READ_SA bit. 92 I2C_SADDR_LEN Address Length in Bytes. Determines the number of bytes to send from I2C1_ADDR as subaddress field of the I2C write transaction. This field follows the device address. The transmission starts with most-significant byte, and which byte this is depends on I2C_SADDR_LEN. The significance of the subaddress field is that it can support an auto increment feature compared with data bytes. 0 = send/read no subaddress field bytes 1 = write/read I2C_SADDR[7:0] 2 = write/read I2C_SADDR[15:0] 3 = write/read I2C_SADDR[23:0] Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.10.4 I2C Read Data The returned data from I2C reads is stored here. The number of bytes received depends on the I2C_DATA_LEN parameter, which can be 0 to 4. The counting and storing of received data starts at the least-significant byte (I2C_RDATA[7:0]). A write must be performed to the I2C{x}_CTRL register to initiate an I2C transaction. Register: I2C1_RDATA Address: 0x0018000C Register: I2C2_RDATA Address: 0x0019000C Register: I2C3_RDATA Address: 0x001A000C Bits [31:0] Type RO Default Name 0x0 Description I2C_RDATA I2C Read Data. Read data is stored in leastsignificant byte first. 3.10.5 I2C Status This address contains status information. Register: I2C1_STAT Address: 0x00180010 Register: I2C2_STAT Address: 0x00190010 Register: I2C3_STAT Address: 0x001A0010 Bits Type Default Name Description [1] RO 1'b0 I2C_XFER_IN_PROG Read or Write transaction is in progress. [0] RO 1'b0 I2C_RACK Received ack successfully. Indicates that slave acknowledged all transmitted bytes. Valid when transaction is no longer in progress. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 93 Registers 3.11 CX23885 Data Sheet Memory Mapped Registers: UART 3.11.1 UART TxD/RxD Control Register: UART_CTL Bits Type Address: 0x001B0000 Default Name Description [31:8] RO 24'b0 Reserved [7] RW 1'b0 [6:4] RO 3'b0 [3:2] RW 2'b0 RX_TRG_SZ RX trigger size (before RxD interrupt). 00 = 1 byte 01 = 4 byte 10 = 8 byte 11 = 12 byte [1] RW 1'b0 RX_EN Enable receiver, reset when disabled. [0] RW 1'b0 TX_EN Enable transmitter, reset when disabled. LOOP_BACK_EN Connects TxD and RxD internally for loopback testing. Reserved 3.11.2 UART Baud Rate Divisor Register: UART_BRD Bits Type Address: 0x001B0004 Default [31:16] RO 16'b0 [15:0] RW 16'h0197 Name Description Reserved BRD Divide 62.5 MHz clock by this value to generate 16X baud rate clock. Default value generates 9600 baud. Register: Reserved Bits [31:0] 94 Type RW Address: 0x001B0008 Default Name 32'b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.11.3 UART Interrupt Status Register Register: UART_ISR Bits Type Address: 0x001B000C Default Name Description [31:9] RO 23'b0 Reserved [8] RW 1'b0 RXD_TIMEOUT RxD timeout interrupt. Interrupt if RX idle for 4 character periods and data is in RX FIFO. [7] RW 1'b0 RXD_TIMEOUT_EN Enable RX timeout interrupt [6] RW 1'b0 FRM_ERR_EN Frame error interrupt enable. A logic 1 enables interrupts on detected frame error. [5] RW 1'b0 RXD_RDY_EN Receive buffer trigger level interrupt enable. A logic 1 enables an interrupt when the RX buffer is ready. [4] RW 1'b0 TXD_EMPTY_EN Transmit buffer empty interrupt enable. A logic 1 enables interrupts when the transmit buffer becomes empty. [3] RR 1'b0 RXD_OVERFLOW Receive data buffer overflow. This bit is set when a byte is received while the RxD buffer is full (RXD_CNT == 16). Cleared when written with a 1. [2] RR 1'b0 FRM_ERR Frame error pending. Set when a framing error occurs. Cleared when written with a 1. Received data should be ignored when this bit is set. [1] RR 1'b0 RXD_RDY Receive buffer ready. Set when the RX buffer has reached trigger level. Cleared when written with a 1. [0] RR 1'b0 TXD_EMPTY Transmitter empty pending. Set when the transmit buffer becomes empty. Cleared when written with a 1. 3.11.4 UART FIFO Status Register: UART_CNT Bits Type Address: 0x001B0010 Default [31:13] RO 19'b0 [12:8] RW 5'b0 [7:5] RO 3'b0 [4:0] RW 5'b0 DSH-201010p2 2/4/09 Name Description Reserved TXD_CNT # of bytes in TxD FIFO. Reserved RXD_CNT # of bytes in RxD FIFO. Conexant Preliminary Information/Conexant Proprietary and Confidential 95 Registers 3.12 CX23885 Data Sheet Rider Registers This module contains all of the registers required to configure and debug Rider. Two categories of registers are implemented: PCI Express Registers and Rider Registers. The PCI Express registers are described in the PCI Express Base Specification, and are used to configure and operate the PCI Express interface. These registers can only be written using PCI Express Configuration Write transactions. Rider is a term used to identify the PCI Express PIPE-compliant Endpoint Controller Core. The Rider Registers provide extra configuration, controllability, and observability of the Rider core. These registers can only be written by the Application Layer. Figure 5 shows the interfaces between the CFG block, the Device Core, and the Transaction Layer. Figure 5. CFG Block, Device Core, and Transaction Layer Interfaces Application Layer Device Core Rider Read 0001 Read and Write Internal Bus Transaction Layer (TL) PCI Express Registers Interface Interface 2FF1 Read and 3001 Write Data Link Layer (DLL) Read Rider Registers MAC Layer (MACL) 3FF1 CFG Block Configuration Transactions Memory Transactions 102740_003 96 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.1 Address Space The PCI Express Base Specification uses 4096 bytes for the PCI and PCI Express configuration space. However, the PCI Express features implemented in Rider require less than 512 bytes. Figure 6 shows the address space used by Rider for PCI Express registers and Rider registers. Figure 6. Address Space FFFh Not Used by Rider(1) (2) 400h 3FFh PCI Express Extended Configuration Space Rider Registers 300h 2FFh Extended Capability Structures 100h 0FFh PCI Configuration Space 040h 03Fh 000h Capability Structures PCI Compatible Header Footnote: (1) This space is available for other use. (2) PCI Express Configuration Transactions always read zeros from this space. 102740_004 3.12.2 Accessing PCI Express Registers PCI Express Registers can only be written by PCI Express configuration transactions because they are tightly controlled by the host operating system. If another entity was able to adjust the PCI Express Registers without the host operating system knowing about the change, the performance and stability of the PCI Express link or the entire fabric could be adversely affected. The Application Layer interface provides a convenient method for the driver or another entity to observe the values of the PCI Express registers. Since none of the PCI express registers are cleared upon being read, the application layer read activity will not interfere with the PCI Express configuration or operation. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 97 Registers CX23885 Data Sheet 3.12.3 Accessing Rider Registers The Rider registers are used to observe and adjust the behavior of Rider above and beyond what is available in the PCI Express registers defined in the PCI Express Base Specification. In order to ensure compliance with the PCI Express Specification, these registers' default values conform to the specification. The Application Layer interface is used to read and write Rider registers. While it is possible to read the values of the Rider registers using configuration read transactions, it is not anticipated that the device driver will use this method. 3.12.4 Register Access Exception - Vital Product Data (VPD) Vital Product Data (VPD) registers are writable from both the Application Layer and the Transaction Layer. Specifically, the flag bit in the VPD Capabilities Header and the VPD Data register need to be able to be written by both agents. The VPD protocol as described in the Conventional PCI Specification is relied upon to avoid conflicting writes to these fields. 3.12.5 Register Type Restrictions In general, PCI Express Registers cannot be written or cleared via the Application Layer regardless of the register type. Similarly, Rider Registers cannot be written or cleared via PCI Express Configuration Transactions. A small number of PCI Express RO Registers can be written by the Application Layer after reset for initialization. 3.12.6 Read-Only Registers The value of Read-Only registers can be set by hardwiring values, by the Application Layer initializing values after reset, or by assigning the value to a signal inside of Rider. 3.12.7 Read-Write Registers Read-Write registers are assigned default values listed. They are implemented as flipflops inside the CFG block and may be written by the Configuration Write Transactions if they are PCI Express Registers or via the Application Layer interface if they are Rider registers. 3.12.8 Read-Only; Write-1-to-Clear Registers Read-Only; Write-1-to-Clear registers are used as status registers. They are asserted when the corresponding signal inside of Rider is asserted, but are only cleared when a 1 is written to them. This type of register is implemented as a flip-flop inside of the CFG block. 3.12.9 Sticky Registers Sticky bits are preserved during hot reset, or cold/warm reset if auxiliary power is available. All registers are the outputs of flip-flops. Flip-flops associated with Sticky Read-Only registers are reset using the signal PE_VAUX_RST_N. All other registers are reset using PE_FUND_RST_N. 98 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.10 Initialization After reset, the register bit CFG_LOCK_INIT_REGS at address RDR_RDRCTL1 is cleared, which permits the Application Layer to write values to PCI Express Registers that are required for initialization. The Application Layer can use any method it chooses to obtain the initialization values. The initialization process can be divided into three phases: MAC, DLL, and TL. After the Application Layer initializes the registers required for the LTSSM, it sets the CFG_MAC_INIT_DONE bit of the RDR_RDRCTL1 register, which allows the LTSSM to proceed with link training. Next, after the Application Layer initializes the registers required for flow control initialization of VC0, it sets the CFG_DLL_INIT_DONE bit of the RDR_RDRCTL1 register, which allows the DLL to begin flow control initialization for VC0. Lastly, after the Application Layer initializes the registers required for PCI Express Configuration and Enumeration, it sets the CFG_TL_INIT_DONE bit of the RDR_RDRCTL1 register, which allows the TL to respond to configuration requests. This three phase process is provided so that link training and flow control initialization can commence prior to all register initialization being complete. If the Application Layer can accomplish all register initialization within the time-outs specified in the PCI Express Base Specification, all three CFG_*_INIT_DONE bits may be set at once. The application layer may set the CFG_LOCK_INIT_REGS bit to prevent changes to the initialization registers. 3.12.11 Interrupt Generation The CFG block generates two interrupts to the Application Layer. The interrupt LINERDR_REQ_CPL_INT indicates when a transfer request has been completed. It is tied directly to CFG_REQ_COMPLETE_INT (RDR_RDRSTAT0[0]). The interrupt line RDR_MISC_INT indicates when other events occur. It is the logical OR of the masked signals CFG_VPD_REQ_INT, CFG_REQ_INVALID_INT, CFG_PWR_STATE_INT, CFG_SLOT_PWR_INT, CFG_VEN_DEF_MSG_INT, and CFG_HOT_PLUG_MSG_INT (RDR_RDRSTAT0[13:8]). 3.12.12 PCI Express Registers - PCI Compatible Header The Type column in this section represents the type of register from the perspective of the Transaction Layer. Register fields in this section cannot be written by the Application Layer unless indicated by an asterisk (*) in the Type column, in which case they can be written by the Application Layer when CFG_LOCK_INIT_REGS is not set. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 99 Registers CX23885 Data Sheet 3.12.13 PCI Device and Vendor ID Register: RDR_CFG0 Bits Address: 0x50000 Type Default Name Description [31:16] RO 16'h 8852 CFG_DEVICE_ID Device ID based on BOND_OPTION input to Rider. Device ID values for each bond option are set during pre-synthesis configuration of Rider IP. [15:0] RO 16'h 14f1 CFG_VENDOR_ID Vendor ID. Set during pre-synthesis configuration of Rider IP. 3.12.14 PCI Status and Command Register: RDR_CFG1 Bits Type Address: 0x50004 Default Name Description [31:31] RR 1`b0 CFG_STAT_DET_P ERR Set if Poisoned TLP is received. [30:30] RR 1`b0 CFG_STAT_SIG_SE RR Set when fatal or non-fatal error message is sent and CFG_CMD_SERR_EN is set. [29:29] RR 1`b0 CFG_STAT_RCV_M A Set when completion is received (by Rider) with Unsupported Request status. [28:28] RR 1`b0 CFG_STAT_RCV_T A Set when completion is received (by Rider) with Completer Abort status. [27:27] RR 1`b0 CFG_STAT_SIG_TA Set when completion is sent (by Rider) with Completer Abort status. [26:25] RO 2'b0 [24:24] RR 1`b0 [23:20] RO 4'b1 [19:19] RO 1`b0 [18:11] RO 8`b0 [10:10] RW 1`b0 100 Reserved CFG_STAT_MD_PE RR Set when a poisoned completion is received or a write request being sent is poisoned. Can only be set when CFG_CMD_PERR_RESP_EN bit is set. Reserved TL_INTX_MSG_OUTST AND Indicates INTx message is outstanding. Reserved CFG_GEN_INTX_DI S Disables ability to generate INTx messages. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [9:9] RO 1`b0 Reserved [8:8] RW 1`b0 [7:7] RO 1`b0 [6:6] RW 1`b0 [5:3] RO 3`b0 [2:2] RW 1`b0 CFG_CMD_BUS_M STR_EN Enables ability to issue memory requests, including MSI messages. [1:1] RW 1`b0 CFG_CMD_MEM_E N Enables memory decoder and allows device to accept memory transactions. [0:0] RO 1`b0 CFG_CMD_SERR_ EN Enables detected fatal and non-fatal errors to be reported to Root Complex. Reserved CFG_CMD_PERR_ RSP_EN Enables ability to set the Master Data Parity Error bit (PE_STAT_MD_PERR). Reserved Reserved 3.12.15 PCI Class Code and Revision ID Register: RDR_CFG2 Bits Type Address: 0x50008 Default Name Description [31:24] RO 8'h04 CFG_CLASS_CODE Class Code. Set during pre-synthesis configuration of Rider IP. [23:16] RO 8`b0 CFG_SUBCLASS_C ODE Subclass Code. Set during pre-synthesis configuration of Rider IP. [15:8] RO 8`b0 CFG_PGM_INTF Programming Interface. Set during pre-synthesis configuration of Rider IP. [7:0] RO 8`b2 CFG_REV_ID Revision ID of the device. Set during presynthesis configuration of Rider IP. Register: Reserved Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x5000c Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 101 Registers CX23885 Data Sheet 3.12.16 PCI Base Address Register 0 Register: RDR_CFG4 Bits Type Address: 0x50010 Default [31:21] RW 11`b0 [20:0] RO 21`b0 Name CFG_BA0 Description Lower part of Base Address 0. Reserved 3.12.17 PCI Base Address Register 1 Register: RDR_CFG5 Bits [31:0] Type RW Address: 0x50014 Default 32`b0 Name CFG_BA1 Description If RDR_CFG4[2] is set, this field is the upper 32 bits of base address at RDR_CFG4. Otherwise, this register is read-only. Register: Reserved Bits [31:0] Type RO Address: 0x50018 Default Name 32`b0 Description Reserved Register: Reserved Bits [31:0] Type RO Address: 0x5001c Default Name 32`b0 Description Reserved Register: Reserved Bits [31:0] Type RO Address: 0x50020 Default Name 32`b0 Description Reserved Register: Reserved Bits [31:0] Type RO Address: 0x50024 Default Name 32`b0 Description Reserved Register: Reserved Bits [31:0] 102 Type RO Address: 0x50028 Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.18 PCI Subsystem and Subsystem Vendor ID Register: RDR_CFGB Bits Type Address: 0x5002c Default Name Description [31:16] RO 16`b0 CFG_SUBSYS_ID Subsystem ID; Initialized by the EEPROM. [15:0] RO 16`b0 CFG_SUBSYS_VEN _ID Subsystem Vendor ID; Initialized by the EEPROM. Register: Reserved Bits [31:0] Type RO Address: 0x50030 Default Name 32`b0 Description Reserved Register: Reserved Bits [31:0] Type RO Address: 0x50034 Default Name 32`h0040 Description Reserved Register: Reserved Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x50038 Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 103 Registers CX23885 Data Sheet 3.12.19 PCI Interrupts Register: RDR_CFGF Address: 0x5003c Bits Type Default Name Description [31:11] RO 21'b0 [10:8] RO 3'b1 CFG_INTX_PIN Interrupt Pin. Indicates which legacy-style INTx message is used for interrupt. Initialized by the Application Layer. 3'b001 = INTA, 3'b010 = INTB, ... 3'b100 = INTD. [7:0] RW 8`b0 CFG_INTX_LINE Interrupt Line. Contains routing information for legacy INTx# style interrupts. Reserved 3.12.20 PCI Express Registers: Capabilities The Type column in this section represents the type of register from the perspective of the transaction layer. Register fields in this section cannot be written by the application layer unless indicated by an asterisk (*) in the Type column, in which case they can be written by the Application Layer when CFG_LOCK_INIT_REGS is not set. Register: Reserved Bits [31:0] 104 Type RO Address: 0x50040 Default Name 32'b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.21 PCI Express Device Capabilities Register: RDR_PEDEVCAP Bits Type Default Address: 0x50044 Name Description [31:28] RO 4`b0 [27:26] RO 2`b0 TL_SLOT_PWR_LIM_S CALE Captured Slot Power Limit Scale. [25:18] RO 8`b0 TL_SLOT_PWR_LIM_V AL Captured Slot Power Limit Value. [17:15] RO 3`b0 [14:14] RO 1`b0 CFG_PWR_IND_PR ES Power indicator present on card. Initialized by the Application Layer. [13:13] RO 1`b0 CFG_ATTN_IND_PR ES Attention indicator present on card. Initialized by the Application Layer. [12:12] RO 1`b0 CFG_ATTN_BUTTO N_PRES Attention button present on card. Initialized by the Application Layer. [11:9] RO 3`b0 CFG_L1ASPM_ACC EPT_LAT L1 Acceptable Latency; Initialized by the Application Layer [8:6] RO 3`b0 CFG_L0S_ACCEPT_ LAT L0s Acceptable Latency. Initialized by the Application Layer. [5:3] RO 3`b0 [2:0] RO 3`b0 DSH-201010p2 2/4/09 Reserved Reserved Reserved CFG_MAX_PAYLD_S UP Max Payload Size Supported; Set during configuration of Rider IP. Conexant Preliminary Information/Conexant Proprietary and Confidential 105 Registers CX23885 Data Sheet 3.12.22 PCI Express Device Status and Control Register: RDR_PEDEVSC Address: 0x50048 Bits Type [31:22] RO 10`b0 [21:21] RO 1`b0 TL_TRANS_PENDIN G 1 = there are pending non-posted requests. [20:20] RO 1`b0 CFG_AUX_PWR_DE T 1 = auxiliary power has been detected; Initialized by the Application Layer. [19:19] RO 1`b0 CFG_UR_RCVD 1 = Unsupported Request (UR) received. [18:18] RO 1`b0 CFG_FATAL_ERR_D ET 1 = one or more fatal errors detected. [17:17] RO 1`b0 CFG_NONFATAL_ERR _DET [16:16] RO 1`b0 CFG_CORR_ERR_D ET [15:15] RO 1`b0 [14:12] RW 3'h2 CFG_MAX_RD_REQ _SZ Maximum Read Request Size (default is 512 bytes). [11:11] RW 1'b1 CFG_NO_SNOOP_E N Enable No Snoop. [10:10] RW 1`b0 CFG_AUX_PWR_EN Auxiliary Power Enable. (Sticky) [9:8] RO 2`b0 [7:5] RW 3`b0 CFG_MAX_PAYLD_S Z Maximum Payload Size (default is 128 bytes). [4:4] RW 1'b1 CFG_RELAX_ORDE R_EN Relaxed Ordering Enable. [3:3] RW 1`b0 CFG_UR_RPT_EN Unsupported Request Reporting Enable. [2:2] RW 1`b0 CFG_FAT_ERR_RPT _EN Fatal Error Reporting Enable. [1:1] RW 1`b0 CFG_NONFAT_ERR_RP T_EN [0:0] RW 1`b0 CFG_CORR_ERR_RP T_EN 106 Default Name Description Reserved 1 = one or more non-fatal errors detected. 1 = one or more correctable errors detected. Reserved Reserved Non-fatal Error Reporting Enable. Correctable Error Reporting Enable. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.23 PCI Express Link Capabilities Register: RDR_PELINKCAP Bits Type Default Address: 0x5004c Name CFG_PORT_NUM Description [31:24] RO 8`b0 Port Number of the Link; Initialized by the Application Layer. [23:18] RO 6`b0 [17:15] RO 3`h2 CFG_L1ASPM_EXIT_L AT Corresponds to L1 Exit Latency; Varies with CFG_COMMON_CLOCK. If CFG_COMMON_CLOCK is 1'b1, this value is l1aspm_exit_lat_crc (from RDR_L1_EXIT_LAT register). If CFG_COMMON_CLOCK is 1'b0, this value is l1aspm_exit_lat_arc (from RDR_L1_EXIT_LAT register). [14:12] RO 3'h5 CFG_L0S_EXIT_LAT L0s Exit Latency; Varies with CFG_COMMON_CLOCK. If CFG_COMMON_CLOCK is 1'b1, this value is l0s_exit_lat_crc (from RDR_L0S_EXIT_LAT register). If CFG_COMMON_CLOCK is 1'b0, this value is l0s_exit_lat_arc (from RDR_L0S_EXIT_LAT register). [11:0] RO 12'hC11 Reserved Reserved 3.12.24 PCI Express Link Status and Control Register: RDR_PELINKSC Address: 0x50050 Bits Type [31:29] RO 3`b0 [28:28] RO 1`b0 [27:8] RO 20'h01100 [7:7] RW 1`b0 CFG_EXTENDED_S YNC 1 = forces extended synchronization when exiting L1 and L0s. [6:6] RW 1`b0 CFG_COMMON_CL OCK 1 = both ends of link are using a common reference clock. [5:4] RW 2`b0 [3:3] RW 1`b0 [2:2] RO 1`b0 [1:0] RW 2`b0 DSH-201010p2 2/4/09 Default Name Description Reserved CFG_SLOT_CLOCK _CFG 1 = using clock from connector; 0 = using independent clock; Initialized by the Application Layer. Reserved Reserved CFG_RCB Read Completion Boundary; 1 = 128b; 0 = 64b. Reserved CFG_ASPM_CTRL ASPM Control: 00 = disabled; 01 = L0s enabled; 10= L1 ASPM enabled; 11 = L0s & L1 ASPM enabled; Initialized by the Application Layer. Conexant Preliminary Information/Conexant Proprietary and Confidential 107 Registers CX23885 Data Sheet 3.12.25 Power Management Interface Capabilities Register: RDR_PMICAP Address: 0x50080 Bits Type Default Name Description [31:27] RO 5'hF CFG_PME_SUPPOR TED D-states in which PME Message is Supported. [26:26] RO 1'b1 CFG_D2_SUPPORT ED Indicates if D2 state is supported. [25:25] RO 1'b1 CFG_D1_SUPPORT ED Indicates if D1 state is supported. [24:22] RO 3'h7 CFG_AUX_CURREN T 3.3 V AUX current required in D3cold state; Initialized by the Application Layer. [21:0] RO 22'h229001 Reserved 3.12.26 Power Management Control/Status Register: RDR_PMCSR Bits Type Default [31:16] RO 16`b0 [15:15] RO 1`b0 [14:9] RO 6`b0 [8:8] RW 1`b0 [7:2] RO 6`b0 [1:0] RW 2`b0 108 Address: 0x50084 Name Description Reserved CFG_PME_STAT Indicates when device experienced a PME. (Sticky) Reserved CFG_PME_EN Enables device to send PME messages. Reserved RDR_PWR_STATE Controls power state of the device. 2'b00 = D0 2'b01 = D1 2'b10 = D2 2'b11 = D3hot Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.27 Vital Product Data Capabilities Register: RDR_VPDCAP Address: 0x50090 Bits Type Default Name Description [31:31] RW 1`b0 VPD_FLAG VPD Flag Bit. Writable by both Application and Transaction Layers. Indicates direction of transfer and when transfer is complete. Write: 1'b1 is written to CFG_VPD_FLAG when CFG_VPD_ADDR is written. AL clears CFG_VPD_FLAG when write is complete. Read: 1'b0 is written to CFG_VPD_FLAG when CFG_VPD_ADDR is written. AL sets CFG_VPD_FLAG when read is complete (i.e., data is available in CFG_VPD_DATA). [30:16] RW 15`b0 VPD_ADDR VPD Address. Writable only by Transaction Layer. [15:0] RO 16'h A003 Reserved 3.12.28 VPD Data Register: RDR_VPDDATA Bits Type [31:31] RW Address: 0x50094 Default 32`b0 Name VPD_DATA Description Vital Product Data. Writable by both Application and Transaction Layers. 3.12.29 Message Signaled Interrupt Capabilities This register is present only if the MSI capability is enabled via the INCLUDE_MSI_REGS REGISTER at address RDR_RDRCTL1. Register: RDR_MSICAP Bits Type Address: 0x500a0 Default Name Description [31:23] RO 9`b1 [22:20] RW 3`b0 CFG_NUM_MSGS_A LLOC Number of messages allocated to the device. [19:17] RO 3`b0 CFG_NUM_MSGS_R EQ Number of messages requested by the device. Set during RTL configuration of Rider IP. [16:16] RW 1`b0 CFG_MSI_EN Enables Message Signaled Interrupts. [15:0] RO 16'h 05 DSH-201010p2 2/4/09 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 109 Registers CX23885 Data Sheet 3.12.30 MSI Address Lower 32 Bits This register is present only if the MSI capability is enabled via the INCLUDE_MSI_REGS register at address RDR_RDRCTL1. Register: RDR_MSIARL Bits Type Address: 0x500a4 Default Name Description [31:2] RW 30`b0 CFG_MSI_ARL Lower 32 bits of 64-bit MSI Address. [1:0] RO 2`b0 CFG_MSI_ARL MSI Address is Dword aligned; always 2'b00. 3.12.31 MSI Address Upper 32 Bits This register is present only if the MSI capability is enabled via the INCLUDE_MSI_REGS register at address RDR_RDRCTL1. Register: RDR_MSIARU Bits [31:0] Type RW Address: 0x500a8 Default 32`b0 Name CFG_MSI_ARU Description Upper 32 bits of 64-bit MSI Address. 3.12.32 MSI Data Pattern This register is present only if the MSI capability is enabled via the INCLUDE_MSI_REGS REGISTER at address RDR_RDRCTL1. Register: RDR_MSIDATA Bits Type Default [31:16] RO 16'b0 [15:0] RW 16`b0 110 Address: 0x500ac Name Description Reserved CFG_MSI_BASE_DA TA Base MSI Data Pattern. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.33 PCI Express Registers: Extended Capabilities The Type column in this section represents the type of register from the perspective of the Transaction Layer. Register fields in this section cannot be written by the Application Layer unless indicated by an asterisk (*) in the Type column, in which case they can be written by the Application Layer when CFG_LOCK_INIT_REGS is not set. Register: Reserved Bits [31:0] Address: 0x50100 Type RO Default Name 32'h20010001 Description Reserved 3.12.34 AER Uncorrectable Error Status Register: RDR_AERUESTA Bits Type [31:21] RO 11'b0 [20:20] RO 1`b0 [19:19] RO 1'b0 [18:18] RO 1`b0 CFG_MALF_TLP_ST AT Malformed TLP Status; set by Transaction Layer. (Sticky) [17:17] RO 1`b0 CFG_RCVR_OVFLW_ STAT Receiver Overflow Status; set by Transaction Layer. (Sticky) [16:16] RO 1`b0 CFG_UNEXP_COMP_S TAT Unexpected Completion Status; set by Transaction Layer. (Sticky) [15:15] RO 1`b0 CFG_COMP_ABORT_S TAT Completer Abort Status; set by Transaction Layer. (Sticky) [14:14] RO 1`b0 CFG_COMP_TO_ST AT [13:13] RO 1`b0 CFG_FC_PROT_ERR_ STAT Flow Control Protocol Error Status; set by Transaction Layer. (Sticky) [12:12] RO 1`b0 CFG_POISONED_TLP_ STAT Poisoned TLP Status; set by Transaction Layer. (Sticky) [11:5] RO 7'b0 [4:4] RO 1`b0 [3:0] RO 4'b0 DSH-201010p2 2/4/09 Default Address: 0x50104 Name Description Reserved CFG_UR_ERR_STAT Unsupported Request Error Status; set by Transaction Layer. (Sticky) Reserved Completion Timeout Status; set by Transaction Layer. (Sticky) Reserved CFG_PROT_ERR_S TAT Data Link Protocol Error Status; set by Data Link Layer. (Sticky) Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 111 Registers CX23885 Data Sheet 3.12.35 AER Uncorrectable Error Mask Register: RDR_AERUEMSK Bits Type Default Address: 0x50108 Name Description [31:21] RO 11'b0 [20:20] RW 1`b0 [19:19] RO 1'b0 [18:18] RW 1`b0 CFG_MALF_TLP_MA SK [17:17] RW 1`b0 CFG_RCVR_OVFLW_M ASK Receiver Overflow Mask. (Sticky) [16:16] RW 1`b0 CFG_UNEXP_COMP_M ASK Unexpected Completion Mask (Sticky) [15:15] RW 1`b0 CFG_COMP_ABORT_M ASK Completer Abort Mask. (Sticky) [14:14] RW 1`b0 CFG_COMP_TO_MA SK [13:13] RW 1`b0 CFG_FC_PROT_ERR_ MASK Flow Control Protocol Error Mask. (Sticky) [12:12] RW 1`b0 CFG_POISONED_TLP_ MASK Poisoned TLP Mask. (Sticky) [11:5] RO 7'b0 [4:4] RW 1`b0 [3:0] RO 1`b0 112 Reserved CFG_UR_ERR_MAS K Unsupported Request Error Reserved Malformed TLP Mask.(Sticky) Completion Timeout Mask. Reserved CFG_PROT_ERR_M ASK Data Link Protocol Error Mask. (Sticky) Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.36 AER Uncorrectable Error Severity Register: RDR_AERUESEV Bits Type Default Address: 0x5010c Name Description [31:21] RO 11`b0 [20:20] RW 1`b0 [19:19] RO 1`b0 [18:18] RW 1'b1 CFG_MALF_TLP_SE V [17:17] RW 1'b1 CFG_RCVR_OVFLW_S EV Receiver Overflow Severity. (Sticky) [16:16] RW 1`b0 CFG_COMP_ABORT_S EV Unexpected Completion Severity. (Sticky) [15:15] RW 1`b0 CFG_COMP_TO_SEV Completer Abort Severity. (Sticky) [14:14] RW 1`b0 CFG_FC_PROT_ERR_ SEV Completion Timeout Severity. (Sticky) [13:13] RW 1'b1 CFG_POISONED_TLP_ SEV Flow Control Protocol Error Severity. (Sticky) [12:12] RW 1`b0 CFG_PROT_ERR_S EV [11:5] RO 1`b0 [4:4] RW 1'b1 [3:0] RO 4`b0 DSH-201010p2 2/4/09 Reserved CFG_UR_ERR_SEV Unsupported Request Error Severity. (Sticky) Reserved Malformed TLP Severity. (Sticky) Poisoned TLP Severity. (Sticky) Reserved CFG_COMP_ABORT_ SEV Data Link Protocol Error Severity. (Sticky) Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 113 Registers CX23885 Data Sheet 3.12.37 AER Correctable Error Status Register: RDR_AERCESTA Bits Type Default Address: 0x50110 Name Description [31:13] RO 19`b0 Reserved [12:12] RO 1`b0 [11:9] RO 3`b0 [8:8] RO 1`b0 CFG_REPLAY_NUM_RO_ STAT [7:7] RO 1`b0 CFG_BAD_DLLP_STA T Bad DLLP Status; set by Data Link Layer. (Sticky) [6:6] RO 1`b0 CFG_BAD_TLP_STAT Bad TLP Status; set by Transaction Layer. (Sticky) [5:1] RO 5`b0 [0:0] RO 1`b0 CFG_REPLAY_TMR_TO_ STAT Replay Timer Timeout Status; set by Data Link Layer. (Sticky) Reserved Replay Counter (aka, REPLAY_NUM) Rollover Status; set by Data Link Layer. (Sticky) Reserved CFG_RCVR_ERR_ST AT Receiver Error Status; set by MAC Layer. (Sticky) 3.12.38 AER Correctable Error Mask Register: RDR_AERCEMSK Bits Type [31:13] RO 19`b0 [12:12] RW 1`b0 [11:9] RO 3`b0 [8:8] RW 1`b0 CFG_REPLAY_NUM_RO_M ASK [7:7] RW 1`b0 CFG_BAD_DLLP_MASK Bad DLLP Mask. (Sticky) [6:6] RW 1`b0 CFG_BAD_TLP_MASK Bad TLP Mask. (Sticky) [5:1] RO 5`b0 [0:0] RW 1`b0 114 Default Address: 0x50114 Name Description Reserved CFG_REPLAY_TMR_TO_M ASK Replay Timer Timeout Mask. (Sticky) Reserved Replay Counter (aka, REPLAY_NUM) Rollover Mask. (Sticky) Reserved CFG_RCVR_ERR_MAS K Receiver Error Mask. (Sticky) Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.39 AER Capability and Control Register: RDR_AERCC Bits Type Address: 0x50118 Default [31:5] RO 27`b0 [4:0] RO 5`b0 Name Description Reserved TL_FIRST_ERR_PT R Bit number of the first error reported in the Uncorrectable Error Status Register (RDR_AERUESTA). (Sticky) 3.12.40 AER Header Log 0 Register: RDR_AERHL Bits [31:0] Type RO Address: 0x5011c Default 32`b0 Name TL_HDR_LOG_0 Description First DW of the header of the packet causing the reported uncorrectable error. (Sticky) 3.12.41 AER Header Log 1 Register: RDR_AERHL1 Bits [31:0] Type RO Address: 0x50120 Default 32`b0 Name TL_HDR_LOG_1 Description Second DW of the header of the packet causing the reported uncorrectable error. (Sticky) 3.12.42 AER Header Log 2 Register: RDR_AERHL2 Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x50124 Default 32`b0 Name TL_HDR_LOG_2 Description Third DW of the header of the packet causing the reported uncorrectable error. (Sticky) Conexant Preliminary Information/Conexant Proprietary and Confidential 115 Registers CX23885 Data Sheet 3.12.43 AER Header Log 3 Register: RDR_AERHL3 Bits [31:0] Type RO Address: 0x50128 Default 32`b0 Name TL_HDR_LOG_3 Description Fourth DW of the header of the packet causing the reported uncorrectable error. (Sticky) Register: Reserved Bits [31:0] Address: 0x50200 Type RO Default Name 32`h10002 Description Reserved 3.12.44 Port VC Capability Register 1 Register: RDR_VCCAP1 Bits Type Address: 0x50204 Default [31:7] RO 25`b0 [6:4] RO 3'b1 [3:3] RO 1`b0 [2:0] RO 3'b1 Name Description Reserved CFG_NUM_VCS_LP G Number of VCs that comprise the Low-Priority VC Group. Reserved CFG_NUM_ADD_VC S Number of Additional VCs (beyond VC0) that are supported. Register: Reserved Bits [31:0] 116 Type RO Address: 0x50208 Default Name 32'h 4000006 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.45 Port VC Status and Control Register: RDR_VCSC Address: 0x5020c Bits Type Default Name Description [31:17] RO 15`b0 [16:16] RO 1`b0 [15:4] RO 12`b0 [3:1] RW 3'h 2 CFG_LPVCG_ARB_SCH _SEL Selected arbitration scheme for Low-Priority VC Group. [0:0] RW 1`b0 CFG_LD_VC_ARB_TABL E Writing 1 causes VC arbitration table to be read and applied; Always reads 0. Reserved CFG_VC_ARB_TABLE_ STAT 1 = New values have been written by Software into RDR_VCARB[0-7] but have not been applied. 0 = VC Arbitration Table has been read from RDR_VCARB[0-7] and applied. Reserved Register: Reserved Bits [31:17] Address: 0x50210 Type RO Default Name 32`b0 Description Reserved 3.12.46 VC Resource 0 Capability Register: RDR_VCR0_CTRL Bits Type Default Address: 0x50214 Name Description [31:8] RO 24'h800000 [7:1] RW 7'h7F CFG_VC0_TCVC_M AP Traffic Classes mapped to VC0 [0:0] RO 1'b1 CFG_VC0_TCVC_M AP Traffic Class 0 always mapped to VC0. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 117 Registers CX23885 Data Sheet 3.12.47 VC Resource 0 Control Register: RDR_VCR0_STAT Bits Type Default [31:18] RO 14`b0 [17:17] RO 1'b1 [16:0] RO 16`b0 Address: 0x50218 Name Description Reserved DLL_VC0_NEGOT_PEN DING For VC0: Indicates status of Flow Control Initialization. Reserved Register: Reserved Bits [31:0] Address: 0x5021c Type RO Default Name 32`b0 Description Reserved 3.12.48 VC Resource 1 Control Register: RDR_VCR1_CTRL Bits Type [31:31] RW 1`b0 [30:27] RO 4`b0 [26:24] RW 3'b1 [23:8] RO 16`b0 [7:1] RW 7`b0 CFG_VC1_TCVC_M AP Traffic Classes mapped to VC1. [31:31] RW 1`b0 CFG_VC1_EN VC1 Enable [0:0] RO 1`b0 CFG_VC1_TCVC_M AP Bit zero of TC/VC map is hardwired to zero for VCs other than VC0. TC0 is never mapped to anything other than VC0. 118 Default Address: 0x50220 Name CFG_VC1_EN Description VC1 Enable Reserved CFG_VC1_ID VC1 ID. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.49 VC Resource 1 Status Register: RDR_VCR1_STAT Bits Type Default [31:18] RO 14`b0 [17:17] RO 1`b0 [16:0] RO 17`b0 Address: 0x50224 Name Description Reserved DLL_VC1_NEGOT_P ENDING Indicates status of VC negotiation. Reserved Register: Reserved Bits [31:0] Type RO Address: 0x50228 Default Name 32`b0 Description Reserved 3.12.50 VC Resource 2 Control Register: RDR_VCR2_CTRL Bits Type [31:31] RW 1`b0 [30:27] RO 4`b0 [26:24] RW 3'h 2 [23:8] RO 16`b0 [7:1] RW 7`b0 CFG_VC2_TCVC_M AP Traffic Classes mapped to VC2. [0:0] RO 1`b0 CFG_VC2_TCVC_M AP Bit zero of TC/VC map is hardwired to zero for VCs other than VC0. TC0 is never mapped to anything other than VC0. DSH-201010p2 2/4/09 Default Address: 0x5022c Name CFG_VC2_EN Description VC2 Enable. Reserved CFG_VC2_ID VC2 ID. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 119 Registers CX23885 Data Sheet 3.12.51 VC Resource 2 Status Register: RDR_VCR2_STAT Bits Type Default [31:18] RO 14`b0 [17:17] RO 1`b0 [16:0] RO 17`b0 Address: 0x50230 Name Description Reserved DLL_VC2_NEGOT_PEN DING Indicates status of VC negotiation. Reserved Register: Reserved Bits [31:0] Type RO Address: 0x50234 Default Name 32`b0 Description Reserved 3.12.52 VC Resource 3 Control Register: RDR_VCR3_CTRL Bits Type [31:31] RW 1`b0 [30:27] RO 4`b0 [26:24] RW 3'h3 [23:8] RO 16`b0 [7:1] RW 7`b0 CFG_VC3_TCVC_M AP Traffic Classes mapped to VC3. [0:0] RO 1`b0 CFG_VC3_TCVC_M AP Bit zero of TC/VC map is hardwired to zero for VCs other than VC0. TC0 is never mapped to anything other than VC0. 120 Default Address: 0x50238 Name CFG_VC3_EN Description VC3 Enable. Reserved CFG_VC3_ID VC3 ID. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.12.53 VC Resource 3 Status Register: RDR_VCR3_STAT Bits Type Default [31:18] RO 14`b0 [17:17] RO 1`b0 [16:0] RO 17`b0 Address: 0x5023c Name Description Reserved DLL_VC3_NEGOT_P ENDING Indicates status of VC negotiation. Reserved 3.12.54 VC Arbitration Table Entries 0-7 Register: RDR_VCARB0 Bits [31:0] Type RW Address: 0x50240 Default 32`b0 Name CFG_VCARB_TBL0 Description Entries 0-7 in the VC Arbitration Table. 3.12.55 VC Arbitration Table Entries 8-15 Register: RDR_VCARB1 Bits [31:0] Type RW Address: 0x50244 Default 32`b0 Name CFG_VCARB_TBL1 Description Entries 8-15 in the VC Arbitration Table. 3.12.56 VC Arbitration Table Entries 16-23 Register: RDR_VCARB2 Bits [31:0] Type RW DSH-201010p2 2/4/09 Address: 0x50248 Default 32`b0 Name CFG_VCARB_TBL2 Description Entries 16-23 in the VC Arbitration Table. Conexant Preliminary Information/Conexant Proprietary and Confidential 121 Registers CX23885 Data Sheet 3.12.57 VC Arbitration Table Entries 24-31 Register: RDR_VCARB3 Bits [31:0] Type RW Address: 0x5024c Default 32`b0 Name CFG_VCARB_TBL3 Description Entries 24-31 in the VC Arbitration Table. 3.12.58 VC Arbitration Table Entries 32-39 Register: RDR_VCARB4 Bits [31:0] Type RW Address: 0x50250 Default 32`b0 Name CFG_VCARB_TBL4 Description Entries 32-39 in the VC Arbitration Table. 3.12.59 VC Arbitration Table Entries 40-47 Register: RDR_VCARB5 Bits [31:0] Type RW Address: 0x50254 Default 32`b0 Name CFG_VCARB_TBL5 Description Entries 40-47 in the VC Arbitration Table. 3.12.60 VC Arbitration Table Entries 48-55 Register: RDR_VCARB6 Bits [31:0] Type RW Address: 0x50258 Default 32`b0 Name CFG_VCARB_TBL6 Description Entries 48-55 in the VC Arbitration Table. 3.12.61 VC Arbitration Table Entries 56-63 Register: RDR_VCARB7 Bits [31:0] 122 Type RW Address: 0x5025c Default 32`b0 Name CFG_VCARB_TBL7 Description Entries 56-63 in the VC Arbitration Table. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.13 Registers Rider Registers - Global The Type column in this section represents the type of register from the perspective of the Application Layer. None of the registers in this section can be written by the Transaction Layer (i.e., via a Configuration Request). RO Register fields in this section cannot be written by the Application Layer unless indicated by an asterisk (*) in the Type column, in which case they can be written by the Application Layer when CFG_LOCK_INIT_REGS is not set. 3.13.1 Rider Status 0 Register: RDR_RDRSTAT0 Bits Type Default Address: 0x50300 Name Description [31:24] RO 8`b0 [23:22] RO 2`b0 TL_PWR_IND_STATU S Reserved Power Indicator Status: 00 = Off 01 = On 10 = Reserved 11 = Blink [21:20] RO 2`b0 TL_ATTN_IND_STATU S Attention Indicator Status: 00 = Off 01 = On 10 = Reserved 11 = Blink [19:14] RO 6`b0 [13:13] RO 1`b0 CFG_VPD_REQ_INT Vital Product Data Request Interrupt Status. [12:12] RO 1`b0 CFG_REQ_INVALID_INT Current Request Invalid Interrupt Status. [11:11] RO 1`b0 CFG_PWR_STATE_INT Power State Interrupt Status (indicates when CFG_PWR_STATE bit was written). [10:10] RO 1`b0 CFG_SLOT_PWR_INT Slot Power Limit Updated Interrupt Status. [9:9] RO 1`b0 CFG_VEN_DEF_MSG_I NT Vendor Defined Message Received Status. [8:8] RO 1`b0 CFG_HOT_PLUG_MSG_ INT Hot-Plug Message Received Status. [7:1] RO 7`b0 [0:0] RO 1`b0 Reserved Reserved CFG_REQ_COMPLETE_ INT Request Complete Interrupt Status. Register: Reserved Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x50304 Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 123 Registers CX23885 Data Sheet 3.13.2 Rider Control 0 Register: RDR_RDRCTL0 Address: 0x50308 Bits Type [31:14] RO 18`b0 [13:13] RW 1`b0 VPD_REQ_MSK Vital Product Data Request Interrupt Mask; Active High (1'b1 masks interrupt) [12:12] RW 1`b0 REQ_INVALID_MSK Current Request Invalid Interrupt Mask; Active High [11:11] RW 1`b0 PWR_STATE_MSK Power State Interrupt Mask; Active High [10:10] RW 1`b0 SLOT_PWR_MSK Slot Power Limit Updated Interrupt Mask; Active High. [9:9] RW 1`b0 VEN_DEF_MSG_MS K Vendor Defined Message Received Interrupt Mask; Active High. [8:8] RW 1`b0 HOT_PLUG_MSG_M SK Hot-Plug Message Received Interrupt Mask; Active High. [7:1] RO 7`b0 [0:0] RW 1`b0 124 Default Name Description Reserved Reserved REQ_COMPLETE_M SK Request Complete Mask; Active High. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.13.3 Rider Control 1 Register: RDR_RDRCTL1 Bits Type Address: 0x5030c Default Name Description [31:10] RO 22`b0 [9:9] RW 1`b0 EN_AUX_PWR_REG Enables the CFG_AUX_PWR_EN field in RDR_PEDEVSC: 1'b0: CFG_AUX_PWR_EN is RO 1'b1: CFG_AUX_PWR_EN is RWS. Note this register is Sticky. [8:8] RW 1`b0 INCLUDE_MSI_REG S Includes the MSI Capabilities registers (RDR_MSICAP, RDR_MSIARL, RDR_MSIARU, RDR_MSIDATA): 1'b0: MSI Registers are not included. 1'b1: MSI Registers are included (legacy INTx messages should not be used). (Sticky) [7:4] RO 4`b0 [3:3] RW 1`b0 CFG_TL_INIT_DONE Indicates when register initialization for PCI Express Configuration/Enumeration is complete. When clear, this bit causes the TL to respond to configuration requests with Configuration Request Retry. This bit must be 1'b1 no later than 1 second after any reset. [2:2] RW 1`b0 CFG_DLL_INIT_DON E Indicates when register initialization for Flow Control Initialization is complete. When clear, this bit causes the DLL CMSM to wait in the DL_INACTIVE state until it is set. This bit must be 1'b1 no later than 1 second after any reset. [1:1] RW 1`b0 CFG_MAC_INIT_DO NE Indicates when register initialization for the LTSSM is complete. When clear, this bit will cause the LTSSM to wait in the Configuration.LinkWidth.Start sub-state until it is set, or the 24 ms timeout occurs to send the LTSSM back to Detect. This bit must be 1'b1 no later than 1 second after any reset.This register is not reset when the link goes down (i.e., when RDR_LINK_DN_RST_N is asserted). [0:0] RW 1`b0 CFG_LOCK_INIT_RE GS Indicates whether registers available for initialization are locked (1'b1) or unlocked (1'b0). DSH-201010p2 2/4/09 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 125 Registers 3.14 CX23885 Data Sheet Rider Registers: Transaction Layer 3.14.1 Transaction Layer Status 0 Register: RDR_TLSTAT0 Address: 0x50310 Bits Type Default Name Description [31:29] RO 3`b0 [28:24] RO 5`b0 TL_DEV_NUM Device Number captured when CfgWr0 packet is received. [23:16] RO 8`b0 TL_BUS_NUM Bus Number captured when CfgWr0 packet is received. [15:8] RO 8'h FF CFG_TC_ENABLED Indicates which Traffic Classes are enabled. [7] = TC7, [6] = TC6, ... [0] = TC0. [7:1] RO 7`b0 [0:0] RO 1`b0 Reserved Reserved TL_BUSY Transaction Layer is busy servicing a request from the Application Layer or Tx Queue is full and cannot accept any more requests until it becomes free. When this bit is set, the Application Layer must not write to registers RDR_RCADDRL, RDR_RCADDRU, RDR_EPADDR, and RDR_ALREQC until this bit is cleared. Register: Reserved Bits [31:0] 126 Type RO Address: 0x50314 Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.14.2 TL Control Register: RDR_TLCTL0 Address: 0x50318 Bits Type [31:26] RO 6`b0 [25:25] RW 1'b1 CFG_VDM1_EN CFG_VDM1_EN: Enable the ability to forward VDM Type 1 Messages to the Application Layer. Default value is enabled (1'b1). [24:24] RW 1`b0 CFG_REQSTAT_PO P_MODE Select popping mode for RDR_REQSTAT register: 1'b0 = next request status available after writing any value to RDR_REQSTAT 1'b1 = next request status available after reading RDR_REQSTAT [23:16] RW 8'h9 CFG_VC0_TIMER Expiration value used for timer to transfer packets from VC0 when Hardware Fixed arbitration scheme is used. Units are s. [15:10] RW 6'h30 CFG_CPL_TIMEOUT Duration to wait for completion before generating Completion Timeout error. Units are chosen by CFG_CPL_TIMER_RES as either 1 ms (default) or 100 s. Accuracy of reporting the Completion Timeout error is +0 / -1 resolution time unit. [9:9] RW 1`b0 CFG_CPL_TIMER_R ES Completion Timeout Timer Resolution: 1'b0 = 1 ms 1'b1 = 100 s. [8:8] RO 1`b0 [7:7] RW 1`b0 CFG_UR_CPL_MOD E Select mode for data in completions with status of Unsupported Request in response to Configuration Read Requests. 1'b0 = completions with UR status do not contain payload data 1'b1 = completions with UR status have payload data of all ones. [6:6] RW 1`b0 CFG_UNCORR_ERR_ QUIET When set, an error message is sent only when the Uncorrectable Error Status bit in RDR_AERUESTA is not set and future detection of uncorrectable errors will not result in an error message until the status bit is cleared. When this bit is cleared, an error message is sent whenever an uncorrectable error is detected by TL. DSH-201010p2 2/4/09 Default Name Description Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 127 Registers CX23885 Data Sheet [5:5] RW 1`b0 CFG_CORR_ERR_Q UIET When set, an error message is sent only when the Correctable Error Status bit in RDR_AERUESTA is not set and future detection of correctable errors will not result in an error message until the status bit is cleared. When this bit is cleared, an error message is sent whenever a correctable error is detected by TL. [4:4] RW 1`b1 CFG_RCB_CK_EN Enable checking for Read Completion Boundary violations and generate a Malformed Packet error if necessary. [3:3] RW 1'b1 CFG_BNDRY_CK_E N Enable checking for 4kB boundary violations and generate a Malformed Packet Error if necessary. [2:2] RW 1'b1 CFG_BYTE_EN_CK_ EN Enable checking for incorrect Byte Enables and generate Malformed Packet Error if necessary. [1:1] RW 1`b0 CFG_RELAX_ORDER_ MSK Mask the Relaxed Ordering bit when it's set by the AL. [0:0] RW 1'b1 CFG_TAG_ORDER_ EN Enable the Row D, Col 5 of the Ordering table. 1'b0=disabled, 1'b1=enabled. 3.14.3 Transmit Queue Control Register: RDR_TLCTL1 Address: 0x5031c Bits Type [31:25] RO 7`b0 [24:24] RW 1`b0 CFG_VC_LIMIT_EN Enable limits on number of requests by Virtual Channel using CFG_TX_VC3_SIZE, CFG_TX_VC2_SIZE, CFG_TX_VC1_SIZE, CFG_TX_VC0_SIZE. By default, the entire queue is shared by all VCs in "first come first serve" manner. [23:18] RW 6'h20 CFG_TX_VC3_SIZE Number of requests that can be stored in VC3 Tx Queue. [17:12] RW 6'h20 CFG_TX_VC2_SIZE Number of requests that can be stored in VC2 Tx Queue. [11:6] RW 6'h20 CFG_TX_VC1_SIZE Number of requests that can be stored in VC1 Tx Queue. [5:0] RW 6'h20 CFG_TX_VC0_SIZE Number of requests that can be stored in VC0 Tx Queue. 128 Default Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.14.4 AL Request Root Complex Lower Address Register: RDR_REQRCAL Bits Type Address: 0x50320 Default Name Description [31:2] RW 30`b0 CFG_RC_ADDR Upper 30 bits of lower 32 bits of Root Complex Address for the request submitted from the Application Layer. [1:0] RO 2`b0 CFG_RC_ADDR Lower 2 bits of lower 32 bits of Root Complex Address. Hardwired to zeros. 3.14.5 AL Request Root Complex Upper Address Register: RDR_REQRCAU Bits [31:0] Type RW Address: 0x50324 Default 32`b0 Name CFG_RC_ADDR Description Upper 32 bits of Root Complex Address for the request submitted from the Application Layer. 3.14.6 AL Request Endpoint Address Register: RDR_REQEPA Bits Type [31:24] RO 8`b0 [23:0] RW 24`b0 DSH-201010p2 2/4/09 Address: 0x50328 Default Name Description Reserved CFG_EP_ADDR The Endpoint address (i.e., destination or source address) of Application Layer request. Conexant Preliminary Information/Conexant Proprietary and Confidential 129 Registers CX23885 Data Sheet 3.14.7 AL Request Parameters When this register is written, the signal CFG_NEW_REQ_WRITTEN is asserted for one PECLK cycle. The TL block uses this signal to begin capturing the new transaction request. Register: RDR_REQCTRL Address: 0x5032c Bits Type [31:20] RW 12`b0 CFG_AL_LENGTH Length of transfer request in bytes. [19:17] RW 3`b0 CFG_AL_OP_TYPE Type of requested transfer: 3'b000:Write 3'b001:Read 3'b010:Vender_Defined Type0 Message 3'b011:Vender_Defined Type1 Message 3'b100:PM_PME Message 3'b101:Hot-Plug ATTENTION_BUTTON_PRESSED Message 3'b11x:Reserved [16:16] RO 1`b0 [15:13] RW 3`b0 [12:10] RO 3`b0 [9:8] RW 2`b0 CFG_AL_ATTR The attribute field of the TLP Header ([9] = Relaxed Ordering; [8] = No Snoop). [7:4] RW 4`b0 CFG_AL_FIRST_BE First DW Byte Enable. [3:0] RW 4`b0 CFG_AL_LAST_BE Last DW Byte Enable. 130 Default Name Description Reserved CFG_AL_TC Traffic Class of the transfer request. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.14.8 AL Request Status The behavior of this register is determined by the CFG_REQSTAT_POP_MODE bit in the RDR_TLCTL0 register. When CFG_REQSTAT_POP_MODE = 1'b0, any write to this register will pop the next value into the status. When CFG_REQSTAT_POP_MODE = 1'b1, any read from this register will pop the next value into the status. Register: RDR_REQSTAT Bits Type Address: 0x50330 Default Name Description [31:31] RO 1`b0 TL_REQ_SUCCESSF UL Request has completed successfully. [30:30] RO 1`b0 TL_NXT_STAT_RDY 1'b1 = another request has completed and is ready to be reported. [29:27] RO 3`b0 [26:24] RO 3`b0 TL_CPL_OP_TYPE Operation Type of the completed request from the Application Layer. [23:0] RO 24`b0 TL_CPL_EP_ADDR End-point address provided by Rider to associate a completed request from the Application Layer. Reserved 3.14.9 Transaction Layer Test Control (Flow Control) When this register is written, the CFG_TST_SET_FC signal is asserted for one PECLK cycle. This pulse directs the TL to load the appropriate flow control counters with the values specified in this register. Register: RDR_TL_TEST Bits Type Address: 0x50334 Default Name Description [31:27] RO 5`b0 [26:24] RW 3`b0 CFG_TST_SET_FC_V CR Selects which VC Resource is to be set by this register. [23:22] RW 2`b0 CFG_TST_SET_FC_S EL Selects which counters are to be set by this register: 2'b00: Credits Consumed 2'b01: Credit Limit 2'b10: Credits Allocated 2'b11: Credits Received [21:20] RW 2`b0 CFG_TST_SET_FC_T YPE Selects the type of counter to be set by CFG_TST_FC_HDR and CFG_TST_FC_DATA: 2'b00: Posted 2'b01: Non-Posted 2'b10: Completion 2'b11: RESERVED [19:12] RW 8`b0 CFG_TST_SET_FC_H DR Value to be loaded into the header credit counter. [11:0] RW 12`b0 CFG_TST_SET_FC_D ATA Value to be loaded into the data credit counter. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 131 Registers CX23885 Data Sheet 3.14.10 Receive Buffer Control Register: RDR_RXBUFCTL Bits Type Default [31:18] RO 14`b0 [17:0] RO 18`b0 Address: 0x50338 Name Description Reserved CFG_CPL_RXBUFFER _SZ Number of DWords reserved for completions in Receive Buffer. Used to hold off a MRd transmitted from Rider if insufficient buffer space is available for the completion(s). 3.14.11 Virtual Channel Resources 0 and 1 Control Register: RDR_VCR01_CT Bits Type Default [31:29] RO 3`b0 [28:16] RW 13'h 3B [15:13] RO 3`b0 [12:0] RW 13'h 3B 132 Address: 0x50348 Name Description Reserved CFG_VCR0_FC_TIM ER Max Payload Size Timer Default 128 bytes 59 (~237 symbol times) 256 bytes 104 (415 symbol times) 512 bytes 140 (~559 symbol times) 1024 bytes 268 (~1071 symbol times) 2048 bytes 524 (~2095 symbol times) 4096 bytes 1036 (~4143 symbol times) Reserved CFG_VCR1_FC_TIM ER Expiration value for Flow Control Update timer for VC Resource 1. Same units and default table as CFG_VCR0_FC_TIMER. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.14.12 Virtual Channel Resources 2 and 3 Control Register: RDR_VCR23_CTL Bits Type Default [31:29] RO 3`b0 [28:16] RW 13'h 3B [15:13] RO 3`b0 [12:0] RW 13'h 3B Address: 0x5034c Name Description Reserved CFG_VCR2_FC_TIM ER Expiration value for Flow Control Update timer for VC Resource 2. Same units and default table as CFG_VCR0_FC_TIMER. Reserved CFG_VCR3_FC_TIM ER Expiration value for Flow Control Update timer for VC Resource 3. Same units and default table as CFG_VCR0_FC_TIMER. 3.14.13 Virtual Channel Resource 0 Initial Flow Control Credits Register: RDR_RX_VCR1_FC Bits Type Default Address: 0x50354 Name Description [31:25] RO 7`b0 [24:18] RO 7'h 4 CFG_RX_VCR1_NP H_FC Number of Flow Control Credits initially advertised for VCR1 Non-Posted Header. VCR1 must be disabled to write this field. [17:7] RO 11'h 100 CFG_RX_VCR1_PD_ FC Number of Flow Control Credits initially advertised for VCR1 Posted Data. VCR1 must be disabled to write this field. [6:0] RO 7'h 4 CFG_RX_VCR1_PH_ FC Number of Flow Control Credits initially advertised for VCR1 Posted Headers. VCR1 must be disabled to write this field. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 133 Registers CX23885 Data Sheet 3.14.14 Virtual Channel Resource 2 Initial Flow Control Credits Register: RDR_RX_VCR2_FC Bits Type Default Address: 0x50358 Name Description [31:25] RO 7`b0 CFG_RX_VCR2_NP H_FC Reserved [24:18] RO 7'h 4 CFG_RX_VCR2_PD_ FC Number of Flow Control Credits initially advertised for VCR2 Non-Posted Header. VCR2 must be disabled to write this field. [17:7] RO 11'h 100 CFG_RX_VCR2_PH_ FC Number of Flow Control Credits initially advertised for VCR2 Posted Data. VCR2 must be disabled to write this field. [6:0] RO 7'h 4 CFG_RX_VCR2_NP H_FC Number of Flow Control Credits initially advertised for VCR2 Posted Headers. VCR2 must be disabled to write this field. 3.14.15 Virtual Channel Resource 3 Initial Flow Control Credits Register: RDR_RX_VCR3_FC Bits Type [31:25] RO 7`b0 [24:18] RO 7'h 4 CFG_RX_VCR3_NP H_FC Number of Flow Control Credits initially advertised for VCR3 Non-Posted Header. VCR3 must be disabled to write this field. [17:7] RO 11'h 100 CFG_RX_VCR3_PD_ FC Number of Flow Control Credits initially advertised for VCR3 Posted Data. VCR3 must be disabled to write this field. [6:0] RO 7'h 4 CFG_RX_VCR3_PH_ FC Number of Flow Control Credits initially advertised for VCR3 Posted Headers. VCR3 must be disabled to write this field. 134 Default Address: 0x5035c Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.15 Registers Rider Registers: Data Link Layer These registers are not reset when the link goes down (i.e., when RDR_LINK_DN_RST_N is asserted). Register: Reserved Bits [31:0] Type RO Address: 0x50360 Default Name 32`b0 Description Reserved 3.15.1 Data Link Layer Control Register: RDR_DLLCTRL Bits Type Address: 0x50364 Default [31:10] RO 22`b0 [9:8] RW 2'h 3 [7:1] RO 7`b0 [0:0] RW 1`b0 Name Description Reserved CFG_TST_REPLAY_ NUM_CNT Sets the number of times the Replay Buffer is replayed before the link is retrained. Reserved CFG_TST_BYP_FLO W_CTRL Bypass Flow Control Initialization. 3.15.2 Replay Timeout Limits Register: RDR_REPLAYTO Bits Type [31:20] RO [19:10] [9:0] Name Description 12'h B2 CFG_REPLAY_TO_U NADJ Unadjusted Replay Timer limit. Corresponds to Table 3-4 of PCI Express Base Specification. Units are 4 symbol times. RO 10'h 3 CFG_RXL0SADJ_CR C Rx_L0s_Adjustment term added to CFG_REPLAY_TO_UNADJ if L0s is enabled and common reference clock configuration. Units are 4 symbol times. RO 10'h 3 CFG_RXL0SADJ_AR C Rx_L0s_Adjustment term added to CFG_REPLAY_TO_UNADJ if L0s is enabled and non-common reference clock configuration. Units are 4 symbol times. (Sticky) DSH-201010p2 2/4/09 Default Address: 0x50368 Conexant Preliminary Information/Conexant Proprietary and Confidential 135 Registers CX23885 Data Sheet 3.15.3 ACK Latency Timeout Limits Register: RDR_ACKLATTO Bits Type [31:21] RO 11'h 3C [20:17] RO 4`b0 [16:8] RO 9'b1 CFG_P0S2P0_LAT Time for Transmitter to transition from P0s to P0. Units are 4 symbol times. (Sticky) [7:0] RO 8`b0 MAC_TX_N_FTS Number of FTS required to be transmitted when exiting L0s. Units are 4 symbol times. This value (x4) is received from the entity on the other side of the link during link training. 136 Default Address: 0x5036c Name Description CFG_ACKLAT_TO_U NADJ Unadjusted Acknowledge Latency Timer limit. Corresponds to Table 3-5 of PCI Express Base Specification. Units are 4 symbol times. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.16 Registers Rider Registers: MAC Layer These registers are not reset when the link goes down (i.e., when RDR_LINK_DN_RST_N is asserted). 3.16.1 MAC Layer Status 0 Register: RDR_MACSTAT0 Bits Type Default Address: 0x50380 Name Description [31:16] RO 16`b0 [15:15] RO 1`b0 [14:13] RO 2`b0 [12:12] RO 1`b0 MAC_LINKUP Indicates when link is up. [11:10] RO 2`b0 MAC_TXL0S_STATE TxL0s State [9:8] RO 2`b0 MAC_RXL0S_STATE RxL0s State [7:0] RO 8`b0 MAC_LTSSM_STATE Indicates current state of LTSSM: 00h: Detect.Quiet 01h: Detect.Active 02h: Polling.Active 03h: Polling.Compliance 04h: Polling.Config 05h: Polling.Speed 06h: Config.Linkwidth.Start 07h: Config.Linkwidth.Accept 08h: Config.Lanenum.Wait 09h: Config.Lanenum.Accept 0Ah: Config.Complete 0Bh: Config.Idle 0Ch: Recovery.RcvrLock 0Dh: Recovery.RcvrCfg 0Eh: Recovery.Idle 0Fh: RxL0_TxL0 1Fh: L1.Entry 20h: L1.Idle 21h: L2.Idle 22h: L2.Transmit.Wake 23h: Disabled 30h: Disalbed.Idle 24h: Loopback.Entry 25h: Loopback.Active.Mstr 26h: Loopback.Active.Slv 27h: Loopback.Exit.Mstr 28h: Loopback.Exit.Slv 29h: Hot Reset DSH-201010p2 2/4/09 Reserved MAC_PATTERN_LO CKED Indicates when loopback pattern checker matches the Rx Pattern with the Tx Pattern. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 137 Registers CX23885 Data Sheet Register: Reserved Bits [31:0] Type RO Address: 0x50384 Default Name 32`b0 Description Reserved 3.16.2 MAC Layer Control 0 Register: RDR_MACCTRL0 Bits Type Default Address: 0x50388 Name Description [31:24] RW 8'h20 CFG_LB_MSTR_TIM EOUT Loopback master timeout. Must receive TS1 ordered set with Loopback bit asserted within this time. Units are 1ms. Maximum is 100 ms. [23:20] RW 4'hA CFG_LB_MSTR_DK SEL Data (0) or Special (1) Symbol select for Loopback Master Data Register [23]: Byte 0 [22]: Byte 1 [21]: Byte 2 [20]: Byte 3 [19:18] RO 2`b0 [17:17] RW 1'b1 CFG_LB_COMPLIAN CE_EN 1'b1 causes TXCOMPLIANCE to be asserted for the first symbol of the loopback data pattern. [16:16] RW 1`b0 CFG_LB_MSTR_EN Enable Loopback Master mode. [15:9] RO 7`b0 [8:0] RW 9'h127 138 Reserved Reserved CFG_SKP_INS_RAT E Skip Insertion Rate. The value of CFG_SKP_INS_RATE is the number of symbol times divided by 4 between SKP Ordered Set Insertion. Recommended values from 295 to 385 (or 1180 to 1538 symbol times). SKP insertion is disabled if 9'h000 is written to this register.(Sticky) Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.16.3 MAC Layer Control 1 Register: RDR_MACCTRL1 Bits Type Default Address: 0x5038c Name Description [31:25] RO 7`b0 Reserved [24:16] RW 9'h190 CFG_TXL0S_TIMEO UT Controls the time the MAC waits when no TLPs or DLLPs need to be transmitted before transitioning to the TxL0s state. Units are 4 symbol times. [15:0] RW 16`b0 CFG_TST_LTSSM_G OTO_STATE A set bit forces the LTSSM to the specified state: [0] = Detect [1] = Polling [2] = Configuration [3] = L0 (4 SKP Ordered Sets Transmitted) [15:4] = Reserved 3.16.4 MAC Control 2 Register: RDR_MACCTRL2 Bits Type Default Address: 0x5039 Name Description [31:17] RO 15`b0 [16:7] RW 10'h380 CFG_TXL1_TIMEOU T Controls the time the MAC waits when no TLPs or DLLPs need to be transmitted before transitioning to theL1ASPM state. Units are 4 symbol times. [6:1] RW 6'h3F CFG_BIST_NUM_TS 1_PA Number of 16 TS1 Ordered Sets transmitted in Polling.Active when entering Loopback Master Mode (CFG_LB_MSTR_EN is 1'b1). [0:0] RO 1`b0 CFG_SCRAMBLE_E N_N Used in TS1/TS2 Ordered Sets to disable scrambling at the other end of the link and used by Rider logic to disable the scrambler. Only disables scrambling in Configuration State. Active Low.(Sticky) DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 139 Registers CX23885 Data Sheet 3.16.5 MAC Loopback Master Data Register: RDR_MAC_LB_DATA Default Address: 0x50394 Bits Type Name Description [31:24] RW 8'h BC CFG_LB_MSTR_DAT A Byte 0 of Loopback Master Data. [23:16] RW 8'h B5 CFG_LB_MSTR_DAT A Byte 1 of Loopback Master Data. [15:8] RW 8'h BC CFG_LB_MSTR_DAT A Byte 2 of Loopback Master Data. [7:0] RW 8'h 4A CFG_LB_MSTR_DAT A Byte 3 of Loopback Master Data. 3.16.6 MAC L0s Exit Latencies Register: RDR_L0S_EXIT_LAT Bits Type [31:30] RO 2`b0 [29:27] RO 3'h 2 L1_EXIT_LAT_CRC L1 ASPMEXIT latency when operating with a common reference clock (CFG_COMMON_CLOCK is set).(Sticky) [26:24] RO 3'h 5 L0S_EXIT_LAT_CRC L0s exit latency when operating with a common reference clock (CFG_COMMON_CLOCK is set).(Sticky) [23:16] RO 8'h 56 CFG_N_FTS_CRC N_FTS when operating with a common reference clock. This value must be compatible with l0s_exit_lat_crc.(Sticky) [15:14] RO 2`b0 [13:11] RO 3'h 2 L1_EXIT_LAT_ARC L1 ASPMEXIT latency when operating with an asynchronous reference clock (CFG_COMMON_CLOCK is 1'b0).(Sticky) [10:8] RO 3'h 5 L0S_EXIT_LAT_ARC L0s exit latency when operating with an asynchronous reference clock (CFG_COMMON_CLOCK is 1'b0).(Sticky) [7:0] RO 8'h 5F CFG_N_FTS_ARC N_FTS when operating with an asynchronous reference clock. This value must be compatible with l0s_exit_lat_arc.(Sticky) 140 Default Address: 0x50398 Name Description Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.17 Registers Audio and Video Core 3.17.1 Serial Slave Registers 3.17.1.1 Host Register 1 Register: HOST_REG1 Bits Type Address: 0x0 Default Name Description [7:7] RW 1`b 0 FORCE_CHIP_SEL Override the CHIP_SEL pin for I2C address decode 0 = Use the CHIP_SEL pin for I2C decode 1 = The I2C chip select signal is forced to a one regardless of the CHIP_SEL pin [6:6] RW 1`b 0 SLV_SI_DIS Control the glitch filters and slew rate control in the I2C pads to enable a faster speed of operation 0 = glitch filters and slew rate control enabled 1 = glitch filters and slew rate control disabled [5:5] RW 1`b 0 AUTO_INC_DIS Control auto-address increment after each byte transfer 0 = do the auto-address increment 1 = don't increment the address [4:4] RW 1`b 0 PREFETCH_EN Enable prefetch on reads. Prefetch is unnecessary unless the interface is operated many times faster than the typical max speed of 400 kHz. However, enabling prefetch can create problems when reading FIFOs. The prefetch operation can pop an entry from a FIFO, whether or not the transaction actually requests the byte. [3:2] RO 2`b 0 [1:1] RW 1`b 0 DIGITAL_PWR_DN Gate digital clocks (SCLK, VCLK, CLKX5, IFCLK, BBCLK) (This bit can be configured to gate down CLK5X or VCLK only. See POWER_CTRL register.) 0 = don't gate 1 = hold clocks in high state [0:0] RW 1`b 0 SLEEP Put the chip in sleep mode. Gate the digital clocks and power down the analog circuitry. (Power down of some analog blocks can be masked when the SLEEP bit is asserted. See POWER_CTRL register.) 0 = don't power down 1 = power down DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 141 Registers CX23885 Data Sheet 3.17.1.2 Host Register 2 Register: HOST_REG2 Bits Type Address: 0x1 Default Name Description [7:6] RW 2`b 1 VREF_PLL_REG Control for PLL supply voltage [5:5] RW 1`b 0 PWR_DN_SYS_PLL Power down the SYS PLL 0 = don't power down 1 = power down [4:4] RW 1`b 0 PWR_DN_AUX_PLL Power down the Auxiliary PLL 0 = don't power down 1 = power down [3:3] RW 1`b 0 PWR_DN_VID_PLL Power down the Video Clock PLL 0 = don't power down 1 = power down [2:2] RW 1`b 0 PWR_DN_PLL_REG 2 Powers down the regulator for the auxiliary clock PLL. [1:1] RW 1`b 0 PWR_DN_PLL_REG 1_3 Powers down the regulator for the video clock PLL and SYS PLL [0:0] RW 1`b 0 PWR_DN_DLL Powers down the ADC DLL 0 = don't power down 1 = power down 3.17.1.3 Host Register 3 Register: HOST_REG3 Bits Type Address: 0x2 Default Name Description [7:7] RW 1`b 0 CLK_IN_EN Enables clock from pad to AFE [6:4] RW 3`h 7 XTAL_CTRL XTAL amplifier gain [3:2] RW 2`b 0 BB_CLK_MODE Controls baseband ADC and PLL reference clocks. 00=xtal/2 01=xtal 10=clk_28M 11=xtal/2 [1:1] RW 1`b 0 REF_DIV_PLL Reference clock divider 0=divide by 2 1=no division [0:0] RW 1`b 0 REF_SEL_PLL1 Selects PLL1 reference clock. 0= PLL3 divided by 5 1=reference clock 142 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.18 Registers Chip Configuration Registers 3.18.1 Baseband Analog Front End and General Chip Configuration Registers 3.18.1.1 Chip Control Register: CHIP_CTRL Address: 0x100 Bits Type [31:30] RW 2`b 0 CH3_SRC Selects input pin to the analog front end Channel 3: 00 = Vin7 01 = Vin8 10 = none 11 = none [29:28] RW 2`b 0 CH2_SRC Selects input pin to the analog front end Channel 2: 00 = Vin4 01 = Vin5 10 = Vin6 11 = none [27:27] RO 1`b 0 [26:24] RW 3`b 0 [23:23] RW 1`b 0 Reserved [22:21] RO 2`b 0 Reserved DSH-201010p2 2/4/09 Default Name Description Reserved CH1_SRC Selects input pin to the analog front end Channel 1: 000 = Vin1 001 = Vin2 010 = Vin3 011 = Vin4 100 = Vin5 101 = Vin6 110 = Vin7 111 = Vin8 Conexant Preliminary Information/Conexant Proprietary and Confidential 143 Registers CX23885 Data Sheet [20:20] RW 1`b 1 [19:19] RO 1`b 0 [18:18] RW 1`b 0 DUAL_MODE_ADC2 Select the ADC2 input source 0 = Selection is based on the CH_SEL_ADC2 bit field 1 = Toggle the ADC2 input between Channel 2 and Channel 3 on every ADC sample clock [17:17] RW 1`b 0 CH_SEL_ADC2 ADC2 input select. 0 = Channel 2 1 = Channel 3 This bit setting has no effect if the DUAL_MODE_ADC2 bit is set to 1 [16:16] RW 1`b 0 SOFT_RST Internal reset 0 = De-assert reset 1 = assert reset [15:0] RO 16`b 0 DEVICE_ID Device ID The AV_CORE device ID will return 0. 144 CHIP_ACFG_DIS Auto-config Disable of chip-level registers. 0 = Allow VID_PLL_INT, VID_PLL_FRAC, and AFE_CTRL fields to be automatically configured based on square pixel, video format, and input mode 1 = Disable auto-config The following fields in the MODE_CTRL (0x400) register can trigger an auto-config: VID_FMT_SEL (or auto-detected format) SQ_PIXEL INPUT_MODE With or without this bit set, the registers can always be written by software. The auto-config hardware only writes the registers when a change in format is detected. See AFE Control Auto-config, for details. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.18.1.2 Baseband AFE Control Register: AFE_CTRL Address: 0x104 Bits Type [31:29] RW 3`b 0 DROOP_COMP_INP UT_DIS Droop Compensation Input Disable.This 3-bit bus is used to disable the input to the droop compensation logic for the 3 input channels. [2] = droop_comp_input_dis_ch3 [1] = droop_comp_input_dis_ch2 [0] = droop_comp_input_dis_ch1 [28:28] RW 1`b 0 DROOP_POL Polarity control for DROOP_UP output from droop compensation correction block. [27:27] RW 1`b 0 IREF_SEL Reference current resistor 0 = external resistor 1 = on-chip resistor [26:26] RW 1`b 1 EXT_GND_CH3 Channel 3 signal ground 0 = internal ground 1 = external ground [25:25] RW 1`b 1 EXT_GND_CH2 Channel 2 signal ground 0 = internal ground 1 = external ground [24:24] RW 1`b 1 EXT_GND_CH1 Channel 1 signal ground 0 = internal ground 1 = external ground [23:23] RW 1`b 0 BYPASS_CH3 Channel 3 anti-alias filter 0 = use 1 = bypass [22:22] RW 1`b 0 BYPASS_CH2 Channel 2 anti-alias filter 0 = use 1 = bypass [21:21] RW 1`b 0 BYPASS_CH1 Channel 1 anti-alias filter 0 = use 1 = bypass [20:20] RW 1`b 0 DROOP_COMP_CH3 Channel 3 input resistance boosting 0 = disable 1 = enable [19:19] RW 1`b 0 DROOP_COMP_CH2 Channel 2 input resistance boosting 0 = disable 1 = enable DSH-201010p2 2/4/09 Default Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential 145 Registers CX23885 Data Sheet [18:18] RW 1`b 1 DROOP_COMP_CH1 Channel 1 input resistance boosting 0 = disable 1 = enable [17:17] RW 1`b 0 CLAMP_EN_CH3 Channel 3 clamping 0 = disable 1 = enable (power up) [16:16] RW 1`b 0 CLAMP_EN_CH2 Channel 2 clamping 0 = disable 1= enable (power up) [15:15] RW 1`b 1 CLAMP_EN_CH1 Channel 1 clamping 0 = disable 1 = enable (power up) [14:14] RW 1`b 1 AUD_IN_SEL ADC input Select for Audio input paths: 0 = ADC1 input 1 = ADC2 input [13:13] RW 1`b 0 LUMA_IN_SEL ADC input Select for Luma input paths: 0 = ADC1 input 1 = ADC2 input [12:12] RW 1`b 1 CHROMA_IN_SEL ADC input Select for Chroma input paths: 0 = ADC1 input 1 = ADC2 input [11:11] RW 1`b 1 CLAMP_SEL_CH3 Channel 3 Clamp level: 0 = video decoder drives clamp level 1 = fixed at 3'b111 (midcode clamp) [10:10] RW 1`b 1 CLAMP_SEL_CH2 Channel 2 Clamp level: 0 = video decoder drives clamp level 1= fixed at 3'b111 (midcode clamp) [9:9] RW 1`b 0 CLAMP_SEL_CH1 Channel 1 Clamp level: 0 = video decoder drives clamp level 1 = fixed at 3'b111 (midcode clamp) [8:8] RW 1`b 1 VGA_SEL_CH3 Channel 3 VGA gain: 0 = video decoder drives VGA gain setting 1 = audio decoder drives VGA gain setting [7:7] RW 1`b 1 VGA_SEL_CH2 Channel 2 VGA gain: 0 = video decoder drives VGA gain setting 1 = audio decoder drives VGA gain setting [6:6] RW 1`b 0 VGA_SEL_CH1 Channel 1 VGA gain: 0 = video decoder drives VGA gain setting 1 = audio decoder drives VGA gain setting 146 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [5:5] RW 1`b 0 HALF_BW_CH3 Channel 3 anti-alias filter bandwidth reduction 0 = no reduction 1 = reduce by half [4:4] RW 1`b 0 HALF_BW_CH2 Channel 2 anti-alias filter bandwidth reduction 0 = no reduction 1 = reduce by half [3:3] RW 1`b 0 HALF_BW_CH1 Channel 1 anti-alias filter bandwidth reduction 0 = no reduction 1 = reduce by half [2:2] RW 1`b 0 EN_12DB_CH3 Channel 3 extra 12 dB gain 0 = disable 1 = enable [1:1] RW 1`b 0 EN_12DB_CH2 Channel 2 extra 12 dB gain 0 = disable 1 = enable [0:0] RW 1`b 0 EN_12DB_CH1 Channel 1 extra 12dB gain 0 = disable 1 = enable DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 147 Registers CX23885 Data Sheet 3.18.1.3 Video PLL Integer/Post Divider Register: VID_PLL_INT_POST Bits Type [31:14] RO 18`b 0 [13:8] RW 6`h 4 [7:6] RO 2`b 0 [5:0] RW 6`h F Address: 0x108 Default Name Description Reserved VID_PLL_POST Video PLL Post Divide Valid values are 2 to 63 (decimal) PLL clock frequency = FREF * (M + (N / 225)) / Post Divide Default Video PLL frequency = 108.000011 MHz. Assuming reference frequency = 28.636363 MHz Reserved VID_PLL_INT Video PLL integer coefficient (M) Valid values are 8 to 59 (decimal) PLL clock frequency = FREF * (M + (N / 225)) / Post Divide Default value places VCO in safe operating range. 3.18.1.4 Video PLL Fractional Register: VID_PLL_FRAC Bits Type Address: 0x10C Default [31:25] RO 7`b 0 [24:0] RW 25`h 2BE2FE 148 Name Description Reserved VID_PLL_FRAC Video PLL fractional coefficient (N) Valid values are 0 to 2^25-1 PLL clock frequency = FREF * (M + (N / 225)) / Post Divide Default Video PLL frequency = 108.000011 MHz. Assuming reference frequency = 28.636363 MHz Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.18.1.5 Auxiliary PLL Integer/Post Divider Register: AUX_PLL_INT_POST Bits Type Default [31:22] RO 10`b 0 [21:16] RW 6`h A [15:14] RO 2`b 0 [13:8] RW 6`h 3 [7:6] RO 2`b 0 [5:0] RW 6`h 18 Address: 0x110 Name Description Reserved AUX_PLL_POST_B Auxiliary PLL Post Divide B Valid values are 2 to 63 (decimal) Reserved AUX_PLL_POST_A Auxiliary PLL Post Divide A Valid values are 2 to 63 (decimal) Reserved AUX_PLL_INT Auxiliary PLL integer coefficient (M) Valid values are 8 to 59 (decimal) Default places VCO in safe operating mode at powerup 3.18.1.6 Auxiliary PLL Fractional Register: AUX_PLL_FRAC Bits Type Default [31:25] RO 7`b 0 [24:0] RW 25`h 1BF0C9D DSH-201010p2 2/4/09 Address: 0x114 Name Description Reserved AUX_PLL_FRAC AUX PLL fractional coefficient (N) (0 to 225 -1) PLL clock frequency = Crystal frequency * (M + (N / 225)) / Post Divide Default is 7680*48e3/28.636363e6 Conexant Preliminary Information/Conexant Proprietary and Confidential 149 Registers CX23885 Data Sheet 3.18.1.7 System PLL Integer/Post Divider Register: SYS_PLL_INT_POST Bits Type [31:14] RO 18`b 0 [13:8] RW 6`h 5 [7:6] RO 2`b 0 [5:0] RW 6`h 13 Address: 0x118 Default Name Description Reserved SYS_PLL_POST SYS PLL Post Divide Valid values are 2 to 63 (decimal) PLL clock frequency = Crystal frequency * (M + (N / 225)) / Post Divide Typical value is 2 Reserved SYS_PLL_INT SYS PLL integer coefficient (M) Valid values are 8 to 59 (decimal) PLL clock frequency = Crystal frequency * (M + (N / 225)) / Post Divide Typical value is 0xA 3.18.1.8 System PLL Fractional Register: SYS_PLL_FRAC Address: 0xB11C Bits Type [31:25] RW 7`b 0 [24:0] RW 25`h 14758E5 150 Default Name Description Reserved SYS_PLL_FRAC SYS PLL fractional coefficient (N) (0 to 225-1) PLL clock frequency = Crystal frequency * (M + (N / 225)) / Post Divide Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.18.1.9 Pin Control Register: PIN_CTRL Address: 0x120 Bits Type [31:31] RW 1`b 0 [30:30] RO 1`b 0 IR_IRQ_STAT Bit is used in OR statement to determine if IRQ out of AV_CORE is set. [29:29] RO 1`b 0 AUD_IRQ_STAT Bit is used in OR statement to determine if IRQ out of AV_CORE is set. [28:28] RO 1`b 0 VID_IRQ_STAT Bit is used in OR statement to determine if IRQ out of AV_CORE is [27:26] RO 2`b 0 [25:25] RW 1`b 0 IRQ_N_OUT_EN Interrupt output enable [24:24] RW 1`b 0 IRQ_N_POLAR Interrupt output polarity [23:22] RW 2`b 0 I2S_SPD I2S Pad Speed [21:20] RW 2`b 0 AGC_SPD AGC_IF/AGC_RF pad speed [19:18] RW 2`b 0 IR_SPD IR_TX/IR_RX pad speed [17:16] RW 2`b 0 VID_DATA_SPD Video clock and data pad speed [13:12] RW 2`b 0 GPIO_SPD GPIO pad speed [15:14] RW 2`b 0 VID_CTRL_SPD Video control signals pad speed [11:11] RW 1`b 1 AGC_OUT_EN Enable AGC RF and IF outputs [10:10] RW 1`b 0 IR_TX_OUT_EN Enable IR transmitter output [9:9] RW 1`b 0 VID_DATA_OUT_EN Enable Video Data outputs [8:8] RW 1`b 0 VID_CTRL_OUT_EN Enable Video Control signal outputs. [7:7] RW 1`b 0 GPIO3_OUT_EN GPIO[3] output enable [6:6] RW 1`b 0 GPIO2_OUT_EN GPIO[2] output enable [5:5] RW 1`b 0 GPIO1_OUT_EN GPIO[1] output enable [4:4] RW 1`b 0 GPIO0_OUT_EN GPIO[0] output enable [3:0] RW 4`b 0 GPIO Write GPIO data to pads Read data at GPIO pads DSH-201010p2 2/4/09 Default Name Description Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 151 Registers CX23885 Data Sheet 3.18.1.10Audio I/O Control Register: AUD_IO_CTRL Bits Type Address: 0x124 Default Name Description [31:8] RO 24`b 0 [7:7] RW 1`b 0 I2S_PORT_DIR I2S port direction 0 - output 1 - input [6:6] RW 1`b 0 I2S_OUT_SRC I2S port source 0 - Audio Decoder 1 - Analog/Digital Converter When 1 is selected, the I2S pins will be directly connected to the A/D Converter I2S ports, providing full 24b I2S data at the A/D Converter sample rate. [5:4] RW 2`b 0 AUD_CHAN3_SRC Audio channel 3 source 00 - Reserved 01 - I2S input 10 - A/D Converter 11 - Reserved [3:2] RW 2`b 0 AUD_CHAN2_SRC Audio Channel 2 Source 00 - Parallel 2 (Audio Decoder Parallel2_SRC out) 01 - I2S input 10 - A/D Converter 11 - Parallel 2 (Audio Decoder Parallel2_SRC out) Parallel 2 SRC source controlled by PARALLEL2_SRC_OUT_SEL in BAND_OUT_SEL register [1:0] RW 2`b 0 AUD_CHAN1_SRC Audio Channel 1 Source 00 - Parallel 1 (Audio Decoder Parallel1_SRC out) 01 - I2S input 10 - A/D Converter 11 - Parallel 1 (Audio Decoder Parallel1_SRC out) Parallel 1 SRC source controlled by PARALLEL1_SRC_OUT_SEL in BAND_OUT_SEL register 152 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.18.1.11Audio Lock Control 1 Register: AUD_LOCK1 Bits Type [31:30] RW [29:28] Address: 0x128 Default Name Description 2`h 2 AUD_LOCK_KI_SHIF T The gain applied to the indirect error path of the loop filter through a left shift from 0 to 3 bit positions. This is in addition to a default right shift. This is used to lock the AUX PLL to the video pixel rate. RW 2`h 2 AUD_LOCK_KD_SHI FT The gain applied to the direct error path of the loop filter through a left shift from 0 to 3 bit positions. This is in addition to a default left shift. This is used to lock the AUX PLL to the video pixel rate [27:25] RO 3`b 0 [24:24] RW 1`b 0 EN_AV_LOCK Enable locking of AUX_PLL to video pixel rate [23:0] RW 24`h 1193F8 VID_COUNT Expected count, minus 1 and times 8, for 8x video PLL clock when the number of audio clocks is counted as reflected in AUD_COUNT. Since this number is in terms of eights of an 8x pixel clock, more resolution is allowed in defining the audio/video clock ratio. Reserved 3.18.1.12Audio Lock Control 2 Register: AUD_LOCK2 Bits Type [31:28] RW [27:24] Address: 0x12C Name Description 4`b 1 AUD_LOCK_KI_MUL T The gain applied to the indirect error path of the loop filter through an unsigned multiply. This is used to lock the AUX PLL to the video pixel rate RW 4`b 1 AUD_LOCK_KD_MU LT The gain applied to the direct error path of the loop filter through an unsigned multiply. This is used to lock the AUX PLL to the video pixel rate [23:22] RO 2`b 0 [21:20] RW 2`h 2 [19:0] RW 20`h 5FFF DSH-201010p2 2/4/09 Default Reserved AUD_LOCK_FREQ_SH IFT AUD_COUNT The gain applied to the frequency error (difference in actual vs. expected counts) before passing to the loop filter. This is in addition to a default scaling that occurs. There is a default left or right shift depending on the length of time over which the sample is collected, as indicated by the VID_COUNT field. Number of audio sample-rate clocks, minus 1, to count before examining VID_COUNT. Conexant Preliminary Information/Conexant Proprietary and Confidential 153 Registers CX23885 Data Sheet 3.18.1.13Power-Down Control Register: POWER_CTRL Bits Type Address: 0x130 Default Name Description [31:16] RO 16`b 0 [15:15] RW 1`b 0 IFCLK_GATE_MSK IFCLK gate mask 0 - DIG_PWR_DN disables IF ADC clock (IFCLK) 1 - gating of IFCLK inhibited [14:14] RW 1`b 0 BBCLK_GATE_MSK BBCLK gate mask 0 - DIG_PWR_DN disables baseband ADC clock (BBCLK) 1 - gating of BBCLK inhibited [13:13] RW 1`b 0 SCLK_GATE_MSK SCLK and I2S_MCLK gate mask 0 - DIG_PWR_DN disables sample clock (SCLK) and I2S master clock (I2S_MCLK) 1 - gating of SCLK and I2S_MCLK inhibited [12:12] RW 1`b 0 CLK5X_GATE_MSK CLK5X gate mask 0 - DIG_PWR_DN disables high-speed audio clock (CLK5X) 1 - gating of CLK5X inhibited [11:11] RW 1`b 0 VCLK_GATE_MSK VCLK gate mask 0 - DIG_PWR_DN disables high-speed video clock (VCLK) 1 - gating of VCLK inhibited [10:10] RW 1`b 0 SLEEP_PLL_MSK PLL sleep mask. 0 - SLEEP powers down PLLs 1 - power down of PLL inhibited [9:9] RW 1`b 0 SLEEP_DLL_MSK DLL sleep mask. 0 - SLEEP powers down DLL circuitry 1 - power down inhibited [8:8] RW 1`b 0 SLEEP_ANALOG_M SK Analog subsystem sleep mask. 0 - SLEEP powers down analog subsystem 1- power down of analog subsystem inhibited including DLL and PLLs [7:7] RW 1`b 0 PWR_DN_CH3 Powers down Channel 3 VGA/filter circuitry. 0 - don't power down Channel 3 1 - power down Channel 3 154 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [6:6] RW 1`b 0 PWR_DN_CH2 Powers down Channel 2 VGA/filter circuitry. 0 - don't power down Channel 2 1 - power down Channel 2 [5:5] RW 1`b 0 PWR_DN_CH1 Powers down Channel 1 VGA/filter circuitry. 0 - don't power down Channel 1 1 - power down Channel 1 [4:4] RW 1`b 0 PWR_DN_ADC2 Powers down ADC2 circuitry. 0 - don't power down ADC 2 1 - power down ADC 2 [3:3] RW 1`b 0 PWR_DN_ADC1 Powers down ADC1 circuitry. 0 - don't power down ADC 1 1 - power down ADC 1 [2:1] RO 2`b 0 [0:0] RW 1`b 0 Reserved PWR_DN_TUNING Powers down filter tuning circuitry. 0 - don't power down filter tuning 1 - power down filter tuning 3.18.1.14AFE Diagnostic Control 1 Register: AFE_DIAG_CTRL1 Default Address: 0x134 Bits Type Name Description [31:31] RW 1`b 0 DROOP_CAL_CH3 Droop calibrate enable for channel 3. While high, the droop comp circuit for channel1 will calibrate. [30:30] RW 1`b 0 DROOP_CAL_CH2 Droop calibrate enable for channel 2. While high, the droop comp circuit for channel1 will calibrate. [29:29] RW 1`b 0 DROOP_CAL_CH1 Droop calibrate enable for channel 1. While high, the droop comp circuit for channel1 will calibrate. [28:28] RW 1`b 0 DROOP_CAL_CALC_C H3 Enable for the droop compensation calibration where the DAC current is calculated. This particular enable bit applies to channel 3. [27:27] RW 1`b 0 DROOP_CAL_CALC_C H2 Enable for the droop compensation calibration where the DAC current is calculated. This particular enable bit applies to channel 2. [26:26] RW 1`b 0 DROOP_CAL_CALC_C H1 Enable for the droop compensation calibration where the DAC current is calculated. This particular enable bit applies to channel 1. RO 6'h 24 Reserved [25:20] DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 155 Registers CX23885 Data Sheet RW 2'b 1 FILTER_BIAS Digital control for the bias current multiplier 00 = 0.5 01 = 1 10 = 1.5 11 = 2 [17:16] RW 2`b 1 S2DIFF_BIAS Digital control for the single-ended to differential converter bias multiplier 00 = 0.75 01 = 1 10 = 1.25 11 = 1.5 [15:15] RW 1`b 0 [14:8] RW 7`h 18 [7:4] RO 4`b 0 [3:3] RW 1`b 0 [2:1] RO 2`b 0 [0:0] RW 1`b 0 [19:18] 156 Reserved BIAS_CTRL_ADC Digital control for the reference buffer bias [14:13] 00 = 50 A default 01 = 62.5 A 10 = 37.5 A 11 = 75.0 A MSB comparator current [12:11] 00 = 12.5 A 01 = 6.25 A 10 = 25.0 uA 11 = 50.0 A default Digital control for REFP and REFM [10] 0 = 1.6 V; 0.8 V default 1 = 1.5 V; 0.9 V Digital control for ADC bias current. [9:8] 00 = 50.0 A default 01 = 37.5 A 10 = 62.5 A 11 = 75.0 A Reserved VREF_CTRL_ADC Digital control for ADC reference voltage 0 = 1.60 V 1 = 1.20 V Reserved FOUR_X_CLK_ADC Choose 4x or 5x DLL output 0 = 5x output 1 = 4x output Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.18.1.15AFE Diagnostics Control 3 Register: AFE_DIAG_CTRL3 Default Address: 0x13C Bits Type Name Description [31:26] RO 6`b 0 [25:25] RW 1`b 0 AUD_DUAL_FLAG_P OL Audio Decoder Dual Flag Polarity Polarity of DUAL_FLAG signal sent to audio decoder 0 = non-inverted polarity 1 = inverted polarity [24:24] RW 1`b 0 VID_DUAL_FLAG_P OL Video Decoder Dual Flag Polarity Polarity of DUAL_FLAG signal sent to video decoder 0 = non-inverted polarity 1 = inverted polarity [23:22] RO 2`b 0 [21:21] RO 1`b 0 TUNING_READY Filter auto-tuning status 0 = not complete 1 = filter tuning complete [20:16] RO 5`b 0 TUNE_OUT The tuning code selected by the auto-tune algorithm. [15:15] RW 1`b 0 FORCE_TUNING Auto-tuning code override Reserved Reserved 0 = don't override 1 = forces tuning code to value contained in TUNE_IN field. [14:13] RO 2`b 0 [12:8] RW 5`b 0 [7:4] RO 4`b 0 [3:3] RW 1`b 0 TEST_MODE_CH1 Disables the filter in CH1 test mode 0 = enable filter 1 = disable filter [2:2] RO 1`b 0 DISCONNECT_CH1 Connects the differential analog signal at ADC1 input to pins VIN2 and VIN3 0 = don't connect 1= connect [1:1] RW 1`b 0 CH_SEL_ADC1 ADC1 test mode 0 = connect ADC1 to output of filter 1 = connects ADC1 to the output of first VGA stage [0:0] RW 1`b 0 TUNE_FIL_RST Reset Filter tuning logic. When 1, filter tuning is reset. When set back to 0, filter will auto-tune itself and after a few clocks return to normal operation. DSH-201010p2 2/4/09 Reserved TUNE_IN Tuning code to be used when FORCE_TUNING is set. Overrides the value chosen by autotuning. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 157 Registers CX23885 Data Sheet 3.18.1.16PLL Diagnostic Control Register: PLL_DIAG_CTRL Default Address: 0x140 Bits Type Name Description [31:31] RW 1`b 0 PLL_VDD_TEST Routes internally generated PLL supply voltage to CLK_AUX pad [30:29] RW 2`b 0 PLL_TEST_SEL Selects voltage to test 00=regulator 1 01=regulator 2 10= regulator reference 11= reserved RO 6'h 2A [22:22] RW 1`b 0 SPD_TST_EN Enables Ring oscillator process speed test circuit [21:21] RW 1`b 0 SPD_TST_SEL Selects between 1.2 V oscillator and 3.3 V oscillator 0 - 1.2 V 1 - 3.3 V [20:20] RO 1`b 0 [19:19] RO 1`b 0 SYS_PLL_UNLOCK System PLL unlock detection 0 = no unlock detected 1 = unlock detected [18:18] RO 1`b 0 AUX_PLL_UNLOCK Auxiliary PLL unlock detection 0 = no unlock detected 1 = unlock detected [17:17] RO 1`b 0 VID_PLL_UNLOCK Video PLL unlock detection 0 = no unlock detected 1 = unlock detected [16:16] RO 1`b 0 SYS_PLL_LOCK Sys PLL lock status 0 = unlocked 1 = locked [15:15] RO 1`b 0 AUX_PLL_LOCK Auxiliary PLL lock status 0 = unlocked 1 = locked [14:14] RO 1`b 0 VID_PLL_LOCK Video PLL lock status 0 = unlocked 1 = locked Reserved [28:23] 158 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [13:13] RW 1`b 0 SYS_PLL_RST SYS PLL reset 0 = don't reset 1 = reset the video PLL [12:12] RW 1`b 0 AUX_PLL_RST Audio PLL reset 0 = don't reset 1 = reset the video PLL [11:11] RW 1`b 0 VID_PLL_RST Video PLL reset 0 = don't reset 1 = reset the auxiliary PLL [10:10] RW 1`b 0 SYS_PLL_DDS SYS PLL delta sigma fractional divide 0 = enable 1 = disable [9:9] RW 1`b 0 AUX_PLL_DDS Auxiliary PLL delta sigma fractional divide 0 = enable 1 = disable [8:8] RW 1`b 0 VID_PLL_DDS Video PLL delta sigma fractional divide 0 = enable 1 = disable [7:6] RO 2`b 0 [5:0] RW 6`h 4 Reserved PLL_SPMP PLL charge pump current 3.18.1.17AFE Clock Out Control Register: AFE_CLK_OUT_CTRL Bits Type Default Address: 0x144 Name Description [31:5] RO 27`b 0 Reserved [4:4] RW 1`b 1 CLK_OUT_MODE AFE clock pad mode 0 = output 1 = input [3:0] RW 4`h 5 CLK_OUT_SEL Selects AFE clock pad output source Register: Reserved Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x148 Default Name 32`b 0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 159 Registers CX23885 Data Sheet Register: Reserved Bits [31:0] Type RO Address: 0x14C Default Name 32`b 0 Description Reserved Register: Reserved Bits [31:0] Type RO Address: 0x150 Default Name 32`b 0 Description Reserved Register: Reserved Bits [31:0] Type RO Address: 0x154 Default Name 32`b 0 Description Reserved Register: Reserved Bits [31:0] 160 Type RO Address: 0x158 Default Name 32`b 0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.18.1.18DLL1 Diagnostic Control Register: DLL1_DIAG_CTRL Address: 0x15C Bits Type Default Name [31:31] RW 19`b 0 [30:29] RO 2`b 0 [28:25] RW 4`b 0 CURRSET Changes current used in DLL [24:23] RW 2`b 0 DLYS MSB adds delay in path of reference. LSB multiplexes the DLL clock out when high. [22:20] RW 3`b 0 DEPTH Used in False Lock Detect: increases stability of decisions in FLD 111:x7 routes DLL output to test pad 110:x6 puts DLL in "fast" lock mode [19:17] RW 3`b 3 COMP_LT Used in False Lock Detect: counts this many pulses in half period to determine up override [16:14] RW 3`b 4 COMP_GT Used in False Lock Detect: counts this many pulses in half period to determine pulse-swallow [13:11] RW 3`b 2 CHPREF Chooses between old false-lock detect scheme and new. [10:10] RW 1`b 0 DOWN_OVRD Overrides the down command to PFD [9:9] RW 1`b 0 UP_OVRD Overrides the up command to PFD [8:8] RW 1`b 1 FLD False Lock Detect mode [7:0] RO 8`b 0 DLL1_BYPASS Description Clock reference for DLL1 (ADC DLL) input from clock pad rather than crystal input. Overrides CLK_OUT_MODE. Reserved Reserved 3.18.1.19GPIO[23:19] Output Enable Register: GPIO2_OUT_EN_REG Bits Type Default [31:5] RO 27`b 0 [4:0] RW 5`h 1F DSH-201010p2 2/4/09 Address: 0x160 Name Description Reserved GPIO2_OUT_ENABL E_N output enable for GPIO[23:19] 1 - normal function 0 - GPIO GPIO[19] map to IR_RX pin GPIO[20] map to IR_TX pin GPIO[21] map to I2S_SDAT GPIO[22] map to I2S_WCLK GPIO[23] map to I2S_BCLK Conexant Preliminary Information/Conexant Proprietary and Confidential 161 Registers CX23885 Data Sheet 3.18.1.20GPIO [23:19] Data Registers Register: GPIO2 Bits Type Address: 0x164 Default [31:21] RO 11`b 0 [20:16] RO 5`b 0 [15:5] RO 11`b 0 [4:0] RW 5`b 0 Name Description Reserved GPIO2_IN GPIO [23:19] input register Reserved GPIO2_OUT GPIO [23:19] data output registers 3.18.1.21IFADC Control Register: IFADC_CTRL Bits Type [31:31] RW 1`b 0 [30:0] RO 31`b 0 162 Address: 0x180 Default Name IF_PWRDN Description Power down IF ADC Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.19 Registers IR Registers 3.19.1 Infrared Remote registers 3.19.1.1 Control Register Register: IR_CNTRL_REG Address: 0x200 Bits Type [31:15] RO 17`b 0 [14:14] RW 1`b 0 R Receive FIFO load on Timer Overflow Disable 0 = Load Rx FIFO with 1s and RX_DATA_LH level on timer overflow 1 = Do not load Rx FIFO on timer overflow. (Shut off when noise occurs but must be turned back on when a real transmission starts) [13:13] RW 1`b 0 LBM Loop Back Mode 0 = Transmit and receive operation functions normally via the IR port's pins 1 = The output of the transmit modulation logic is fed into the input of the receive demodulation logic internal to the IR port. Transmit pin continues to reflect transmit data, receive pin is ignored by the IR receive logic [31:15] RO 17`b 0 [12:12] RW 1`b 0 DSH-201010p2 2/4/09 Default Name Description Reserved Reserved CPL Carrier Polarity (Transmitter Only) 0 = If mod/demodulation enabled, ones transmitted and received as series of carrier transitions (mark), zeros transmitted and received as the absence of a carrier or no transitions (space). If mod/demodulation disabled, ones transmitted/received as logic high, zeros as logic low, and the IR_TX_DATA PIN is driven low when idle. 1 = If mod/demodulation enabled, ones transmitted and received as the absence of a carrier or no transitions (space), zeros transmitted and received as a series of carrier transitions (mark). If mod/demodulation disabled, ones transmitted/received as logic low, zeros as logic high, and the IR_TX_DATA pin is driven high when idle. Note: Receive carrier polarity can be changed by software. No hardware support for this. Conexant Preliminary Information/Conexant Proprietary and Confidential 163 Registers CX23885 Data Sheet [11:11] RW 1`b 0 TIC Transmitter Interrupt Control 0 = Transmit FIFO service interrupt/DMA request asserted when TX FIFO is half full or less, negated when TX FIFO is more than half full 1 = Transmit FIFO service interrupt/DMA request asserted after transmitter becomes idle, negated when transmitter becomes busy (see status register below for a description of this IRQ) [10:10] RW 1`b 0 RIC Receiver Interrupt Control 0 = Receive FIFO service interrupt/DMA request asserted when RX FIFO is half full or greater, negated when RX FIFO is less than half full. 1 = Receive FIFO service interrupt/DMA request asserted when RX FIFO is not empty, negated when RX FIFO is empty.(see status register below for a description of this interrupt request) [9:9] RW 1`b 0 TXE Transmitter Enable 0 = Disable transmitter 1 = Enable transmitter [8:8] RW 1`b 0 RXE Receiver Enable 0 = Disable receiver 1 = Enable receiver [7:7] RW 1`b 0 TFE Transmit FIFO Enable 0 = Disable and reset transmit FIFO to all zeros 1 = Enable transmit FIFO [6:6] RW 1`b 0 RFE Receive FIFO Enable 0 = Disable and reset receive FIFO to all zeros 1 = Enable receive FIFO [5:5] RW 1`b 0 MOD Transmit Modulation Enable 0 = Disable transmit carrier modulation, transmit data as simple logic levels 1 = Enable transmit carrier modulation, transmit a mark as a burst of IR_TX_DATA pin transitions, and a space as the absence of transitions programming the carrier polarity bit determines whether ones or zeros are encoded into marks/high or spaces/low 164 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [4:4] RW 1`b 0 DMD Receive Demodulation Enable 0 = Disable receive carrier demodulation, receive data as simple logic levels 1 = Enable receive carrier demodulation, detect a mark as a series of RX pin transitions, and a space as the absence of transitions programming the carrier polarity bit determines whether marks/high or spaces/low are decoded as ones or zeros [3:2] RW 2`b 0 EDG Receive Edge Detect Control 00 = Disabled 01 = Falling edges trigger RX filter/pulse timer start/stop 10 = Rising edges trigger RX filter/pulse timer start/stop 11 = Either edge trigger RX filter/pulse timer start/stop The RX low pass filter and pulse width timer starts/ends a pulse duration measurement each time the programmed edge on the demodulated input is detected. [1:0] RW 2`b 0 WIN Next Predicted Receive Carrier Edge Window Limits 00 = Next carrier edge predicted to be 16 RX clocks -3/+3 01 = Next carrier edge predicted to be 16 RX clocks -4/+3 10 = Next carrier edge predicted to be 16 RX clocks -3/+4 11 = Next carrier edge predicted to be 16 RX clocks -4/+4 Once the first rising edge within a carrier burst is detected, each subsequent rising-edge should occur 16 RX clock cycles later, plus or minus the programmed limits above, transitions out of this range are not detected. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 165 Registers CX23885 Data Sheet 3.19.1.2 Transmit Clock Divider Register Register: IR_TXCLK_REG Address: 0x204 Bits Type Default [31:16] RO 16`b 0 [15:0] RW 16`h FFFF Name Description Reserved TCD Transmit Clock Divider 16-bit value used by the transmit clock down counter as a modulus value to generate the transmit clock for the modulator and TX pulse width timer. Transmit clock counter reloaded any time this register is written. A value of `b00 is not permitted for the TCD. 3.19.1.3 Receive Clock Divider Register Register: IR_RXCLK_REG Bits Type Address: 0x208 Default [31:16] RO 16`b 0 [15:0] RW 16`h FFFF Name Description Reserved RCD Receive Clock Divider 16-bit value used by the receive clock down counter as a modulus value to generate the receive clock for the demodulator and RX pulse width timer. Receive clock counter reloaded any time this register is written. A value of `b00 is not permitted for the RCD. 3.19.1.4 Transmit Carrier Duty Cycle Register Register: IR_CDUTY_REG Bits Type Default [31:4] RO 28`b 0 [3:0] RW 4`b 0 166 Address: 0x20C Name Description Reserved CDC Transmit Carrier Duty Cycle 0000 = 1 TX clock high and 15 TX clocks low 0001 = 2 TX clocks high and 14 TX clocks low 0010 = 3 TX clocks high and 13 TX clocks low... 1101 = 14 TX clocks high and 2 TX clocks low 1110 = 15 TX clocks high and 1 TX clock low 1111 = 16 TX clocks high and 0 TX clocks low Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.19.1.5 Status Register Register: IR_STAT_REG Bits Type Address: 0x210 Default Name Description [31:6] RO 26`b 0 [5:5] RO 1`b 0 TSR Transmit FIFO Service Request 0 = If TIC = 0 in IR_CNTL_REG, transmit FIFO is more than half full. If TIC=1, transmitter is busy. 1 = IF TIC= 0, transmit FIFO is half full or less. If TIC= 1, transmitter is idle. Generate an IRQ request if the TSE mask bit is set in the IR_IRQEN_REG [4:4] RO 1`b 0 RSR Receive FIFO Service Request 0 = If RIC=0 in IR_CNTL_REG, receive FIFO is less than half full. If RIC=1, receive FIFO is empty. 1 = IF RIC = 0, receive FIFO is half full or more. If RIC= 1, receive FIFO is not empty. Generate an IRQ request if the RSE mask bit is set in the IR_IRQEN_REG. [3:3] RO 1`b 0 TBY Transmitter Busy (non-interruptible) 0 = Transmitter is idle 1 = Transmitter is busy [2:2] RO 1`b 0 RBY Receiver Busy (non-interruptible) 0 = Receiver is idle 1 = Receiver is busy [1:1] RO 1`b 0 ROR Receive FIFO Overrun 0 = Receive FIFO contains one or more empty entries or is full but has not experienced an overrun 1 = Receive FIFO has experienced an overrun, generate an IRQ request if the ROE mask bit is set in the IR_IRQEN_REG Note: When an overrun occurs, data within the FIFO remains intact, and any new data from the RX pulse width counter is lost until the FIFO once again contains one or more empty entries. [0:0] RO 1`b 0 RTO Receive Pulse Width Timer Timeout 0 = Receive pulse width counter has not reached its limit 1 = Receive pulse width counter has reached its limit (contains all ones), generate an IRQ request if the RTE mask bit is set in the IR_IRQ. Note: Cleared by disabling RXE (Rx enable) bit of the IR_CNTRL_REG. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 167 Registers CX23885 Data Sheet 3.19.1.6 Interrupt Enable Register Register: IR_IRQEN_REG Bits Type Address: 0x214 Default Name Description [31:6] RO 16`b 0 Reserved [5:5] RW 1`b 1 TSE Transmit FIFO Service Request Interrupt Enable 0 = Transmit FIFO/Idle interrupt disabled 1 = Transmit FIFO/Idle interrupt enabled [4:4] RW 1`b 1 RSE Receive FIFO Service Request Interrupt Enable 0 = Receive FIFO interrupt disabled 1 = Receive FIFO interrupt enabled [3:2] RO 2`b 0 [1:1] RW 1`b 1 ROE Receive FIFO Overrun Interrupt Enable 0 = Receive FIFO overrun interrupt disabled 1 = Receive FIFO overrun interrupt enabled [0:0] RW 1`b 1 RTE Receive Pulse Width Timer Time-out Interrupt Enable 0 = Receive pulse width timer time-out interrupt disabled 1 = Receive pulse width timer time-out interrupt enabled Reserved 3.19.1.7 Low Pass Filter Register Register: IR_FILTR_REG Bits Type [31:16] RO 16`b 0 [15:0] RW 16`b 0 168 Address: 0x218 Default Name Description Reserved LPF Low Pass Filter Modulus 16-bit value used as a modulus value to filter out pulses below a minimum width. Filter counter is reloaded with modulus each time programmed edge is encountered. Counter decrements using the host bus clock, if next edge seen before counter reaches zero, pulse measurement is discarded. If counter reaches zero it retains this value until the next edge is seen. Whenever the counter contains a zero, pulse measurements are saved to the RX FIFO. A value of 0x0000 disables the filter function, and values 0x0001 through 0x0004 are not permitted. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.19.1.8 FIFO Register Register: IR_FIFO_REG Bits Type Address: 0x23C Default Name Description [31:18] RO 14`b 0 [17:17] RO 1`b 0 RXNDV Receive Next Data Valid 0 = No more data in the RX FIFO 1 = One or more entries of valid data remain in RX FIFO [16:16] RW 1`b 0 IR_RXTXLVL Transmit/Receive Pin Level Read: Value of demodulated input at end of RX pulse width measurement Write: Value to send to modulator for TX pulse width count output [15:0] RW 16`b 0 IR_RXTXFIFO Transmit/Receive Pulse Width Count/ Measurement Value Read: Bottom entry of the receive FIFO Write: Top entry of the transmit FIFO DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 169 Registers 3.20 CX23885 Data Sheet Video Decoder Registers 3.20.1 Basic Video Decoder Mode Control Register: MODE_CTRL Address: 0x400 Bits Type [31:30] RO 2`b 0 [29:29] RW 1`b 0 AFD_PAL60_DIS Disable auto-detection of PAL-60 formats. 0 = PAL-60 can be detected and discriminated from NTSC-443 based on phase alternation 1 = Any 525-line 4.43 format is assumed to be NTSC-443. [28:28] RW 1`b 0 AFD_FORCE_SECA M Force SECAM format when 625 lines are detected. 0 = The Auto-detect algorithm proceeds normally. 1 = SECAM format is chosen when a 625-line format is detected. [27:27] RW 1`b 0 AFD_FORCE_PALN C Force PAL-Nc format when 625 lines are detected. 0 = The Auto-detect algorithm proceeds normally. 1 = PAL-Nc is chosen when a 625-line format is detected. [26:26] RW 1`b 0 AFD_FORCE_PAL Force PAL-BG format when 625 lines are detected. 0 = The Auto-detect algorithm proceeds normally. 1 = PAL-BG/PAL-N is chosen when a 625-line format is detected according to the AFD_PAL_SEL bit. [25:24] RW 2`b 0 AFD_PALM_SEL Select PAL-M format when 525-lines and 3.58 carrier is detected. 0 = NTSC will be detected according to the AFD_NTSC_SEL bit. 1 = PAL-M format is chosen when 525 lines and a 3.58 carrier are detected. 2 = Enable algorithm to dynamically discriminate between NTSC-M and PAL-M [23:22] RO 2`b 0 170 Default Name Description Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [21:20] RW 2`b 0 [19:18] RO 2`b 0 [17:17] RO 1`b 0 CLR_LOCK_STAT Clear HLOCK, VLOCK, and CLOCK status bits [16:16] RW 1`b 0 FAST_LOCK_MD Active-high fast lock algorithm select. This register selects between a standard and a fast vertical locking algorithm. This has two effects: 1. The fast locking algorithm (1'b1) will lock onto the first VSYNC that it encounters, regardless of its position. The normal vertical locking algorithm (1'b0) will look for a sync within an expected window. If no sync appears during the next expected window then it will lock onto the first subsequent incoming VSYNC. 2. The FAST_LOCKING ALGORITHM (1'b1) will bypass the 8 field hysteresis that is built into the field detection logic. In this mode as soon as the even/odd field is detected, the field signal will reflect the status. When this is disabled (1'b0) the field detection needs to be stable for 8 consecutive fields before the field signal will reflect the change. [15:15] RW 1`b 1 WCEN White Crush enable [14:14] RW 1`b 1 CAGCEN Chroma AGC enable [13:13] RW 1`b 1 CKILLEN Chroma killer enable [12:12] RW 1`b 1 AUTO_SC_LOCK Auto chroma subcarrier lock speed select. 0 = Manual mode. Lock speed is determined by MAN_SC_FAST_LOCK. 1 = Auto Mode. When unlocked, chose fast lock speed. When locked, choose slow speed. [11:11] RW 1`b 0 DSH-201010p2 2/4/09 CKILL_MODE Color Kill Mode. Defines how luma output is generated when color kill is asserted: 0 = Chroma output is forced to zero, and luma output is generated from normal comb filter operation (default) 1 = Chroma output is forced to zero, entire chroma band is notched from luma output. The comb filter is forced into notch mode 1. (See COMB_NOTCH_MODE field.) 2 = Black and White mode.Chroma output is forced to zero, and entire composite signal is treated as luma. The comb filtered is forced into notch mode 3. (See COMB_NOTCH_MODE field.) Reserved MAN_SC_FAST_LOCK Manual chroma subcarrier lock speed select. When set, chooses fast lock speed. This bit is a don't-care if the AUTO_SC_LOCK bit is set. Conexant Preliminary Information/Conexant Proprietary and Confidential 171 Registers CX23885 Data Sheet [10:9] RW 2`b 0 INPUT_MODE Signal Input Format: 0 - CVBS 1 - Y/C 2 - Y/ half-rate C 3 - Y/U/V [8:8] RW 1`b 0 AFD_ACQUIRE By setting to 1 and then 0, forces the auto format detect state machine to re-evaluate the incoming video format and update AFD_FMT_STAT accordingly. 0 = The auto-detect state machine operates normally. 1 = Auto-detect state machine soft reset. The auto-detect state machine is forced back to the INIT state, and held there until the bit is cleared. [7:7] RW 1`b 0 AFD_NTSC_SEL This bit is used by the Auto Format Detect block to differentiate between NTSC-M and NTSC-J. 0 = NTSC-M 1 = NTSC-J [6:6] RW 1`b 0 AFD_PAL_SEL This bit is used by the Auto Format Detect block to differentiate between PAL-N and PALB,D,G,H,I. 0 = PAL-BDGHI 1 = PAL-N [5:5] RW 1`b 0 ACFG_DIS Disable auto-config of registers addressed 0x70 to 0x7F based on format. [4:4] RW 1`b 0 SQ_PIXEL Square-pixel mode [3:0] RW 4`b 0 VID_FMT_SEL Manual video format select value. This value is used to force the video decoder into a certain video format when it is non-zero. 4'b0000 AUTO-DETECT 4'b0001 NTSC-M 4'b0010 NTSC-J 4'b0011 NTSC-4.43 4'b0100 PAL-BDGHI 4'b0101 PAL-M 4'b0110 PAL-N 4'b0111 PAL-NC 4'b1000 PAL-60 4'b1100 SECAM 4'b1101 SECAM-60 [currently not supported] 172 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.1 Output Control 1 Register: OUT_CTRL1 Bits Type Address: 0x404 Default Name Description [31:31] RO 1`b 0 [30:24] RW 7`b 0 [23:23] RO 1`b 0 [22:21] RW 2`b 0 RND_MODE Rounding style for 8b output 00 - standard rounding 01 - rounding controlled by pseudo random number generator 10 - error diffusion 11 - error diffusion gated with PRNG [20:20] RW 1`b 1 VIPCLAMP_EN Clamp luma and chroma data in VIP modes (i.e., OUT_MODE[1]==1'b1) to 1-254.75. Affects all output bytes except control codes, raw data, and ancillary data fields. [19:19] RW 1`b 0 VIPBLANK_EN Enable substitution of blanking data during horizontal and vertical blanking intervals during VIP modes (i.e., OUT_MODE[1] == 1'b1) [18:18] RW 1`b 0 VIP_OPT_AL VIP optional active line enable. In VIP modes, the transition of the V-bit from 1 to 0 is determined by either the VBLANK register or V656BLANK register. 0 = VBLANK 1 = V656BLANK [17:17] RW 1`b 0 IDID0_SOURCE Source of IDID0 byte in VIP ancillary data; 0 = IDID0 register 1 = Line Count from VBI Slicer [16:16] RW 1`b 0 DCMODE Determines the format of the data count field in ancillary data in 8-bit mode (MODE10B = 1'b0); 0 = Data Count is number of blocks of 4 UDWs (with padding) 1 = Data Count is number UDWs DSH-201010p2 2/4/09 Reserved POLAR When bit is set, invert polarity of output. [0]: VRESET_N [1]: HRESET_N [2]: ACTIVE [3]: FIELD [4]: CBFLAG [5]: VACTIVE [6]: VALID Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 173 Registers CX23885 Data Sheet [15:14] RW 2`b 0 CLK_GATING Select pixel clock gating scheme. 0X = no gating; 10 = gate with valid output; 11 = gate with logical AND of valid and active outputs [13:13] RW 1`b 1 CLK_INVERT When set, the pixel clock output is inverted. [12:12] RW 1`b 0 HSFMT Selects width of HRESET_N. 0 = nominal width; 1 = one pixel clock (VOF_PIXCLK) pulse wide [11:11] RW 1`b 0 VALIDFMT Valid signal format. 0 = valid indicates nonscaled pixels; 1 = valid is logical AND of nominal valid and active, where active is controlled by ACTFMT register. [10:10] RW 1`b 1 ACTFMT Active signal format. 0 = active is composite active; 1 = active is horizontal active [9:9] RW 1`b 0 SWAPRAW Switch the positioning of the raw samples between the luma and chroma data paths. 0 = Even samples on chroma; odd samples on luma; 1 = Odd samples on chroma; even samples on luma [8:8] RW 1`b 1 CLAMPRAW_EN Enable clamping of raw ADC samples to 1254.75 when video output format mode uses control codes [7:7] RW 1`b 0 BLUE_FIELD_EN Enable generation of blue field on output when decoder loses lock. [6:6] RW 1`b 0 BLUE_FIELD_ACT Activate blue field on output regardless of BLUE_FIELD_EN register. [5:5] RW 1`b 1 TASKBIT_VAL Task bit value in VIP 2.0 mode. [4:4] RW 1`b 1 ANC_DATA_EN Enable Ancillary Data Insertion for BT.656 or VIP modes. [3:3] RW 1`b 0 VBIHACTRAW_EN Enables raw data output during the horizontal active region of the vertical blanking interval [2:2] RW 1`b 0 MODE10B Selects either 8-bit or 10-bit output for 4:2:2 Luma and Chroma output. 0 = Luma and Chroma Output are rounded to 8 bits; 1 = Luma and Chroma Output have 10 bits of resolution [1:0] RW 2`b 1 OUT_MODE Sets video output format: 00 = ITU-R BT.601 coded video Synchronous Pixel Interface (SPI); 01 = ITU-R BT.656 control codes 10 = VIP 1.1 control codes 11 = VIP 2.0 control codes 174 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.2 Output Control 2 Register: OUT_CTRL2 Address: 0x408 Bits Type [31:30] RW 2`b 0 [29:28] RW 2`b 0 SAMPLE_RATE [27:27] RW 1`b 0 AUD_ANC_EN This bit enables audio ancillary data insertion.This bit along with the respective enables for the FIFO will enables data insertion.For example, to enable FIFO_A data insertion, AUD_ANC_EN has to be 1'b1 and EN_A has to be 1'b1. [26:26] RW 1`b 0 EN_C This bit enables data insertion from the FIFO_C in the VOF into the output stream. [25:25] RW 1`b 0 EN_B This bit enables data insertion from the FIFO_B in the VOF into the output stream [24:24] RW 1`b 0 EN_A This bit enables data insertion from the FIFO_A in the VOF into the output stream [23:20] RO 4`b 0 [19:18] RW 2`b 0 IDID1_LSB Value for IDID1byte in VIP ancillary data.([1:0] are used for enabling 10-bit mode.) [17:16] RW 2`b 0 IDID0_LSB Value for IDID0 byte in VIP ancillary data.([1:0] are used for enabling 10-bit mode.) [15:8] RW 8`h 80 IDID1_MSB Value for IDID1 byte in VIP ancillary data.([9:2] are used in 8-bit mode.) [7:0] RW 8`b 0 IDID0_MSB Value for IDID0 byte in VIP ancillary data.([9:2] are used in 8-bit mode.) DSH-201010p2 2/4/09 Default Name AUD_GRP Description This field indicates the Audio group that particular data flow belongs to. 2'b00: Audio Group1 2'b01: Audio Group2 2'b10: Audio Group3 2'b11: Audio Group4 This indicates the sampling rate of the audio data available for insertion in the FIFOs. 2'b00: 48 kHz 2'b01: 44.1 kHz 2'b10: 32 kHz 2'b11: Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 175 Registers CX23885 Data Sheet 3.20.1.3 General Status Register: GEN_STAT Address: 0x40C Bits Type [31:24] RO 8`b 0 [23:23] RO 1`b 0 VCR_DETECT VCR detection status [22:22] RO 1`b 0 SPECIAL_PLAY_N Special Play mode. Active-low special play mode (fast forward, rewind, pause or slow motion). This is used to disable certain algorithms when not in a normal play mode. Special play mode is assumed when the detected VSYNC falls outside of a narrow 2 line expected window. [21:21] RO 1`b 0 VPRES Active-high video present. Indication of the presence of a reasonable video signal, one that we can lock onto horizontally or both horizontally & vertically. If VPRES_VERT_EN = 0 then VPRES is dependant upon the location of the last 32 HSYNC pulses relative to their expected location. If VPRES_VERT_EN = 1 then VPRES is dependant upon both the location of the last 16 VSYNC pulses and the last 32 HSYNC pulses relative to their expected locations. [20:20] RO 1`b 0 AGC_LOCK VGA lock status [19:19] RO 1`b 0 CSC_LOCK Color Subcarrier lock status [18:18] RO 1`b 0 VLOCK Vertical lock status [17:17] RO 1`b 0 SRC_LOCK Sample Rate Converter lock Status [16:16] RO 1`b 0 HLOCK Horizontal lock status [15:15] RO 1`b 0 VSYNC_N Vertical sync, active low [14:14] RO 1`b 0 SRC_FIFO_UFLOW Sample Rate Converter FIFO Underflow [13:13] RO 1`b 0 SRC_FIFO_OFLOW Sample Rate Converter FIFO Overflow [12:12] RO 1`b 0 FIELD Field status (even/odd) [11:8] RO 4`b 1 AFD_FMT_STAT Current detected Format [7:7] RO 1`b 0 MV_TYPE2_PAIR Macrovision Type 2 pair detected [6:6] RO 1`b 0 MV_T3CS A 1 indicates the presence of type 3 of the color stripe process. A one here always triggers 1 in the MV_CS bit. 176 Default Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [5:5] RO 1`b 0 MV_CS Macrovision Color Striping Detected [4:4] RO 1`b 0 MV_PSP Macrovision Pseudo Sync Pulses detected [3:2] RO 2`b 0 [1:0] RO 2`b 0 Reserved MV_CDAT Macrovision Copy Control Bits as described in the Macrovision spec. This an encoding of the same information that is contained in MV_CS, MV_T3CS, and MV_PSP. 3.20.1.4 Interrupt Status and Mask Register: INT_STAT_MASK Bits Type [31:31] RO 1`b 1 [30:30] RW 1`b 1 WSS_DAT_AVAIL_M SK When set, WSS_DAT_AVAIL_STAT is masked from generating an interrupt. [29:29] RW 1`b 1 GS2_DAT_AVAIL_MS K When set, GS2_DAT_AVAIL_STAT is masked from generating an interrupt. [28:28] RW 1`b 1 GS1_DAT_AVAIL_MS K When set, GS1_DAT_AVAIL_STAT is masked from generating an interrupt. [27:27] RW 1`b 1 CC_DAT_AVAIL_MS K When set, CC_DAT_AVAIL_STAT is masked from generating an interrupt. [26:26] RW 1`b 1 VPRES_CHANGE_M SK When set, VPRES_CHANGE_STAT is masked from generating an interrupt. [25:25] RW 1`b 1 MV_CHANGE_MSK When set, MV_CHANGE_STAT is masked from generating an interrupt. [24:24] RW 1`b 1 END_VBI_EVEN_MS K When set, END_VBI_EVEN_STAT is masked from generating an interrupt. [23:23] RW 1`b 1 END_VBI_ODD_MSK When set, END_VBI_ODD_STAT is masked from generating an interrupt. [22:22] RW 1`b 1 FMT_CHANGE_MSK When set, FMT_CHANGE_STAT is masked from generating an interrupt. [21:21] RW 1`b 1 VSYNC_TRAIL_MSK When set, VSYNC_TRAIL_STAT is masked from generating an interrupt. [20:20] RW 1`b 1 HLOCK_CHANGE_M SK When set, HLOCK_CHANGE_STAT is masked from generating an interrupt. DSH-201010p2 2/4/09 Default Address: 0x410 Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 177 Registers CX23885 Data Sheet [19:19] RW 1`b 1 VLOCK_CHANGE_M SK [18:18] RW 1`b 1 CSC_LOCK_CHANGE _MSK When set, CSC_LOCK_CHANGE_STAT is masked from generating an interrupt. [17:17] RW 1`b 1 SRC_FIFO_UFLOW_M SK When set, SRC_FIFO_UFLOW_STAT is masked from generating an interrupt. [16:16] RW 1`b 1 SRC_FIFO_OFLOW_M SK When set, SRC_FIFO_OFLOW_STAT is masked from generating an interrupt. [15:15] RO 1`b 0 [14:14] RO 1`b 0 WSS_DAT_AVAIL_S TAT VBI FIFO for Wide-Screen-Signaling has data (not empty) [13:13] RO 1`b 0 GS2_DAT_AVAIL_ST AT VBI FIFO for Gemstar 2X has data (not empty) [12:12] RO 1`b 0 GS1_DAT_AVAIL_ST AT VBI FIFO for Gemstar 1X has data (not empty) [11:11] RO 1`b 0 CC_DAT_AVAIL_STA T VBI FIFO for Closed Caption has data (not empty) [10:10] RO 1`b 0 VPRES_CHANGE_S TAT A change in the VPRES (video present) status bit sets this bit. [9:9] RO 1`b 0 MV_CHANGE_STAT A change in the MV_CDAT field sets this bit. [8:8] RO 1`b 0 END_VBI_EVEN_ST AT The end of the VBI region of an even field sets this bit. [7:7] RO 1`b 0 END_VBI_ODD_STA T The end of the VBI region of an odd field sets this bit. [6:6] RO 1`b 0 FMT_CHANGE_STA T A change in the detected video format sets this bit. [5:5] RO 1`b 0 VSYNC_TRAIL_STAT The falling edge of the detected VSYNC sets this bit. [4:4] RO 1`b 0 HLOCK_CHANGE_S TAT A change in the horizontal lock status sets this bit. [3:3] RO 1`b 0 VLOCK_CHANGE_S TAT A change in the vertical lock status sets this bit. [2:2] RO 1`b 0 CSC_LOCK_CHANGE_ STAT A change in the Color Subcarrier Lock status sets this bit. [1:1] RO 1`b 0 SRC_FIFO_UFLOW_S TAT The detection of a SRC FIFO Underflow sets this bit. [0:0] RO 1`b 0 SRC_FIFO_OFLOW_S TAT The detection of a SRC FIFO Overflow sets this bit. 178 When set, VLOCK_CHANGE_STAT is masked from generating an interrupt. Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.5 Luma Data Path Control Register: LUMA_CTRL Address: 0x414 Bits Type Default Name Description [31:24] RO 8`b 0 [23:22] RW 2`b 0 LUMA_CORE_SEL Luma coring threshold select. This value determines the cutoff threshold for the luma coring logic. 2'b00 = no coring 2'b01 = coring threshold set to +/- 16 2'b10 = coring threshold set to +/- 32 2'b11 = coring threshold set to +/- 64As a result, any pixel value between the selected threshold limits will result in 0. [21:20] RW 2`b 0 RANGE Selects the allowed luma output range. This allows the user to select between three possible output ranges. 2'b00 = range: 64 - 1016 Nominal 656 range with excursions allowed up to 1016. 2'b01 = range: 4 - 1016 Nominal 656 range with excursions allowed up to 1016 and down to 4. 2'b1x = range: 0 - 1023 Full-range. [19:19] RO 1`b 0 [18:18] RW 1`b 0 PEAK_EN Peaking enable [17:16] RW 2`b 0 PEAK_SEL Select for peaking filter response (reg). This value selects from the four available peaking filter responses. Reserved Reserved 2'b00 = +2.0 dB response @ center freq 2'b01 = +3.5 dB response @ center freq 2'b10 = +5.0 dB response @ center freq 2'b11 = +6.0 dB response @ center freq [15:8] RW 8`h 80 CNTRST Contrast multiply value. This value is a 1.7 number that is multiplied by the luma level to produce an adjusted luma signal. The resulting range of the contrast multiplication factor is 0 to 1.996. [7:0] RW 8`b 0 BRITE Brightness offset. This value is effectively an offset that is added to the luma signal to produce a brighter output. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 179 Registers CX23885 Data Sheet 3.20.1.6 Horizontal Scaling Control Register: HSCALE_CTRL Bits Type Address: 0x418 Default Name Description [31:26] RO 6`b 0 Reserved [25:24] RW 2`b 0 HFILT Low pass filter select. This is used in the LUMA_LPF block to determine which of the three filters or the auto mode should be used. 2'b00 Auto Mode 2'b01 CIF 2'b10 QCIF 2'b11 ICON [23:0] RW 24`b 0 HSCALE Horizontal Scaling Ratio (HSCALE = (scaling ratio-1)*220). 3.20.1.7 Vertical Scaling Control Register: VSCALE_CTRL Bits Type Address: 0x41C Default [31:25] RO 6`b 0 [24:24] RW 1`b 0 Name Description Reserved LINE_AVG_DIS PAL line average disable. 0 = PAL line averaging is enabled. Adjacent lines are averaged together to produce output lines. (default) 1 = PAL line averaging is disabled. [23:20] RO 4`b 0 [19:19] RW 1`b 1 180 Reserved VS_INTRLACE VS Interlace Format. The initial output phase must alternate if the scaled images are to be interlaced. 0 = Non-interlace VS 1 = Interlace VS Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [18:16] RW 3`b 0 [15:13] RO 3`b 0 [12:0] RW 13`b 0 VFILT These bits control the number of taps in the Vertical Scaling Filter. The number of taps must be chosen in conjunction with the horizontal scale factor to ensure the needed data does not overflow the internal FIFO. vfilt[1:0] Interpolation 00 = 2-tap interpolation.(*) 01 = 3-tap interpolation.(**) 10 = 4-tap interpolation.(***) 11 = 5-tap interpolation.(***) vfilt[2] - Reserved (*) Available at all resolutions (**) Available if scaling to less than 385 horizontal active pixels (***) Available if scaling to less than 193 horizontal active pixels Reserved Vertical Scaling Ratio (VSF = 216 - (scaling ratio - 1)*29) VSCALE 3.20.1.8 Chroma Data Path Control Register: CHROMA_CTRL Bits Type Address: 0x420 Default Name Description [31:30] RO 2`b 0 [29:29] RW 1`b 1 C_LPF_EN Enables chroma low pass filter in chroma processing block [28:26] RW 3`b 0 CHR_DELAY Chroma Delay. A signed number representing the number of pixels the chroma is delayed relative to the luma. A value of 0 matches the luma to chroma. Valid values are: 110 = -2 111 = -1 000 = 0 001 = +1 010 = +2 others = 0 [25:24] RW 2`b 0 C_CORE_SEL Chroma coring select. 00 = no coring 01 = +/- 7 10 = +/- 15 11 = +/- 31 [23:16] RW 8`b 0 HUE Hue adjust. [15:8] RW 8`h 80 VSAT Saturation adjust for V chroma. [7:0] RW 8`h 80 USAT Saturation adjust for U chroma. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 181 Registers CX23885 Data Sheet 3.20.1.9 VBI Line Data Type Control 1 Register: VBI_LINE_CTRL1 Bits Type [31:24] RW 8`b 0 VBI_MD_LINE4 4th VBI line data type [23:16] RW 8`b 0 VBI_MD_LINE3 3rd VBI line data type [15:8] RW 8`b 0 VBI_MD_LINE2 2nd VBI line data type [7:0] RW 8`b 0 VBI_MD_LINE1 1st VBI line data type Lines are numbered relative to first line after VSYNC, which is line 10 for 525-line standards and line 6 for 625-line standards. The VBI_VOFFSET field is added to these lines to determine the 1st VBI line. (VBI_VOFFSET is by default 0 for 525-line standards, and 1 for 625line standards.)The mode consists of 4 bits as listed below. The most significant nibble is used for the odd field and the least significant nibble is used for the even field. 525 line modes: 0000 = no VBI data slicing 0001 = WST525-B 0010 = WST525-C (NABTS) 0011 = WST525-D (Moji) 0100 = WSS525 0101 = VITC525 0110 = CC525 0111 = Gemstar 1x 1000 = Gemstar 2x 1010 = Custom VBI1 1011 = Custom VBI2 1100 = Custom VBI3 625 line modes: 0000 = no VBI data slicing 0001 = WST625-B 0010 = WST625-A 0011 = RESERVED 0100 = WSS625 0101 = VITC625 0110 = CC625 1000 = RESERVED 1001 = VPS 1010 = Custom VBI1 1011 = Custom VBI2 1100 = Custom VBI3 182 Default Address: 0x424 Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.10VBI Line Data Type Control 2 Register: VBI_LINE_CTRL2 Default Address: 0x428 Bits Type Name Description [31:24] RW 8`b 0 VBI_MD_LINE8 8th VBI line data type [23:16] RW 8`b 0 VBI_MD_LINE7 7th VBI line data type [15:8] RW 8`b 0 VBI_MD_LINE6 6th VBI line data type [7:0] RW 8`b 0 VBI_MD_LINE5 5th VBI line data type 3.20.1.11VBI Line Data Type Control 3 Register: VBI_LINE_CTRL3 Default Address: 0x42C Bits Type Name Description [31:24] RW 8`b 0 VBI_MD_LINE12 12th VBI line data type [23:16] RW 8`b 0 VBI_MD_LINE11 11th VBI line data type [15:8] RW 8`b 0 VBI_MD_LINE10 10th VBI line data type [7:0] RW 8`b 0 VBI_MD_LINE9 9th VBI line data type 3.20.1.12VBI Line Data Type Control 4 Register: VBI_LINE_CTRL4 Bits Type [31:24] RW 8`b 0 VBI_MD_LINE16 16th VBI line data type [23:16] RW 8`b 0 VBI_MD_LINE15 15th VBI line data type [15:8] RW 8`b 0 VBI_MD_LINE14 14th VBI line data type [7:0] RW 8`b 0 VBI_MD_LINE13 13th VBI line data type DSH-201010p2 2/4/09 Default Address: 0x430 Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential 183 Registers CX23885 Data Sheet 3.20.1.13VBI Line Data Type Control 5 Register: VBI_LINE_CTRL5 Bits Type Default [31:8] RO 24`b 0 [7:0] RW 8`b 0 Address: 0x434 Name Description Reserved VBI_MD_LINE17 17th VBI line data type 3.20.1.14VBI Frame Code Config Register: VBI_FC_CFG Address: 0x438 Bits Type [31:24] RW 8`b 0 FC_ALT2 Alternate frame code used when VBIMODE matches FC_ALT2_TYPE. [23:16] RW 8`b 0 FC_ALT1 Alternate frame code used when VBIMODE matches FC_ALT1_TYPE. [15:12] RW 4`b 0 FC_ALT2_TYPE When this field matches the VBIMODE setting for a particular line, the FC_ALT2 frame code is used instead of the default frame code associated with a given auto-config mode. This allows using an alternate frame code for any given auto-config mode. [11:8] RW 4`b 0 FC_ALT1_TYPE When this field matches the VBIMODE setting for a particular line, the FC_ALT1 frame code is used instead of the default frame code associated with a given auto-config mode. This allows using an alternate frame code for any given auto-config mode. [7:1] RO 7`b 0 [0:0] RW 1`b 0 184 Default Name Description Reserved FC_SEARCH_MODE Frame Code Search Mode. Allows dynamic search for frame code: 0 = Frame code match is declared only if frame code (start code, data run-in) is found at expected bit position. 1 = Frame code match is declared upon discovering the first bit sequence that matches the expected pattern.The second option (FC_SEARCH_MODE = 1) only works for common frame code lengths of 3, 8, 12, 16, and 24. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.15VBI Miscellaneous Config1 Register: VBI_MISC_CFG1 Bits Type [31:20] RW 12`h FFF TTX_PKTADRU Teletext packet address upper limit for packet filtering purposes, enabled when VBIx_TTX_MODE = 1. [19:8] RW 12`b 0 TTX_PKTADRL Teletext packet address lower limit for packet filtering purposes, enabled when VBIx_TTX_MODE = 1. [7:6] RO 2`b 0 [5:5] RW 1`b 0 MOJI_PACK_DIS Moji Packing Disable. 0 = WST525, System D formats cause the decoder to extract the first 6 bits for the first byte packet. The subsequent bit stream is packed into standard byte packets. 1 = The WST525, System D bit stream is packed into byte packets in a normal fashion. [4:4] RW 1`b 0 VPS_DEC_DIS VPS bi-phase decode disable. 0 = VPS formats are decoded based on a twobit bi-phase pattern 1 = Raw slice bits are transmitted. [3:2] RW 2`b 1 [31:20] RW 12`h FFF [1:1] RW 1`b 1 EDGE_RESYNC_EN Enable dynamic timing resynchronization based on edge detection. 0 = Sample point timing is determined by initial edge synchronization during clock run-in 1 = Sample point timing is re-synchronized upon detecting any edge during data pattern. [0:0] RW 1`b 0 ADAPT_SLICE_DIS Disable adaptive slice level. 0 = Slice level comes from averaging points in clock run-in 1 = Slice level is set to pre-determined level based on mode. DSH-201010p2 2/4/09 Default Address: 0x43C Name Description Reserved CRI_MARG_SCALE TTX_PKTADRU Clock run-in margin scale. Used to loosen or tighten lock criteria for clock run-in. 0 = Divide default timing margin by 2. 1 = Use default timing margin. 2 = Multiply default timing margin by 2. 3 = Multiply default timing margin by 4. Teletext packet address upper limit for packet filtering purposes, enabled when VBIx_TTX_MODE = 1. Conexant Preliminary Information/Conexant Proprietary and Confidential 185 Registers CX23885 Data Sheet 3.20.1.16VBI Miscellaneous Config2 Register: VBI_MISC_CFG2 Bits Type [31:28] RO 4`b 0 [27:24] RW `b0 [23:20] RO 4`b 0 [19:19] RW 1b 0 WSS_FIFO_RST When = 1, reset WSS payload FIFO. [18:18] RW 1`b 0 GS2_FIFO_RST When = 1, reset Gemstar2x payload FIFO. [17:17] RW 1`b 0 GS1_FIFO_RST When = 1, reset Gemstar1x payload FIFO. [16:16] RW 1`b 0 CC_FIFO_RST When = 1, reset Closed Caption/XDS payload FIFO. [15:12] RO 4`b 0 [11:8] RW 4`h C VBI3_SDID SDID to use when VBI_CUST3 data type is selected. [7:4] RW 4`h B VBI2_SDID SDID to use when VBI_CUST3 data type is selected. [3:0] RW 4`h A VBI1_SDID SDID to use when VBI_CUST1 data type is selected. 186 Default Address: 0x440 Name Description Reserved HAMMING_TYPE When this field matches the VBIMODE setting for a particular line, hamming comparison is enabled for that type. Leave this field at 4'h0 to disable the feature. When enabled, the leastsignificant four bits of the framing code are used for hamming comparison. Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.17VBI Payload 1 Register: VBI_PAY1 Bits Type Address: 0x444 Default Name Description [31:24] RO 8`b0 GS1_FIFO_DAT Gemstar1x payload data.Data pointer advanced after reading this byte. [23:16] RO 8`b0 GS1_STAT See description of CC_STAT byte, [15:8] RO 8`b0 CC_FIFO_DAT CC/XDS payload data.Data pointer advanced after reading this byte. [7:0] RO 8`b0 CC_STAT Generic payload status format: Bit 7 - PARERR 0 - No parity error detected 1 - Parity error detected Bit 6 - FF 0 - FIFO not full 1 - FIFO full Bit 5 - DA 0 - FIFO is empty 1 - One or more bytes available for read Bit 4 - CC/XDS 0 - CC byte (odd field) 1 - XDS byte (even field) Bits 3-2 - RESERVED Bits 1-0 - BYTE_NUM BYTE_NUM describes byte number within a field. For payloads larger than four, the number will wrap. 00 - byte 1 01 - byte 2 02 - byte 3 03 - byte 4 3.20.1.18VBI Payload 2 Register: VBI_PAY2 Bits Type Address: 0x448 Default Name Description [31:24] RO 8`b0 WSS_FIFO_DAT Wide Screen Signalling payload data.Data pointer advanced after reading this byte. [23:16] RO 8`b0 WSS_STAT See description of CC_STAT byte. (PARERR will be held at 0.) [15:8] RO 8`b0 GS2_FIFO_DAT Gemstar2x payload data.Data pointer advanced after reading this byte. [7:0] RO 8`b0 GS2_STAT See description of CC_STAT byte. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 187 Registers CX23885 Data Sheet 3.20.1.19VBI Custom Mode 1, Config1 Register: VBI_CUST1_CFG1 Default Address: 0x44C Bits Type Name Description [31:31] RO 1`b0 [30:24] RW 7`h2c VBI1_CRIWIN Specifies the time window during which edge detection (positive and negative) is inhibited. This window is based on the clock run-in frequency. Avoids spurious edges from being detected.VBI1_CRIWIN = 4 * PIXEL_RATE * CLOCK_RUNIN_HALF_PERIOD * war; war = window ratio, portion of cycle to inhibit detection; [23:20] RW 4`b1 VBI1_SLICE_DIST Slice level sample distance. Controls how often samples are taken for the adaptive slice level routine. Distance is defined in terms of 1/8 of a bit period time, where the bit period is defined by bit INC. The parameter describes the number of points where samples are NOT taken. Therefore, to take one sample every four points, put three in this field. [19:8] RW 12`h99 VBI1_BITINC Value used to increment 14-bit counter measures the bit sample rate. A bit is sampled when the 14-bit counter rolls over. The bit sample rate defines the rate at which the waveform is sampled during the payload. For biphase encoding modes, this sampling rate should be set to six times the effective bit rate. VBI1_BITINC = 214 / ((4 * PIXEL_RATE) / bit SAMPLE_RATE) [7:0] RW 8`h70 VBI1_HDELAY Delay from internal HRESET signal to start of Clock Run-in in number of pixel clock cycles.VBI1_HDELAY = (HDELAY (us)* PIXEL_RATE (MHz)) - 13. Reserved 3.20.1.20VBI Custom Mode 1, Config2 Register: VBI_CUST1_CFG2 Bits Type Default Address: 0x450 Name Description [31:29] RO 3`b0 [28:24] RW 5`h3 VBI1_FC_LENGTH Number of start bits (or frame code bits) [23:0] RW 24`b1 VBI1_FRAME_CODE Start code bit pattern in transmission order 188 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.21VBI Custom Mode 1, Config3 Register: VBI_CUST1_CFG3 Bits Type [31:31] RW 1`b0 VBI1_HAM_EN Enable hamming comparison for framing comparison when this bit is set. When set, VBI1_FRAME_CODE[3:0] are used for hamming comparison. [30:28] RW 3`h2 VBI1_FIFO_MODE Determines which payload FIFO is loaded. 000 = Don't load to payload FIFO 001 = Load to Gemstar 1x FIFO 010 = Load to CC FIFO011 = Load to WSS FIFO 100 = Load to Gemstar 2x FIFO DSH-201010p2 2/4/09 Default Address: 0x454 Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential 189 Registers [27:24] CX23885 Data Sheet RW 4`h6 VBI1_FORMAT_TYP E Specifies basic VBI decoding model. Find the standard format which most closely matches the intended format, and program this field to match the type field encoding specified in the VBI_MD_LINEX registers. Special operating modes are enabled based on the format type as described below: Format type # of lines Feature 0000 n.a. No special features currently defined 0101, 1010, 0011 n.a. Teletext - enable packet address filter 0011 525 Enable Moji style byte alignment - first six bits go into separate byte packet 0100 525 Wide-screen-signaling - assume signal includes single sync pulse, and no frame code. 0100 625 Wide-screen-signaling - implement WSS625style bi-phase decoding 0101 n.a VITC - assume sync pulses every 8 bits 0110, 0111, 1000 n.a. Closed caption - assume 50 IRE signal amplitude 1001 n.a. VPS - implement VPS-style bi-phase decoding [23:16] 190 RW 8`h8 VBI1_PAYLD_LENGT H Number of data bits to be captured, divided by two. If N is the number of bits in the payload, program this register with N/2. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [15:12] RW 4`hC VBI1_CRI_LENGTH Number of clock run-in edges expected in the CRI period. This does not include the edge that transitions into the frame or start code, and this is an N-1 parameter. For example, in a teletext waveform with 16 bit periods and 16 edges, program 4'hF in this register. For closed caption with 6.5 bit periods, but 13 edges, program 4'hC.This number is both used to specify the point at which to begin looking for the frame code, and to measure the elapsed time to determine frequency lock. (See VBI1_CRI_TIME and VBI1_CRI_MARGIN.) [11:8] RW 4`h4 VBI1_CRI_MARGIN This field specifies the margin around vbi1_cri_time in which the measured time of the Clock Run-in period can fall. See vbi1_cri_time. This is in units of eights of the bit period defined by vbi1_bitinc. [7:0] RW 8`hD VBI1_CRI_TIME Expected time period of Clock Run-in period in terms of halves of the bit period specified in vbi1_bitinc. The algorithm detects the number of edges specified in vbi1_cri_length and compares the elapsed time with this parameter. If the result is within vbi1_cri_margin of this parameter, then the waveform is decoded. 3.20.1.22VBI Custom Mode 2, Config1 Register: VBI_CUST2_CFG1 Bits Type Default Address: 0x458 Name Description [31:31] RO 1`b0 [30:24] RW 7`h54 VBI2_CRIWIN See descriptions for VBI_CUST1_CFG equivalent. [23:20] RW 4`b0 VBI2_SLICE_DIST See descriptions for VBI_CUST1_CFG equivalent. [19:8] RW 12`h88 VBI2_BITINC See descriptions for VBI_CUST1_CFG equivalent. [7:0] RW 8`h77 VBI2_HDELAY See descriptions for VBI_CUST1_CFG equivalent. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 191 Registers CX23885 Data Sheet 3.20.1.23VBI Custom Mode 2, Config2 Register: VBI_CUST2_CFG2 Bits Type Default Address: 0x45C Name Description [31:29] RO 3`b0 Reserved [28:24] RW 5`b0 VBI2_FC_LENGTH See descriptions for VBI_CUST1_CFG equivalent. [23:0] RW 24`b0 VBI2_FRAME_CODE See descriptions for VBI_CUST1_CFG equivalent. 3.20.1.24VBI Custom Mode 2, Config3 Register: VBI_CUST2_CFG3 Bits Type [31:31] RW 1`b0 VBI2_HAM_EN See descriptions for VBI_CUST1_CFG equivalent. [30:28] RW 3`h3 VBI2_FIFO_MODE See descriptions for VBI_CUST1_CFG equivalent. [27:24] RW 4`h4 VBI2_FORMAT_TYP E See descriptions for VBI_CUST1_CFG equivalent. [23:16] RW 8`hA VBI2_PAYLD_LENGT H See descriptions for VBI_CUST1_CFG equivalent. [15:12] RW 4`h1 VBI2_CRI_LENGTH See descriptions for VBI_CUST1_CFG equivalent. [11:8] RW 4`h4 VBI2_CRI_MARGIN See descriptions for VBI_CUST1_CFG equivalent. [7:0] RW 8`h2 VBI2_CRI_TIME See descriptions for VBI_CUST1_CFG equivalent. 192 Default Address: 0x460 Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.25VBI Custom Mode 3, Config1 Register: VBI_CUST3_CFG1 Bits Type Default Address: 0x464 Name Description [31:31] RO 1`b0 Reserved [30:24] RW 7hb6 VBI3_CRIWIN See descriptions for VBI_CUST1_CFG equivalent. [23:20] RW 4`h3 VBI3_SLICE_DIST See descriptions for VBI_CUST1_CFG equivalent. [19:8] RW 12`h6CA VBI3_BITINC See descriptions for VBI_CUST1_CFG equivalent. [7:0] RW 8`h6E VBI3_HDELAY See descriptions for VBI_CUST1_CFG equivalent. 3.20.1.26VBI Custom Mode 3, Config2 Register: VBI_CUST3_CFG2 Bits Type Default Address: 0x468 Name Description [31:29] RO 3`b0 [28:24] RW 5`h8 VBI3_FC_LENGTH See descriptions for VBI_CUST1_CFG equivalent. [23:0] RW 24`hE7 VBI3_FRAME_CODE See descriptions for VBI_CUST1_CFG equivalent. DSH-201010p2 2/4/09 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 193 Registers CX23885 Data Sheet 3.20.1.27VBI Custom Mode 3, Config3 Register: VBI_CUST3_CFG3 Default Address: 0x46C Bits Type Name Description [31:31] RW 1`b0 VBI3_HAM_EN See descriptions for VBI_CUST1_CFG equivalent. [30:28] RW 3`b0 VBI3_FIFO_MODE See descriptions for VBI_CUST1_CFG equivalent. [27:24] RW 4`h2 VBI3_FORMAT_TYP E See descriptions for VBI_CUST1_CFG equivalent. [23:16] RW 8`h84 VBI3_PAYLD_LENGT H See descriptions for VBI_CUST1_CFG equivalent. [15:12] RW 4hbF VBI3_CRI_LENGTH See descriptions for VBI_CUST1_CFG equivalent. [11:8] RW 4`h6 VBI3_CRI_MARGIN See descriptions for VBI_CUST1_CFG equivalent. [7:0] RW 8`h20 VBI3_CRI_TIME See descriptions for VBI_CUST1_CFG equivalent. 3.20.1.28Horizontal Timing Control Register: HORIZ_TIM_CTRL Bits Type [31:24] RW 8`h5B [23:22] RO 2`b0 [21:12] RW 10`h2D0 [11:10] RO 2`b0 [9:0] RW 10`h7A 194 Default Address: 0x470 Name BGDEL_CNT Description Burst gate delay. The last four clocks of this period are used to generate the window during which the color burst is sampled. It is the delay, in pixel clocks, between the leading edge of HSYNC and the center of the color burst, plus two. The additional two clocks will center the four-clock burst accumulate window in the center of the burst. Reserved HACTIVE_CNT Horizontal active region duration. It is the number of pixels in the active region of the line. Reserved HBLANK_CNT Horizontal blanking delay. It is number of pixels between the leading edge of HSYNC and the start of active video Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.29Vertical Timing Control Register: VERT_TIM_CTRL Bits Type Default [31:24] RW 8`h18 [23:22] RO 2`b0 [21:12] RW 10`h1E7 [11:10] RO 2`b0 [9:0] RW 10h`14 Address: 0x474 Name V656BLANK_CNT Description Vertical blanking for 656 output. Determines the timing of the internal v656blank signal. It allows us to control the v-bit transition in the 656 output independently of the VBLANK signal seen by the rest of the chip. The counter starts 12 halflines before the expected trailing edge of VRESET. Thus it must = VBLANK_CNT + `b04 to have VBANK and v656blank line up. Reserved VACTIVE_CNT Vertical active region duration. It is the number of half lines in the vertical active region. This register is only valid when the reg override bit is set. Reserved VBLANK_CNT Vertical blanking interval. Determines the start of the internal VBLANK signal. It is the number of half lines between the trailing edge of VRESET and the start of active video. 3.20.1.30Sample Rate Convert and Comb Filter Register: SRC_COMB_CFG Bits Type [31:31] RO 1`b1 [30:30] RW 1`b1 CCOMB_3LN_EN Enables the adaptation algorithm to choose the 3 line chroma comb. [29:29] RW 1`b1 CCOMB_2LN_EN Enables the adaptation algorithm to choose the 2-line chroma comb. [28:27] RW 2`b0 [26:26] RW 1`b1 LCOMB_3LN_EN Enables the adaptation algorithm to choose the 3 line luma comb. [25:25] RW 1`b1 LCOMB_2LN_EN Enables the adaptation algorithm to choose the 2-line luma comb. [24:24] RW 1`b0 DSH-201010p2 2/4/09 Default Address: 0x478 Name Description Reserved Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 195 Registers CX23885 Data Sheet [23:22] RW 2`b1 LUMA_LPF_SEL Selects Luma low-pass filter bandwidth:0 low (~600 kHz),1 medium (~1 MHz)2 high (~1.5MHz)3 reserved [21:20] RW 2`b1 UV_LPF_SEL Selects U/V low-pass filter bandwidth:0 low (~600 kHz),1 medium (~1 MHz)2 high (~1.5MHz)3 reserved [19:10] RW 10`h8 [9:0] RW 10`h21F 196 Reserved SRC_DECIM_RATIO Default phase increment (N = 256 * Fin/Fpix).Fin = ADC sampling frequency. Fpix = pixel rate (should be consistent with SQUARE_PIXEL setting.) Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.31Chroma Config and VBI Offset Register: CHROMA_VBIOFF_CFG Bits Type Address: 0x47C Default [31:29] RO 3`b0 [28:24] RW 5`b0 [23:20] RO 4`b0 [19:0] RW 20`h87C1F Name Description Reserved VBI_VOFFSET The offset in lines from VRESET to enable the VBI Slicer to capture data. Reserved SC_STEP Chroma subcarrier DTO step size, Fsc/Fpix* 221 where Fsc = subcarrier frequency, and Fpix = pixel rate. However, the pixel rate used in this calculation should be based on the exact pixel rate that is defined in the SRC_DECIM_RATIO field of the SRC_COMB_CFG register above: (Fpix = 256/SRC_DECIM_RATIO * Fin). [Note: this does not imply that the effective pixel rate is only as accurate as this equation. This equation just determines the initial pixel rate, which will then be fine-tuned to achieve the exact ratio. However, the initial subcarrier frequency must be based on the initial pixel rate.] 3.20.1.32Field Counter Register: FIELD_COUNT Bits Type Default [31:10] RO 22`b0 [9:0] RO 10`b0 DSH-201010p2 2/4/09 Address: 0x480 Name Description Reserved FIELD_COUNT Counts fields continuously, and wraps around when it reaches the max count of `b3FF. It is reset to zero by writing to either byte. Conexant Preliminary Information/Conexant Proprietary and Confidential 197 Registers CX23885 Data Sheet 3.20.1.33Miscellaneous Timing Control Register: MISC_TIM_CTRL Bits Type [31:30] RW [29:28] Address: 0x484 Name Description 2`b1 DEBOUNCE_COUNT Number of consecutive fields of detected video format stability required before switching video formats. This period is provided to help prevent us from erroneously switching detected formats due to noise or other very short term errors. 2'b00: 2 consecutive fields of stability 2'b01: 4 consecutive fields of stability 2'b10: 8 consecutive fields of stability 2'b11: 16 consecutive fields of stability RW 2`b0 VT_LINE_CNT_HYS T Number of consecutive fields with approximately 525/2 or 625/2 lines before changing the detected line count, VT_LINE_CNT, input to the auto format detect state machine. 2'b00: 2 consecutive fields with approximately 525/2 or 625/2 lines 2'b01: 4 consecutive fields with approximately 525/2 or 625/2 lines 2'b10: 8 consecutive fields with approximately 525/2 or 625/2 lines 2'b11: 16 consecutive fields with approximately 525/2 or 625/2 lines [27:16] RO 12`b0 [15:15] RW 1`b0 [14:12] RO `b0 [11:11] RW 1`b0 HR32 This bit controls the width of the HRESET output.A logic 1 indicates a 32 clock wide HRESET while a logic 0 indicates that HRESET is 64 clocks wide. [10:10] RW 1`b0 TDALGN Aligns start of decimation with even or odd field. 0 - start on odd field 1 - start on even field [9:9] RW 1`b0 TDFIELD This signal is an indication of whether the temporal decimation is done on a frame (0) or field (1) basis. [8:6] RO 3`b0 [5:0] RW 6`b0 198 Default Reserved VPRES_VERT_EN Enable for the vertical portion of the video present logic. When enabled, the VPRES logic reflects when the video is both locked vertically and horizontally. Otherwise the VPRES reflects the horizontal locking only. Reserved Reserved TEMPDEC This signal is the control for the temporal decimation logic. This value is the number of fields or frames to discard out of 50 (625/50) or 60 (525/60). This value should not exceed 60 for a 60 Hz system or 50 for a 50 Hz system. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.34DFE Control 1 Register: DFE_CTRL1 Address: 0x488 Bits Type Default Name Description [31:31] RW 1`b1 CLAMP_AUTO_EN Analog clamp setting is tied to VGA gain [30:30] RW 1`b1 AGC_AUTO_EN AGC enable 0 = freeze/manual 1 = auto mode [29:29] RW 1`b1 VGA_CRUSH_EN ADC overflow protection enable (decreases VGA_SYNC if ADC overflows) [28:28] RW 1`b1 VGA_AUTO_EN VGA enable (0 = freeze/manual, 1 = auto mode) [27:27] RW 1`b1 VBI_GATE_EN Enable gating of back porch updates during vertical blanking interval [26:24] RW 3`b0 CLAMP_LEVEL Analog clamp setting (if CLAMP_AUTO_EN = 0) [23:20] RO 4'h 2 [19:8] RW 12`h100 [7:6] RO 2`b0 [5:0] RW 6`h20 Reserved AGC_GAIN R/W register for AGC digital gain (can be written when AGC_AUTO_EN = 0) Reserved VGA_GAIN R/W register for VGA gain (can be written when VGA_AUTO_EN = 0) 3.20.1.35DFE Control 2 Register: DFE_CTRL2 Address: 0x48C Bits Type [31:24] RO 8`b0 [23:16] RW 8`h10 VGA_ACQUIRE_RA NGE Maximum error of sync height before declaring VGA lock [15:8] RW 8`h40 VGA_TRACK_RANG E Minimum error of sync height before losing VGA lock [7:0] RW 8`hDC VGA_SYNC Sync pulse height out of ADC (VGA_SYNC = 2N) DSH-201010p2 2/4/09 Default Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 199 Registers CX23885 Data Sheet 3.20.1.36DFE Control 3 Register: DFE_CTRL3 Address: 0x490 Bits Type Default Name Description [31:24] RW 8`hCD BP_PERCENT Percent of line expected to be above or equal to backporch threshold. Used in sync slicing algorithm for initial sync location. [23:16] RW 8`h3F DFT_THRESHOLD Correlator threshold for SC detect (threshold = 256 * setting) [15:12] RO 4`b0 [11:10] RW 2`b0 SYNC_WIDTH_SEL Selects minimum sync width used to qualify sync detection 2'b00 - 40 sample clocks 2'b01 - 32 sample clocks 2'b1X - Minimum sync width controlled by VCR detect status. When a VCR is detected, minimum sync width is 32, otherwise 40 [9:8] RW 2`b2 BP_LOOP_GAIN Backporch level detect control loop gain = 2^n / 4 [7:6] RW 2`b2 SYNC_LOOP_GAIN Sync level detect control loop gain = 2^n / 4 [5:4] RO 2`b0 [3:2] RW 2`b2 AGC_LOOP_GAIN AGC control loop gain = 2^n / 1024 [1:0] RW 2`b2 DCC_LOOP_GAIN Backporch clamp control loop gain = 2^n / 4 Reserved Reserved 3.20.1.37PLL Loop Filter Control Register: PLL_CTRL Address: 0x494 Bits Type [31:24] RW 8`h 16 PLL_KD PLL control loop direct gain = 1/2n [23:16] RW 8`h 1F PLL_KI PLL control loop indirect gain = 1/2(n+11) [15:0] RW 16`h 300 PLL_MAX_OFFSET Video PLL maximum adjustment offset =29 * PLL_MAX_OFFSET 200 Default Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.38Horizontal Timing Loop Control Register: HTL_CTRL Address: 0x498 Bits Type Default Name Description [31:20] RO 12`b 0 [19:19] RW 1`b 0 AUTO_LOCK_SPD Enables automatic loop filter speed control. [18:18] RW 1`b 0 MAN_FAST_LOCK Enables fast loop speed if AUTO_LOCK_SPD is not set. [17:17] RW 1`b 0 HTL_15K_EN Enables the 15 kHz digital PLL line locking algorithm. [16:16] RW 1`b 0 HTL_500K_EN Enables the 500 kHz LPF data to be used for locking (CVBS only). [15:8] RW 8`h 20 HTL_KD Horizontal Tracking Loop direct gain = 1/2n [7:0] RW 8`h 40 HTL_KI Horizontal Tracking Loop indirect gain = 1/2n Reserved Register: COMB_CTRL Address: 0x49C Bits Type [31:24] RW 8`h20 COMB_PHASE_ LIMIT Comb filter is enabled when the burst phase difference between adjacent lines is measured to be less than this limit. The phase difference is measured by taking the burst phase of the current line and subtracting it from the phase of a vertically aligned burst sample points in the previous lines, allowing for the expected phase shift. Lack of alignment shows that there is too much horizontal jitter to enable comb filter. [23:16] RW 8`h50 CCOMB_ERR_LIMIT Maximum comb error before falling back to notch filter mode. [15:8] RW 8`b0 LUMA_THRESHOLD Minimum chroma amplitude before using luma comb filter. [7:0] RW 8`h14 LCOMB_ERR_LIMIT Maximum comb error before falling back to complimentary filter mode. DSH-201010p2 2/4/09 Default Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential 201 Registers CX23885 Data Sheet 3.20.1.39White Crush Control Register: CRUSH_CTRL Address: 0x4A0 Bits Type [31:23] RO 9`b0 [22:22] RW 1`b0 WTW_EN Active-high enable for the white crush whiterthan-white peak threshold.1'b0 = 100 IRE peak threshold1'b1 = 110 IRE peak threshold [21:21] RW 1`b0 CRUSH_FREQ White Crush Adjust frequency. This bit is used to determine whether to perform the white crush adjustments on a field or frame basis(0=field rate, 1=frame rate) [20:20] RW 1`b0 MAJ_SEL_EN Enables adaptive majority select logic [19:18] RW 2`h3 MAJ_SEL White crush majority comparison point select bits. This value is the intensity threshold that the white crush logic compares each pixel to in order to determine if the majority of the image is too dark.2'h0 3/4 maximum luma2'h1 1/2 maximum luma2'h2 1/4 maximum luma2'h3 Automatic [17:15] RO 3`b0 [14:9] RW 6`b1 [8:6] RO 3`b0 [5:0] RW 6`hF 202 Default Name Description Reserved Reserved SYNC_TIP_REDUCE White crush decrement value. This value is the step amount that the sync height can be decreased by the white crush logic on any single adjustment. Reserved SYNC_TIP_INC Sync tip increment value. This value is the step amount that the sync height can be increased by the white crush logic on any single adjustment. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.40Soft Reset Control Register: SOFT_RST_CTRL Default Address: 0x4A4 Bits Type Name Description [31:16] RO 16`b0 [15:15] RW 1`b0 VD_SOFT_RST Video Decoder Soft Reset.Resets video decoder core, pending mask bits for each module. [14:12] RO 3`b0 REG_SOFT_RST Masks soft reset for Register module. [11:11] RW 1`b0 REG_RST_MSK Masks soft reset for Video Output Formatter module. [10:10] RW 1`b0 VOF_RST_MSK Masks soft reset for Macrovision Detect module. [9:9] RW 1`b0 MVDET_RST_MSK Masks soft reset for VBI Slicer module. [8:8] RW 1`b0 VBI_RST_MSK Masks soft reset for Scaling module. [7:7] RW 1`b0 SCALE_RST_MSK Masks soft reset for Chroma Data Path module. [6:6] RW 1`b0 CHROMA_RST_MSK Masks soft reset for Register module. [5:5] RW 1`b0 LUMA_RST_MSK Masks soft reset for Luma Data Path module. [4:4] RW 1`b0 VTG_RST_MSK Masks soft reset for Video Timing Generator module. [3:3] RW 1`b0 YCSEP_RST_MSK Masks soft reset for YC Separation module. [2:2] RW 1`b0 SRC_RST_MSK Masks soft reset for Sample Rate Converter module. [1:1] RW 1`b0 DFE_RST_MSK Masks soft reset for Digital Front End module. [0:0] RO 1`b0 Reserved Reserved Register: Reserved Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x4A4-0x4B0 Default Name 326`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 203 Registers CX23885 Data Sheet 3.20.1.41Version ID Register: VERSION Bits Type Address: 0x4B4 Default [31:8] RO 24`b0 [7:0] RO 8`h4 Name Description Reserved REV_ID Revision ID. The initial value is set to 8'h01. This refers to the revision of the video decoder core only, and should not be confused with the chiplevel revision ID. Register: Reserved Bits [31:0] 204 Type RO Address: 0x4B8 Default Name `b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.20.1.42VBI Passthrough Control Register: VBI_PASS_CTRL Bits Type [31:22] RO 10`b0 [21:21] RW 1`b0 VBI_PASS_MD Enable special passthrough mode processing of VBI line according to the PASS_LINE_CTRL field. These special pass through modes allow an encoder to reproduce VBI data waveforms and test signals by processing the output of the video decoder: 0 = Y/C separation operates in normal adaptive comb filter mode on all lines equally. 1 = First 20 lines following VSYNC (VRESET) are processed according to special passthrough modes described in PASS_LINE_CTRL. [20:20] RW 1`b0 VBI_SETUP_DIS Disable the luma-decoding path from subtracting the setup or pedestal during VBI lines. This bit is a don't-care for video formats that do not contain a pedestal. This bit allows the proper decoding of VBI data waveforms and video test signals that contain levels below the pedestal. DSH-201010p2 2/4/09 Default Address: 0x4BC Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 205 Registers [19:0] CX23885 Data Sheet RW 20`b0 PASS_LINE_CTRL On a line-by-line basis, selects the method for encoding the waveform in the VBI. Each line is controlled by it's own bit in the vector. This control will extend into the beginning of the active region to control out Closed Caption lines are processed. The lines that are within the VBI are processed as follows: 0 = Y/C Separation operates in chroma notch mode - output of chroma bandpass filter is sent to chroma path, and subtracted from the luma path. 1 = Y/C Separation operates in Black & White mode - all input bandwidth is sent to luma path, none to chroma path. Lines inside the active region are processed as follows: 0 = Y/C Separation operates in normal adaptive comb filter mode 1 = Y/C Separation operates in Black & White mode. The line control starts at the first line after vsync (vreset), which is line 10 for 525 line modes, and line 6 for 625-line modes. The correspondence between the individual bits of pass_line_ctrl and the field line numbers is shown below. Bit Line, 525-line mode Line, 625-line mode 0 10 6 1 11 7 2 12 8 19 29 25 Register: Reserved Bits [31:0] 206 Type RO Address: 0x4C0 Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet 3.21 Registers Audio Decoder Registers 3.21.1 8051 Configuration Register: DL_CTL Address: 0x800 Bits Type Default Name Description [31:29] RO 3`b 0 [28:28] RW 1`b 0 START_8051 0 - 8051 is stopped 1 - 8051 is running [27:27] RW 1`b 0 DL_ENABLE Download Enable [26:26] RW 1`b 0 DL_AUTO_INC Increment Mode Reserved 0 = Increment on Write 1 = Increment on Read [25:24] RW 2`b 0 DL_MAP Memory Map Mode [23:16] RW 8`b 0 DL_DATA_CTL Refer to Audio Decoder spec. for operation Control data port for 8051 code download [15:0] RW 16`b 0 DL_ADDR Address byte for 8051 code download Only Byte access guarantees correct operation. Refer to Audio Decoder Spec. for operation DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 207 Registers CX23885 Data Sheet 3.21.2 Format Detection and Subcarrier Monitoring Register: STD_DET_STATUS Bits Type Default Address: 0x804 Name Description [31:24] RO 8`b0 SPARE_STATUS1 Spare Status Register for future use [23:16] RO 8`b0 SPARE_STATUS0 Spare Status Register for future use [15:8] RO 8`b0 MOD_DET_STATUS1 Detected audio standard 0x00: Mono 0x01: Stereo 0x02: Dual 0x04: Tri 0x10: SAP [7:0] RO 8`b0 MOD_DET_STATUS0 Detected audio standard 0x00: BTSC 0x01: EIAJ 0x02: A2 M 0x03: A2 BG 0x04: A2 DK1 0x05: A2 DK2 0x06: A2 DK3 0x07: A1 I 0x08: AM L 0x09: NICAM BG 0x0A: NICAM DK 0x0B: NICAM I 0x0C: NICAM L 0x0D: BTSC/EIAJ/A2 M mono 0xFF: undefined 208 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.3 User Preference Register: STD_DET_CTL Address: 0x808 Bits Type [31:28] RW 4`b0 SPARE_CTL0 Spare Control Register for future use [27:27] RW 1`b0 TUNER_OUTPUT_F ORMAT 0 - 2nd IF 1 - AF [26:26] RW 1`b0 FORMAT_65MHZ 0 - system DK 1 - system L [25:24] RW 2`b0 FORMAT_45MHZ 00 - BTSC 01 - EIAJ 10 - A2 M [23:23] RO 1`b0 DIS_DBX DBX processing is disabled by bond option [22:22] RO 1`b0 DIS_BTSC BTSC processing is disabled by bond option [21:21] RO 1`b0 DIS_NICAM_A2 NICAM/A2 processing is disabled by bond option [20:20] RO 1`b0 VIDEO_PRESENT Video present signal from video decoder [19:16] RO 4`b0 [15:14] RW 2`b0 FM_DEVIATION 00 - Normal FM 01 - High deviation FM - up to 360 kHz 10 - Very high deviation FM - up to 540 kHz [13:13] RW 1`b0 DE_EMPHASIS_TIM E 0 - 75 de-emphasis 1 - 50 de-emphasis [12:12] RW 1`b0 MUTE_NO_PREF_MO DE [11:8] RW 4`b0 DSH-201010p2 2/4/09 Default Name DW8051_VIDEO_FOR MAT PREF_MODE Description Detected video format by video decoder 1 - Mute output if the preferred mode is not available 0: Mono1 - Whatever is the currently broadcast audio format, force to mono channel, L+R for BTSC and EIA-J, FM1 for A2 or FM/AM for NICAM. 1: Mono2 - language B 2: Mono3 - NICAM stereo forced mono 3: Mono4 - language C 4: Stereo 5: Dual1 - language A/C 6: Dual2 - language B/C 7: Dual3 - language A/B Conexant Preliminary Information/Conexant Proprietary and Confidential 209 Registers [7:4] 210 CX23885 Data Sheet RW 4`b0 AUD_STANDARD 0: BTSC 1: EIAJ 2: A2 M 3: A2 BG 4: A2 DK1 5: A2 DK2 6: A2 DK3 7: A1 I 8: AM L 9: NICAM BG A: NICAM DK B: NICAM I C: NICAM L D: FM radio F: Automatic standard detection Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet [3:0] RW DSH-201010p2 2/4/09 Registers 4`b0 AUD_MODE Force audio mode: NOTE: (Applicable for AUD_STANDARD = 0to E) 0: MONO1 (LANGUAGE A/Mono L+R channel for BTSC,EIAJ,A2)) 1: MONO2 (LANGUAGE B) 2: MONO3 (STEREO forced MONO) 3: MONO4 (NICAM ANALOG) 4: STEREO 5: DUAL1 (AB) 6: DUAL2 (AC)(FM) 7: DUAL3 (BC)(FM) 8: DUAL4 (AC)(AM) 9: DUAL5 (BC)(AM) A: SAP Audio system: NOTE: (Applicable for AUD_STANDARD = F) 0: BG (Auto-detect NICAM BG/A2-BG, Autodetect Mode) 1: DK1 (Auto-detect NICAM DK/A2-DK1, check FM_DEVIATION, Auto-detect Mode) 2: DK2 (Auto-detect NICAM DK/A2-DK2, Autodetect Mode) 3: DK3 (Auto-detect NICAM DK/A2-DK3, Autodetect Mode) 4: I (Auto-detect NICAM I/A1, Auto-detect Mode) 5: L (Auto-detect NICAM L/AM-L, Auto-detect Mode) 6:BTSC (check TUNER_OUTPUT_FORMAT, Auto-detect Mode) 7: EIAJ (Auto-detect Mode) 8: A2-M (Auto-detect Mode) 9:FM Radio (check TUNER_OUTPUT_FORMAT, check DE_EMPHASIS_TIME, Auto-detect Mode) F: Automatic standard and mode detection, except for FM Radio and AF standards Conexant Preliminary Information/Conexant Proprietary and Confidential 211 Registers CX23885 Data Sheet 3.21.4 8051 Interrupt Register: DW8051_INT Bits Type Address: 0x80C Default Name Description [31:31] RO 1`b0 VIDEO_PRESENT_C HANGE 1 - video present status changed [30:30] RO 1`b0 VIDEO_CHANGE 1 - Video format changed 0 - No [29:29] RO 1`b0 RDS_READY 1 - RDS data ready interrupt asserted 0 - RDS data ready interrupt negated [28:28] RO 1`b0 [27:27] RO 1`b0 NICAM_BIT_ERROR _TOO_HIGH 1 - Nicam bit error rate too high interrupt asserted 0 - Nicam bit error rate too high interrupt negated [26:26] RO 1`b0 NICAM_LOCK NICAM change to locked 1 - change happened 0 - No change [25:25] RO 1`b0 NICAM_UNLOCK NICAM change to unlocked 1 - change happened 0 - No change [24:24] RO 1`b0 DFT4_TH_CMP DFT 4 threshold compare status 1 - exceed threshold 0 - within threshold [23:22] RO 1`b0 [21:21] RO 1`b0 LOCK_IND_INT QPSK lock indicator status register 1 - QPSK locked 0 - not locked [20:20] RO 1`b0 DFT3_TH_CMP DFT 3 threshold compare status 1 - exceed threshold 0 - within threshold [19:19] RO 1`b0 DFT2_TH_CMP DFT 2 threshold compare status 1 - exceed threshold 0 - within threshold [18:18] RO 1`b0 DFT1_TH_CMP DFT 1 threshold compare status 1 - exceed threshold 0 - within threshold [17:17] RO 1`b0 FM2_DFT_TH_CMP FM 2 DFT threshold compare status 1 - exceed threshold 0 - within threshold [16:16] RO 1`b0 FM1_DFT_TH_CMP FM 1 DFT threshold compare status 1 - exceed threshold 0 - within threshold 212 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [15:15] RW 1`b0 VIDEO_PRESENT_E N 1 - video present status changed interrupt enabled 0 - video present status changed interrupt disabled [14:14] RW 1`b0 VIDEO_CHANGE_E N 1 - Video format changed interrupt enabled 0 - Video format changed interrupt disabled [13:13] RW 1`b0 RDS_READY_EN 1 - RDS data ready interrupt enabled 0 - RDS data ready interrupt disabled [12:12] RW 1`b0 [11:11] RW 1`b0 NICAM_BIT_ERROR _TOO_HIGH_EN 1 - Nicam bit error rate too high interrupt enabled 0 - Nicam bit error rate too high interrupt disabled [10:10] RW 1`b0 NICAM_LOCK_EN 1 - NICAM change to locked interrupt enabled 0 - NICAM change to locked interrupt disabled [9:9] RW 1`b0 NICAM_UNLOCK_E N 1 - NICAM change to unlocked interrupt enabled 0 - NICAM change to unlocked interrupt disabled [8:8] RO 1`b0 DFT4_TH_CMP_EN 1 - DFT 4 threshold compare interrupt enabled 0 - DFT 4 threshold compare interrupt disabled [7:7] RO 1`b0 [6:6] RW 1`b0 LOCK_IND_INT_CTL QPSK lock indicator interrupt control 0 - disabled 1 - enabled [5:5] RW 1`b0 BB_SRC_INT_CTL baseband SRC interrupt control 0 - interrupt disabled 1 - interrupt enable [4:4] RW 1`b0 DFT3_INT_CTL DFT3 interrupt control 0 - interrupt disabled 1 - interrupt enable [3:3] RW 1`b0 DFT2_INT_CTL DFT2 interrupt control 0 - interrupt disabled 1 - interrupt enable [2:2] RW 1`b0 DFT1_INT_CTL DFT 1 interrupt control 0 - interrupt disabled 1 - interrupt enable [1:1] RW 1`b0 FM2_DFT_INT_CTL FM 2 DFT interrupt control 0 - interrupt disabled 1 - interrupt enable [0:0] RW 1`b0 FM1_DFT_INT_CTL FM 1 DFT interrupt control 0 - interrupt disabled 1 - interrupt enable DSH-201010p2 2/4/09 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 213 Registers CX23885 Data Sheet 3.21.5 General Control/Interrupt Control/Rev Number/Soft Reset Register: GENERAL_CTL Bits Type Address: 0x810 Default Name Description [31:31] RO 1`b0 RDS_INT 1- RDS data ready interrupt asserted [30:30] RO 1`b0 NBER_INT 1 - NICAM bit error rate too high interrupt asserted [29:29] RO 1`b0 NLL_INT 1 - NICAM lost lock interrupt asserted [28:28] RO 1`b0 IFL_INT 1 - IF signal lost interrupt asserted [27:27] RO 1`b0 FDL_INT 1 - Format detection loop complete interrupt asserted [26:26] RO 1`b0 AFC_INT 1 - Audio format change interrupt asserted [25:25] RO 1`b0 AMC_INT 1 - Audio mode change interrupt asserted [24:24] RO 1`b0 [23:23] RW 1`b1 RDS_INT_DIS 0 - RDS data ready interrupt enabled 1 - Disabled [22:22] RW 1`b1 NBER_INT_DIS 0 - NICAM bit error rate too high interrupt enabled 1 - Disabled [21:21] RW 1`b1 NLL_INT_DIS 0 - NICAM lost lock interrupt enabled 1 - Disabled [20:20] RW `b1 IFL_INT_DIS 0 - IF signal lost interrupt enabled 1 - Disabled [19:19] RW `b1 FDL_INT_DIS 0 - Format detection loop complete interrupt enabled 1 - Disabled [18:18] RW 1`b1 FC_INT_DIS 0 - Audio format change interrupt enabled 1 - Disabled [17:17] RW 1`b1 AMC_INT_DIS 0 - Audio mode change interrupt enabled (i.e., mono to stereo, stereo to SAP) 1 - Disabled [16:16] RW 1`b1 [15:8] RO 1`b4 [7:5] RO 1`b0 [4:4] RW 1`b0 DBX_SOFT_RESET DBX soft reset [3:3] RW 1`b0 AD_SOFT_RESET Analog demod soft reset [2:2] RW 1`b0 SRC_SOFT_RESET Baseband SRC soft reset [1:1] RW 1`b0 CDMOD_SOFT_RESE T CDMOD Soft reset [0:0] RW 1`b0 SOFT_RESET Soft reset to ensure smooth transition of operation modes*Write with 1 to clear interrupt flag 214 Reserved Reserved REV_NUM Merlin design revision number register Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.6 Audio Analog AGC Register: AAGC_CTL Address: 0x814 Bits Type Default Name Description [31:31] RW 1`b0 AFE_12DB_EN Enables a +12 dB gain in the analog front end (AFE). When using a filtered sound-IF output from a tuner, the signals level is typically about 100 mVrms. In this case the gain should be enabled. When the sound IF is not filtered, the output will be closer to 1Vrms, so this gain should not be used [30:30] RW 1`b0 AAGC_DEFAULT_EN Enables bypass of the AGC [29:24] RW 6`h20 AAGC_DEFAULT Bypass value for the AGC when AAGC_DEFAULT_EN is asserted. [23:23] RO 1`b0 [22:21] RW 2`b0 AAGC_GAIN Controls the gain of the AGC feedback. [20:16] RW 5`hE AAGC_TH Control AGC error threshold [15:14] RO 2`b0 [13:8] RW 6`h9 [7:6] RO 2`b0 [5:0] RW 6`h5 Reserved Reserved AAGC_HYST2 Controls the wide range hysteresis of the AGC. Reserved AAGC_HYST1 Controls the tight range hysteresis of the AGC. Register: Reserved Bits [31:0] Type RW DSH-201010p2 2/4/09 Address: 0x818-0x8C8 Default Name 32`b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 215 Registers CX23885 Data Sheet 3.21.7 Phase Fix/Dematrix/Analog Demod Source Select/ Prescaler Register: DEMATRIX_CTL Address: 0x8CC Bits Type [31:28] RW 4`b0 [27:24] RW 4`b0 I2S_IN_SHIFT I2S input shift. Signed 2's complement format. Shift left or right by this amount.This bit value is used to set the gain or attenuate mode, and value. If Bit[3] = 0 then gain. If Bit [3] = 1 then attenuate. Bits [2:0] set the value for gain or attenuate. [23:16] RW 8`b0 DEMATRIX_SEL_CT L 00001000 - BTSC force mono 00001001 - BTSC force SAP 00001010 - BTSC force stereo 00001011 - BTSC force dual 00010000 - A2 force mono 100010001 - A2 force mono 2 00010010 - A2 force stereo 00010011 - A2 force dual 00100000 - EIAJ force mono 100100001 - EIAJ force mono 2 00100010 - EIAJ force stereo 00100011 - EIAJ force dual 01000000 - NICAM FM force mono 1 - A 01000001 - NICAM FM force mono 2 - B 01000010 - NICAM FM force mono 3 - (A+B)/2 for stereo source 01000011 - NICAM FM force mono 4 - C analog 01000100 - NICAM FM force stereo 01000101 - NICAM FM force dual 1 - A/ C01000110 - NICAM FM force dual 2 - B/C 01000111 - NICAM FM force dual 3 - A/B 01001000 - NICAM AM force mono 1 - A 01001001 - NICAM AM force mono 2 - B 01001010 - NICAM AM force mono 3 - (A+B)/2 for stereo source 01001011 - NICAM AM force mono 4 - C analog 01001100 - NICAM AM force stereo 01001101 - NICAM AM force dual 1 - A/C 01001110 - NICAM AM force dual 2 - BC 01001111 - NICAM AM force dual 3 - A/B 10000000 - FM force mono 10000010 - FM force stereo 216 Default Name Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers [15:11] RO 5`b0 Reserved [10:10] RW 1`b0 DMTRX_BYPASS Dematrix bypass enable bit 1 - force Dematrix block use mode set above 0 - system decide dematrix mode [9:8] RW 2`b0 DEMATRIX_MODE 0 - Dematrix Sum/Diff 1 - Dematrix Sum/R2 - Dematrix LR3 - Dematrix Mono [7:6] RO 2`b0 [5:5] RW 1`b0 PH_DBX_SEL Selects DBX input to be channel 2 when asserted. [4:4] RW 1`b0 PH_CH_SEL Selects channel to be phase delayed 0 - channel 1 1 - channel 2 [3:0] RW 4`h9 PHASE_FIX Phase fix delay measured in samples of delay at the output sample rate Reserved 3.21.8 Path 1 Source Select Register: PATH1_CTL1 Bits Type [31:29] RO 3`b0 [28:24] RW 5`b1 [23:22] RO 2`b0 [21:20] RW 2`b0 DSH-201010p2 2/4/09 Address: 0x8D0 Default Name Description Reserved PATH1_MUTE_CTL 5'h01: SOFT_MUTE_EN (soft mute) 5'h02: SRC_MUTE_EN (source mute) 5'h04: I2S_MUTE_EN (I2S mute) 5'h08: PAR_MUTE_EN (parallel output mute) 5'h10: Reserved Reserved PATH1_AVC_CG Define AVC compression gain 00 - 1 01 - 1.5 10 - 2 11 - 4 Conexant Preliminary Information/Conexant Proprietary and Confidential 217 Registers CX23885 Data Sheet [19:16] RW 4`h6 PATH1_AVC_RT Define AVC release time 0000 - 0 0001 - 10ms 0010 - 20ms 0011 - 100ms 0100 - 500ms 0101 - 1s 0110 - 2s 0111 - 4s 1000 - 8s Suggested Values: 20ms, 2s, 4s, 8s [15:12] RW 4`h3 PATH1_AVC_AT Define AVC attack time 0000 - 0 0001 - 10ms 0010 - 20ms 0011 - 100ms 0100 - 500ms 0101 - 1s 0110 - 2s 0111 - 4s 1000 - 8s Suggested values: 10ms, 100ms, 500ms, 1s [11:11] RW 1`b1 PATH1_AVC_STERE O 0: Independence Mode 1: Stereo Mode [10:8] RW 3`b0 PATH1_AVC_CR Define AVC compression ratio 000 - 2:1 001 - 4:1 010 - 8:1 011 - 16:1 100 - 32:1 101 ~ 111 Reserved Suggested values: 2:1, 4:1, 8:1, 16:1 [7:4] RW 4`h7 PATH1_AVC_RMS_C ON Define AVC time gain for level detection 0000 - 0 0001 - 10ms 0010 - 20ms 0011 - 100ms 0100 - 500ms 0101 - 1s 0110 - 2s 0111 - 4s 1111 - 8s Suggested values: 0, 20ms, 2s, 4s [3:0] RW 4`b0 PATH1_SEL_CTL 0 - Analog Demod Main Channel 1 - Analog Demod Sub Channel 2 - I2S3 3 - Reserved 218 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.9 Path 1 Volume/Balance Control Register: PATH1_VOL_CTL Default Address: 0x8D4 Bits Type Name Description [31:16] RW 16`h7FFF PATH1_AVC_THRESH OLD Define AVC Threshold [15:15] RW 1`b0 PATH1_BAL_LEFT Select left channel for balance control if 1, select right channel if 0 [14:8] RW 7`b0 PATH1_BAL_LEVEL Attenuation to be provided to the selected channel in dB. Range is 0 to - 96 dB in 1 dB steps [7:0] RW 8`h24 PATH1_VOLUME Volume control in dB steps. +18dB to -96dB in 1/2 dB steps 3.21.10 Path 1 Equalizer Control Register: PATH1_EQ_CTL Bits Type Default [31:30] RO 2`b0 [29:24] RW 6`b18 [23:22] RO 2`b0 [21:16] RW 6`h18 [15:14] RO 2`b0 [13:8] RW 6`h18 [7:1] RO 7`b0 [0:0] RW 1`b0 DSH-201010p2 2/4/09 Address: 0x8D8 Name Description Reserved PATH1_EQ_TREBLE_ VOL Equalizer Treble Volume control in dB steps. +12dB to -12dB in 1/2 dB steps Reserved PATH1_EQ_MID_VO L Equalizer Mid-tone Volume control in dB steps. +12dB to -12dB in 1/2 dB steps Reserved PATH_EQ_BASS_VO L Equalizer Bass Volume control in dB steps. +12dB to -12dB in 1/2 dB steps Reserved PATH1_EQ_BAND_S EL Equalizer band selection 0 - 500 Hz, 1 kHz, 2 kHz1 - 450 Hz, 1.5 kHz, 5 kHz Conexant Preliminary Information/Conexant Proprietary and Confidential 219 Registers CX23885 Data Sheet 3.21.11 Path 1 Soft Clip Control Register: PATH1_SC_CTL Bits Type Address: 0x8DC Default Name Description [31:16] RW 16`h7FFF PATH1_SC_THRESHO LD Define SC Threshold [15:12] RW 4`h3 PATH1_SC_RT Define SC release time 0000 - 0 0001 - 10ms 0010 - 20ms 0011 - 100ms 0100 - 500ms 0101 - 1s 0110 - 2s 0111 - 4s 1000 - 8s Suggested values: 10ms, 100ms, 500ms, 1s [11:8] RW 4`h3 PATH1_SC_AT Define SC attack time 0000 - 0 0001 - 10ms 0010 - 20ms 0011 - 100ms 0100 - 500ms 0101 - 1s 0110 - 2s 0111 - 4s 1000 - 8s Suggested values: 10ms, 100ms, 500ms, 1s [7:7] RW 1`b1 PATH1_SC_STEREO 0: Independence Mode 1: Stereo Mode [6:4] RW 3`h2 PATH1_SC_CR Define SC compression ratio 000 - 2:1 001 - 4:1 010 - 8:1 011 - 16:1 100 - 32:1 101 ~ 111 Reserved Suggested values: 4:1, 8:1, 16:1, 32:1 [3:0] RW 4`h3 PATH1_SC_RMS_CON Define SC time gain for level detection 0000 - 0 0001 - 10ms 0010 - 20ms 0011 - 100ms 0100 - 500ms 0101 - 1s 0110 - 2s 0111 - 4s 1111 - 8s Suggested values: 0, 10ms, 100ms, 1s 220 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.12 Path 2 Source Select Register: PATH2_CTL1 Bits Type Address: 0x8E0 Default Name Description [31:26] RO 6`b0 [25:24] RW 2`b1 [23:22] RO 2`b0 [21:20] RW 2`b0 PATH2_AVC_CG Define AVC compression gain 00 - 1 01 - 1.5 10 - 2 11 - 4 [19:16] RW 4`h6 PATH2_AVC_RT Define AVC release time 0000 - 0 0001 - 10 ms 0010 - 20 ms 0011 - 100 ms 0100 - 500 ms 0101 - 1s 0110 - 2s 0111 - 4s 1000 - 8s Suggested Values: 20 ms, 2 s, 4 s, 8 s [15:12] RW `b3 PATH2_AVC_AT Define AVC attack time 0000 - 0 0001 - 10 ms 0010 - 20 ms 0011 - 100 ms 0100 - 500 ms 0101 - 1s 0110 - 2s 0111 - 4s 1000 - 8s Suggested values: 10 ms, 100 ms, 500 ms, 1 s [11:11] RW `b1 PATH2_AVC_STERE O 0: Independence Mode 1: Stereo Mode DSH-201010p2 2/4/09 Reserved PATH2_MUTE_CTL Bit 0: SOFT_MUTE_EN (soft mute enable) Bit 1: SRC_MUTE_EN (source mute) Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 221 Registers CX23885 Data Sheet [10:8] RW `b0 PATH2_AVC_CR Define AVC compression ratio 000 - 2:1 001 - 4:1 010 - 8:1 011 - 16:1 100 - 32:1 101 ~ 111 Reserved Suggested values: 2:1, 4:1, 8:1, 16:1 [7:4] RW `b7 PATH2_AVC_RMS_C ON Define AVC time gain for level detection 0000 - 0 0001 - 10 ms 0010 - 20 ms 0011 - 100 ms 0100 - 500 ms 0101 - 1s 0110 - 2s 0111 - 4s 1111 - 8s Suggested values: 0, 20 ms, 2 s, 4 s [3:0] RW `b0 PATH2_SEL_CTL 0 - Analog Demod Main Channel 1 - Analog Demod Sub Channel 2 - I2S 3 - Reserved 222 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.13 Path 2 Volume/Balance Control Register: PATH2_VOL_CTL Default Address: 0x8E4 Bits Type Name [31:16] RW 16`h 7FFF [15:15] RW 1`b 0 PATH2_BAL_LEFT Select left channel for balance control if 1, select right channel if 0 [14:8] RW 7`b 0 PATH2_BAL_LEVEL Attenuation to be provided to the selected channel in dB. Range is 0 to - 96 dB in 1 dB steps [7:0] RW 8`h 24 PATH2_VOLUME Volume control in dB steps. +18dB to -96dB in 1/2 dB steps PATH2_AVC_THRESH OLD Description Define AVC Threshold 3.21.14 Path 2 Equalizer Control Register: PATH2_EQ_CTL Bits Type [31:30] RO 2`b 0 [29:24] RW 6`h 18 [23:22] RO 2`b 0 [21:16] RW 6`h 18 [15:14] RO 2`b 0 [13:8] RW 6`h 18 [7:1] RO 7`b 0 [0:0] RW 1`b 0 DSH-201010p2 2/4/09 Address: 0x8E8 Default Name Description Reserved PATH2_EQ_TREBLE_ VOL Equalizer Treble Volume control in dB steps. +12dB to -12dB in 1/2 dB steps Reserved PATH2_EQ_MID_VO L Equalizer Mid-tone Volume control in dB steps. +12dB to -12dB in 1/2 dB steps Reserved PATH2_EQ_BASS_V OL Equalizer Bass Volume control in dB steps. +12dB to -12dB in 1/2 dB steps Reserved PATH2_EQ_BAND_S EL Equalizer band selection 0 - 500 Hz, 1 kHz, 2 kHz 1 - 450 Hz, 1.5 kHz, 5 kHz Conexant Preliminary Information/Conexant Proprietary and Confidential 223 Registers CX23885 Data Sheet 3.21.15 Path 2 Soft Clip Control Register: PATH2_SC_CTL Bits Type Address: 0x8EC Default Name Description [31:16] RW 16'h 7FFF PATH2_SC_THRESHO LD Define SC Threshold [15:12] RW 4`h 3 PATH2_SC_RT Define SC release time 0000 - 0 0001 - 10 ms 0010 - 20 ms 0011 - 100 ms 0100 - 500 ms 0101 - 1 s 0110 - 2 s 0111 - 4 s 1000 - 8 s Suggested values: 10 ms, 100 ms, 500 ms, 1 s [11:8] RW 4`h 3 PATH2_SC_AT Define SC attack time 0000 - 0 0001 - 10 ms 0010 - 20 ms 0011 - 100 ms 0100 - 500 ms 0101 - 1 s 0110 - 2 s 0111 - 4 s 1000 - 8 s Suggested values: 10 ms, 100 ms, 500 ms, 1 s [7:7] RW 1`b 1 PATH2_SC_STEREO 0: Independence Mode1: Stereo Mode [6:4] RW 3`h 2 PATH2_SC_CR Define SC compression ratio 000 - 2:1 001 - 4:1 010 - 8:1 011 - 16:1 100 - 32:1 101 ~ 111 Reserved Suggested values: 4:1, 8:1, 16:1, 32:1 [3:0] 224 RW 4`h 3 PATH2_SC_RMS_C ON Define SC time gain for level detection. 0000 - 0 0001 - 10 ms 0010 - 20 ms 0011 - 100 ms 0100 - 500 ms 0101 - 1 s 0110 - 2 s 0111 - 4 s 1111 - 8 s Suggested values: 0, 10 ms, 100 ms, 1 s Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.16 Sample Rate Converter Control Register: SRC_CTL Bits Type Address: 0x8F0 Default Name Description [31:8] RO 24`b 0 SRC_STATUS FIFO status, OF = OverFlow UF = UnderFlow [11:8] SRC6 Right OF/UF - Left OF/UF [15:12] SRC5 Right OF/UF - Left OF/UF [19:16] SRC4 Right OF/UF - Left OF/UF [23:20] SRC3 Right OF/UF - Left OF/UF [27:24] SRC6: SRC5: SRC4: SRC3 FIFO Pointer bigger than or equal to 12, used for checking the pointer level during loop filter adaptation so as to improve FIFO sizing. [31:28] SRC6: SRC5: SRC4: SRC3 FIFO Pointer less than or equal to 3, used for checking the pointer level during loop filter adaptation so as to improve FIFO sizing. [7:2] RW 6`h 3F FIFO_LF_EN Enable SRC FIFO loop filter [7]: SRC6 FIFO loop filter enable .... [2]: SRC1 FIFO loop filter enable [1:1] RW 1`b 0 BYPASS_LI Bypass linear interpolation [0:0] RW 1`b 0 BYPASS_PF Latest input sample feeds through SRCs but decimation/interpolation timing remains. ** WC Same as RW, but software writing a 1 resets corresponding bit location, writing 0 has no effect. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 225 Registers CX23885 Data Sheet 3.21.17 Sample Rate Converter Loop Filter Coefficients Register: SRC_LF_COEF Address: 0x8F4 Bits Type Default Name Description [31:16] RW 16'h 3333 LOOP_FILTER_COE F2 KD, direct gain of proportional path [19:16] SRC3_KD, valid data 3,4,5,6,7 [23:20] SRC4_KD, valid data 3,4,5,6,7 [27:24] SRC5_KD, valid data 3,4,5,6,7 [31:28] SRC6_KD,validdata 3,4,5,6,7 Default to 5 for all SRCs; invalid setting results in the default. [15:0] RW 16'h 8888 LOOP_FILTER_COE F1 KI, indirect gain of integrated path [3:0] SRC3_KI, valid data 6,7,8,9,10 [7:4] SRC4_KI, valid data 6,7,8,9,10 [11:8] SRC5_KI, valid data 6,7,8,9,10 [15:12] SRC6_KI, valid data 6,7,8,9,10 Default to 8 for all SRCs; invalid setting results in the default. 3.21.18 SRC1 Control Register: SRC1_CTL Bits Type Address: 0x8F8 Default [31:28] RO 4`b 0 [27:24] RW 4`h 8 [23:18] RO 6`b 0 [17:0] RW 18`h 1867C 226 Name Description Reserved SRC1_FIFO_RD_TH SRC 1 FIFO threshold for Read Enable. Apply to both left channel and right channel. Reserved SRC1_PHASE_INC SRC 1 phase increment calculated by (Fin/Fout) * 216, default Fin = Fout Shared by left channel and right channel. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.19 SRC2 Control Register: SRC2_CTL Bits Type Address: 0x8FC Default [31:28] RO 4`b 0 [27:24] RW 4`h 8 [23:18] RO 6`b 0 [17:0] RW 18`h 1867C Name Description Reserved SRC2_FIFO_RD_TH SRC 2 FIFO threshold for Read Enable. Apply to both left channel and right channel. Reserved SRC2_PHASE_INC SRC 2 phase increment calculated by (Fin/Fout) * 216, default Fin = Fout Shared by left channel and right channel. 3.21.20 SRC3 Control Register: SRC3_CTL Bits Type Address: 0x900 Default [31:28] RO 4`b 0 [27:24] RW 4`h 8 [23:18] RO 6`b 0 [17:0] RW 18`h 14FAA Name Description Reserved SRC3_FIFO_RD_TH SRC 3 FIFO threshold for Read Enable. Apply to both left channel and right channel. Reserved SRC3_PHASE_INC SRC 3 phase increment calculated by (Fin/Fout) * 216, default Fin = Fout Shared by left channel and right channel. 3.21.21 SRC4 Control Register: SRC4_CTL Bits Type Address: 0x904 Default [31:28] RO 4`b 0 [27:24] RW 4`h 8 [23:18] RO 6`b 0 [17:0] RW 18`h 14FAA DSH-201010p2 2/4/09 Name Description Reserved SRC4_FIFO_RD_TH SRC 4 FIFO threshold for Read Enable. Apply to both left channel and right channel. Reserved SRC4_PHASE_INC SRC 4 phase increment calculated by (Fin/Fout) * 216, default Fin = Fout Shared by left channel and right channel. Conexant Preliminary Information/Conexant Proprietary and Confidential 227 Registers CX23885 Data Sheet 3.21.22 SRC5 Control Register: SRC5_CTL Bits Type Address: 0x908 Default [31:28] RO 4`b 0 [27:24] RW 4`h 8 [23:18] RO 6`b 0 [17:0] RW 18`h 10453 Name Description Reserved SRC5_FIFO_RD_TH SRC 5 FIFO threshold for Read Enable. Apply to both left channel and right channel. Reserved. SRC5_PHASE_INC SRC 5 phase increment calculated by (Fin/Fout) * 216, default Fin = Fout Shared by left channel and right channel. 3.21.23 SRC6 Control Register: SRC6_CTL Bits Type Address: 0x90C Default [31:28] RO 4`b 0 [27:24] RW 4`h 8 [23:18] RO 6`b 0 [17:0] RW 18`h 14FAA 228 Name Description Reserved SRC6_FIFO_RD_TH SRC 6 FIFO threshold for Read Enable. Apply to both left channel and right channel. Reserved SRC6_PHASE_INC SRC 6 phase increment calculated by (Fin/Fout) * 216, default Fin = Fout Shared by left channel and right channel. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.24 Output Selects/Bypass Control Register: BAND_OUT_SEL Bits Type [31:30] RW 2`b 0 SRC6_IN_SEL SRC input source select. 00 - select from path 1 output 01 - select from path 2 output 10 - select from de-matrix stereo 11 - select from mono/SAP output [29:28] RW 2`b 1 SRC6_CLK_SEL SRC output fifo read select 00 - select from I2S WS 01 - Reserved 10 - select from NICAM ENABLE (64 kHz) 11 - select from SRC6 FIFO write [27:26] RW 2`b 0 SRC5_IN_SEL SRC input source select. 00 - select from analog demod OUTA, OUTC 01 - select from analog demod RDS output 10 - select from de-matrix stereo 11 - select from mono/SAP output [25:24] RW 2`h 2 SRC5_CLK_SEL SRC output fifo read select 00 - select from I2S WS 01 - Reserved 10 - select from NICAM ENABLE (64 kHz) 11 - select from SRC5 FIFO write [23:22] RW 2`h 2 SRC4_IN_SEL SRC input source select. 00 - select from path 1 output 01 - select from path 2 output 10 - select from de-matrix stereo 11 - select from mono/SAP output [21:20] RW 2`h 3 SRC4_CLK_SEL SRC output fifo read select 00 - select from I2S WS 01 - Reserved 10 - select from NICAM ENABLE (64 kHz) 11 - select from SRC4 FIFO write [19:18] RW 2`b 0 SRC3_IN_SEL SRC input source select. 00 - select from path 1 output 01 - select from path 2 output 10 - select from de-matrix stereo 11 - select from mono output DSH-201010p2 2/4/09 Default Address: 0x910 Name Description Conexant Preliminary Information/Conexant Proprietary and Confidential 229 Registers CX23885 Data Sheet [17:16] RW 2`b 0 [15:8] RW 8`b 0 [7:6] RO 2`h 3 [5:4] RW 2`b 0 I2S_SRC_SEL Output source select. 00 - select from SRC 3 01 - select from SRC 4 10 - select from SRC 5 11 - select from SRC 6 [3:2] RW 2`h 2 PARALLEL2_SRC_S EL Output source select. 00 - select from SRC 3 01 - select from SRC 4 10 - select from SRC 5 11 - select from SRC 6 [1:0] RW 2`b 1 PARALLEL1_SRC_S EL Output source select. 00 - select from SRC 3 01 - select from SRC 4 10 - select from SRC 5 11 - select from SRC 6 230 SRC3_CLK_SEL BASEBAND_BYPASS_ CTL SRC output fifo read select 00 - select from I2S WS 01 - Reserved 10 - select from NICAM ENABLE (64 kHz) 11 - select from SRC3 FIFO write Baseband block bypass control 0 - Normal operation 1 - The block is bypassed bit 7 - path2 soft-clip 6 - path2 volume/balance control 5 - path2 equalizer 4 - path2 automatic volume control 3 - path1 soft-clip 2 - path1 volume/balance control 1 - path1 equalizer 0 - path1 automatic volume control Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.25 I2S Input Control Register Register: I2S_N_CTL Address: 0x914 Bits Type [31:11] RO 21`b 0 [10:10] RW 1`b 0 I2S_UP2X_BW20K 20 kHz upsample by 2 bandwidth 1 - 20 kHz bandwidth (44.1 - 64 kHz sample rate) 0 - 15 kHz bandwidth (32 kHz sample rate) [9:9] RW 1`b 0 I2S_UP2X_BYPASS 0 = normal operation 1 = up sample by 2 block is bypassed for input sample rate higher than 64 kHz [8:8] RW 1`b 0 I2S_IN_MASTER_MOD E [7:7] RW 1`b 0 I2S_IN_SONY_MOD E 0 = Philips mode: 2nd SCK rising edge after WS transition for first bit of audio word. 1 = Sony mode: 1st SCK rising edge after WS transition for first bit of audio word. [6:6] RW 1`b 0 I2S_IN_RIGHT_JUST 0 = left justified serial data 1 = right justified meaning aligned with [5:5] RW 1`b 0 I2S_IN_WS_SEL Control for Word Select (WS_IN/WS_OUT) polarity. 0 = Left sample on WS=0 1 = Left sample on WS=1 [4:0] RW 5`b 0 I2S_IN_BCN_DEL Controls a number of SCK_IN cycles delay for programmable Right justify mode. DSH-201010p2 2/4/09 Default Name Description Reserved 0 = Slave operation 1 = Master: SCK_OUT, and WS_OUT are generated Conexant Preliminary Information/Conexant Proprietary and Confidential 231 Registers CX23885 Data Sheet 3.21.26 I2S Output Control Register Register: I2S_OUT_CTL Bits Type Address: 0x918 Default Name Description [31:17] RO 15`b 0 Reserved [16:16] RW 1`b 0 [15:9] RO 7`b 0 [8:8] RW 1`b 1 I2S_OUT_MASTER_M ODE [7:7] RW 1`b 0 I2S_OUT_SONY_MO DE 0 = Philips mode: 2nd SCK rising edge after WS transition for first bit of audio word. 1 = Sony mode: 1st SCK rising edge after WS transition for first bit of audio word. [6:6] RW 1`b 0 I2S_OUT_RIGHT_JU ST 0 = left justified serial data 1 = right justified meaning aligned with [5:5] RW 1`b 0 I2S_OUT_WS_SEL Control for Word Select (WS_IN/WS_OUT) polarity. 0 = Left sample on WS=0 1 = Left sample on WS=1 [4:0] RW 5`b 0 I2S_OUT_BCN_DEL Controls a number of SCK_IN cycles delay for programmable Right justify mode. I2S_OUT_SOFT_RESE T_EN I2S output soft reset control 1: soft reset will reset I2S output 0: soft reset do not reset I2S output Reserved 0 = Slave operation 1 = Master: SCK_OUT, and WS_OUT are generated Register: Reserved Bits [31:0] 232 Type RO Address: 0x91C-0x9C0 Default Name 32`b 0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.21.27 Autoconfiguration Control Register: AUTOCONFIG_REG Bits Type Default [31:4] RO 28'b 0 [3:0] RW 4'b 0 Address: 0x9C4 Name Description Reserved AUTOCONFIG_MOD E Audio Standard 0:BTSC 1:FM Radio 2:EIA-J 3:A2-BG 4:NICAM AM/FM 5:NICAM High Deviation FM 6:NICAM Very High Deviation FM 7:AF FM - baseband FM input, bypass first rotator and FM decoder 8: A1 9:A2-M A:A2-DK Register: Reserved Bits [31:0] Type RO DSH-201010p2 2/4/09 Address: 0x9C8-0x9D0 Default Name 32'b 0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 233 Registers 3.22 CX23885 Data Sheet Audio ADC Registers Unless specified explicitly, the same register control is applicable to both left channel and right channel. 3.22.1 Delta-Sigma ADC Miscellaneous Register 1 Register: DSM_CTRL1 Bits Type Address: 0x0 Default Name Description [7:7] RW 1'b1 DYN_DIT_EN Enables dynamic dithering. [6:6] RW 1'b1 DIT_EN Enables dithering. [5:5] RW 1'b0 RND_MODE Switches between two different length LFSRs. [4:4] RW 1'b1 STAB_DET_EN Enables stability detector. [3:3] RO 1'b0 [2:0] RW 3'h2 Reserved STAB_TH Sets threshold for stability detection in deltasigma. 3.22.2 Delta-Sigma ADC Miscellaneous Register 2 Register: DSM_CTRL2 Bits Type Default [7:2] RO 6'b0 [1:0] RW 2'h3 234 Address: 0x1 Name Description Reserved DIT_REF Changes the dither amplitude used in dynamic dithering. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.22.3 Chopper Clocks Enable Register Register: CHP_EN_CTRL Bits Type Address: 0x2 Default Name Description [7:5] RO 3'b0 Reserved [4:4] RW 1'b1 CHP_CLK_EN_REF Enables chopper clock for refbuf and bandgap. [3:3] RW 1'b1 CHP_CLK_EN_S2D Enables chopping for S2D. [2:2] RW 1'b0 CHP_CLK_MODE Changes the M variable described in CHP_CLKDV_REF for the bandgap from 6 to 8. [1:1] RW 1'b1 CHP_EN_BG Enables chopping for bandgap. [0:0] RW 1'b1 CHP_EN_REFBUF Enables chopping for refbuf. 3.22.4 Chopper Clock Reference and Bandgap Divide Settings Register: CHP_CLK_CTRL1 Bits Type Default [7:5] RO 3'b0 [4:0] RW 5'h8 Address: 0x4 Name Description Reserved CHP_CLKDV_REF Changes the reference buffers and bandgap chopper frequency: Reference buffer CHOP CLK: (PLL_CLK)/ (10*6*2n) where 0<n<32. Bandgap CHOP CLK: (PLL_CLK)/(10*M*2n) where 0<n<32 and M is determined by the CHP_CLK_MODE bit. 3.22.5 Chopper Clock S2D Divide Settings Register: CHP_CLK_CTRL2 Bits Type Default [7:5] RO 3'b0 [4:0] RW 5'h8 DSH-201010p2 2/4/09 Address: 0x5 Name Description Reserved CHP_CLKDV_S2D Change S2D chopper frequency, (PLL_CLK)/ (8*10*2n) (where 0<n<32) Conexant Preliminary Information/Conexant Proprietary and Confidential 235 Registers CX23885 Data Sheet 3.22.6 Bandgap Testing Register Register: BG_REF_CTRL Bits Type Address: 0x6 Default Name Description [7:5] RO 3'b0 Reserved [6:6] RW 1'b0 OCURR_REFBUF Increases refbuf current by 66%. 0 = nom 1 = 66% more current. [5:5] RW 1'b0 TEST_BG Bypass refbuf, route bandgap to reference pin. [4:4] RW 1'b0 BIAS_SEL Bases all Audio ADC currents off either Audio ADC bandgap or a current external from audio ADC. 0 = internal 1 = external from audio ADC [3:3] RO 1'b0 [2:0] RW 3'h3 Reserved BG_TRIM Changes the output voltage (slightly) and temp coefficient for tuning of bandgap over PVT. 3.22.7 SD2 MUX Control for Right Channel Register: S2D_SW_CTRL1 Bits Type Default [7:5] RO 3'b0 [4:0] RW 5'h13 Address: 0x8 Name Description Reserved SW_CTRL_S2D_R Changes input switches for right channel. 3.22.8 SD2 MUX Control for Left Channel Register: S2D_SW_CTRL2 Bits Type Default [7:5] RO 3'b0 [4:0] RW 5'h13 236 Address: 0x9 Name Description Reserved SW_CTRL_S2D_L Changes input switches for left channel. Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.22.9 S2D Bias and Startup Control Register: S2D_BIAS_CTRL Bits Type Default Address: 0xA Name Description [7:5] RO 3'b0 [4:4] RW 1'b0 S2D_STRTL_N Disables S2D startup circuitry: 0 = startup circuit on 1 = startup circuit off [3:2] RW 2'h2 AMP_BIAS_S2D Changes bias for amp in S2D: [1:0] RW DSH-201010p2 2/4/09 2'h2 Reserved CMFB_BIAS_S2D Amp Current <1> <0> 0 0 Base*4 0 1 Base*3 1 0 Base*2 1 1 Base Changes bias for CMFB in S2D: CMFB Current <1> <0> 0 0 Base*4 0 1 Base*3 1 0 Base*2 1 1 Base Conexant Preliminary Information/Conexant Proprietary and Confidential 237 Registers CX23885 Data Sheet 3.22.10 Delta-Sigma ADC Amplifier Bias Registers Register: AMP_BIAS_CTRL Bits Type Default Address: 0xC Name Description [7:5] RO 3'b0 Reserved [4:4] RW 1'b0 COMP_BIAS Changes comparator bias in delta-sigma: 1 = 50% more current 0 = base current [3:2] RW 2'b1 AMP1_BIAS Changes first amplifier bias in delta-sigma: <0>: 1 = 66% more current from base <1>: 1 = 33% more current from base [1:0] RW 2'b1 AMP2_BIAS Changes second amplifier bias in delta-sigma: <0>: 1 = 66% more current from base <1>: 1 = 33% more current from base 3.22.11 Miscellaneous Testing Register Register: CH_PWR_CTRL1 Bits Type Default Address: 0xE Name Description [7:6] RO 2'b0 [5:5] RW 1'b1 CLK_EN Enables clock to delta-sigma and decimation filter. [4:4] RW 1'b0 CLK_SEL Selects clock from CLK_IN OR CLK_TEST: 0 = differential PLL CLK Input 1 = ALTERNATE CLK input [3:3] RW 1'b0 CH_SEL Selects channel: 0 = channel 1 1 = channel 2 [2:2] RW 1'b0 TEST_S2D Puts S2D into test mode: 0 = normal mode 1 = test mode [1:1] RW 1'b0 DS_MUTE_L Mutes left channel [0:0] RW 1'b0 DS_MUTE_R Mutes right channel 238 Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.22.12 Power Down Register Register: CH_PWR_CTRL2 Bits Type Default Address: 0xF Name Description [7:6] RO 2'b0 Reserved [5:5] RW 1'b0 PWR_DN_REFBUF Powers down rebuf. [4:4] RW 1'b0 PWR_DN_BANDG Powers down bandgap. [3:3] RW 1'b0 PWR_DN_DS_L Powers down S2D left channel. [2:2] RW 1'b0 PWR_DN_DS_R Powers down S2D right channel. [1:1] RW 1'b0 PWR_DN_S2D_L Powers down S2D left channel. [0:0] RW 1'b0 PWR_DN_S2D_R Powers down S2D right channel. 3.22.13 DS and S2D Stability Register Register: DSM_STATUS1 Bits Type Address: 0x10 Default Name Description [7:4] RO 1'b0 Reserved [3:3] RO 1'b0 S2D_STRT_R Reads stability of right channel S2D. [2:2] RO 1'b0 S2D_STRT_L Reads stability of left channel S2D. [1:1] RO 1'b0 STAB_FLAG_R Reads right channel delta-sigma stability. [0:0] RO 1'b0 STAB_FLAG_L Reads left channel delta-sigma stability. 3.22.14 Dynamic Dither Amplitude Read Register Register: DSM_STATUS2 Bits Type Address: 0x11 Default Name Description [7:4] RO 4'b0 DIT_AMPL_L Reads dynamic dither amplitude for left channel. [3:0] RO 4'b0 DIT_AMPL_R Reads dynamic dither amplitude for right channel. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 239 Registers CX23885 Data Sheet 3.22.15 Digital Control Register 1 This register specifies decimation output rate and scale. Register: DIG_CTL1 Bits Type Address: 0x12 Default Name Description [7:4] RW 4'h7 SCALE Digital output full-range scale enable 4'b0000: 1.0 4'b0001: 1+16/64 4'b0010: 1+18/64 4'b0011: 1+20/64 4'b0100: 1+22/64 4'b0101: 1+24/64 4'b0110: 1+26/64 4'b0111: 1+27/64 4'b1000: 1+28/64 4'b1001: 1+29/64 4'b1010: 1+30/64 4'b1011: 1+32/64 4'b1100 ~ 4'b1111: Reserved [3:0] RW 4'b1 RATE_SEL Select output rate (96/64/88.2 kHz) 4'b0000: Reserved 4'b0001: 96 kHz 4'b0010: 64 kHz 4'b0011: Reserved 4'b0100: 88.2 kHz 4'b0101: Reserved 4'b0110 ~ 4'b1111: Reserved 240 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Registers 3.22.16 Digital Register 2 This register specifies various mode control including Injection Mode, FCLK polarity, and Bypass Modulator so Modulator output is directly placed on I2S I/F (I2S_DATA_SEL). Register: DIG_CTL2 Bits Type Address: 0x13 Default Name INJ_MODE Description [7:7] RW 1'b0 Delta Sigma modulator is bypassed and DSM samples are injected through INJ_DL for left channel and INJ_DR for right channel, all at DSM sampling speed. Refer to Corona pad description for the pads associated. [6:5] RO 2'b0 [4:4] RW 1'b0 SOFT_RST High active soft reset, initializes digital registers. [3:3] RW 1'b1 FCLK_POL Digital clock polarity control 0: aligned in phase with analog modulator clock 1: aligned out phase (180deg) with modulator clk [2:1] RO 2'b0 [0:0] RW 1'b0 Reserved Reserved I2S_DATA_SEL Select internal signals placed on Audio ADC output I2S I/F 0: Audio ADC Normal Operation, decimation output 1: Delta Sigma Modulator Output (24 bits) Note: SONY_PHILLIP Mode Control and LRCK Polarity Control apply to all I2S_DATA_SEL Register: Reserved Bits [7:0] Type RO DSH-201010p2 2/4/09 Address: 0x14-0x18 Default Name 8'b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential 241 Registers CX23885 Data Sheet 3.22.17 I2S_TX_CFG Register: I2S_TX_CFG Bits Type Address: 0x1A Default Name Description [7:2] RO 6'b0 Reserved [1:1] RW 1'b1 SONY_PHILLIP_MO DE 1: Sony Mode 0: Phillip Mode Must be configured the same as I2S Rx in Corona. [0:0] RW 1'b0 LRCK_POL Specify the I2S Tx LRCK polarity. 0: low for left channel 1: low for right channel Register: Reserved Bits [7:0] 242 Type RO Address: 0x1C-0x23 Default Name 8'b0 Description Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 4 4.1 Thermal/Mechanical Information Introduction The ETQFP package features an exposed die paddle to improve both thermal and electrical performance. To make optimum use of these performance improvements, the PCB must be designed with this technology in mind. This section focuses on the specifics of integrating the ETQFP into the PCB design. 4.2 Center Pad Geometry To take advantage of the ETQFP performance improvements, a solder-tinned-copper pad with thermal vias is required on the PCB. This thermal via pattern represents a copper cross section in the barrel of the thermal via of approximately 1 percent of the total center pad area. For the exposed region of the center pad, if the plating thickness is not sufficient enough to effectively plug the barrel of the via when plated, the solder mask should be used to cap the vias with a dimension equal to the via diameter + 0.1 mm minimum. This prevents the solder from being wicked through the thermal via and potentially creating a solder void in the region between the package bottom and the center pad on the surface of the PCB. NOTE: DSH-201010p2 2/4/09 Please contact your Conexant representative for additional thermal information regarding the CX23885. Conexant Preliminary Information/Conexant Proprietary and Confidential 243 Thermal/Mechanical Information 4.3 CX23885 Data Sheet Mechanical Drawing Figure 7 provides a mechanical drawing of the 128-pin ETQFP. Figure 8 provides a diagram of the exposed pad. Figure 7. 128-Pin ETQFP Control Dimensions are in Milimeters 102740_005 Figure 8. Exposed Pad NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 2. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Miminum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm Pitch packages. 3. All dimensions of 128L were based on those of 120L, since they are not mentioned in JEDEC Spec MS-026. 102740_006 244 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 5 5.1 Electrical Information DC Electrical Parameters Table 5. Absolute Maximum Ratings Parameters Min Typ Max Units VAA (measured to VSS) -- -- 5 V VDDO (measured to VSSO) -- -- 5 V VDD 1.8 V supply pins (measured to VSS) -- -- 3 V VDD 1.2 V supply pins (measured to VSS) -- -- 2 V Voltage on any signal pin (see note below) VSSO - 0.5 -- VDDO + 0.5 Vpp Analog input voltage -- -- VAA + 0.5 V Operating temperature 0 -- 70 C Storage temperature -65 -- +150 C Junction temperature -- -- +125 C Peak reflow temperature -- -- 260 C GENERAL NOTE: 1. Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V, or drops below ground by more than 0.5 V can induce destructive latchup. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 245 Electrical Information CX23885 Data Sheet Table 6. Recommended Operating Conditions Parameters Analog power supply Symbols VAA_PLL Min Typ Max Units 3.135 3.3 3.465 V 1.14 1.2 1.26 V 1.71 1.8 1.89 V 3 3.3 3.6 V VAA_CHx VAA_ADCx VAA_XTAL VAA_DSx Core power 1.2 V supply VDD VDDA VDDTA Core power 1.8 V Supply VDDT VDDTO VDDRO Digital I/O power supply VDDIO VDDO_PLL Analog input CVBS or luma amplitude range (AC coupling required) Yin 0.5 1 2 Vp-p Analog input chroma amplitude range (AC coupling required) Cin 0.1 1 2 Vp-p Analog audio input Ain -- 2.262 2.828 Vp-p Ambient operating temperature Ta 0 -- 70 C 246 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 CX23885 Data Sheet Electrical Information Table 7. Signal Characteristics Parameters Min Symbol Typ Max Units Digital Inputs Input high voltage VIH 2 -- VDDO + 0.5 V Input low voltage VIL -0.5 -- 0.8 V Input high current (Vin = 2.4 V) IIH 1 A Input low current (Vin = 0.4 V) IIL -1 A Input capacitance (1MHz, 2.4 V) Ci 7 pF Crystal Inputs (XTI, XTO) Input low voltage VIL -0.5 -- 0.4 V Input high voltage VIH 2.4 -- VDDO + 0.5 V Digital Outputs Output voltage high (IOH = -400 A) VOH 2.4 -- VDDO V Output voltage low (IOL = 4 mA) VOL 0 -- 0.4 V Three-state current IOZ -- -- 10 A Analog input capacitance Ca 5.2 5 pF AC Electrical Parameters Table 8. Clock Timing Parameters Parameters Symbol Min Typ Max Units XTI / XTO Crystal cycle time 1 34.919 34.921 34.922 ns High time 2 17.46 ns Low time 3 17.46 ns ITU-R BT.656 Operation PIXCLK frequency 4 -- PIXCLK duty cycle 5 45 PIXCLK to data delay (see note) 6 27 -- MHz 55 % 5 ns GENERAL NOTE: 1. Data delay value is measured relative to the rising edge of PIXCLK but note that PIXCLK can be inverted for systems requiring data to output relative to the falling edge of PIXCLK. DSH-201010p2 2/4/09 Conexant Preliminary Information/Conexant Proprietary and Confidential 247 Electrical Information CX23885 Data Sheet Table 9. Control Signal Timing Parameters Symbol Min Typ Max Units VIP Input Port Data to VIPCLK setup 8 5 -- -- ns Data to VIPCLK hold 9 0 -- -- ns -- 11 ns VIP Output Port PIXCLK to timing/indicator delay 10 -- Symbol Min Table 10. Power Supply Currents Parameters Typ Max Units Analog current IAA 165 173 mA Digital core current (1.2 V) IDD1.2 300 415 mA Digital core current (1.8 V) IDD1.8 129 132 mA Digital I/O current IDDIO 15 40 mA 248 Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 6 6.1 Connecting the CX23885 to the CX23417 CX23885 and CX23417 Pin Connections Table 11 lists the CX23885 pins that are to be connected to the CX23417. Each row indicates a connection. NOTE: Pin 113 of CX23885 is connected to two pins on the CX23417. Table 11. CX23885 and CX23417 Pin Connections (1 of 2) CX23885 Pin Number DSH-201010p2 2/4/09 Pin Name CX23417 Coordinate Pin Number 53 GPIO15 U12 MIRDY# 59 GPIO14 P16 MIADDR3 60 IRQ_N (GPIO[16]) R11 MICS# 61 URX (GPIO[17]) P15 MIRD# 62 UTX (GPIO[18]) U14 MIWR# 64 GPIO13 R17 MIADDR2 65 GPIO12 L14 MIADDR1 67 GPIO11 M15 MIADDR0 68 TS2_SOP H17 STRODREQ# 69 TS2_VAL H16 STRODVLD# 70 TS2_CLK G17 STROCLK 71 TS2_DAT J17 STRODATA7 74 TS1_CLK C8 LLC 76 GPIO10 U3 MIDATA7 86 GPIO9 U4 MIDATA6 87 GPIO8 R6 MIDATA5 92 GPIO3 U6 MIDATA0 Conexant Preliminary Information/Conexant Proprietary and Confidential 249 Connecting the CX23885 to the CX23417 CX23885 Data Sheet Table 11. CX23885 and CX23417 Pin Connections (2 of 2) CX23885 Pin Number 250 Pin Name CX23417 Coordinate Pin Number 95 GPIO4 R7 MIDATA1 100 GPIO5 T6 MIDATA2 101 GPIO6 U5 MIDATA3 103 I2S_BCLK (GPIO[23]) B7 AICLKIN 104 I2S_WCLK (GPIO[22]) A6 AILRIN 105 I2S_SDAT (GPIO[21]) A7 AIDAT 111 GPIO[7] T5 MIDATA4 113 AUX_PLL_CLK C6 RCLK G17 STROCLK Conexant Preliminary Information/Conexant Proprietary and Confidential DSH-201010p2 2/4/09 www.conexant.com General Information: U.S. and Canada: (888) 855-4562 International: (949) 483-4600 Headquarters - Newport Beach 4000 MacArthur Blvd. Newport Beach, CA 92660