Supertex inc. PS10 Quad Power Sequencing Controller Features General Description Sequencing of four supplies, ICs, or subsystems Independently programmable delays between open drain PWRGD flags (5.0 to 200ms) 10 to 90V operation Tracking in combination with Schottky diodes Input supervisors including: * UV/OV lock out/enable * Power-on-Reset (POR) Low power consumption, 0.4mA supply current Available in a space saving 14-Lead SOIC package Many of today's high performance FPGA's, microprocessors, DSP and industrial/embedded subsystems require sequencing of the input power. Historically this has been accomplished by: i) discretely using comparators, references & RC circuits; ii) using expensive programmable controllers; or iii) with low voltage sequencers requiring resistor drop downs and several high voltage optocoupler or level shift components. The PS10 saves board space, improves accuracy, eliminates optocouplers or level shifts and reduces overall component count by combining four timers, programmable input UV/OV supervisors, a programmable POR, and four 90V open drain outputs. A high reliability, high voltage, junction isolated process allows the PS10 to be connected directly across the high voltage input rails. Applications Power supply sequencing -48V telecom and networking distributed systems -24V cellular and fixed wireless systems -24V PBX systems +48V storage systems FPGA, microprocessor tracking Industrial/embedded system timing/sequencing High voltage MEMs driver's supply sequencing High voltage display driver's supply sequencing The power-on-reset interval (POR) may be programmed by a capacitor on CRAMP. To sequence additional systems, multiple PS10s may be daisy-chained together. If at any time the input supply falls outside the UV/OV detector range, the PWRGD outputs will immediately become IN-ACTIVE. The PS10 is available in a space saving 14-Lead SOIC package. Typical Application Circuit GND or +48V 14 487k 6 PS10 5 7 Doc.#DSFP-PS10 C080613 PWRGD-C PWRGD-B OV VEE TB TC 11 RTB -48V or GND PWRGD-D UV 6.81k 9.76k /EN VIN TD 12 RTC PWRGD-A RAMP 13 RTD 10 10nF 1 2 3 4 DC/DC Converter /EN DC/DC Converter /EN DC/DC Converter /EN DC/DC Converter +12V COM +5V COM +3.3V COM +2.5V COM Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. Supertex inc. www.supertex.com PS10 Pin Configuration Ordering Information Part Number Package Option Packing PS10NG-G 14-Lead SOIC 53/Tube PS10NG-G-G M905 14-Lead SOIC 2500/Reel 14 1 -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Parameter Value VEE referenced to VIN pin +0.3V to -100V VPWRGD referenced to VEE voltage -0.3V to +100V VUV and VOV referenced to VEE voltage (top view) -0.3V to 12V Operating ambient temperature -40C to +85C Operating junction temperature -40C to +125C Storage temperature range 14-Lead SOIC Product Marking Top Marking -65 to +150C Power dissipation @ 25 C PS10NG 750mW O YWW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. LLLLLLLL Bottom Marking CCCCCCCCC AAA *May be part of top marking PWRGD Logic Condition Package may or may not include the following marks: Si or PWRGD-A/B/C/D Inactive (not ready) 0 VEE Active (ready) 1 Hi Z Electrical Characteristics (-10V V IN Sym Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging 14-Lead SOIC Typical Thermal Resistance Package ja 14-Lead SOIC 75OC/W* -90V, TA = 25C unless otherwise specified) Parameter Min Typ Max Units Conditions Supply (Referenced to VIN pin) VEE Supply voltage - -90 - -10 V --- IEE Supply current - - 400 450 A VEE = -48V OV and UV Control (Referenced to VEE pin) VUVH UV high threshold # 1.16 1.22 1.28 V Low to high transition VUVL UV low threshold # 1.06 1.12 1.18 V High to low transition VUVHY UV hysteresis # - 100 - mV --- UV input current - - - 1.0 nA VUV = VEE + 1.9V VOVH OV high threshold # 1.16 1.22 1.28 V Low to high transition VOVL OV low threshold # 1.06 1.12 1.18 V VOVHY OV hysteresis # - 100 - mV --- OV input current - - - 1.0 nA VUV = VEE + 1.9V IUV IOV High to low transition # Specifications apply over 0OC TA 70OC Doc.#DSFP-PS10 C080613 2 Supertex inc. www.supertex.com PS10 Electrical Characteristics (cont.) (-10V V IN Sym -90V, TA = 25C unless otherwise specified) Parameter Min Typ Max Units Conditions Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V) IRAMP Ramp pin output current - - 10 - A --- tPWRGD-A Time from UV high to PWRGD-A - - 8.8 - ms VEE = -48V, CRAMP = 10nF, see typical application circuit tPWRGD-B Maximum time from PWRGD-A to PWRGD-B - 150 200* 250 ms RTB = 120k tPWRGD-B Minimum time from PWRGD-A to PWRGD-B - 3.0 5.0* 8.0 ms RTD = 3.0k tPWRGD-C Maximum time from PWRGD-B to PWRGD-C - 150 200* 250 ms RTB = 120k tPWRGD-C Minimum time from PWRGD-B to PWRGD-C - 3.0 5.0* 8.0 ms RTD = 3.0k tPWRGD-D Maximum time from PWRGD-C to PWRGD-D - 150 200* 250 ms RTB = 120k tPWRGD-D Minimum time from PWRGD-C to PWRGD-D - 3.0 5.0* 8.0 ms RTD = 3.0k * Variations will track. For example if tPWRGD-A is 250ms, then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version. Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V) VPWRGD-X(hi) Power good pin breakdown voltage - 90 - - V VPWRGD-X(lo) Power good pin output low voltage - - 0.4 0.5 V IPWRGD-X(lk) Maximum leakage current - - <1.0 10 A PWRGD-X = HI Z IPWRGD = 1.0mA, PWRGD-X = LOW VPWRGD = 90V, PWRGD-X = HI Z Functional Block Diagram VINT Band Gap Reference UV VIN Regulator & POR + Logic VBG PWRGD-A UVLO - OV + PWRGD-B VEE PWRGD-C VINT Programmable Timer - + 10A PWRGD-D VINT 1.2V TB RAMP Doc.#DSFP-PS10 C080613 3 TC TD Supertex inc. www.supertex.com PS10 Functional Description The PS10 is designed to sequence up to 4 power supply modules, ICs or subsystems when the backplane voltage is within the programmed under voltage and over voltage limits. The power good open drain outputs are sequentially enabled starting from PWRGD-A to PWRGD-D. The time delay between power goods is programmable up to 200ms simply by changing the value(s) of RTB, RTC, and RTD. The initial time between satisfaction of the UV/OV supervisors & PWRGD-A can be programmed with CRAMP. The undervoltage and overvoltage shut down thresholds can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows: Description of Operation Where (VEEUV(off)) and (VEEOV(off)) relative to VEE are under and over voltage shut down threshold points. UVOFF = VUVL = 1.12 = (VEEUV(off)) x (R2+R3)/(R1+R2+R3) OVOFF = VOVL = 1.22 = (VEEOV(off)) x R3/(R1+R2+R3) During the initial power application, the Power Good pins are held low (rising with VIN). Once the internal under voltage lock out has been satisfied, the circuit checks the input supply under voltage (UV) and over voltage (OV) sense circuits to ensure that the input voltage is within programmed limits. These limits are determined by the selected values for R1, R2, and R3, which form a voltage divider. If we select a divider current of 100A at a nominal operating input voltage of 50V, then: R1+R2+R3 = 50V/100A = 500k From the second equation, for an OV shut down threshold of 65V, the value of R3 may be calculated. At the same time, a 10A current source is enabled, charging the external capacitor connected to the ramp pin. The rise time of the RAMP pin is determined by the value of the capacitor (10A/CRAMP). When the ramp voltage reaches 8.8V, the PWRGD-A pin will change into an active state. PWRGDB will change into an active state after a programmed time delay from PWRGD-A inactive to active transition. PWRGDC will change into an active state after a programmed time delay from PWRGD-B inactive to active transition. PWRGDD will change into an active state after a programmed time delay from PWRGD-C inactive to active transition. OVOFF = 1.22 = (65xR3)/500k R3 = (1.22x 500k)/65 = 9.38k The closest 1% value is 9.31k. From the first equation, for a UV shut down threshold of 35V, the value of R2 can be calculated. UVOFF = 1.12 = 35 x (R2+R3)/ 500k The controller continuously monitors the UV and OV pins as long as the internal UVLO and POR circuits are satis-fied. At any time during the start up cycle or thereafter, crossing the UV low and OV high limits will cause an im-mediate discharge on Cramp and reset on the power good pins. When the input voltage returns to a value within the programmed UV and OV limits, a new start up sequence will initiate immediately. R2 = ((1.12 x 500k)/35) - 9.76k = 6.69k 6.65k is a standard 1% value Then: R1 = 500k - R2 - R3 = 484.04k. 487k, is a standard 1% value. Programming the Under and Over Voltage Limits From the calculated resistor values the OV and UV start up threshold voltages can be calculated as follows: The UV and OV pins are connected to comparators with nominal 1.17V thresholds and 100mV of hysteresis (1.17V 50mV). They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above its high threshold (1.22V) or the UV pin falls below its low threshold (1.12V), the PWRGD outputs immediately deactivate. UVON = VUVH = 1.22 = (VEEUV(on)) x (R2+R3)/(R1+R2+R3) OVON = VOVL = 1.12 = (VEEOV(on)) x R3/(R1+R2+R3) Where (VEEUV(on)) and (VEEOV(on)) are under and over voltage start up threshold points relative to VEE. Calculations can be based on either the desired input voltage operating limits or the input voltage shutdown limits. In the following equations the shutdown limits are assumed. Doc.#DSFP-PS10 C080613 4 Supertex inc. www.supertex.com PS10 PWRGD Flags Delay Programming Then: When the ramp voltage hits VINT - 1.17V, PWRGD-A becomes active indicating that the input supply voltage is within the programmed limits. PWRGD-B goes active after a programmed time delay after PWRGD-A went active. PWRGDC goes active after a programmed time delay after PWRGDB went active. PWRGD-D goes active after a programmed time delay after PWRGD-C went active. (VEEUV(on)) = 1.22 x (R1+R2+R3)/(R2+R3) (VEEUV(on)) = 1.22 x (487k+6.65k+9.31k)/(6.65k+9.31k) = 38.45V And: The resistors connected from TB, TC, and TD to VEE pin determines the delay times between the PWRGD flags. (VEEOV(on)) = 1.12 x (R1+R2+R3)/R3 (VEEOV(on)) = 1.12 x (487k +6.65k +9.31k)/9.31k The value of the resistors determines the capacitor charging and discharging current of a triangular wave oscillator. The oscillator output is fed into an 8-bit counter to generate the desired time delay. = 60.51V Therefore, the circuit will start when the input supply voltage is in the range of 38.45V to 60.51V. The respective time delay is defined by the following equation: Undervoltage/Overvoltage Protection tTX = (255 x 2 x COSC x VPP)/ICD GND and UVOFF UVON ICD = VBG / (4 x RTX) VIN Where: OVON OVOFF PWRGD SET tTX = Time delay between respective PWRGD flags COSC = 120pF (internal oscillator capacitor) VPP = 8.2V (peak-to-peak voltage swing of oscillator) ICD = Charge and discharge current of oscillator VBG = 1.17V (internal band gap reference) RTX = Programming resistor at TB, TC, or TD RESET tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going active. It can be approximated by: Combining the two equations and solving for RTX yields: RTX = (VBG x tTX) / (2040 x COSC x VPP) tPWRGD-A = CRAMP x (VINT-1.17)/IRAMP = 0.585 x 106 x tTX where: For a time delay of 200ms CRAMP = capacitor connected from RAMP pin to VEE pin VINT = internal regulated power supply voltage (10V typ.) IRAMP = 10A charge current RTX = 0.585 x 106 x 0.2 = 117k For a time delay of 5ms RTX = 0.585 x 106 x 0.005 = 2.925k Doc.#DSFP-PS10 C080613 5 Supertex inc. www.supertex.com PS10 PWRGD Output Configuration The PS10 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter. The internal pull-up and clamp of the DC/DC converter sets the logic High Enable/Disable voltage. GND 487k VIN UV PWRGD-C COM TB RTB -48V +3.3V EN PWRGD-A OV 9.76k DC/DC Converter PWRGD-B PS10 6.81k VEE V+ PWRGD-D TC RTD RTC V- RAMP TD 10nF Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. Opto-isolated Enable Some applications require opto-isolator interface to the Enable pin of the DC/DC converter. GND 487K 49.9k VIN V+ PWRGD-D UV PWRGD-C PS10 6.81K OV Opto-coupler PWRGD-B EN PWRGD-A DC/DC Converter +3.3V COM V- VEE 9.76K RTB -48V Doc.#DSFP-PS10 C080613 TB TC RTC TD RTD RAMP 10nF Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 6 Supertex inc. www.supertex.com PS10 Increasing the Under and Over Voltage Hysteresis If the internal UV hysteresis is insufficient for a particular system application, then it may be increased by using separate resis-tor dividers for UV and OV and providing a resistor feedback from UV pin to the PWRGD pin. GND 487k 499k VIN PWRGD-D UV PWRGD-C R UVHYS PS10 OV VEE 16.5k V+ PWRGD-B PWRGD-A DC/DC Converter +3.3V EN COM TC TB TD RAMP V- 9.76k RTB -48V RTC 10nF RTD Notes: 1. Other power good outputs will have the same configuration as: PWGRGD-A for Active High Enabled Converters. 2. Over voltage shut down set to 63.6V RUVHYS can be calculated based on higher UV On voltage (say 42V): RUVHYS = (VUVON - VDIODE - VPWRGDLOW )/((VIN - VUVON )/487k - VUVON /16.5k) = (1.22-0.65-0.4)/((42-1.22)/487k - 1.22/16.5k) = 17.35k Doc.#DSFP-PS10 C080613 7 Supertex inc. www.supertex.com PS10 Pin Description Pin Function 1 PWRGD-D Description This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-C goes active. To function as an indicator, a pullup resistor must be connected from this pin to a voltage rail no more than 90V from VEE. 2 PWRGD-C This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-B goes active. 3 PWRGD-B This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-A goes active. 4 PWRGD-A This open drain Power Good Output Pin is held inactive on initial power application and goes active one POR delay after the UV pin goes above its High threshold (provided VIN stays within the UV/OV window during this period). 5 OV This Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. 6 UV This Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin rises above the low threshold limit, initiating a new start-up cycle. 7 VEE 8 NC 9 NC 10 RAMP This pin provides a current output so that a timing ramp is generated when a capacitor is connected. This timing Ramp is used to program POR and the time from satisfaction of the UV/OV supervisors to PWRGD-A. 11 TB The resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active to PWRGD-B going active. 12 TC The resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active to PWRGD-C going active. 13 TD The resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active to PWRGD-D going active. 14 VIN This pin is the positive terminal of the power supply input to the circuit and can withstand 90V with respect to VEE. Doc.#DSFP-PS10 C080613 This pin is the negative terminal of the power supply input to the circuit. No Connect. This pin can be grounded or left floating. 8 Supertex inc. www.supertex.com PS10 14-Lead SOIC (Narrow Body) Package Outline (NG) 8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch D 1 14 Note 1 (Index Area D/2 x E1/2) E1 E Gauge Plane L2 e 1 L1 b Top View L Seating Plane View B View B A h h A A2 Seating Plane A1 Side View View A-A A Note: 1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A MIN 1.35* Dimension NOM (mm) MAX 1.75 A1 A2 b 0.10 1.25 0.31 - - - 0.25 1.65* 0.51 D E E1 8.55* 5.80* 3.80* 8.65 6.00 3.90 8.75* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 L2 1.04 REF 0.25 BSC 1 0O 5O - - 8O 15O JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-14SOICNG, Version F041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. (c)2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.#DSFP-PS10 C080613 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com