Supertex inc.
Supertex inc.
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Doc.#DSFP-PS10
C080613
PS10
Features
►Sequencing of four supplies, ICs, or subsystems
►Independently programmable delays between open
drain PWRGD ags (5.0 to 200ms)
►±10 to ±90V operation
►Tracking in combination with Schottky diodes
►Input supervisors including:
• UV/OV lock out/enable
• Power-on-Reset (POR)
►Low power consumption, 0.4mA supply current
►Available in a space saving 14-Lead SOIC package
Applications
►Power supply sequencing
►-48V telecom and networking distributed systems
►-24V cellular and xed wireless systems
►-24V PBX systems
►+48V storage systems
►FPGA, microprocessor tracking
►Industrial/embedded system timing/sequencing
►High voltage MEMs driver’s supply sequencing
►High voltage display driver’s supply sequencing
General Description
Many of today’s high performance FPGA’s, microprocessors,
DSP and industrial/embedded subsystems require sequencing
of the input power. Historically this has been accomplished
by: i) discretely using comparators, references & RC circuits;
ii) using expensive programmable controllers; or iii) with low
voltage sequencers requiring resistor drop downs and several
high voltage optocoupler or level shift components.
The PS10 saves board space, improves accuracy, eliminates
optocouplers or level shifts and reduces overall component
count by combining four timers, programmable input UV/OV
supervisors, a programmable POR, and four 90V open drain
outputs. A high reliability, high voltage, junction isolated process
allows the PS10 to be connected directly across the high voltage
input rails.
The power-on-reset interval (POR) may be programmed by a
capacitor on CRAMP
. To sequence additional systems, multiple
PS10s may be daisy-chained together. If at any time the input
supply falls outside the UV/OV detector range, the PWRGD
outputs will immediately become IN-ACTIVE.
The PS10 is available in a space saving 14-Lead SOIC package.
Typical Application Circuit
Quad Power
Sequencing Controller
RTB
9.76kΩ
6.81kΩ
487kΩ
RTD
RTC
COM
COM
COM
+2.5V
+3.3V
+5V
+12V
COM
-48V or GND
GND or +48V
Notes:
1. Under Voltage Shutdown (UV) set to 37V.
2. Over Voltage Shutdown (OV) to 57.8V.
10nF
13 10
4
3
2
1
14
6
5
7
11 12
TB
OV
UV
VIN
TC
PWRGD-C
PWRGD-D
TD
PWRGD-A
PWRGD-B
PS10
RAMP
VEE
/EN
DC/DC
Converter
/EN
DC/DC
Converter
/EN
DC/DC
Converter
/EN
DC/DC
Converter
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C080613
PS10
Absolute Maximum Ratings
Parameter Value
VEE referenced to VIN pin +0.3V to -100V
VPWRGD referenced to VEE voltage -0.3V to +100V
VUV and VOV referenced to VEE voltage -0.3V to 12V
Operating ambient temperature -40°C to +85°C
Operating junction temperature -40°C to +125°C
Storage temperature range -65° to +150°C
Power dissipation @ 25OC750mW
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
PWRGD Logic
Condition PWRGD-A/B/C/D
Inactive (not ready) 0 VEE
Active (ready) 1 Hi Z
Pin Conguration
Product Marking
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
PS10NG
YWW LLLLLLLL
CCCCCCCCC AAA
14-Lead SOIC
Electrical Characteristics (-10V ≤ VIN ≤ -90V, TA = 25°C unless otherwise specied)
1 14
14-Lead SOIC
(top view)
Sym Parameter Min Typ Max Units Conditions
Supply (Referenced to VIN pin)
VEE Supply voltage - -90 --10 V ---
IEE Supply current - - 400 450 µA VEE = -48V
OV and UV Control (Referenced to VEE pin)
VUVH UV high threshold #1.16 1.22 1.28 V Low to high transition
VUVL UV low threshold #1.06 1.12 1.18 V High to low transition
VUVHY UV hysteresis # - 100 -mV ---
IUV UV input current - - - 1.0 nA VUV = VEE + 1.9V
VOVH OV high threshold #1.16 1.22 1.28 V Low to high transition
VOVL OV low threshold #1.06 1.12 1.18 V High to low transition
VOVHY OV hysteresis # - 100 -mV ---
IOV OV input current - - - 1.0 nA VUV = VEE + 1.9V
# Specications apply over 0OC ≤ TA ≤ 70OC
Package may or may not include the following marks: Si or
Ordering Information
Part Number Package Option Packing
PS10NG-G 14-Lead SOIC 53/Tube
PS10NG-G-G M905 14-Lead SOIC 2500/Reel
-G indicates package is RoHS compliant (‘Green’)
Typical Thermal Resistance
Package θja
14-Lead SOIC 75OC/W*
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C080613
PS10
Functional Block Diagram
Electrical Characteristics (cont.) (-10V ≤ VIN ≤ -90V, TA = 25°C unless otherwise specied)
Sym Parameter Min Typ Max Units Conditions
Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V)
IRAMP Ramp pin output current - - 10 -µA ---
tPWRGD-A Time from UV high to PWRGD-A - - 8.8 - ms
VEE = -48V,
CRAMP = 10nF, see
typical application circuit
tPWRGD-B Maximum time from PWRGD-A to PWRGD-B -150 200* 250 ms RTB = 120kΩ
tPWRGD-B Minimum time from PWRGD-A to PWRGD-B -3.0 5.0* 8.0 ms RTD = 3.0kΩ
tPWRGD-C Maximum time from PWRGD-B to PWRGD-C -150 200* 250 ms RTB = 120kΩ
tPWRGD-C Minimum time from PWRGD-B to PWRGD-C -3.0 5.0* 8.0 ms RTD = 3.0kΩ
tPWRGD-D Maximum time from PWRGD-C to PWRGD-D -150 200* 250 ms RTB = 120kΩ
tPWRGD-D Minimum time from PWRGD-C to PWRGD-D - 3.0 5.0* 8.0 ms RTD = 3.0kΩ
* Variations will track. For example if tPWRGD-A is 250ms, then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version.
Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V)
VPWRGD-X(hi) Power good pin breakdown voltage - 90 - - V PWRGD-X = HI Z
VPWRGD-X(lo) Power good pin output low voltage - - 0.4 0.5 V IPWRGD = 1.0mA,
PWRGD-X = LOW
IPWRGD-X(lk) Maximum leakage current - - <1.0 10 µA VPWRGD = 90V,
PWRGD-X = HI Z
Regulator &
POR
+
UVLO
VBG
UV - VIN
VEE
Band Gap
Reference
Programmable
Timer
TD
PWRGD-B
PWRGD-A
PWRGD-C
PWRGD-D
TC
TB
10µA
VINT
RAMP
-
+
+
-
OV
VINT
1.2V
VINT
Logic
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C080613
PS10
Functional Description
The PS10 is designed to sequence up to 4 power supply
modules, ICs or subsystems when the backplane voltage
is within the programmed under voltage and over voltage
limits. The power good open drain outputs are sequentially
enabled starting from PWRGD-A to PWRGD-D. The time
delay between power goods is programmable up to 200ms
simply by changing the value(s) of RTB, RTC, and RTD. The
initial time between satisfaction of the UV/OV supervisors &
PWRGD-A can be programmed with CRAMP
.
Description of Operation
During the initial power application, the Power Good pins
are held low (rising with VIN). Once the internal under voltage
lock out has been satised, the circuit checks the input sup-
ply under voltage (UV) and over voltage (OV) sense circuits
to ensure that the input voltage is within programmed limits.
These limits are determined by the selected values for R1,
R2, and R3, which form a voltage divider.
At the same time, a 10µA current source is enabled, charging
the external capacitor connected to the ramp pin. The rise
time of the RAMP pin is determined by the value of the ca-
pacitor (10µA/CRAMP). When the ramp voltage reaches 8.8V,
the PWRGD-A pin will change into an active state. PWRGD-
B will change into an active state after a programmed time
delay from PWRGD-A inactive to active transition. PWRGD-
C will change into an active state after a programmed time
delay from PWRGD-B inactive to active transition. PWRGD-
D will change into an active state after a programmed time
delay from PWRGD-C inactive to active transition.
The controller continuously monitors the UV and OV pins as
long as the internal UVLO and POR circuits are satis-ed.
At any time during the start up cycle or thereafter, crossing
the UV low and OV high limits will cause an im-mediate dis-
charge on Cramp and reset on the power good pins. When
the input voltage returns to a value within the programmed
UV and OV limits, a new start up sequence will initiate im-
mediately.
Programming the Under and Over Voltage
Limits
The UV and OV pins are connected to comparators with
nominal 1.17V thresholds and 100mV of hysteresis (1.17V
±50mV). They are used to detect under voltage and over
voltage conditions at the input to the circuit. Whenever the
OV pin rises above its high threshold (1.22V) or the UV pin
falls below its low threshold (1.12V), the PWRGD outputs
immediately deactivate.
Calculations can be based on either the desired input volt-
age operating limits or the input voltage shutdown limits. In
the following equations the shutdown limits are assumed.
The undervoltage and overvoltage shut down thresholds
can be programmed by means of the three resistor divider
formed by R1, R2 and R3. Since the input currents on the
UV and OV pins are negligible the resistor values may be
calculated as follows:
UVOFF = VUVL = 1.12 = (VEEUV(off)) x (R2+R3)/(R1+R2+R3)
OVOFF = VOVL = 1.22 = (VEEOV(off)) x R3/(R1+R2+R3)
Where (VEEUV(off)) and (VEEOV(off)) relative to VEE are under and
over voltage shut down threshold points.
If we select a divider current of 100µA at a nominal oper-
ating input voltage of 50V, then:
R1+R2+R3 = 50V/100µA = 500kΩ
From the second equation, for an OV shut down threshold of
65V, the value of R3 may be calculated.
OVOFF = 1.22 = (65xR3)/500kΩ
R3 = (1.22x 500kΩ)/65 = 9.38kΩ
The closest 1% value is 9.31kΩ.
From the rst equation, for a UV shut down threshold of 35V,
the value of R2 can be calculated.
UVOFF = 1.12 = 35 x (R2+R3)/ 500kΩ
R2 = ((1.12 x 500kΩ)/35) – 9.76kΩ = 6.69kΩ
6.65kΩ is a standard 1% value
Then:
R1 = 500kΩ – R2 – R3 = 484.04kΩ.
487kΩ, is a standard 1% value.
From the calculated resistor values the OV and UV start up
threshold voltages can be calculated as follows:
UVON = VUVH = 1.22 = (VEEUV(on)) x (R2+R3)/(R1+R2+R3)
OVON = VOVL = 1.12 = (VEEOV(on)) x R3/(R1+R2+R3)
Where (VEEUV(on)) and (VEEOV(on)) are under and over voltage
start up threshold points relative to VEE.
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C080613
PS10
Then:
(VEEUV(on)) = 1.22 x (R1+R2+R3)/(R2+R3)
(VEEUV(on)) = 1.22 x (487k+6.65k+9.31k)/(6.65k+9.31k)
= 38.45V
And:
(VEEOV(on)) = 1.12 x (R1+R2+R3)/R3
(VEEOV(on)) = 1.12 x (487kΩ +6.65kΩ +9.31kΩ)/9.31kΩ
= 60.51V
Therefore, the circuit will start when the input supply voltage
is in the range of 38.45V to 60.51V.
Undervoltage/Overvoltage Protection
tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going
active. It can be approximated by:
tPWRGD-A = CRAMP x (VINT-1.17)/IRAMP
where:
CRAMP = capacitor connected from RAMP pin to VEE pin
VINT = internal regulated power supply voltage (10V typ.)
IRAMP = 10µA charge current
PWRGD Flags Delay Programming
When the ramp voltage hits VINT - 1.17V, PWRGD-A be-
comes active indicating that the input supply voltage is within
the programmed limits. PWRGD-B goes active after a pro-
grammed time delay after PWRGD-A went active. PWRGD-
C goes active after a programmed time delay after PWRGD-
B went active. PWRGD-D goes active after a programmed
time delay after PWRGD-C went active.
The resistors connected from TB, TC, and TD to VEE pin
determines the delay times between the PWRGD ags.
The value of the resistors determines the capacitor charging
and discharging current of a triangular wave oscillator. The
oscillator output is fed into an 8-bit counter to generate the
desired time delay.
The respective time delay is dened by the following equa-
tion:
tTX = (255 x 2 x COSC x VPP)/ICD
and
ICD = VBG / (4 x RTX)
Where:
tTX = Time delay between respective PWRGD ags
COSC = 120pF (internal oscillator capacitor)
VPP = 8.2V (peak-to-peak voltage swing of oscillator)
ICD = Charge and discharge current of oscillator
VBG = 1.17V (internal band gap reference)
RTX = Programming resistor at TB, TC, or TD
Combining the two equations and solving for RTX yields:
RTX = (VBG x tTX) / (2040 x COSC x VPP)
= 0.585 x 106 x tTX
For a time delay of 200ms
RTX = 0.585 x 106 x 0.2 = 117kΩ
For a time delay of 5ms
RTX = 0.585 x 106 x 0.005 = 2.925kΩ
GND
UVOFF
UVON
VIN
OVON
OVOFF
PWRGD SET RESET
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C080613
PS10
PWRGD Output Conguration
The PS10 open drain power good outputs can be connect-
ed directly to the Enable pins of the DC/DC converter. The
internal pull-up and clamp of the DC/DC converter sets the
logic High Enable/Disable voltage.
Opto-isolated Enable
Some applications require opto-isolator interface to the En-
able pin of the DC/DC converter.
COM
+3.3V
RTB
9.76kΩ
6.81kΩ
487kΩ
RTD
RTC
-48V
GND
Notes:
1. Under Voltage Shutdown (UV) set to 37V.
2. Over Voltage Shutdown (OV) to 57.8V.
3. Other power good outputs will have the same configuration
as PWGRGD-A for Active High Enabled Converters.
10nF
V-
V+ DC/DC
Converter
EN
TB
OV
UV
VIN
TC
PWRGD-C
PWRGD-D
TD
PWRGD-A
PWRGD-B
PS10
RAMP
VEE
Opto-coupler
49.9kΩ
EN
DC/DC
Converter
COM
V-
+3.3V
V+
RTB
9.76KΩ
6.81KΩ
487KΩ
RTD
RTC
-48V
Notes:
1. Under Voltage Shutdown (UV) set to 37V.
2. Over Voltage Shutdown (OV) to 57.8V.
3. Other power good outputs will have the same configuration
as PWGRGD-A for Active High Enabled Converters.
10nF
TB
OV
UV
VIN
TC
PWRGD-C
PWRGD-D
TD
PWRGD-A
PWRGD-B
PS10
RAMP
VEE
GND
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C080613
PS10
Increasing the Under and Over Voltage
Hysteresis
If the internal UV hysteresis is insufcient for a particular
system application, then it may be increased by using sepa-
rate resis-tor dividers for UV and OV and providing a resistor
feedback from UV pin to the PWRGD pin.
COM
+3.3V
RTB
16.5kΩ
9.76kΩ
487kΩ
RTD
RTC
-48V
GND
Notes:
1. Other power good outputs will have the same configuration as:
PWGRGD-A for Active High Enabled Converters.
2. Over voltage shut down set to 63.6V
10nF
V-
V+
DC/DC
Converter
EN
R
UVHYS
499kΩ
RUVHYS can be calculated based on higher UV On voltage (say 42V):
RUVHYS = (VUVON - VDIODE - VPWRGDLOW )/((VIN - VUVON )/487kΩ - VUVON/16.5kΩ)
= (1.22-0.65-0.4)/((42-1.22)/487kΩ - 1.22/16.5kΩ)
= 17.35kΩ
TB
OV
UV
VIN
TC
PWRGD-C
PWRGD-D
TD
PWRGD-A
PWRGD-B
PS10
RAMP
VEE
8
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C080613
PS10
Pin Function Description
1 PWRGD-D This open drain Power Good Output Pin is held inactive on initial power application
and goes active a programmed time delay after PWRGD-C goes active. To function as
an indicator, a
pullup resistor
must be
connected from
this pin to a
voltage rail no
more than 90V
from VEE.
2PWRGD-C This open drain Power Good Output Pin is held inactive on initial power application
and goes active a programmed time delay after PWRGD-B goes active.
3 PWRGD-B This open drain Power Good Output Pin is held inactive on initial power application
and goes active a programmed time delay after PWRGD-A goes active.
4 PWRGD-A
This open drain Power Good Output Pin is held inactive on initial power application
and goes active one POR delay after the UV pin goes above its High threshold
(provided VIN stays within the UV/OV window during this period).
5 OV
This Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause the
Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin falls
below the low threshold limit, initiating a new start-up cycle.
6UV
This Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause the
Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin rises
above the low threshold limit, initiating a new start-up cycle.
7VEE This pin is the negative terminal of the power supply input to the circuit.
8NC No Connect. This pin can be grounded or left oating.
9NC
10 RAMP
This pin provides a current output so that a timing ramp is generated when a capacitor is connected.
This timing Ramp is used to program POR and the time from satisfaction of the UV/OV supervisors
to PWRGD-A.
11 TB The resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active to
PWRGD-B going active.
12 TC The resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active to
PWRGD-C going active.
13 TD The resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active to
PWRGD-D going active.
14 VIN This pin is the positive terminal of the power supply input to the circuit and can withstand 90V with
respect to VEE.
Pin Description
PS10
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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Doc.#DSFP-PS10
C080613
14-Lead SOIC (Narrow Body) Package Outline (NG)
8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 8.55* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM ----8.65 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 8.75* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-14SOICNG, Version F041309.
Top View
Side View View A-A
View B
A
A
Seating
Plane
14
1
Seating
Plane
Gauge
Plane
L
L1
L2
θ1
θ
View B
h
h
b
AA2
A1
e
E
E1
D
Note 1
(Index Area
D/2 x E1/2)
Note:
1. This chamfer feature is optional. If it is not present, then a Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be:
a molded mark/identier; an embedded metal marker; or a printed indicator.
