KM44V16004BK-5 - Samsung Electronics

KM44V16004B, KM44V16104B CMOS DRAM

This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5, or -6), power consumption(Normal

or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh

capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated using Sam-

sung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Part Identification

- KM44V16004B/B-L(3.3V, 8K Ref.)

- KM44V16104B/B-L(3.3V, 4K Ref.)

• Extended Data Out Mode operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• Fast parallel test mode capability

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic SOJ and TSOP(II) packages

• +3.3V±0.3V power supply

Control

Clocks

RAS

CAS

Vcc

Vss

A0~A12

(A0~A11)*1

A0~A10

(A0~A11)*1

Memory Array

16,777,216 x 4

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

16M x 4bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Note) *1 : 4K Refresh

• Refresh Cycles

Part

NO. Refresh

cycle Refresh time

Normal L-ver

KM44V16004B* 8K 64ms 128ms

KM44V16104B 4K

Unit : mW

Sense Amps & I/O

DQ0

DQ3

Data out

Buffer

Data in

Buffer

* Access mode & RAS only refresh mode

: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

• Active Power Dissipation

Speed 8K 4K

-45 360 468

-5 324 432

-6 288 396

• Performance Range

Speed tRAC tCAC tRC tHPC

-45 45ns 12ns 74ns 17ns

-5 50ns 13ns 84ns 20ns

-6 60ns 15ns 104ns 25ns

Row Decoder

Column Decoder

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

KM44V16004B, KM44V16104B CMOS DRAM

VCC

DQ0

DQ1

N.C

RAS

VCC

VSS

DQ3

DQ2

N.C

CAS

A12(N.C)*

A11

A10

VSS

PIN CONFIGURATION (Top Views)

* (N.C) : N.C for 4K Refresh product

Pin Name Pin Function

A0 - A12 Address Inputs(8K Product)

A0 - A11 Address Inputs(4K Product)

DQ0 - 3 Data In/Out

VSS Ground

RAS Row Address Strobe

CAS Column Address Strobe

WRead/Write Input

OE Data Output Enable

VCC Power(+3.3V)

N.C No Connection

(S : 400mil TSOP(II))

VCC

DQ0

DQ1

N.C

RAS

VCC

VSS

DQ3

DQ2

N.C

CAS

A12(N.C)*

A11

A10

VSS

(K : 400mil SOJ)

• KM44V160(1)04BK • KM44V160(1)04BS

KM44V16004B, KM44V16104B CMOS DRAM

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -0.5 to +6.5 V

Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V

Storage Temperature Tstg -55 to +150 °C

Power Dissipation PD1W

Short Circuit Output Current IOS Address 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : 6.5V at pulse width ≤15ns which is measured at VCC

*2 : -1.3 at pulse width ≤15ns which is measured at VSS

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 3.0 3.3 3.6 V

Ground VSS 0 0 0 V

Input High Voltage VIH 2.0 -+5.5*1 V

Input Low Voltage VIL -0.3*2 -0.8 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,

all other pins not under test=0 Volt) II(L) -5 5uA

Output Leakage Current

(Data out is disabled, 0V≤VOUT≤VCC)IO(L) -5 5uA

Output High Voltage Level(IOH=-2mA) VOH 2.4 -V

Output Low Voltage Level(IOL=2mA) VOL -0.4 V

KM44V16004B, KM44V16104B CMOS DRAM

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.

ICC is specified as an average current. In I CC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In I CC4,

address can be changed maximum once within one EDO mode cycle time, tHPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current ( RAS and CAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Extended Data Out Mode Current (RAS=VIL, CAS, Address cycling @ tHPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V

W, OE=VIH, Address=Don ′t care, DQ=Open, TRC=31.25us

ICCS : Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open

Symbol Power Speed Max Units

KM44V16004B KM44V16104B

ICC1 Don′t care -45

-5

-6

100

130

120

110

ICC2 Normal

L Don′t care 2

2mA

ICC3 Don′t care -45

-5

-6

100

130

120

110

ICC4 Don′t care -45

-5

-6

110

100

120

110

100

ICC5 Normal

LDon′t care 500

300 500

300 uA

ICC6 Don′t care -45

-5

-6

100

130

120

110

ICC7 LDon′t care 400 400 uA

ICCS LDon′t care 400 400 uA

KM44V16004B, KM44V16104B CMOS DRAM

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 -5pF

Input capacitance [RAS, CAS, W, OE]CIN2 -7pF

Output capacitance [DQ0 - DQ3] CDQ -7pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition : V CC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

Parameter Symbol -45 -5 -6 Units Note

Min Max Min Max Min Max

Random read or write cycle time tRC 74 84 104 ns

Read-modify-write cycle time tRWC 101 113 138 ns

Access time from RAS tRAC 45 50 60 ns 3,4,10

Access time from CAS tCAC 12 13 15 ns 3,4,5

Access time from column address tAA 23 25 30 ns 3,10

CAS to output in Low-Z tCLZ 333ns 3

Output buffer turn-off delay from CAS tCEZ 3 13 3 13 3 13 ns 6,14

OE to output in Low-Z tOLZ 333ns 3

Transition time (rise and fall) tT1 50 1 50 1 50 ns 2

RAS precharge time tRP 25 30 40 ns

RAS pulse width tRAS 45 10K 50 10K 60 10K ns

RAS hold time tRSH 8 8 10 ns

CAS hold time tCSH 35 38 40 ns

CAS pulse width tCAS 75K 810K 10 10K ns

RAS to CAS delay time tRCD 11 33 11 37 14 45 ns 4

RAS to column address delay time tRAD 9 22 9 25 12 30 ns 10

CAS to RAS precharge time tCRP 555ns

Row address set-up time tASR 000ns

Row address hold time tRAH 7 7 10 ns

Column address set-up time tASC 000ns

Column address hold time tCAH 7 7 10 ns

Column address to RAS lead time tRAL 23 25 30 ns

Read command set-up time tRCS 000ns

Read command hold time referenced to CAS tRCH 000ns 8

Read command hold time referenced to RAS tRRH 000ns 8

Write command hold time tWCH 7 7 10 ns

Write command pulse width tWP 6 7 10 ns

Write command to RAS lead time tRWL 8 8 10 ns

Write command to CAS lead time tCWL 7 7 10 ns

Data set-up time tDS 000ns 9

KM44V16004B, KM44V16104B CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter Symbol -45 -5 -6 Units Note

Min Max Min Max Min Max

Data hold time tDH 7 7 10 ns 9

Refresh period (Normal) tREF 64 64 64 ms

Refresh period (L-ver) tREF 128 128 128 ms

Write command set-up time tWCS 000ns 7

CAS to W delay time tCWD 24 27 32 ns 7

RAS to W delay time tRWD 57 64 77 ns 7

Column address to W delay time tAWD 35 39 47 ns 7

CAS set-up time (CAS -before-RAS refresh) tCSR 555ns

CAS hold time (CAS -before-RAS refresh) tCHR 10 10 10 ns

RAS to CAS precharge time tRPC 555ns

Access time from CAS precharge tCPA 24 28 35 ns 3

Hyper Page cycle time tHPC 17 20 25 ns 13

Hyper Page read-modify-write cycle time tHPRWC 47 47 56 ns 13

CAS precharge time (Hyper page cycle) tCP 6.5 710 ns

RAS pulse width (Hyper page cycle) tRASP 45 200K 50 200K 60 200K ns

RAS hold time from CAS precharge tRHCP 24 30 35 ns

OE access time tOEA 12 13 15 ns

OE to data delay tOED 810 13 ns

CAS precharge to W delay time tCPWD 36 41 52 ns

Output buffer turn off delay time from OE tOEZ 3 11 3 13 313 ns 6

OE command hold time tOEH 555ns

Write command set-up time (Test mode in) tWTS 10 10 10 ns 11

Write command hold time (Test mode in) tWTH 10 10 10 ns 11

W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns

W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns

Output data hold time tDOH 455ns

Output buffer turn off delay from RAS tREZ 3 13 3 13 313 ns 6,14

Output buffer turn off delay from WtWEZ 3 13 3 13 313 ns 6

W to data delay tWED 815 15 ns

OE to CAS hold time tOCH 555ns

CAS hold time to OE tCHO 555ns

OE precharge time tOEP 555ns

W pulse width (Hyper Page Cycle) tWPE 555ns

RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 15,16,17

RAS precharge time (C-B-R self refresh) tRPS 74 90 110 ns 15,16,17

CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 15,16,17

KM44V16004B, KM44V16104B CMOS DRAM

TEST MODE CYCLE

Parameter Symbol -45 -5 -6 Units Note

Min Max Min Max Min Max

Random read or write cycle time tRC 79 89 109 ns

Read-modify-write cycle time tRWC 110 121 145 ns

Access time from RAS tRAC 50 55 65 ns 3,4,10,12

Access time from CAS tCAC 17 18 20 ns 3,4,5,12

Access time from column address tAA 28 30 35 ns 3,10,12

RAS pulse width tRAS 50 10K 55 10K 65 10K ns

CAS pulse width tCAS 12 10K 13 10K 15 10K ns

RAS hold time tRSH 18 18 20 ns

CAS hold time tCSH 39 43 50 ns

Column Address to RAS lead time tRAL 28 30 35 ns

CAS to W delay time tCWD 29 35 39 ns 7

RAS to W delay time tRWD 62 72 84 ns 7

Column Address to W delay time tAWD 40 47 54 ns 7

Hyper Page cycle time tHPC 22 25 30 ns 13

Hyper Page read-modify-write cycle time tHPRWC 52 53 61 ns 13

RAS pulse width (Hyper page cycle) tRASP 50 200K 55 200K 65 200K ns

Access time from CAS precharge tCPA 29 33 40 ns 3

OE access time tOEA 17 18 20 ns

OE to data delay tOED 13 18 20 ns

OE command hold time tOEH 13 18 20 ns

( Note 11 )

KM44V16004B, KM44V16104B CMOS DRAM

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between

VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.

Measured with a load equivalent to 1 TTL load and 100pF.

Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

Assumes that tRCD≥tRCD(max).

This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-

acteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the

duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle

and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the

condition of the data out is indeterminate.

Either tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle

and read-modify-write cycles.

Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.

If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

These specifications are applied in the test mode.

In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

tASC≥6ns, Assume tT = 2.0ns

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes

high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within

64ms before and after self refresh, in order to meet refresh specification.

For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

10.

11.

12.

13.

14.

15.

16.

17.

KM44V16004B, KM44V16104B CMOS DRAM

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VOH -

VOL -

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCRP

tRP

tCSH tRSHtRCD tCAS

tRAL

tASR tRAH tASC tCAH

tCRP

tAA

tOEA

tCLZ

tRAC

OPEN

tRCH

Don′t care

Undefined

tRAD

tRRH

DATA-OUT

tREZ

tRCS

READ CYCLE

tOEZ

tCEZ tWEZ

DQ0 ~ DQ3(7)

tOLZ

tCAC

KM44V16004B, KM44V16104B CMOS DRAM

tWCS

NOTE : D OUT = OPEN

WRITE CYCLE ( EARLY WRITE )

RAS VIH -

VIL -

VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VIH -

VIL -

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCRP

tRP

tCSH tRSHtRCD tCAS

tRAL

tRAD

tASR tRAH tASC tCAH

tCRP

Don′t care

Undefined

tWCH

tWP

CAS

tRWL

tCWL

tDS tDH

DATA-IN

DQ0 ~ DQ3(7)

KM44V16004B, KM44V16104B CMOS DRAM

NOTE : DOUT = OPEN

WRITE CYCLE ( OE CONTROLLED WRITE )

RAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VIH -

VIL -

DQ0 ~ DQ3(7)

COLUMN

ADDRESS

ROW

ADDRESS

tRAS tRC

tCRP

tRP

tCSH tRSHtRCD tCAS

tRAL

tRAD

tASR tRAH tASC tCAH

tCRP

tWP

Don′t care

Undefined

CAS VIH -

VIL -

tRWL

tCWL

tDH

tOEH

tOED

DATA-IN

tDS

KM44V16004B, KM44V16104B CMOS DRAM

READ - MODIFY - WRITE CYCLE

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VI/OH -

VI/OL -

DQ0 ~ DQ3(7)

ROW

ADDR

tRAS tRWC tRP

tRSHtRCD tCAS

tCSH

tRAD

tASR tRAH tASC tCAH

tCRP

VALID

tWP

Don′t care

tRWL

tCWL

tOEZ

tOEA

tOED

tAWD

tCWD

tRWD

DATA-OUT

Undefined

VALID

DATA-IN

tRAC

tAA

tCAC

tCLZ

tDS tDH

COLUMN

ADDRESS

tOLZ

KM44V16004B, KM44V16104B CMOS DRAM

tDOH

HYPER PAGE READ CYCLE

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

COLUMN

ADDRESS

ROW

ADDR

tRASP tRP

tRCD

tASR

tCRP

Don′t care

Undefined

VOH -

VOL -

DQ0 ~ DQ3(7)

tOEP

COLUMN

ADDRESS

tCAS tCAS tCAS tCAS

tCP tCP tCP

tHPC tHPC tHPC tRHCP

tCSH

tRAD

tRAH tASC tCAH tCAH tCAH tASC tCAH

tRCS

tAA

tRCH

tASC

COLUMN

ADDRESS COLUMN

ADDR

VALID

DATA-OUT

tOEZ

tOEA

tOEP

tAA

tCAC

tAA

tCPA

VALID

DATA-OUT VALID

DATA-OUT

tOEZ

tCLZ

tRAC

tOEA

tOLZ

tCAC

tRRH

tCHO

tREZ

tOEZ

tCAC

tOCH

tCPA

tCAC

VALID

DATA-OUT

¡ó

tASC

tAA

tRAL

tOEA

KM44V16004B, KM44V16104B CMOS DRAM

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

COLUMN

ADDRESS

ROW

ADDR.

tRASP tRP

tRCD

tASR

tCRP

Don′t care

HYPER PAGE WRITE CYCLE ( EARLY WRITE )

Undefined

VIH -

VIL -

DQ0 ~ DQ3(7)

tRHCP

tRAD

tRAH tCAH tCAH tASC tCAHtASC

VALID

DATA-IN

tDS

¡ó

COLUMN

ADDRESS COLUMN

ADDRESS

tCAS

tCP tCAS

tRSH

¡ó

tCSH

tASC

¡ó

tWP

tWCS tWCH

tWP

tWCS tWCH

tWP

tWCH

¡ó

VALID

DATA-IN VALID

DATA-IN

¡ó

tDH tDS tDH tDS tDH

tCWL tCWL tCWL

tRWL

NOTE : DOUT = OPEN

tHPC tHPC

tWCS

tRAL

KM44V16004B, KM44V16104B CMOS DRAM

Don′t care

HYPER PAGE READ-MODIFY-WRITE CYCLE

Undefined

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

VI/OH -

VI/OL -

ROW

ADDR

tCSH tRASP tRP

tASR

tRCD tCP

tRAD

tCAH

tWP

tDH

COL.

ADDR COL.

ADDR

tCAS tCAS

tCRP

tASC tCAH tRAL

tRCS tCWL

tCWD

tAWD

tRWD

tWP

tCWD

tAWD

tCWL

tRAC

tOEA

tCLZ

tOEZ

tCPWD

tOED

tASC

tCLZ

tOEA

tCACtAA tDH

tOED

tRWL

tCRP

tDS tOEZ

VALID

DATA-OUT VALID

DATA-IN VALID

DATA-OUT VALID

DATA-IN

tDS

DQ0 ~ DQ3(7)

tRSH

tOLZ tOLZ

tHPRWC

tCAC

tAA

tRAH

KM44V16004B, KM44V16104B CMOS DRAM

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

COLUMN

ADDRESS

ROW

ADDR

tRASP tRP

Don′t care

Undefined

VI/OH -

VI/OL -

DQ0 ~ DQ3(7)

tWEZ

tCP tCP

tHPC tHPC tHPC

tRAD tRAH

tASC tCAH tCAH tCAH tASC tCAH

tRCHtRCS tRCS tRCH

tASC

COLUMN

ADDRESS COL.

ADDR

VALID

DATA-OUT

tREZ

tAA

tWCS

VALID

DATA-OUT VALID

DATA-IN

tRAC

COL.

ADDR

tCAS

tASR

tCAStCAS tCAS

tASC

tCP

tRCH tWCH

tWPE

tCLZ

tCPA tWED

tAA tWEZ tDS

tDH

tCAC

tOEA

READ(tCAC)READ(tCPA)WRITE READ(tAA)

tRHCP

tRAL

tCLZ

KM44V16004B, KM44V16104B CMOS DRAM

Don′t care

RAS - ONLY REFRESH CYCLE*

NOTE : W, OE, DIN = Don′t care

Undefined

DOUT = OPEN

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL - ROW

ADDR

tRC tRP

tASR

tCRP

tRAS

tRAH

tRPC tCRP

OPEN

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE , A = Don′t care

RAS VIH -

VIL -

CAS VIH -

VIL -

tRC tRP

tRAS

tRPC

tCP

tRPC

tCSR tCHR

tCEZ

VOH -

VOL -

DQ0 ~ DQ3(7)

tWRP tWRH

WVIH -

VIL -

tRP

KM44V16004B, KM44V16104B CMOS DRAM

HIDDEN REFRESH CYCLE ( READ )

tOEZ

DATA-OUT

tRP

RAS VIH -

VIL -

CAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

ROW

ADDRESS

tRAS

tRC

tCHRtRCD tRSH

tRAD

tASR tRAH tASC

tCRP

Don′t care

Undefined

VOH -

VOL -

DQ0 ~ DQ3(7)

tWRH

COLUMN

ADDRESS

tOEA

tRAS

tRC

tCAH

tRCS

tAA

tRAC

tCLZ tCAC

tCEZ

OPEN

tRP

tWEZ

tREZ

tOLZ

* In Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.

tRAL

KM44V16004B, KM44V16104B CMOS DRAM

tCRP

tWCS

tRP

RAS VIH -

VIL -

AVIH -

VIL -

WVIH -

VIL -

OE VIH -

VIL -

ROW

ADDRESS

tRAS

tRC

tRAD

tASR tRAH tASC

Don′t care

HIDDEN REFRESH CYCLE ( WRITE )

Undefined

CAS VIH -

VIL -

VIH -

VIL -

DQ0 ~ DQ3(7)

tRSHtRCD

tWRH

COLUMN

ADDRESS

tRAS

tRC

tCHR

tCAH

tWRP

tDS

NOTE : DOUT = OPEN

tWP tWCH

DATA-IN

tDH

tRP

tRAL

KM44V16004B, KM44V16104B CMOS DRAM

OPEN

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE, A = Don′t care

RAS VIH -

VIL -

CAS VIH -

VIL -

tRPS

tRASS

tRPC

tCP

tRPC

tCSR

tCEZ

VOH -

VOL -

DQ0 ~ DQ3(7)

tRP

Don′t care

Undefined

tCHS

tWRP tWRH

WVIH -

VIL -

OPEN

TEST MODE IN CYCLE

NOTE : OE , A = Don′t care

RAS VIH -

VIL -

CAS VIH -

VIL -

tRP

tRC

tRPC

tCP

tRPC

tCSR

tOFF

VOH -

VOL -

DQ0 ~ DQ3(7)

tWTS tWTH

WVIH -

VIL -

tCHR

tRP tRAS

KM44V16004B, KM44V16104B CMOS DRAM

32 SOJ 400mil

0.400 (10.16)

0.435 (11.06)

0.445 (11.30)

0.830 (21.08)

0.820 (20.84)

MAX

0.841 (21.36)

MAX

0.148 (3.76)

0.032 (0.81)

0.026 (0.66)

0.021 (0.53)

0.015 (0.38)

0.027 (0.69)

0.012 (0.30)

0.006 (0.15)

0.360 (9.15)

0.380 (9.65)

MIN

#32

0.0375 (0.95) 0.050 (1.27)

Units : Inches (millimeters)

PACKAGE DIMENSION

32 TSOP(II) 400mil

0.455 (11.56)

0.471 (11.96)

0.829 (21.05)

0.821 (20.85)

MAX

0.841 (21.35)

0.037 (0.95) 0.050 (1.27)

Units : Inches (millimeters)

0.047 (1.20)

MIN

0.002 (0.05)

0.020 (0.50)

0.012 (0.30)

MAX

0.010 (0.25)

0.004 (0.10)

0.400 (10.16)

0~8

0.030 (0.75)

0.018 (0.45)

TYP

0.010 (0.25)