Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 TPS92690 N-Channel Controller for Dimmable LED Drives With Low-Side Current Sense 1 Features 3 Description * * * * * * * * * * * * * The TPS92690 device is a high-voltage, low-side NFET controller with an adjustable output current sense resistor voltage. Ideal for LED drivers, it contains all of the features needed to implement current regulators based on boost, SEPIC, flyback, and Cuk topologies. 1 Input Voltage Range from 4.5 to 75 V Adjustable Current Sense (50 to 500 mV) Low-Side Current Sensing 2- MOSFET Gate Driver Input Undervoltage Protection Output Overvoltage Protection Cycle-by-Cycle Current Limit PWM Dimming Input Programmable Oscillator Frequency External Synchronization Capability Slope Compensation Programmable Soft-Start Function HTSSOP (PWP), 16-Pin, Exposed Pad Package Output current regulation is based on peak currentmode control supervised by a control loop. This methodology eases the design of loop compensation while providing inherent input voltage feed-forward compensation. The TPS92690 device includes a high-voltage start-up regulator that operates over a wide input range between 4.5 and 75 V. The PWM controller is designed for high-speed capability including an oscillator frequency range up to 2 MHz. The TPS92690 device includes an error amplifier, precision reference, cycle-by-cycle current limit, and thermal shutdown. 2 Applications * * Device Information(1) LED Drivers Constant Current Regulator: Boost, Cuk, Flyback, and SEPIC PART NUMBER TPS92690 PACKAGE HTSSOP (16) BODY SIZE (NOM) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application VIN VOUT TPS92690 VOUT 1 nDIM VIN 16 2 OVP VCC 15 3 RT IS 14 4 SYNC GATE 13 5 SS/SD PGND 12 6 COMP CSP 11 7 AGND IADJ 10 8 ILIM VREF 9 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 17 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Applications ............................................... 20 9 Power Supply Recommendations...................... 31 9.1 Bench Supply Current Limit .................................... 31 10 Layout................................................................... 32 10.1 Layout Guidelines ................................................. 32 10.2 Layout Example .................................................... 33 11 Device and Documentation Support ................. 34 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 34 34 34 34 12 Mechanical, Packaging, and Orderable Information ........................................................... 34 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2012) to Revision A Page * Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 * Separated data sheet from TPS92690-Q1. For the TPS92690-Q1 data sheet, see SLVSCU0 on www.ti.com. .................. 1 2 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 5 Pin Configuration and Functions PWP Package 16-Pin HTSSOP With PowerPAD Top View nDIM 1 16 VIN OVP 2 15 VCC RT 3 14 IS SYNC 4 13 GATE SS/SD 5 12 PGND COMP 6 11 CSP AGND 7 10 IADJ ILIM 8 Thermal Pad 9 VREF Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 7 GND COMP 6 I Connect ceramic capacitor to GND to set loop compensation. CSP 11 I Connect to positive terminal of sense resistor in series with LED stack. GATE 13 O Connect to main N-channel MOSFET gate of switching converter. IADJ 10 I Connect resistor divider from VREF to set error amplifier reference voltage. ILIM 8 I Connect resistor divider from VREF to set current limit threshold voltage at IS pin. IS 14 I Connect to drain of main N-channel MOSFET or to source of MOSFET if sense resistor is used for improved accuracy. nDIM 1 I Connect resistor divider from VIN to set UVLO threshold and hysteresis. Connect through diode or MOSFET to PWM dim concurrently. OVP 2 I Connect resistor divider from output voltage to set OVP threshold and hysteresis. PGND 12 GND Connect to AGND through the exposed thermal pad for proper ground return path. RT 3 O Connect resistor to AGND to set base switching frequency. SS/SD 5 I Connect capacitor to AGND to set soft-start delay. Pull pin below 75 mV for low-power shutdown. SYNC 4 I Connect external PWM signal to set switching frequency. Must be higher than base frequency set at RT pin. Can also connect series resistor and capacitor to drain of main MOSFET and capacitor to AGND to implement zero-crossing detection for quasi-resonant topologies. In either case, a falling edge on SYNC triggers a new on-time at GATE. If tied to ground, internal oscillator is used. VCC 15 O Bypass with 2.2-F ceramic capacitor to provide bias supply for controller. VIN 16 I Connect to input supply of converter. Bypass with 100-nF ceramic capacitor to AGND as close to the device as possible. VREF 9 O Connect to the IADJ pin directly or through resistor divider. Bypass with 100-nF ceramic capacitor to AGND. Thermal Pad Connect to PGND through DAP exposed thermal pad for proper ground return path. GND Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 3 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings All voltages are with respect to GND, -40C < TJ = TA< 125C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) (1) Supply voltage Input voltage Output voltage MIN MAX UNIT VIN -0.3 76 V nDIM, OVP -0.3 76 IS (2) -0.3 76 CSP, IADJ, SS/SD, ILIM -0.3 6 VCC, GATE (3) -0.3 14 COMP, RT, VREF -0.3 6 IS Continuous input current Output current -1 1 mA SYNC 1 VREF -1 mA 150 C 150 C Storage Temperature (2) (3) (4) V -1 GATE Operating junction temperature, TJ (4) (1) V -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The IS pin can sustain -2 V for 100 ns without damage. the GATE pin can sustain -2.5 V for 100 ns. The VCC pin can sustain -2.5 V for 100 ns. Maximum junction temperature is internally limited. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VIN Input voltage 4.5 12 75 V TJ Operating junction temperature -40 25 125 C VIADJ(max) Maximum operating IADJ voltage 5 V 0 UNIT 6.4 Thermal Information TPS92690 THERMAL METRIC (1) PWP (TSSOP) UNIT 16 PINS RJA Junction-to-ambient thermal resistance 39.1 C/W RJC(top) Junction-to-case (top) thermal resistance 23.8 C/W RJB Junction-to-board thermal resistance 17.5 C/W JT Junction-to-top characterization parameter 0.6 C/W JB Junction-to-board characterization parameter 17.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 1.9 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 6.5 Electrical Characteristics -40C < TJ = TA < 125C, VIN = 14 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 7.45 UNIT STARTUP REGULATOR (VCC) VCCREG VCC regulation voltage ICC = 0 mA 6.35 6.9 ICCLIM VCC current limit VVCC = 0 V -20 -30 IQ Quiescent current ISD Shutdown current VCCUV VCC UVLO threshold VCCHYS VCC UVLO hysteresis 2 3 mA A VSS/SD = 0 V 45 65 VVCC rising 4.1 4.50 VVCC falling 3.61 V mA 4.01 83 V mV REFERENCE VOLTAGE OUTPUT VREF Reference voltage No load 2.4 2.45 2.5 V ERROR AMPLIFIER gM CSP input bias current -0.6 0 0.6 A COMP sink current 17.1 28.5 39.9 A -12.6 -16.8 -21 A COMP source current VIADJ = 5 V Transconductance VIADJ = 1 V, 0 V VCSP 0.8 V Transconductance bandwidth -6dB IADJ pin input impedance VCSP Error amplifier reference voltage Precise value implied in offset Error amplifier input offset voltage 33 A/V 1 MHz 1 M VIADJ/10 V VVCC = 4.5 V, 1 V VCOMP 1.4 V, TA = 25C -1.5 0 1.5 VVCC > 6 V, 1 V VCOMP 3 V, VIADJ 1.25 V, TA = 25C -1.8 0 1.8 VVCC > 6 V, 1 V VCOMP 3 V, VIADJ > 1.25 V, TA = 25C (% of ) -1.44 0 1.44 90% 94.4% 950 1100 mV VCSP% PWM COMPARATOR and SLOPE COMPENSATION DMAX Maximum duty cycle Internal oscillator only No slope added IS to PWM offset voltage IOFF D = DMAX (maximum slope added) IS source current No slope added IOFF + ISL 1250 125 D = DMAX (maximum slope added) mV -11.9 A -60 A CURRENT LIMIT ILIM delay to output tON(min) Leading edge blanking time Current limit off-timer 60 100 200 300 D = 50% ns s 38 ILIM offset voltage ns -19 -5.6 5 mV 30 86 mV 24 mV -10.8 A -1.1 A LOW POWER SHUTDOWN and SOFTSTART VSD Shutdown threshold voltage VSDH Shutdown hysteresis ISS SS/SD current source VSS/SD falling VSS/SD > (VSD + VSDH) VSS/SD < VSD OSCILLATOR and EXTERNAL SYNCHRONIZATION SW Switching frequency SYNC threshold voltage (falling edge triggers on-time) RRT = 121 k 312 350 389 RRT = 100 k 372 418 464 RRT = 84.5 k 436 490 544 2.05 2.36 Rising Falling 0.95 1.31 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 kHz V 5 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) -40C < TJ = TA < 125C, VIN = 14 V (unless otherwise noted) PARAMETER SYNC Clamp Voltage TEST CONDITIONS MIN TYP Positive 6.2 Negative -0.5 MAX UNIT V OVERVOLTAGE PROTECTION OVP OVLO threshold OVP hysteresis source current Rising Falling OVP active (high) 1.23 1.282 1.144 1.19 -14 -21.5 -28 1.23 1.285 V A PWM DIMMING INPUT and UVLO nDIM/UVLO threshold Rising Falling nDIM hysteresis current V 1.14 1.19 -14 -21.6 -28 A GATE DRIVER GATE sourcing resistance GATE = High 2.4 6 GATE sinking resistance GATE = Low 1 5 Peak GATE current Source Sink -0.47 A 1.1 A 175 C 25 C THERMAL SHUTDOWN TSD Thermal shutdown temperature TSD(hys) Thermal shutdown hysteresis 6 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 6.6 Typical Characteristics 95 95 93 93 Efficiency (%) Efficiency (%) Unless otherwise noted, -40C TA = TJ 125C, VVIN = 14 V, CBYP = 2.2 F, CCOMP = 0.1 F 91 89 87 91 89 87 12 LEDs 500mA 85 8 12 16 20 24 Input Voltage (V) 28 32 6 LEDs 500mA 85 36 8 10 12 Input Voltage (V) G000 Figure 1. Boost Efficiency vs Input Voltage 14 16 G000 Figure 2. Boost Efficiency vs Input Voltage 505 1000 Switching Frequency (kHz) 900 Output Current (mA) 503 501 499 497 12 LEDs 495 10 15 20 25 Input Voltage (V) 30 700 600 500 400 300 35 40 60 80 G000 Figure 3. Boost Line Regulation 100 120 RT Resistance (k) 140 160 G000 Figure 4. Switching Frequency vs RT Resistance 800 800 Output Current (mA) Output Current (mA) 800 600 400 600 400 200 200 1A Nominal 20 40 60 PWM Duty Cycle (%) 80 100 0.0 G000 Figure 5. 160-Hz Boost PWM Dimming 0.5 1.0 1.5 IADJ Voltage (V) 2.0 2.5 G000 Figure 6. IADJ Analog Dimming (RCS = 0.25 ) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 7 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise noted, -40C TA = TJ 125C, VVIN = 14 V, CBYP = 2.2 F, CCOMP = 0.1 F 95 430 94 425 Efficiency (%) Switching Frequency (kHz) 435 420 415 93 92 91 410 12V Input 36V Output @ 350mA 405 -40 -25 -10 5 20 35 50 65 80 Ambient Temperature (C) 95 90 -40 -25 -10 110 125 Figure 7. Switching Frequency vs Ambient Temperature (RT = 100 k) 95 110 125 G000 Figure 8. Efficiency vs Ambient Temperature 2.5 370 2.48 360 VREF Voltage (V) Output Current (mA) 5 20 35 50 65 80 Ambient Temperature (C) G000 350 340 2.46 2.44 2.42 12V Input 36V Output @ 350mA 330 -40 -25 -10 5 20 35 50 65 80 Ambient Temperature (C) 95 110 125 G000 Figure 9. Output Current vs Ambient Temperature 8 2.4 0 50 Ambient Temperature (C) 100 G000 Figure 10. VREF Voltage vs Ambient Temperature Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 7 Detailed Description 7.1 Overview The TPS92690 device is an N-channel MOSFET (NFET) controller for boost, SEPIC, Cuk, and flyback current regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a variety of LED loads. The low-side current sense, with low adjustable threshold voltage, provides an excellent method for regulating output current while maintaining high system efficiency. The TPS92690 device uses peak current mode control providing good noise immunity and an inherent cycle-bycycle current limit. The adjustable current sense threshold provides a way to analog dim the LED current, which can also be used to implement thermal foldback. The dual function nDIM pin provides a PWM dimming input that controls the main GATE output for PWM dimming the LED current also. When designing, the maximum attainable LED current is not internally limited because the TPS92690 device is a controller. Instead it is a function of the system operating point, component choices, and switching frequency allowing the TPS92690 device to easily provide constant currents up to 5 A. This simple controller contains all the features necessary to implement a high efficiency versatile LED driver. 7.2 Functional Block Diagram 6.9-V LDO Regulator VIN 75 mV VCC VCC UVLO UVLO (4.1 V) + SS/SD Reference 1.24 V Standby 20 A nDIM TLIM Thermal Limit 1.24 V + 100 NY + 1.24 V nUVLO 100 NY Reset Dominant Clock S SYNC VREF VCC Q GATE Oscillator Artificial Ramp RT PGND R COMP ISS nUVLO SS/SD SS/SD IADJ + gM Error Amplifier IOFF Fault 20 A ROFF + 9R AGND PWM Fault CSP LEB DMAX = 0.9 Standby RSL R ILIM + 40-s Latch IS OVP + 1.24 V ILIM LEB Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 9 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 7.3 Feature Description 7.3.1 Current Regulators Current regulators can be designed to accomplish different functions: boost, buck-boost, and flyback. The TPS92690 device is designed to drive a ground referenced N-channel FET and sense a ground referenced LED load. This control architecture is perfect for driving boost, SEPIC, flyback, or Cuk topologies. It does not work with a floating buck or buck-boost topology since the LED current sense amplifier is ground referenced. Looking at the boost design in the Typical Boost Application, the basic operation of a current regulator can be analyzed. During the time that the N-channel FET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while the output capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode (D1) becomes forward biased and L1 provides energy to both CO and the LED load. Figure 11 shows the inductor current (iL(t)) waveform for a regulator operating in CCM. IL(max) 'iL(P-P) iL tON = DxtS . IL(min) tOFF = (1D)xtS 0 tS . Time Figure 11. Basic CCM Inductor Current Waveform The average output LED current (ILED) is proportional to the average inductor current (IL), therefore if IL is tightly controlled, ILED is well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D) is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio: Use Equation 1 to calculate the duty cycle for an application using the boost topology. V - VIN D = O VO (1) Use Equation 2 to calculate the duty cycle for an application using the buck-boost (SEPIC/Cuk) topology. VO D = VO + VIN (2) Use Equation 3 to calculate the duty cycle for an application using the flyback topology. nVO D = nVO + VIN where * n is the primary to secondary turns ratio of the coupled inductor, n:1 (3) 7.3.2 Peak Current Mode Control Peak current mode control is used by the TPS92690 device to regulate the average LED current through an array of HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can use either a series resistor in the MOSFET path or the MOSFET RDS(on) for both cycle-by-cycle current limit and input voltage feed forward. The controller has a fixed switching frequency set by an internal programmable oscillator therefore slope compensation is added to mitigate current mode instability. A detailed explanation of this control method is presented in the following sections. 10 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Feature Description (continued) 7.3.3 Switching Frequency and Synchronization The switching frequency of the TPS92690 device is programmed using an external resistor (RT) connected from the RT pin to GND. This switching frequency is defined as shown in Equation 4. 1 | SW = -11 2.29 10 RT + 80 10-9 (4) The Typical Characteristics shows a graph of switching frequency versus timing resistance on RT. For maximum operational range and best efficiency, TI recommends a switching frequency of 1 MHz or lower. It is possible to reduce the solution size in applications with switching frequencies as high as 2 MHz in some situations. Higher frequencies require an increased gate-drive current and that can result in higher AC losses, both of which result in decreased efficiency. It is also possible that the minimum on-time (leading edge blanking time) limits the minimum operational duty cycle and reduces the input voltage range for a given output voltage. Alternatively, an external PWM signal can be applied to the SYNC pin to synchronize the device to an external clock. If the PWM signal frequency applied is higher than the base frequency set by the timing (RT) resistor, the internal oscillator is bypassed and the switching frequency is equal to the synchronized frequency. The PWM signal should have an amplitude between 2.5 and 5 V. The device triggers a switch-on time on the falling edge of the PWM signal and operates correctly regardless of the duty cycle of the applied signal. ILED COMP CCMP CSP * RF gM Error Amplifier + VCS RCS CF * + IADJ 0-5V IT GATE PWM + IOFF 9R R ROFF To GATE Artificial Ramp IS RSL + VLIM RLIM + * ILIM ILIM 0 - 400 mV Figure 12. Current Sense and Control Circuitry (* optional) 7.3.4 Current Sense and Current Limit The TPS92690 device implements peak current mode control using the circuit shown in Figure 12. The peak detection is accomplished with a comparator that monitors the main MOSFET current, comparing it with the COMP pin. When the IS pin voltage (plus the DC level shift and the ramp discussed later) exceeds the COMP pin voltage, the MOSFET is turned off. The MOSFET is turned back on when the oscillator starts a new on-time and the cycle repeats. The IS pin incorporates a cycle-by-cycle overcurrent protection function. Current limit is accomplished by a redundant internal current sense comparator. If the voltage at the current sense comparator input (IS) exceeds the voltage at the ILIM pin, the MOSFET is turned off and the COMP pin is pulled to ground and discharged. The MOSFET turns back on after either the 43-s current limit timeout has passed or after the COMP pin is recharged, whichever is longer. The IS input pin has an internal N-channel MOSFET which pulls it down at the conclusion of every cycle. The discharge device remains on an additional 216 ns (typical) after the beginning of a new cycle to blank the leading edge spike on the current sense signal. This blanking time also results in a minimum switch-on time of 216 ns which determines a minimum duty cycle dependent upon switching frequency. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 11 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) IS sensing can be done in one of two ways. The most accurate current sensing is accomplished by using a resistor, RLIM. This adds a component that dissipates additional power but the result is higher accuracy and no limitation on the maximum MOSFET drain voltage. For applications that have a maximum MOSFET drain voltage below 75 V MOSFET RDS(on) sensing can be used by connecting the IS pin directly to the drain of the MOSFET and eliminating RLIM. This results in higher efficiency but the accuracy depends on the accuracy of the MOSFET RDS(on). Care must be taken to use the maximum expected RDS(on) when setting the current limit threshold at the ILIM pin. 7.3.5 Average LED Current The COMP pin voltage is dynamically adjusted, via the internal error amplifier, to maintain the desired regulation. A sense resistor in series with the LEDs sets the average LED current regulation. The voltage across the sense resistor (VCS) is regulated to the IADJ voltage divided by 10. The IADJ pin can be set to any value up to 2.45 V by connecting it to VREF through a resistor divider for static output current settings. IADJ can also be used to change the regulation point if connected to a controlled voltage source up to 5 V or potentiometer to provide analog dimming. It is also possible to configure the IADJ pin for thermal foldback functions. V ILED = CS RCS (5) VCS = VIADJ 10 (6) The TPS92690 device maintains high accuracy at any level of VCS. However, the accuracy remains better with higher levels as offsets and other errors become a smaller percentage of the overall VCS voltage. Power losses are also higher with higher VCS voltages. A good tradeoff for accuracy and efficiency is to set the maximum VCS voltage to between 100 and 250 mV. In some applications, such as standard boost or flyback topologies, the output capacitor can be connected from the output directly to ground. In these cases the CS pin can be directly connected to RCS. In other applications an additional filter may be desired on the CS pin (RF and CF). Use these filters with topologies where the current through RCS is not continuous such as in the Cuk configuration. Another example would be a boost regulator where PWM dimming is required and the output capacitor is connected directly across the LEDs. In these cases it is recommended to add a 47- resistor for RF and a 47-nF capacitor for CF to achieve the best accuracy and line regulation. 7.3.6 Precision Reference (VREF) The TPS92690 device includes a precision 2.45-V reference. This can be used in conjunction with a resistor divider to set voltage levels for the ILIM pin and the IADJ pin to set the maximum current limit and LED current. It can also be used with high impedance external circuitry requiring a reference. To set the current limit (ICL) using VREF you can use the following equations: V ICL = LIM RLIM (7) VLIM = VILIM = VREF RLIM1 RLIM1 + RLIM2 (8) When RDS(on) sensing is being used substitute RLIM in the above equation with RDS(on). A small amount of capacitance (CLIM) can be placed from the ILIM pin to ground for filtering if desired. If so, a value between 47 pF and 100 nF should be used but this value should not exceed the value of CCMP to avoid false triggering of the current limit. To set the IADJ voltage level using VREF use the following equation: R ADJ1 VIADJ = VREF R ADJ1 + R ADJ2 (9) If desired, place a small capacitor (CADJ) from the IADJ pin to ground for additional filtering. A value between 47 pF and 100 nF should be sufficient. 12 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Feature Description (continued) 7.3.7 Low-Level Analog Dimming The IADJ pin can be driven as low as 0 V. The device encounters a minimum on-time at some level, depending on the switching frequency. When the voltage on the IADJ pin falls beyond this point, the device begins to skip pulses to maintain average output current regulation. Depending on external components and regulator bandwidth this skipping may or may not result in visible flicker. If flicker is present below this level higher inductor and/or output capacitor values may help and a lower COMP pin capacitor value may help. In many cases this level occurs at very low LED current and it is more desirable to simply limit the low level on the IADJ pin as shown in Figure 13. TPS92690 VREF RADJ2 IADJ RADJ1 VIADJ Figure 13. Limiting Minimum IADJ Voltage The resulting IADJ voltage can be found using the following equation: R ADJ1 VIADJ = (VREF - VADJ ) R ADJ1 + R ADJ2 (10) 7.3.8 Soft-Start and Shutdown The TPS92690 device can be placed into low power shutdown by grounding the SS/SD pin (any voltage below 86 mV). During low power shutdown, the device limits the quiescent current to approximately 40 A, typical. The SS/SD pin also has a 10-A current source (or 1 A when below the 86-mV shutdown threshold), which charges a capacitor from SS/SD to GND to soft-start the converter. The SS/SD pin is attached through a PNP transistor to COMP therefore it controls the speed at which COMP rises at startup. When VCCUV is below the falling threshold, SS/SD is pulled down to reset the capacitor voltage to zero. Then when VCCUV rising threshold is exceeded, the pin is released and charges via the 10-A current source. 7.3.9 VCC Regulator and Start-Up The TPS92690 device includes a high voltage, low dropout bias regulator. When power is applied, or SS/SD is released, the regulator is enabled and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended bypass capacitance for the VCC regulator is 2.2 to 3.3 F. This capacitor should be rated for 10 V or greater and an X7R dielectric ceramic is recommended. The output of the VCC regulator is monitored by an internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the supply is also internally current limited. VCC may also be driven externally to increase the GATE voltage and reduce the RDS(on) of the external switching MOSFET. The maximum voltage on this pin is 14 V and should not exceed the VIN voltage. The bypass capacitor voltage rating may need to be increased accordingly. The start-up time of the device to full output current depends on the value of CBYP, CSS (soft-start capacitor), CCMP, and CO (output capacitor) as shown in Figure 14: Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 13 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) 1.0 Voltage (V) tVCC 0 tCMP-SS tCO 1.0 0.7 0 tCMP-SS tVCC tSS tCO TIme Figure 14. Start-up Waveforms First, CBYP is charged to be above the VCC UVLO threshold of 4.1 V. The CBYP charging time (tVCC) can be estimated as: 4.1V CBYP t VCC = 30 mA (11) Assuming there is no CSS (top trace), or if CSS is less than 40% of CCMP, CCMP is then charged to 1V over the charging time (tCMP) which can be estimated as: 1V CCMP t CMP = VCS 35 mS (12) Once CCMP = 1 V, the device starts switching to charge CO until the LED current is in regulation. The CO charging time (tCO) can be roughly estimated as: C VO t CO = O ILED (13) If CSS is greater than 40% of CCMP (bottom trace), the compensation capacitor only charges to 0.7 V over a smaller CCMP charging time (tCMP-SS) which can be estimated as: 0.7V CCMP t CMP -SS = VCS 35 mS (14) Then COMP clamps to SS, forcing COMP to rise (the last 300 mV before switching begins) according to the CSS charging time (tSS) which can be estimated as: 0.3V CSS t SS = 11 mA (15) The system start-up time tSU (for CSS < 0.4 CCMP) or tSU-SS (for CSS > 0.4 CCMP) is defined as: t SU = t VCC + t CMP + t CO 14 Submit Documentation Feedback (16) Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Feature Description (continued) t SU-SS = t VCC + t CMP -SS + t SS + t CO (17) As a general rule of thumb, standard smooth startup operation can be achieved with CSS = CCMP. If SD/SS is being driven by an external source the equations above may need to be modified depending on the current sourcing capability of the external source. 7.3.10 Overvoltage Protection (OVP) TPS92690 20 A VO ROV2 OVP OVLO + 1.24 V ROV1 Figure 15. Overvoltage Protection Circuitry The TPS92690 device includes a dedicated OVP pin which can be used for either input or output over-voltage protection. This pin features a precision 1.24-V threshold with 20 A (typical) of hysteresis current as shown in Figure 15. When the OVP threshold is exceeded, the GATE pin is immediately pulled low and a 20-A current source provides hysteresis to the lower threshold of the OVP hysteretic band. The over-voltage turn-off threshold (VTURN-OFF) and the hysteresis (VHYSO) are defined by: R ROV2 VTURN-OFF = 1.24V OV1 ROV1 VHYSO = 20 mA ROV2 (18) (19) 7.3.11 Input Undervoltage Lockout (UVLO) The nDIM pin is a dual function input that features an accurate 1.24-V threshold with programmable hysteresis as shown in Figure 16. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO. When the pin voltage rises and exceeds the 1.24-V threshold, 20 A (typical) of current is driven out of the nDIM pin into the resistor divider providing programmable hysteresis. TPS92690 20 A VIN RUV2 RUVH nDIM + RUV1 (optional) UVLO 1.24 V Figure 16. UVLO Circuit Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 15 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra resistor to set the hysteresis. This allows the standard resistor divider to have smaller values minimizing PWM delays due to a pull-down MOSFET at the nDIM pin (see PWM Dimming). In general, at least 3 V of hysteresis is preferable when PWM dimming if operating near the UVLO threshold. The turn-on threshold (VTURN-ON) is defined as follows: R RUV2 VTURN-ON = 1.24V UV1 RUV1 (20) The hysteresis (VHYS) is defined as follows: UVLO Only VHYS = 20 mA RUV 2 (21) PWM Dimming and UVLO ae RUVH (RUV1 + RUV2 ) o VHYS = 20 mA c RUV2 + / c / RUV1 e o (22) 7.3.12 PWM Dimming The active low nDIM pin can be driven with a PWM signal which controls the main N-channel FET. The brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness is approximately proportional to the PWM signal duty cycle (that is, 30% nDIM high duty cycle equals about 30% LED brightness). This function can be ignored if PWM dimming is not required by using nDIM solely as a VIN UVLO input as described in the Input Undervoltage Lockout (UVLO) section or by tying it directly to VCC or VIN when UVLO is not required. VIN DDIM RUV2 TPS92690 Inverted PWM nDIM RUVH RUV1 QDIM Standard PWM Figure 17. PWM Dimming Circuit When using a MOSFET (QDIM), connect the drain to the nDIM pin and the source to GND. Apply an external logic-level PWM signal to the gate of QDIM. Brightness is proportional to the negative duty cycle of the PWM signal. When using a Schottky diode (DDIM), connect the anode to the nDIM pin. Apply an external logic-level PWM signal to the cathode of the diode and brightness is proportional to the positive duty cycle of the PWM signal. 7.3.13 Control Loop Compensation Compensating the TPS92690 device is relatively simple for most applications. To prevent subharmonic oscillations due to current mode control, a minimum inductor value should be chosen. This minimum value can be approximated with the following equation: 16 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Feature Description (continued) Lmin = VO 425 103 (mH) 2 | SW (23) Compensating the control loop simply requires a capacitor from the COMP pin to ground. Most LED driver applications do not require high bandwidth response since there are no significant output transients and generally limited, low bandwidth input transients. The high output impedance (RO) of the error amplifier (typically 200M) enables a low bandwidth system where standard poles and zeros, including the right half plane zero in many cases, can be neglected. In this case the bandwidth of the system generally becomes the bandwidth of the error amplifier. TI recommends a CCMP value of 1 to 100 nF, which results in the following dominant pole and crossover frequency: 1 |P1 = 2p RO CCMP (24) gm |C = 2p CCMP (25) A 1-nF capacitor results in a bandwidth of approximately 5.2 kHz while a 100-nF capacitor results in a bandwidth of approximately 52 Hz. Larger values are recommended for most applications unless higher bandwidth is required. Larger values are also recommended for applications requiring PWM dimming as it allows the COMP pin to hold its level more accurately during the LED current off time. In applications where the duty cycle (D) exceeds 0.5 (VIN < VO / 2 for a boost regulator) the location of the right half plane zero should be calculated to ensure stability using the following equation: |RHPZ = rD D'2 2p D L1 (26) Where D and D' are calculated using the minimum input voltage. The crossover frequency, C, should be a decade below RHPZ for maximum stability. CCMP should be adjusted accordingly if required. 7.3.14 Thermal Shutdown The TPS92690 device includes thermal shutdown protection. If the die temperature reaches approximately 175C the device shuts down (GATE pin low). If the die temperature is allowed to cool until it reaches approximately 150C the device resumes normal operation. 7.4 Device Functional Modes This device has no additional functional modes Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 17 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not included in the TI component specification, and TI does not warrant its accuracy or completeness. TI customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Inductor The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy is stored in the inductor and transferred to the load in different ways (as an example, boost operation is detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the switching subinterval (tON or tOFF) determines the inductor current ripple (iL-PP). In the design process, L1 is chosen to provide a desired iL-PP. For a Cuk regulator the second inductor (L2) has a direct connection to the load, which is good for a current regulator. This requires little to no output capacitance therefore iL-PP is basically equal to the LED ripple current iLED-PP since the inductor ripple in L2 is equal to that in L1. However, for boost and other buck-boost regulators, there is always an output capacitor which reduces iLED-PP, therefore the inductor ripple can be larger than in the Cuk regulator case where output capacitance is minimal or completely absent. In general, iLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED). Therefore, for the Cuk regulator with no output capacitance, iLED-PP should also be less than 40% of ILED unless a large output capacitor is used. For the boost and other buck-boost topologies, iL-PP can be much higher depending on the output capacitance value. However, iL-PP is suggested to be less than 100% of the average inductor current (iL) to limit the RMS inductor current. iL-PP is defined as: V D DiL -PP = IN L fSW (27) Be sure to observe the minimum inductor value from the Control Loop Compensation section. L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable RMS inductor current (IL-RMS). 8.1.2 LED Dynamic Resistance When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RCS. LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the forward voltage of a single LED (VLED) by the forward current (ILED) can lead to an incorrect calculation of the dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value. Figure 18. Dynamic Resistance Obtaining rLED is accomplished by referring to the manufacturer LED I-V characteristic. It can be calculated as the slope at the nominal operating point as shown in Figure 18. For any application with more than 2 series LEDs, RCS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED. 18 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Application Information (continued) 8.1.3 Output Capacitor For boost, SEPIC, and flyback regulators, the output capacitor (CO) provides energy to the load when the recirculating diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a Cuk topology simply reduces the LED current ripple (iLED-PP) below the inductor current ripple (iL-PP). In all cases, CO is sized to provide a desired iLED-PP. As mentioned in Inductor, iLED-PP is recommended by manufacturers to be <40% of the average LED current (ILED). CO should be carefully chosen to account for derating due to temperature and operating voltage. It must also have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R dielectric rating is suggested. 8.1.4 Input Capacitor The input capacitor (CIN) only needs to provide the ripple current due to the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (VIN-PP) which can be tolerated. VIN-PP is suggested to be less than 10% of the input voltage (VIN). An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to minimize the large current draw from the input voltage source during the rising transition of the LED current waveform. The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R dielectric rating is suggested. For most applications, it is recommended to bypass the VIN pin with an 0.1-F ceramic capacitor placed as close as possible to the pin. In situations where the bulk input capacitance may be far from the TPS92690 device, a 10- series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150kHz filter to eliminate undesired high frequency noise. 8.1.5 MOSFET Selection The TPS92690 device requires an external N-channel FET (Q1) as the main power MOSFET for the switching regulator. Q1 is recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the power loss given the average transistor current and the N-channel FET on-resistance (RDS(on)). In general, the N-channel FET should be chosen to minimize total gate charge (Qg) when SW is high and minimize RDS(on) otherwise. This minimizes the dominant power losses in the system. Frequently, higher current N-channel FETs in larger packages are chosen for better thermal performance. 8.1.6 Recirculating Diode A recirculating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe operation during the ringing of the switch node and a current rating at least 10% higher than the average diode current. The power rating is verified by calculating the power loss through the diode. This is accomplished by checking the typical diode forward voltage from the I-V curve on the product datasheet and multiplying by the average diode current. In general, higher current diodes have a lower forward voltage and come in better performing packages minimizing both power losses and temperature rise. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 19 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 8.2 Typical Applications 8.2.1 Basic Topology Schematics PWM Dim CCUK L1 L2 VIN RUV2 RUVH 1 nDIM TPS92690 VIN 16 D1 CIN RUV1 2 OVP VCC OVP 15 CBYP 3 IS RT 14 RT CO 4 CSS 5 CCMP 6 SYNC GATE SS/SD PGND COMP CSP 13 Q1 ILED 12 RF 11 ROV 1 CADJ CF 7 AGND CLIM IADJ RCS 10 Q2 DAP RADJ 1 Q3 RADJ 2 8 ILIM VREF 9 OVP RLIM1 CREF ROV 3 RLIM 2 ROV 2 Figure 19. CUK Topology (Buck-Boost) PWM Dim T1 D1 VOUT VIN RUV2 RUV1 RUVH VOUT 1 nDIM TPS92690 VIN 16 ROV 2 CIN 2 VCC OVP 15 ROV 1 CBYP 3 IS RT 14 ILED RT 4 GATE SYNC 13 Q1 CSYNC1 RSYNC 5 PGND SS/SD 12 SYNC CSS 6 CSP COMP RF 11 CADJ CCMP CF 7 AGND CLIM IADJ ILIM RCS 10 DAP 8 RLIM1 CO CSYNC2 RADJ 1 RADJ 2 VREF 9 CREF RLIM 2 Figure 20. Quasi-Resonant Flyback Topology 20 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Typical Applications (continued) PWM Dim VIN RUV2 L1 D1 VOUT RUVH 1 nDIM ROV 2 TPS92690 VIN 16 L2 VOUT RUV1 CS CIN 2 VCC OVP 15 ROV 1 CBYP 3 IS RT 14 RT CO ILED 4 5 13 SYNC GATE SS/SD PGND COMP CSP Q1 12 CSS 6 11 CADJ CCMP RCS 7 AGND IADJ CLIM 10 DAP 8 RADJ 1 RADJ 2 ILIM VREF 9 RLIM 1 CREF RLIM2 Figure 21. SEPIC Topology (Buck-Boost) PWM Dim L1 D1 VOUT VIN RUV2 RUVH 1 ROV2 RUV1 nDIM TPS92690 VIN 16 VOUT CIN 2 OVP VCC 15 ROV1 CBYP 3 RT IS 14 RT ILED 4 CSS CCMP 5 6 SYNC GATE SS/SD PGND COMP CSP 13 CO Q1 12 RF 11 CF 7 AGND CLIM IADJ 10 DAP 8 RLIM 1 RLIM 2 ILIM RADJ 2 VREF RCS RADJ 1 9 CADJ CREF Figure 22. Boost Topology With PWM Dimming Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 21 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) 8.2.1.1 Design Requirements N = 10 VLED = 3.5 V rLED = 500 m VIN = 12 V VIN-MIN = 8 V VIN-MAX = 19 V fSW = 420 kHz VCS = 50 mV ILED = 500 mA iL-PP < 650 mA iLED-PP < 50 mA vIN-PP = 50 mV VLIM = 100 mV ILIM = 5 A VTURN-ON = 7.8 V VHYS = 2 V VTURN-OFF = 40 V VHYSO = 5 V 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Operating Point Solve for VO and rD: VO N u VLED 10 u 3.5V rD N u rLED 10 u 0.5 : 35V (28) 5: (29) Solve for D, DMAX, and DMIN: VO F VIN 23 = = 0.657 VO 35 VO F VIN (max ) 16 DMIN = = = 0.457 35 VO VO F VIN(min ) 27 DMAX = = = 0.771 35 VO D= (30) (31) (32) 8.2.1.2.2 Switching Frequency Solve for RT: RT = 1F80x10 F9 2.29x10 F11 x420kHz = 103.9k3 (33) A close standard resistor is 105 k resulting in fSW = 402 kHz. Choose RT = 105 k. 22 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Typical Applications (continued) 8.2.1.2.3 Average LED Current Solve for RCS using our desired 50-mV sense voltage: VCS 50 mV RCS 0.1 : ILED 500 mA (34) Solve for VIADJ: VIADJ = 10 x VCS = 10 x 50mV = 500mV (35) A resistor divider can be used from the reference pin (VREF) to IADJ, select RIAD2 = 100 k and solve for RIAD1: R ADj2 u VIADj 100 k: u 0.5 V R ADj1 25 k: VREF VIADI 2.5 V 0.5 V (36) The closest standard value is to choose RADJ1 = 25.5 k. 8.2.1.2.4 Inductor Ripple Current Solve for the minimum value of L1 for stability: L1min = VO x 425 x 103 35V x 425 x 103 = = 17.yJH 2 x fSW 2 x 420kHz (37) The inductor value required to meet the ripple current requirements is: VIN u D 12 V u 0.657 L 28.9 PH 'iL PP u fSW 650 mA u 420 kHz (38) The closest standard inductor is 33 H therefore iL-PP is: iLFPP = VIN x D 12V x 0.657 = = 640mA L x fSW uuJH x 420kHz (39) Determine minimum allowable RMS current rating: IL ILED 1 'IL PP u D' * 1 u D' 12 (c) ILED RMS 2 500 mA 1 640 mA u 0.343 * 1 u 0.343 12 (c) 500 mA 2 1.47 A (40) The chosen component is L1 = 33 H. 8.2.1.2.5 Output Capacitance Solve for CO: CO = ILED x D 500mA x 0.657 = = 3.suJF rD x iLED FPP x fSW w3 x 50mA x 420kHz (41) Add some capacitance to account for voltage de-rating and temperature and choose CO = 4.7 F. Determine minimum allowable RMS current rating: ICO RMS ILED u DMAX 1 DMAX 500 mA u 0.771 0.229 0.92 A (42) Since this is a PWM dimming application the output capacitor should be placed directly across the LED string and not connected to ground. So the CS pin should have additional filtering in the form of RF = 47 and CF = 47 nF. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 23 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) 8.2.1.2.6 Peak Current Limit Solve for RLIM: R LIM = VLIM 100mV = = 0.rt3 5A ILIM (43) The closest standard resistor is 0.02 ; therefore, choose RLIM = 0.02 . Assume RLIM2 = 100 k and calculate RLIM1: RLIM2 u VLIM 100 k: u 0.1 V RLIM1 4.17 k: VREF VLIM 2.5 V 0.1 V (44) The closest standard value is RLIM1 = 4.22 k 8.2.1.2.7 Loop Compensation Check the frequency of the output pole: 1 1 fpCo 2S u rD u CO 2S u 5 : u 4.7 PF 6.77 kHz (45) Check the frequency of the RHP zero: fRHPZ = rD x :1 F DMAX ;2 w3 x :1 F 0.771;2 = = 1.64kHz tN x DMAX x L1 tN x 0.771 x uuJH (46) The lower of the two is the RHP zero at 1.64 kHz, so the maximum crossover frequency should be 164 Hz or less. Calculate the minimum COMP capacitor value: CCMP (min ) = gm uuJA/V = = 32nF tN x fC tN x 164Hz (47) To ensure stability over all conditions add some margin and choose CCMP = 47 nF. 8.2.1.2.8 Input Capacitance Solve for the minimum CIN: CIN = iLFPP 640mA = = 3.zJF 8 x VINFPP x fSW 8 x 50mV x 420kHz (48) To minimize power supply interaction a 200% larger capacitance or more should be used particularly with PWM dimming, therefore the actual vIN-PP is much lower. Choose CIN = 10 F. Determine minimum allowable RMS current rating: 'iL PP 640 mA ICIN RMS 185 mA 12 12 (49) 8.2.1.2.9 NFET Determine minimum Q1 voltage rating and current rating: VT MAX VO 35 V ITFMAX = (50) DMAX 0.771 x ILED = x 500mA = 1.68A 1 F DMAX 1 F 0.771 (51) The RMS current rating used in conjunction with the chosen FET RDS-ON to calculate power dissipation is: I 500 mA IT RMS LED u D u 0.657 1.18 A D' 1 0.657 24 Submit Documentation Feedback (52) Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Typical Applications (continued) 8.2.1.2.10 Diode Determine minimum D1 voltage rating and current rating: VRD FMAX = VO = 35V IDFMAX = ILED = 500mA (53) (54) 8.2.1.2.11 Input UVLO Since this is a PWM dimming application RUVH will be used. Start by picking RUV2 = 10 k and solve for RUV1: R UV1 = 1.24V xR U V2 V TURN FON F1.24V 1.24V x10k3 7.8VF1.24V = = 1.89k: (55) The closest standard resistor is 1.89 k so choose RUV1 = 1.89 k. Solve for RUVH given the hysteresis requirements: R UVH = R UV1 x :VHYS F trJA x R UV2 ; 1.89k3 x :2V F trJA x 10k3; = = 14.3k3 trJA x :R UV1 + R UV2 ; trJA x :10k3 x 1.89k3; (56) The closest standard resistor is 14.3 k so choose RUVH = 14.3 k. 8.2.1.2.12 Output OVLO Solve for ROV2: R OV2 = VHYSO 5V = = 250k3 trJA trJA (57) The closest standard resistor is 249 k; therefore, choose RUV2 = 249 k. Solve for ROV1: R OV1 = 1.24V xR OV2 V TURN FOFF F1.24V = 1.24V x249k3 40V F1.24V = 8k: (58) Choose the nearest standard resistor value of ROV1 = 8.06 k. 8.2.1.3 Application Curve 100 Efficiency (%) 98 96 94 92 10 LEDs @ 500mA 90 10 12 14 Input Voltage (V) 16 18 G000 Figure 23. Efficiency vs Input Voltage Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 25 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) 8.2.2 Simplified Application VIN VOUT TPS92690 VOUT 1 nDIM VIN 16 2 OVP VCC 15 3 RT IS 14 4 SYNC GATE 13 5 SS/SD PGND 12 6 COMP CSP 11 7 AGND IADJ 10 8 ILIM VREF 9 Figure 24. Simplified Application Schematic 8.2.2.1 Design Requirements Number of series LEDs: N Single LED forward voltage: VLED Single LED dynamic resistance: rLED Nominal input voltage: VIN Input voltage range: VIN-MAX, VIN-MIN Switching frequency: fSW Current sense voltage: VCS Average LED current: ILED Inductor current ripple: iL-PP LED current ripple: iLED-PP Peak current limit: ILIM Input voltage ripple: vIN-PP Output OVLO characteristics: VTURN-OFF, VHYSO Input UVLO characteristics: VTURN-ON, VHYS Total start-up time: tTSU 26 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Typical Applications (continued) 8.2.2.2 Detailed Design Procedure 8.2.2.2.1 Operating Point Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED, solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD): VO = N VLED rD = N rLED (59) (60) Solve for the ideal nominal duty cycle (D): Boost D= VO - VIN VO (61) Buck-Boost D= VO VO + VIN (62) Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D. 8.2.2.2.2 Switching Frequency Set the switching frequency (fSW) by solving for RT: RT 1 80 u 10 2.29 u 10 11 9 u fSW (63) 8.2.2.2.3 Average LED Current For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VCS) and solving for RCS: VIADJ VCS 10 (64) VCS RCS ILED (65) If the calculated RCS is too far from a desired standard value, then VCS will have to be adjusted to obtain a standard value. Setup the IADJ voltage by assuming RADJ2 = 100 k and solving for RADJ1: R ADJ1 = R ADJ2 x VIADJ VREF F VIADJ (66) If the calculated RADJ1 is too far from a desired standard value, then RADJ2 can be adjusted to obtain a standard value. 8.2.2.2.4 Inductor Ripple Current Find the minimum inductor value and calculate the nominal inductor ripple current (iL-PP) by solving for the appropriate inductor (L1): 8.2.2.2.4.1 Minimum Inductor Value L1min = VO x 425 x 103 :JH; 2 x fSW (67) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 27 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) 8.2.2.2.4.2 Inductor Ripple Current DiL -PP = VIN D L fSW (68) If the inductor ripple current is too high given the chosen value increase L1 to get the required inductor current ripple. For buck-boost applications replace VO with VIN + VO when solving for L1. The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as: 8.2.2.2.4.3 RMS Inductor Current 1 'IL-PP x D' * x x 1+ IL-RMS = 12 ILED D' ILED (c) 2 (69) 8.2.2.2.5 LED Ripple Current Set the nominal LED ripple current (iLED-PP), by solving for the output capacitance (CO): 8.2.2.2.5.1 Output Capacitor CO = ILED x D rD xuiLED- PP x fSW (70) To set the worst case LED ripple current, use DMAX when solving for CO. The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated: 8.2.2.2.5.2 Output Capacitor RMS Current ICO-RMS = ILED x DMAX 1-DMAX (71) 8.2.2.2.6 Peak Current Limit Set the peak current limit (ILIM) by setting the ILIM pin voltage and solving for the transistor path sense resistor (RLIM): RLIM1 VLIM VREF u RLIM1 RLIM2 (72) R LIM = VLIM ILIM (73) 8.2.2.2.7 Loop Compensation Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the necessary loop compensation can be determined. A maximum bandwidth (fC) of 10 kHz is recommended and the COMP pin capacitor can be calculated using: 8.2.2.2.7.1 Compensation Capacitor CCMP gm 2S u fC (74) Check the location of the right-half plane zero and the output pole and make sure the crossover frequency is at least a decade below the lowest of the two using the following equations: 28 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Typical Applications (continued) 8.2.2.2.7.2 RHP Zero |RHPZ = rD D'2 2p D L1 (75) 8.2.2.2.7.3 Output Capacitor Pole fpCo = 1 2e x rD x CO (76) If the input voltage range is wide use the maximum duty cycle (DMAX) corresponding to the minimum input voltage to calculate the RHP zero. In general smaller CCMP values will provide greater bandwidth but the bandwidth may be limited by the location of the RHP zero or output pole. For PWM dimming applications the largest capacitor value that will fit the applications requirements is suggested. 8.2.2.2.8 Input Capacitance Set the nominal input voltage ripple (vIN-PP) by solving for the required capacitance (CIN): Boost CIN = 'iL-PP 8 x 'VIN-PP x fSW (77) Buck-Boost CIN = ILED x D 'VIN-PP x fSW (78) Use DMAX to set the worst case input voltage ripple. The minimum allowable RMS input current rating (ICIN-RMS) can be approximated: Boost ICIN-RMS = 'iL-PP 12 (79) Buck-Boost ICIN-RMS = ILED x DMAX 1-DMAX (80) 8.2.2.2.9 NFET The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (VTMAX): Boost VT - MAX = VO (81) Buck-Bosst VT - MAX = VIN - MAX + VO (82) The current rating should be at least 10% higher than the maximum average NFET current (IT-MAX): 8.2.2.2.9.1 Maximum Average NFET Current IT-MAX = DMAX 1 - DMAX x ILED (83) Approximate the nominal RMS transistor current (IT-RMS) : Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 29 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) 8.2.2.2.9.2 RMS Transistor Current IT - RMS = ILED x D Dc (84) Given an NFET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT): 2 PT = IT - RMS x R DSON (85) 8.2.2.2.10 Diode The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX): Boost VRD-MAX = VO (86) Buck-Boost VRD-MAX = VIN-MAX + VO (87) The current rating should be at least 10% higher than the maximum average diode current (ID-MAX): 8.2.2.2.10.1 Maximum Average Diode Current ID-MAX = ILED (88) Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward voltage (VFD), solve for the nominal power dissipation (PD): PD = ID x VFD (89) 8.2.2.2.11 Output OVLO The output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF) and the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2: VHYSO ROV2 = 20 PA (90) To set VTURN-OFF, solve for ROV1: 1.24V x ROV2 ROV1 = VTURN - OFF - 1.24V (91) 8.2.2.2.12 Input UVLO For all topologies, input UVLO is programmed with the turn-on threshold voltage (VTURN-ON) and the desired hysteresis (VHYS). Method 1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2: VHYS RUV2 = 20 PA (92) To set VTURN-ON, solve for RUV1: 1.24V x RUV2 RUV1 = VTURN - ON - 1.24V (93) Method 2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2 = 10 k and solve for RUV1 as in Method 1. To set VHYS, solve for RUVH: RUVH = 30 R UV1 x (VHYS - 20 PA x RUV2) 20 PA x (RUV1 + R UV2) (94) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 Typical Applications (continued) 8.2.2.2.13 Soft-Start For all topologies, if soft-start is desired, find the start-up time without CSS (tSU): t SU = t VCC + t CMP + t CO (95) Then, if the desired total start-up time (tTSU) is larger than tSU, solve for the base start-up time (tSU-SS-BASE), assuming that a CSS greater than 40% of CCMP will be used: V t SU - SS - BASE = 168: x CBYP + 28 k: x CCMP + O x CO ILED (96) Then solve for CSS: CSS = 10 PA x (t TSU - t SU - SS - BASE) 0.2V (97) 8.2.2.2.14 PWM Dimming Method PWM dimming can be performed several ways: Method 1: Connect the dimming MosFET (Q3) with the drain to the nDIM pin and the source to GND. Apply an external PWM signal to the gate of QDIM. A pull down resistor may be necessary to properly turn off Q3. Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the cathode of the same diode. 8.2.2.2.15 Analog Dimming Method Analog dimming can be performed several ways: Method 1: Place a potentiometer in place of RIADJ1. Method 2: Connect a controlled voltage source to the IADJ pin to control the current sense voltage (VCS). 9 Power Supply Recommendations 9.1 Bench Supply Current Limit It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your converter analysis and optimization. If not set high enough, current limit can be tripped during start up or when your converter output power is increased, causing a foldback or shut-down condition. It is a common oversight when powering up a converter for the first time. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 31 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines The performance of any switching regulator depends as much upon the layout of the PCB as the component selection. Following a few simple guidelines maximizes noise rejection and minimizes the generation of EMI within the circuit. Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these paths. In the boost regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1, and RLIM (if used). These loops should be kept as small as possible and the connections between all the components should be short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect) should be just large enough to connect the components. To minimize excessive heating, large copper pours can be placed adjacent to the short current path of the switch node. The RT, COMP, CSP, IS, IADJ, ILIM, and SYNC pins are all high-impedance inputs which couple external noise easily. Therefore, the loops containing these nodes should be minimized whenever possible. In some applications the LED or LED array can be far away (several inches or more) from the TPS92690, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor. 32 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 TPS92690 www.ti.com SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 10.2 Layout Example Note critical paths and component placement: Minimize power loop containing discontinuous currents Minimize signal current loops (components close to IC) x Ground plane under IC for signal routing helps minimize noise coupling discontinuous switching frequency currents VOUT VIN Input Power GND TPS92690 1 VOUT 2 3 4 5 6 7 nDIM VIN OVP VCC IS RT SYNC GATE SS/SD PGND COMP CSP AGND IADJ 16 15 14 ILED 13 12 11 10 DAP 8 ILIM VREF 9 STAR GROUND Power Ground Figure 25. Layout Recommendation Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 33 TPS92690 SLVSBK3A - DECEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 34 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92690 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) TPS92690PWP/NOPB ACTIVE HTSSOP PWP 16 92 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 TP92690 PWP TPS92690PWPR/NOPB ACTIVE HTSSOP PWP 16 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 TP92690 PWP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 OTHER QUALIFIED VERSIONS OF TPS92690 : * Automotive: TPS92690-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS92690PWPR/NOPB HTSSOP PWP 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92690PWPR/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 14X 0.65 16 1 2X 4.55 5.1 4.9 NOTE 3 8 9 B 4.5 4.3 16X 0.30 0.19 0.1 C A B (0.15) TYP SEE DETAIL A 4X 0.166 MAX NOTE 5 2X 1.34 MAX NOTE 5 THERMAL PAD 3.3 2.7 17 0.25 GAGE PLANE 1.2 MAX 0.15 0.05 0 -8 0.75 0.50 (1) 3.3 2.7 DETAIL A TYPICAL 4214868/A 02/2017 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may not be present. www.ti.com EXAMPLE BOARD LAYOUT PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 SOLDER MASK DEFINED PAD (3.3) 16X (1.5) SYMM SEE DETAILS 1 16 16X (0.45) (1.1) TYP 17 SYMM (3.3) (5) NOTE 9 14X (0.65) 8 9 ( 0.2) TYP VIA (1.1) TYP METAL COVERED BY SOLDER MASK (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL 0.05 MAX ALL AROUND EXPOSED METAL 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-16 4214868/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (3.3) BASED ON 0.125 THICK STENCIL 16X (1.5) (R0.05) TYP 1 16 16X (0.45) (3.3) BASED ON 0.125 THICK STENCIL 17 SYMM 14X (0.65) 9 8 SYMM METAL COVERED BY SOLDER MASK (5.8) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.15 0.175 3.69 X 3.69 3.3 X 3.3 (SHOWN) 3.01 X 3.01 2.79 X 2.79 4214868/A 02/2017 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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