S29WSxxxN MirrorBitTM Flash Family S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory PRELIMINARY Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.70 to 1.95 volt) Manufactured on 110 nm MirrorBitTM process technology VersatileIOTM (VIO) Feature -- Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin -- VIO options available for 1.8 V (1.70 V - 1.95 V) Performance Characteristics Simultaneous Read/Write operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency between read and write operations -- Sixteen bank architecture: Each bank consists of 16Mb (WS256N) / 8Mb (WS128N) / 4Mb (WS064N) Programable Burst Interface -- 2 Modes of Burst Read Operation -- Linear Burst: 32, 16, and 8 words with or without wrap-around -- Continuous Sequential Burst -- 84-ball (8 mm x 11.6 mm) FBGA package for WS128N -- 80-ball (7 mm x 9 mm) FBGA package for WS064N SecSiTM (Secured Silicon) Sector region -- 256 words accessible through a command sequence, 128 words for the Factory SecSi Sector and 128 words for the Customer SecSi Sector. -- Non-erasable region Sector Architecture -- S29WS256N: Eight 16 Kword sectors and twohundred-fifty-four 64 Kword sectors -- S29WS128N: Eight 16 Kword sectors and onehundred-twenty-six 64 Kword sectors -- S29WS064N: Eight 16 Kword sectors and sixty-two 64 Kword sectors -- Banks 0 and 15 each contain 16 Kword sectors and 64 Kword sectors; Other banks each contain 64 Kword sectors -- Eight 16 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range Hardware Features Sector Protection -- Write protect (WP#) function allows protection of eight outermost boot sectors, four at top and four at bottom of memory, regardless of sector protect status Handshaking feature available -- Provides host system with minimum possible latency by monitoring RDY Boot Option -- Dual Boot Low VCC write inhibit Security Features Cycling Endurance: 100,000 cycles per sector typical Data Retention: 20 years typical MCP-Compatible Packages -- 84-ball (8 mm x 11.6 mm) FBGA package for WS256N Publication Number S29WSxxxN_00 Read access times at 80/66/54 MHz -- Burst access times of 9/11.2/13.5 ns -- Synchronous initial latency of 69/69/69 ns -- Asynchronous random access times of 70/70/70 ns Program and Erase Performance -- Typical word programming time of 40 s -- Typical effective word programming time of 9.4 s utilizing a 32-Word Write Buffer at VCC Level -- Typical effective word programming time of 6 s utilizing a 32-Word Write Buffer at ACC Level -- Typical sector erase time of 150 ms for 16 Kword sectors and 800 ms sector erase time for 64 Kword sectors Power dissipation (typical values @ 66 MHz) -- Continuous Burst Mode Read: 35 mA -- Simultaneous Operation: 50 mA -- Program: 19 mA -- Erase: 19 mA -- Standby mode: 20 A Advanced Sector Protection consists of the two following modes of operation Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Revision C Amendment 0 Issue Date June 14, 2004 P r e l i m i n a r y Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector using a user-defined 64-bit password Program Suspend/Resume -- Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences Software Features Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards Data# Polling and toggle bits -- Provides a software method of detecting program and erase operation completion Erase Suspend/Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation 2 Additional Features Program Operation -- Ability to perform synchronous and asynchronous program operation independent of burst control register setting ACC input -- Acceleration function reduces programming and erase time in a factory setting. S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y General Description The WSxxxN family consists of 256, 128, and 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory devices, organized as 16, 8, or 4 Mwords of 16 bits. These devices use a single VCC of 1.70 to 1.95 V to read, program, and erase the memory array. A 9.0-volt VHH on ACC may be used for faster program performance in a factory setting. These devices can be programmed in standard EPROM programmers. At 80 MHz and 1.8V VIO, the device provides a burst access of 9 ns at 30 pF with an initial latency of 69 ns at 30 pF. At 66 MHz and 1.8V VIO, the device provides a burst access of 11.2 ns at 30 pF with an initial latency of 69 ns at 30 pF. At 54 MHz and 1.8V VIO, the device provides a burst access of 13.5 ns at 30 pF with an initial latency of 69 ns at 30 pF. The device operates within the industrial temperature range of -40C to +85C or wireless temperature range of -25C to +85C. These devices are offered in MCP compatible FBGA packages. See the product selector guide for details The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into sixteen banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The devices are divided into banks and sectors as shown in the following table: Bank 0 Quantity of Sectors (WS256N/WS128N/WS064N) Sector Size 4/4/4 16 Kwords 15/7/3 64 Kwords 1 16/8/4 64 Kwords 2 16/8/4 64 Kwords 3 16/8/4 64 Kwords 4 16/8/4 64 Kwords 5 16/8/4 64 Kwords 6 16/8/4 64 Kwords 7 16/8/4 64 Kwords 8 16/8/4 64 Kwords 9 16/8/4 64 Kwords 10 16/8/4 64 Kwords 11 16/8/4 64 Kwords 12 16/8/4 64 Kwords 13 16/8/4 64 Kwords 14 16/8/4 64 Kwords 15/7/3 64 Kwords 4/4/4 16 Kwords 15 The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 3 P r e l i m i n a r y The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and then wrap or non-wrap through the same memory space, or read the flash array in continuous mode. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program Algorithm -- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. The additional Write Buffer Programming feature provides superior programming performance by grouping locations being programmed. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase Algorithm -- an internal algorithm that automatically preprograms the array (if it is not already fully programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The Program Suspend/Program Resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. If a read is needed from the SecSi Sector area, Persistent Protection area, Dynamic Protection area, or the CFI area, after an program suspend, then the user must use the proper command sequence to enter and exit this region. The program suspend/resume functionality is also available when programming in erase suspend (1 level depth only). The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area, Persistent Protection area, Dynamic Protection area, or the CFI area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a memory array program or erase operation is complete by using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been completed, the device automatically returns to reading array data. 4 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL, WP# locks the four outermost boot sectors at the top of memory and the four outermost boot sectors at the bottom of memory. When the ACC pin = VIL, the entire flash memory array is protected. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. SpansionTM Flash memory products combine years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector. The data is programmed using hot electron injection. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 5 P r e l i m i n a r y Table of Contents Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . .9 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 10 MCP Look-ahead Connection Diagram ......................................... 13 Multi-Chip Compatible Packages ...................................................... 14 Special Handling Instructions for FBGA Package ......................... 14 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 15 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering Information (256 Mb) . . . . . . . . . . . . . . . 17 Ordering Information (128 Mb) . . . . . . . . . . . . . . . 18 Ordering Information (64 Mb) . . . . . . . . . . . . . . . . 19 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .20 Table 1. Device Bus Operations ..........................................20 VersatileIOTM (VIO) Control ...............................................................20 Requirements for Asynchronous (Non-Burst) Read Operation .....................................................................................20 Requirements for Synchronous (Burst) Read Operation ......... 21 Table 2. Address Dependent Additional Latency ....................21 Table 3. Address Latency for x Wait States ( 80 MHz) ...........21 Table 4. Address Latency for 6 Wait States ( 80 MHz) ..........22 Table 5. Address Latency for 5 Wait States ( 68 MHz) ..........22 Table 6. Address Latency for 4 Wait States ( 54 MHz) ..........22 Table 7. Address Latency for 3 Wait States ( 40 MHz) ..........22 Table 8. Address/Boundary Crossing Latency for 6 Wait States ( 80 MHz) .......................................................................22 Table 9. Address/Boundary Crossing Latency for 5 Wait States (< 66 MHz) ......................................................................23 Table 10. Address/Boundary Crossing Latency for 4 Wait States (< 54 MHz) ......................................................................23 Table 11. Address/Boundary Crossing Latency for 3 Wait States (< 40 MHz) ......................................................................23 Table 12. Burst Address Groups ..........................................24 Configuration Register ........................................................................ 24 Handshaking ........................................................................................... 24 Simultaneous Read/Write Operations with Zero Latency ...... 25 Writing Commands/Command Sequences .................................. 25 Accelerated Program/Chip Erase Operations ............................. 25 Write Buffer Programming Operation .......................................... 26 Autoselect Mode .................................................................................. 27 Advanced Sector Protection and Unprotection .........................28 Sector Protection ................................................................................. 29 Persistent Sector Protection ............................................................. 29 Table 13. Sector Protection Schemes ...................................31 Password Sector Protection ............................................................. 32 Lock Register ..........................................................................................33 Table 14. Lock Register .....................................................33 Hardware Data Protection Mode ....................................................33 Standby Mode ........................................................................................ 34 Automatic Sleep Mode ........................................................................ 34 RESET#: Hardware Reset Input ....................................................... 34 Output Disable Mode ...........................................................................35 SecSiTM (Secured Silicon) Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 15. SecSiTM Sector Addresses .....................................36 Common Flash Memory Interface (CFI) . . . . . . . 36 Table 16. CFI Query Identification String ..............................37 6 Table 17. System Interface String ...................................... 37 Table 19. Primary Vendor-Specific Extended Query ............... 38 Table 20. WS256N Sector & Memory Address Map ................ 40 Table 21. WS128N Sector & Memory Address Map ................ 48 Table 22. WS064N Sector & Memory Address Map ................ 52 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 54 Reading Array Data ............................................................................. 54 Set Configuration Register Command Sequence ....................... 54 Read Configuration Register Command Sequence .................... 55 Figure 1. Synchronous/Asynchronous State Diagram ............. 55 Table 23. Programmable Wait State Settings ....................... 56 Table 24. Wait States for Handshaking ............................... 56 Table 25. Burst Length Configuration .................................. 57 Table 26. Configuration Register ........................................ 58 Reset Command ................................................................................... 58 Autoselect Command Sequence ...................................................... 59 Table 27. Autoselect Addresses .......................................... 60 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ..60 Word Program Command Sequence .............................................60 Figure 2. Word Program Operation ...................................... 61 Write Buffer Programming Command Sequence ........................ 61 Table 28. Write Buffer Command Sequence ......................... 62 Figure 3. Write Buffer Programming Operation...................... 63 Chip Erase Command Sequence ...................................................... 64 Sector Erase Command Sequence .................................................. 64 Figure 4. Erase Operation .................................................. 65 Erase Suspend/Erase Resume Commands .................................... 66 Program Suspend/Program Resume Commands ........................ 66 Lock Register Command Set Definitions ...................................... 67 Password Protection Command Set Definitions ........................ 67 Non-Volatile Sector Protection Command Set Definitions ....68 Figure 5. PPB Program/Erase Algorithm ............................... 70 Global Volatile Sector Protection Freeze Command Set ......... 71 Volatile Sector Protection Command Set ..................................... 71 SecSi Sector Entry Command ........................................................... 72 Command Definition Summary .........................................................73 Table 29. Memory Array Commands .................................. 73 Table 30. Sector Protection Commands ............................... 74 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 75 DQ7: Data# Polling .............................................................................. 75 Figure 6. Data# Polling Algorithm ....................................... 76 DQ6: Toggle Bit I .................................................................................. 76 Figure 7. Toggle Bit Algorithm ............................................ 78 DQ2: Toggle Bit II ................................................................................ 78 Table 31. DQ6 and DQ2 Indications .................................... 79 Reading Toggle Bits DQ6/DQ2 ........................................................ 79 DQ5: Exceeded Timing Limits .......................................................... 79 DQ3: Sector Erase Timer ..................................................................80 DQ1: Write to Buffer Abort .............................................................80 Table 32. Write Operation Status ....................................... 81 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 82 Figure 8. Maximum Negative Overshoot Waveform................ 82 Figure 9. Maximum Positive Overshoot Waveform ................. 82 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 82 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 83 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 10. Test Setup ........................................................ 84 Table 33. Test Specifications ............................................. 84 Key to Switching Waveforms. . . . . . . . . . . . . . . . 84 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 84 Figure 11. Input Waveforms and Measurement Levels............ 84 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 12. VCC Power-up Diagram ....................................... 85 AC Characteristics--Synchronous . . . . . . . . . . . 86 CLK Characterization .........................................................................86 Figure 13. CLK Characterization .......................................... 86 Synchronous/Burst Read .................................................................... 87 Timing Diagrams ...................................................................................88 Figure 14. CLK Synchronous Burst Mode Read ...................... 88 Figure 15. 8-word Linear Burst with Wrap Around ................. 89 Figure 16. 8-word Linear Burst without Wrap Around ............. 89 Figure 17. Linear Burst with RDY Set One Cycle Before Data... 90 AC Characteristics--Asynchronous. . . . . . . . . . . 91 Asynchronous Mode Read .................................................................. 91 Timing Diagrams .................................................................................... 91 Figure 18. Asynchronous Mode Read with Latched Addresses.. 91 Figure 19. Asynchronous Mode Read ................................... 92 Hardware Reset (RESET#) ................................................................ 92 Figure 20. Reset Timings ................................................... 92 Erase/Program Timing Operations .................................................. 93 Figure 21. Asynchronous Program Operation Timings: WE# Latched Addresses ............................................................ 94 Figure 22. Synchronous Program Operation Timings: June 14, 2004 S29WSxxxN_00C0 CLK Latched Addresses...................................................... 95 Figure 23. Accelerated Unlock Bypass Programming Timing .... 96 Figure 24. Data# Polling Timings (During Embedded Algorithm) ............................................ 96 Figure 25. Toggle Bit Timings (During Embedded Algorithm) ............................................ 97 Figure 26. Synchronous Data Polling Timings/ Toggle Bit Timings ............................................................ 97 Figure 27. DQ2 vs. DQ6..................................................... 98 Figure 28. Latency with Boundary Crossing when Frequency > 66 MHz ......................................................... 98 Figure 29. Latency with Boundary Crossing into Program/ Erase Bank ...................................................................... 99 Figure 30. Example of Wait States Insertion ....................... 100 Figure 31. Back-to-Back Read/Write Cycle Timings .............. 101 Erase and Programming Performance . . . . . . . 102 Physical Dimensions (256 Mb and 128 Mb) . . . . . 103 VBH084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package .........................................103 Physical Dimensions (64 Mb) . . . . . . . . . . . . . . . . 104 TBD--80-ball Fine-Pitch Ball Grid Array (FBGA) 7x9 mm MCP Compatible Package .................................................................104 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . 105 S29WSxxxN MirrorBitTM Flash Family 7 P r e l i m i n a r y Product Selector Guide Part Number S29WS256N, S29WS128N, S29WS064N Speed Option (Burst Frequency) (See Note) 80 MHz 66 MHz 54 MHz Max Synchronous Latency, ns (tIACC) 69 69 69 Max Synchronous Burst Access Time, ns (tBACC) 9 11.2 13.5 Max Asynchronous Access Time tCE), ns 70 70 70 Max CE# Access Time, ns (tCE), ns 70 70 70 11.2 11.2 13.5 Max OE# Access Time, ns (tOE) Note: 80 MHz available for standalone applications only, 66 MHz and 54 MHz available for both multi-chip and standalone applications. Block Diagram DQ15-DQ0 VCC VSS VIO RDY Buffer RDY Erase Voltage Generator State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector AVD# CLK Burst State Control Timer Burst Address Counter Address Latch WE# RESET# WP# ACC Input/Output Buffers Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix Amax-A0* * WS256N: A23-A0 WS128N: A22-A0 WS064N: A21-A0 8 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Block Diagram of Simultaneous Operation Circuit VCC Bank 0 Latches and Control Logic Bank Address Y-Decoder VSS VIO DQ15-DQ0 Amax-A0 X-Decoder OE# WP# ACC RESET# WE# CE# AVD# RDY DQ15-DQ0 Bank 1 Latches and Control Logic Y-Decoder Bank Address DQ15-DQ0 X-Decoder Amax-A0 STATE CONTROL & COMMAND REGISTER DQ15-DQ0 Status Control Amax-A0 Bank 14 Latches and Control Logic Bank Address Amax-A0 Y-Decoder X-Decoder DQ15-DQ0 Amax-A0 Bank 15 Latches and Control Logic Bank Address Y-Decoder X-Decoder DQ15-DQ0 Note: Amax=A23 for the WS256N, A22 for the WS128N, and A21 for the WS064N. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 9 P r e l i m i n a r y Connection Diagrams S29WS256N-MCP Compatible 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A10 A1 NC 10 B2 B3 B4 B5 B6 B7 B8 B9 AVD# RFU CLK RFU RFU RFU RFU RFU C2 C3 C4 C5 C6 C7 C8 C9 WP# A7 RFU ACC WE# A8 A11 RFU D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 RFU RESET# RFU A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RDY A20 A9 A13 A21 F2 F3 F4 F5 F6 F7 F8 F9 A1 A4 A17 RFU A23 A10 A14 A22 G2 G3 G4 G5 G6 G7 G8 G9 A0 VSS DQ1 RFU RFU DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 H9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU J2 J3 J4 J5 J6 J7 J8 RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS K2 K3 K4 K5 K6 K7 K8 K9 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU L2 L3 L4 L5 L6 L7 L8 L9 RFU RFU RFU VCC RFU RFU RFU RFU NC J9 M1 M10 NC NC S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y S29WS128N-MCP Compatible 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A10 A1 NC B2 B3 B4 B5 B6 B7 B8 B9 AVD# RFU CLK RFU RFU RFU RFU RFU C2 C3 C4 C5 C6 C7 C8 C9 WP# A7 RFU ACC WE# A8 A11 RFU D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 RFU RESET# RFU A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RDY A20 A9 A13 A21 F2 F3 F4 F5 F6 F7 F8 F9 A1 A4 A17 RFU RFU A10 A14 A22 G2 G3 G4 G5 G6 G7 G8 G9 A0 VSS DQ1 RFU RFU DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 H9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU J2 J3 J4 J5 J6 J7 J8 RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS K2 K3 K4 K5 K6 K7 K8 K9 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU L2 L3 L4 L5 L6 L7 L8 L9 RFU RFU RFU VCC RFU RFU RFU RFU NC J9 M1 M10 NC NC June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 11 P r e l i m i n a r y S29WS064N-MCP Compatible 80-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) 12 A1 A2 A3 A4 A5 A6 A7 A8 AVD# RFU CLK RFU RFU RFU RFU RFU B1 B2 B3 B4 B5 B6 B7 B8 WP# A7 RFU ACC WE# A8 A11 RFU C1 C2 C3 C4 C5 C6 C7 C8 A3 A6 RFU RESET# RFU A19 A12 A15 D1 D2 D3 D4 D5 D6 D7 D8 A2 A5 A18 RDY A20 A9 A13 A21 E4 E5 E6 E7 E8 RFU A10 A14 RFU E1 E2 E3 A1 A4 A17 RFU F1 F2 F3 F4 F5 F6 F7 F8 A0 VSS DQ1 RFU RFU DQ6 RFU A16 G1 G2 G3 G4 G5 G6 G7 G8 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU H1 H2 H3 H4 H5 H6 H7 H8 RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS J1 J2 J3 J4 J5 J6 J7 J8 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU K1 K2 K3 K4 K5 K6 K7 K8 RFU RFU RFU VCC RFU RFU RFU RFU S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y MCP Look-ahead Connection Diagram 96-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) Legend: A9 A10 NC NC B2 B9 B10 NC NC NC A1 A2 NC NC B1 NC Shared or NC (not connected) Data-storage Only C2 C3 C4 C5 C6 C7 C8 C9 AVD# VSSds CLK CE#f2 D2 D3 D4 D5 D6 D7 D8 D9 WP# A7 LB#s WP/ACC WE# A8 A11 CE1#ds VCCds RESET#ds CLKds RY/BY#ds E2 E3 E4 E5 E6 E7 E8 E9 A3 A6 UB#s RESET#f CE2s1 A19 A12 A15 F2 F3 F4 A2 A5 A18 F5 F6 F7 F8 F9 RDY A20 A9 A13 A21 G2 G3 G4 G5 G6 G7 G8 G9 A1 A4 A17 CE1#s2 A23 A10 A14 A22 H2 H3 H4 H5 H6 H7 H8 H9 A0 VSS DQ1 VCCs2 CE2s2 DQ6 A24 A16 J2 J3 J4 J5 J6 J7 J8 J2 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 CREs Flash Shared Only 1st Flash Only 2nd Flash Only 1st RAM Only 2nd RAM Only K2 K3 K4 K5 K6 K7 K8 K9 CE1#s1 DQ0 DQ10 VCCf VCCs1 DQ12 DQ7 VSS L2 L4 L4 L5 L6 L7 L8 L9 DQ8 DQ2 DQ11 A25 DQ5 VCCnds RAM Shared Only DoC Only DQ14 LOCK or WP#/ACCds M2 M3 M4 M5 M6 M7 M8 M9 A27 A26 VSSnds VCCf CE2#ds VCCQs1 NC or VCCQds DNU NC or ds N1 N2 N9 N10 NC NC NC NC P1 P2 P9 P10 NC NC NC NC Note: To provide customers with a migration path to higher densities and an option to stack more die in a package, Spansion has prepared a standard pinout that supports NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and pSRAM densities up to 4 Gigabits NOR Flash and pSRAM and DATA STORAGE densities up to 4 Gigabits See MCP data sheet (publication number S71WS256_512NC0) for input/output descriptions. The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package outline may vary. Any pinout in any MCP, however, will be a subset of the pinout above. In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, treat them as reserved and do not connect them to any other signal. For any further inquiries about the above look-ahead pinout, please refer to the application note on this subject or contact your sales office. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 13 P r e l i m i n a r y Multi-Chip Compatible Packages For this family of products, a single multi-chip compatible package is offered for each density to allow both standalone and multi-chip qualification using a single, adaptable package. This new methodology allows package standardization resulting in faster development. The multi-chip compatible package includes all the pins required for standalone device operation and verification. In addition, extra pins are included for insertion of common data storage or logic devices to be used for multi-chip products. If a standalone device is required, the extra multi-chip specific pins are not connected and the standalone device operates normally. The multi-chip compatible package sizes were chosen to serve the largest number of combinations possible. There are only a few cases where a larger package size would be required to accommodate the multi-chip combination. This multi-chip compatible package set does not allow for direct package migration from legacy products. Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. 14 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Input/Output Descriptions A23-A0 = DQ15-DQ0 CE#f1 = = OE# = WE# VCC VSS NC RDY CLK = = = = = = AVD# = RESET# = WP# = ACC = RFU = June 14, 2004 S29WSxxxN_00C0 Address inputs for WS256N (A22-A0 for WS128 and A21-A0 for WS064N). Data input/output. Chip Enable input. Asynchronous relative to CLK for the Burst mode. Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Device Power Supply. Ground. No Connect; not connected internally. Ready output. Indicates the status of the Burst read. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs. Hardware reset input. Low = device resets and returns to reading array data. Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates. programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use (see MCP look-ahead pinout for use with MCP). S29WSxxxN MirrorBitTM Flash Family 15 P r e l i m i n a r y Logic Symbol Max*+1 Amax*-A0 CLK 16 DQ15-DQ0 WP# ACC CE# OE# WE# RESET# RDY AVD# * max = 23 for the WS256N, 22 for the WS128N, and 21 for the WS064N. 16 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Ordering Information (256 Mb) The ordering part number is formed by a valid combination of the following: S29WS 256 N 0S BA W 01 0 PACKING TYPE 0 = Tray (standard; see Note 1) 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel MODEL NUMBER (Note 3) (VIO Range, Ball Count, Package Dimensions, DYB Protect/Unprotect After Power-up) 01 = 1.8 V VIO, 84-ball, 8 mm x 11.6 mm, DYB Unprotect 11 = 1.8 V VIO, 84-ball, 8 mm x 11.6 mm, DYB Protect TEMPERATURE RANGE (Note 3) W = Wireless (-25C to +85C) I = Industrial (-40C to +85C) PACKAGE TYPE AND MATERIAL BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package SPEED OPTION (BURST FREQUENCY) 0S = 80 MHz 0P = 66 MHz 0L = 54 MHz PROCESS TECHNOLOGY N = 110 nm MirrorBitTM Technology FLASH DENSITY 256 = 256 Mb DEVICE FAMILY S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory S29WS256N Valid Combinations Base Ordering Part Number Speed Option Package Type, Material, & Temperature Range S29WS256N 0S, 0P, 0L BAW (Lead (Pb)-free Compliant), BFW (Lead (Pb)-free) Model Number Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S29" and packing type designator from ordering part number. 3. For 1.5 VIO option, other boot options, or industrial temperature range, contact your local sales office. June 14, 2004 S29WSxxxN_00C0 01 11 Packing Type 0, 2, 3 (Note 1) VIO Range 1.70-1.95 V DYB Power Up State Unprotect Protect Package Type (Note 2) 8 mm x 11.6 mm 84-ball MCP-Compatible Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29WSxxxN MirrorBitTM Flash Family 17 P r e l i m i n a r y Ordering Information (128 Mb) The ordering part number is formed by a valid combination of the following: S29WS 128 N 0S BA W 01 0 PACKING TYPE 0 = Tray (standard; see note 1) 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel MODEL NUMBER (Note 3) (VIO Range, Ball Count, Package Dimensions, DYB Protect/Unprotect After Power-up) 01 = 1.8 V VIO, 84-ball, 8 mm x 11.6 mm, DYB Unprotect 11 = 1.8 V VIO, 84-ball, 8 mm x 11.6 mm, DYB Protect TEMPERATURE RANGE (Note 3) W = Wireless (-25C to +85C) I = Industrial (-40C to +85C) PACKAGE TYPE AND MATERIAL BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package SPEED OPTION (BURST FREQUENCY) 0S = 80 MHz 0P = 66 MHz 0L = 54 MHz PROCESS TECHNOLOGY N = 110 nm MirrorBitTM Technology FLASH DENSITY 128 = 128 Mb DEVICE FAMILY S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory S29WS128N Valid Combinations Base Ordering Part Number Speed Option Package Type, Material, & Temperature Range S29WS128N 0S, 0P, 0L BAW (Lead (Pb)-free Compliant), BFW (Lead (Pb)-free) Model Number Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S29" and packing type designator from ordering part number. 3. For 1.5 VIO option, other boot options, or industrial temperature range, contact your local sales office. 18 01 11 Packing Type 0, 2, 3 (Note 1) VIO Range 1.70-1.95 V DYB Power Up State Unprotect Protect Package Type (Note 2) 8 mm x 11.6 mm 84-ball MCP Compatible Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Ordering Information (64 Mb) The ordering part number is formed by a valid combination of the following: S29WS 064 N 0S BA W 05 0 PACKING TYPE 0 = Tray (standard; see note 1) 2 = 2-inch Tape and Reel 3 = 3-inch Tape and Reel MODEL NUMBER (Note 3) (VIO Range, Ball Count, Package Dimensions, DYB Protect/Unprotect After Power-up) 01 = 1.8 V VIO, 80-ball, 7 mm x 9 mm, DYB Unprotect 11 = 1.8 V VIO, 80-ball, 7 mm x 9 mm, DYB Protect TEMPERATURE RANGE (Note 3) W = Wireless (-25C to +85C) I = Industrial (-40C to +85C) PACKAGE TYPE AND MATERIAL BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package SPEED OPTION (BURST FREQUENCY) 0S = 80 MHz 0P = 66 MHz 0L = 54 MHz PROCESS TECHNOLOGY N = 110 nm MirrorBitTM Technology FLASH DENSITY 064 = 64 Mb DEVICE FAMILY S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory S29WS064N Valid Combinations Base Ordering Part Number Speed Option Package Type, Material, & Temperature Range S29WS064N 0S, 0P, 0L BAW (Lead (Pb)-free Compliant), BFW (Lead (Pb)-free) Model Number Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S29" and packing type designator from ordering part number. 3. For 1.5 VIO option, other boot options, or industrial temperature range, contact your local sales office. June 14, 2004 S29WSxxxN_00C0 01 11 Packing Type 0, 2, 3 (Note 1) VIO Range 1.70-1.95 V DYB Power Up State Unprotect Protect Package Type (Note 2) 7 mm x 9 mm 80-ball MCP-Compatible Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29WSxxxN MirrorBitTM Flash Family 19 P r e l i m i n a r y Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Operation Device Bus Operations CE# OE# WE# Addresses DQ15-0 RESET# CLK Asynchronous Read - Addresses Latched L L H Addr In I/O H X AVD# Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L Asynchronous Write L H L Addr In I/O H X L Synchronous Write L H L Addr In I/O H Standby (CE#) H X X X HIGH Z H X X Hardware Reset X X X X HIGH Z L X X Load Starting Burst Address L X H Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus L L H X Burst Data Out H Terminate current Burst read cycle H X H X HIGH Z H Terminate current Burst read cycle via RESET# X X H X HIGH Z L Terminate current Burst read cycle and start new Burst read cycle L X H Addr In I/O H Burst Read Operations (Synchronous) H X X X Legend: L = Logic 0, H = Logic 1, X = Don't Care. VersatileIOTM (VIO) Control The VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. Requirements for Asynchronous (Non-Burst) Read Operation To read data from the memory array, the system must first assert a valid address on A23-A0 for WS256N (A22-A0 for the WS128N, A21-A0 for WS064N), while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15-DQ0. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. 20 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst read and linear burst read of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See Set Configuration Register Command Sequence for further details. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle at which point the internal address counter is automatically incremented. Note that the device has a fixed internal address boundary that occurs every 128 words, starting at address 00007Fh. No boundary crossing latency is required when the device operates at or below 66 MHz to reach address 000080h. When the device operates above 66 MHz, a boundary crossing of one additional wait state is required. The timing diagram can be found in Figure 28. When the starting burst address is not divisible by four, additional waits are required. For example, if the starting burst address is divisible by four A1:0 = 00, no additional wait state is required, but if the starting burst address is at address A1:0 = 01, 10, or 11, one, two or three wait states are required, respectively, until data D4 is read. The RDY output indicates this condition to the system by deasserting (see Table 2). Table 2. Address Dependent Additional Latency Initial Address A[10] Cycle X X+1 X+2 X+3 X+4 X+5 00 D0 D1 D2 D3 D4 D5 D6 01 D1 D2 D3 -- D4 D5 D6 10 D2 D3 -- -- D4 D5 D6 11 D3 -- -- -- D4 D5 D6 X+6 Table 3 shows the address latency for variable wait state scheme, as implemented in WS256N. Table 3. Address Latency for x Wait States ( 80 MHz) Word Wait States 0 x ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 x ws D1 D2 D3 1 ws D4 D5 D6 D7 D8 2 x ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8 3 x ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8 June 14, 2004 S29WSxxxN_00C0 Cycle S29WSxxxN MirrorBitTM Flash Family 21 P r e l i m i n a r y Tables 4-7 show the address latency for variable wait state scheme, as implemented in WS128N and WS064N. Table 4. Address Latency for 6 Wait States ( 80 MHz) Word Wait States 0 6 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 6 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8 2 6 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8 3 6 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8 Cycle Table 5. Address Latency for 5 Wait States ( 68 MHz) Word Wait States 0 5 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 5 ws D1 D2 D3 D4 D5 D6 D7 D8 D9 2 5 ws D2 D3 1 ws D4 D5 D6 D7 D8 D9 3 5 ws D3 1 ws 1 ws D4 D5 D6 D7 D8 D9 Cycle Table 6. Address Latency for 4 Wait States ( 54 MHz) Word Wait States 0 4 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 4 ws D1 D2 D3 D4 D5 D6 D7 D8 D9 2 4 ws D2 D3 D4 D5 D6 D7 D8 D9 D10 3 4 ws D3 1 ws D4 D5 D6 D7 D8 D9 D10 Cycle Table 7. Address Latency for 3 Wait States ( 40 MHz) Word Wait States 0 3 ws D0 D1 D2 D3 D4 D5 D6 D7 1 3 ws D1 D2 D3 D4 D5 D6 D7 D8 D9 2 3 ws D2 D3 D4 D5 D6 D7 D8 D9 D10 3 3 ws D3 D4 D5 D6 D7 D8 D9 D10 D11 Cycle D8 Tables 8-11 show the address/boundary crossing latency for variable wait state if a boundary crossing occurs during initial access as implemented in WS128N and WS064N. Table 8. 22 Address/Boundary Crossing Latency for 6 Wait States ( 80 MHz) Word Wait States 0 6 ws D0 D1 D2 D3 1 ws D4 D5 D6 D7 1 6 ws D1 D2 D3 1 ws 1 ws D4 D5 D6 D7 2 6 ws D2 D3 1 ws 1 ws 1 ws D4 D5 D6 D7 3 6 ws D3 1 ws 1 ws 1 ws 1 ws D4 D5 D6 D7 Cycle S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 9. Address/Boundary Crossing Latency for 5 Wait States (< 66 MHz) Word Wait States 0 5 ws D0 D1 1 5 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8 2 5 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8 3 5 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8 Table 10. Cycle D2 D3 D4 D5 D6 D7 D8 Address/Boundary Crossing Latency for 4 Wait States (< 54 MHz) Word Wait States 0 4 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 4 ws D1 D2 D3 D4 D5 D6 D7 D8 D9 2 4 ws D2 D3 1 ws D4 D5 D6 D7 D8 D9 3 4 ws D3 1 ws 1 ws D4 D5 D6 D7 D8 D9 Table 11. Cycle Address/Boundary Crossing Latency for 3 Wait States (< 40 MHz) Word Wait States 0 3 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 3 ws D1 D2 D3 D4 D5 D6 D7 D8 D9 2 3 ws D2 D3 D4 D5 D6 D7 D8 D9 D10 3 3 ws D3 1 ws D4 D5 D6 D7 D8 D9 D10 Cycle Continuous Burst The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1. If the host system crosses a 128-word line boundary while reading in burst mode, and the subsequent word line is not programming or erasing, a one-cycle latency is required as described above if the device is operating above 66 MHz. If the device is operating at or below 66 MHz, no boundary crossing latency is required. If the host system crosses the bank boundary while the subsequent bank is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. 8-, 16-, and 32-Word Linear Burst with Wrap Around The next three burst read modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 12.) June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 23 P r e l i m i n a r y Table 12. Burst Address Groups Mode Group Size Group Address Ranges 8-word 8 words 0-7h, 8-Fh, 10-17h,... 16-word 16 words 0-Fh, 10-1Fh, 20-2Fh,... 32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh,... For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-3839-3A-3Bh if wrap around is enabled. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group and stops at the group size, terminating the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (except during the initial access). (See Figure 15.) 8-, 16-, and 32-Word Linear Burst without Wrap Around If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to the maximum memory address of the selected number of words. The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. For example: if the starting address in the 8word mode is 3Ch, the address range to be read would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read will require a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words. Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active. For more information, see Table 26. RDY: Ready The RDY is a dedicated output, controlled by CE#. When the device is configured in the Synchronous mode and RDY is at logic low, the system should wait 1 clock cycle before expecting the next word of data. Handshaking The device is equipped with a handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. See Set Configuration Register Command Sequence and Requirements for Synchronous (Burst) Read Operation for more information. 24 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 31 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored when the device is configured in the Asynchronous mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK- and AVD#-induced address latches are supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE# (see Table 26). An erase operation can erase one sector, multiple sectors, or the entire device. Table 21 indicates the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A "bank address" is the set of address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. ICC2 in "DC Characteristics" represents the active current specification for the write mode. "AC Characteristics--Synchronous" and "AC Characteristics--Asynchronous" contain timing specification tables and timing diagrams for write operations. Unlock Bypass Mode The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a set of words, instead of four. See Unlock Bypass Command Sequence for more details. Accelerated Program/Chip Erase Operations The device offers accelerated program and accelerated chip/erase operations through the ACC function. ACC is intended to allow faster manufacturing throughput at the factory and not to be used in system operations. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a "Write-to-Buffer-Abort Reset" is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 25 P r e l i m i n a r y reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. Write Buffer Programming Operation Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard "word" programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the starting address in which programming will occur. At this point, the system writes the number of "word locations minus 1" that will be loaded into the page buffer at the starting address in which programming will occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the "Program Buffer to Flash" confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: the number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the "writebuffer-page" address. All subsequent address/data pairs must fall within the "selected-write-buffer-page". The "write-buffer-page" is selected by using the addresses AMAX - A5 where AMAX is A23 for WS256N, A22 for WS128N, and A21 for WS064N. The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple "write-buffer-pages". This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected "write-bufferpage", the operation will ABORT.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. Note that if a Write Buffer address location is loaded multiple times, the "address/ data pair" counter will be decremented for every data load operation. Also, the last data loaded at a location before the "Program Buffer to Flash" confirm command will be programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then "go busy." The Data Bar polling techniques 26 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer "embedded" programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the "Number of Locations to Program" step. Write to an address in a sector different than the one specified during the "Write-Buffer-Load" command. Write an Address/Data pair to a different write-buffer-page than the one selected by the "Starting Address" during the "write buffer data loading" stage of the operation. Write data other than the "Confirm Command" after the specified number of "data load" cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A "Write-to-Buffer-Abort reset" command sequence is required when using the Write-Buffer-Programming features in Unlock Bypass mode. Note that the SecSiTM sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. However, programming the same word address multiple times without intervening erases requires a modified programming method. Please contact your local SpansionTM representative for details. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (separate from the memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 21). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The autoselect codes can also be accessed in-system through the command register. See Command Definition Summary for command sequence requirements. Note that if a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle of the autoselect command, the host system can read au- June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 27 P r e l i m i n a r y toselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes, the host system must issue the autoselect command via the command register, as shown in the Command Definition Summary section. See Autoselect Command Sequence for more information. Advanced Sector Protection and Unprotection This advanced security feature provides an additional level of protection to all sectors against inadvertant program or erase operations. The advanced sector protection feature disables both programming and erase operations in a sector while the advanced sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented using either or both of the two methods Hardware method Software method Persistent/Password Sector Protection is achieved by using the software method while the sector protection with WP# pin is achieved by using the hardware method. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. Persistent Mode Lock Bit Password Mode Lock Bit If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Mode Lock Bit. This will permanently set the part to operate using only Persistent Sector Protection. However, if the customer decides to use the Password Sector Protection method, they must set the Password Mode Lock Bit. This will permanently set the part to operate using only Password Sector Protection. It is important to remember that setting either the Persistent Mode Lock Bit or the Password Mode Lock Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. If both are selected to be set at the same time, the operation will abort. This is done so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Sector Protection Mode. The device is shipped with all sectors unprotected. Optional SpansionTM programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for more details. Persistent Mode Lock Bit A Persistent Mode Lock Bit exists to guarantee that the device remain in software sector protection. Once programmed (set to "0"), the Persistent Mode Lock Bit prevents programming of the Password Mode Lock Bit. This allows protection from potential hackers locking the device by placing the device in password sector protection mode and then changing the password accordingly. 28 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Password Mode Lock Bit In order to select the Password Sector Protection scheme, the customer must first program the password. It is recommended that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1.It permanently sets the device to operate using the Password Sector Protection Mode. It is not possible to reverse this function. 2.It also disables all further commands to the password region. All program and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is after it is set. If the password is lost after setting the Password Mode Lock Bit, there will be no way to clear the PPB Lock Bit. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Lock Bit is not erasable. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. Sector Protection The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection A software enabled command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated software enabled protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin (WP#) can prevent program or erase operations in the outermost sectors.The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Persistently Locked--A sector is protected and cannot be changed. Dynamically Locked--The sector is protected and can be changed by a simple command June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 29 P r e l i m i n a r y Unlocked--The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" namely Persistent Protection Bit (PPB), Dynamic Protection Bit (DYB), and Persistent Protection Bit Lock (PPB Lock) are used to achieve the desired sector protection scheme Persistent Protection Bit (PPB) PPB is used to as an advanced security feature to protect individual sectors from being programmed or erased thereby providing additional level of protection. Every sector is assigned a Persistent Protection Bit. Each PPB is individually programmed through the PPB Program Command. However all PPBs are erased in parallel through the All PPB Erase Command. Prior to erasing, these bits don't have to be preprogrammed. The Embedded Erase algorithm automatically preprograms and verifies prior to an electrical erase. The system is not required to provide any controls or timings during these operations. The PPBs retain their state across power cycles because they are Non-Volatile. The PPBs have the same endurance as the flash memory. Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode PPB Lock Bit is a global volatile bit and provides an additional level of protection to the sectors. When programmed (set to "0"), all the PPBs are locked and hence none of them can be changed. When erased (cleared to "1"), the PPBs are changeable. There is only one PPB Lock Bit in every device. Only a hardware reset or a power-up clears the PPB Lock Bit. Note that there is no software solution; that is, there is no command sequence that would unlock the PPB Lock Bit. Once all PPBs are configured to the desired settings, the PPB Lock Bit may be set (programmed to "0"). The PPB Lock Bit is set by issuing the PPB Lock Bit Set Command. Programming or setting the PPB Lock Bit disables program and erase commands to all the PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock Bit is to go through a hardware or power-up reset. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can disable the PPB Lock Bit to prevent any further changes to the PPBs during system operation. Dynamic Protection Bit (DYB) DYB is another security feature used to protect individual sectors from being programmed or erased inadvertently. It is a volatile protection bit and is assigned to each sector. Each DYB can be individually modified through the DYB Set Command or the DYB Clear Command. The Protection Status for a particular sector is determined by the status of the PPB and the DYB relative to that sector. For the sectors that have the PPBs cleared (erased to "1"), the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Set or Clear command sequences, the DYBs will be set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. These states are the so-called Dynamic Locked or Unlocked states due to the fact that they can switch back and forth between the protected and unprotected states. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the 30 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y easy removal of protection when changes are needed. The DYBs maybe set (programmed to "0") or cleared (erased to "1") as often as needed. When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs are set or cleared depending upon the ordering option chosen. If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectors may be modified depending upon the PPB state of that sector. (See Table 13) If the option to set the DYBs after power up is chosen (programmed to "0"), then the sectors would be in the protected state. The PPB Lock Bit defaults to the cleared state (erased to "1") after power up and the PPBs retain their previous state as they are non-volatile. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set or Clear command for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again will lock the PPBs, and the device operates normally again. To achieve the best protection, execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC = VIH. Table 13. Sector Protection Schemes DYB PPB PPB Lock Sector State 1 1 1 Sector Unprotected 0 1 1 Sector Protected through DYB 1 0 1 Sector Protected through PPB 0 0 1 Sector Protected through PPB and DYB 1 1 0 Sector Unprotected 0 1 0 Sector Protected through DYB 1 0 0 Sector Protected through PPB 0 0 0 Sector Protected through PPB and DYB Table 13 contains all possible combinations of the DYB, PPB, and PPB Lock relating to the status of the sector. In summary, if the PPB is set (programmed to "0"), and the PPB Lock is set (programmed to "0"), the sector is protected and the protection can not be removed until the next power cycle clears (erase to "1") the PPB Lock Bit. Once the PPB Lock Bit is cleared (erased to "1"), the sector can be persistently locked or unlocked. Likewise, if both PPB Lock Bit or PPB is cleared (erased to "1") the sector can then be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 31 P r e l i m i n a r y If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. Password Sector Protection The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection Mode and the Password Sector Protection Mode: When the device is first powered up, or comes out of a reset cycle, the PPB Lock Bit is set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock Bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a non-erasable region of the flash memory. Once the Password Mode Lock Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock Bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock Bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a builtin 1 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands. The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode The Persistent Protection Bit Lock (PPB Lock Bit) is a volatile bit that reflects the state of the Password Mode Lock Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command to enter the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET# or taking the device through a power-on reset, resets the PPB Lock Bit to a "1". If the Password Mode Lock Bit is not set (device is operating in the default Persistent Protection Mode). The Password Unlock command is ignored in Persistent Sector Protection Mode. 32 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Lock Register The Lock Register consists of 3 bits. The Customer SecSi Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, and the Password Protection Mode Lock Bit is DQ2. Each of these bits are non-volatile. DQ15-DQ3 are reserved and will be 1's. Table 14. DQ15-3 1's Lock Register DQ2 DQ1 DQ0 Password Protection Persistent Protection Customer SecSi Mode Lock Bit Mode Lock Bit Sector Protection Bit Hardware Data Protection Mode The device offers two types of data protection at the sector level: When WP# is at VIL, the four outermost sectors are locked (device specific). When ACC is at VIL, all sectors are locked. The write protect pin (WP#) adds a final level of hardware program and erase protection to the outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of outermost sectors in a dual-bootconfigured device. When this pin is low it is not possible to change the contents of these outermost sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin during the command sequence, the device disables program and erase functions in the "outermost" boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected after the embedded operation. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 33 P r e l i m i n a r y Write Pulse "Glitch" Protection Noise pulses of less than tWEP on WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the standby mode when the CE# and RESET# inputs are both held at VCC. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in "DC Characteristics" represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in "DC Characteristics" represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not at VSS, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. 34 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y See Hardware Reset (RESET#) for RESET# parameters and to Figure 20 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 words in length. All reads outside of the 256 word address range will return non-valid data. The Factory Indicator Bit (DQ7) is used to indicate whether or not the Factory SecSi Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer SecSi Sector is locked when shipped from the factory. The Factory SecSi bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN and customer code once the product is shipped to the field. The Factory portion of the SecSi Sector is locked when shipped and the Customer SecSi Sector that is either locked or is lockable. The Factory SecSi Sector is always protected when shipped from the factory, and has the Factory Indicator Bit (DQ7) permanently set to a "1". The Customer SecSi Sector is typically shipped unprotected (set to "0"), allowing customers to utilize that sector in any manner they choose. Once the Customer SecSi Sector area is protected, the Customer Indicator Bit will be permanently set to "1." The system accesses the SecSi Sector through a command sequence (see Enter SecSiTM Sector/Exit SecSi Sector Command Sequence). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. While SecSi Sector access is enabled, Memory Array read access, program operations, and erase operations to all sectors other than SA0 are also available. On powerup, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory In a factory sector locked device, the Factory SecSi Sector is protected when the device is shipped from the factory. The Factory SecSi Sector cannot be modified in any way. The device is pre programmed with both a random number and a secure ESN. The Factory SecSi Sector is located at addresses 000000h-00007Fh. The device is available pre programmed with one of the following: A random, secure ESN only within the Factor SecSi Sector Customer code within the Customer SecSi Sector through the SpansionTM programming service Both a random, secure ESN and customer code through the SpansionTM programming service. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 35 P r e l i m i n a r y Table 15. SecSiTM Sector Addresses Sector Sector Size Address Range Customer 128 words 000080h-0000FFh Factory 128 words 000000h-00007Fh Customers may opt to have their code programmed through the SpansionTM programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory SecSi Sector and Customer SecSi Sector permanently locked. Contact your local representative for details on using SpansionTM programming services. Customer SecSi Sector If the security feature is not required, the Customer SecSi Sector can be treated as an additional Flash memory space. The Customer SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer SecSi Sector, but reading in Banks 1 through 15 is available. The Customer SecSi Sector is located at addresses 000080h-0000FFh. The Customer SecSi Sector area can be protected by writing the SecSi Sector Protection Bit Lock command sequence. Once the Customer SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the memory array. The device returns to the memory array at bank 0. The Customer SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Customer SecSi Sector area and none of the bits in the Customer SecSi Sector memory space can be modified in any way. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at valid addresses within that bank (see Tables 16- 19). All reads outside of the CFI address range, within the bank, will return non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. For further information, please refer to the CFI Specification and CFI Publication 100. Please contact your sales office for copies of these documents. 36 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 16. CFI Query Identification String Addresses Data 10h 11h 12h 0051h 0052h 0059h Description Query Unique ASCII string "QRY" 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 17. System Interface String Addresses Data Description 1Bh 0017h VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1Ch 0019h VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0006h Typical timeout per single byte/word write 2N s 20h 0009h Typical timeout for Min. size buffer write 2N s (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0003h Max. timeout for byte/word write 2N times typical 24h 0001h Max. timeout for buffer write 2N times typical 25h 0002h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Table 18. Addresses Device Geometry Definition Data Description 0019h (WS256N) 27h 0018h (WS128N) Device Size = 2N byte 0017h (WS064N) 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0006h 0000h Max. number of bytes in multi-byte write = 2N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0003h 0000h 0080h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 37 P r e l i m i n a r y Table 18. Device Geometry Definition (Continued) Addresses Data 31h 00FDh (WS256N) 007Dh (WS128N) 003Dh (WS064N) 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information Table 19. Description Erase Block Region 2 Information Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string "PRI" 43h 0031h Major version number, ASCII 44h 0034h Minor version number, ASCII 45h 0100h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0100 = 0.11 m 38 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0000h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0008h Sector Protect/Unprotect scheme 08 = Advanced Sector Protection 4Ah 00DFh (WS256N) 006Fh (WS128N) 0037h (WS064N) 4Bh 0001h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page 4Dh 0085h 4Eh 0095h 4Fh 0001h Simultaneous Operation Number of Sectors in all banks except boot bank ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 0001h = Dual Boot Device S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 19. Primary Vendor-Specific Extended Query (Continued) Addresses Data 50h 0001h 51h 0001h 52h 0007h SecSi Sector (Customer OTP Area) Size 2N bytes 53h 0014h Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns 54h 0014h Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns 55h 0005h Erase Suspend Time-out Maximum 2N ns 56h 0005h Program Suspend Time-out Maximum 2N ns 57h 0010h Bank Organization: X = Number of banks 58h 0013h (WS256N) 000Bh (WS128N) 0007h (WS064N) Bank 0 Region Information. X = Number of sectors in bank 59h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 1 Region Information. X = Number of sectors in bank 5Ah 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 2 Region Information. X = Number of sectors in bank 5Bh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 3 Region Information. X = Number of sectors in bank 5Ch 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 4 Region Information. X = Number of sectors in bank 5Dh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 5 Region Information. X = Number of sectors in bank 5Eh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 6 Region Information. X = Number of sectors in bank 5Fh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 7 Region Information. X = Number of sectors in bank 60h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 8 Region Information. X = Number of sectors in bank 61h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 9 Region Information. X = Number of sectors in bank 62h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 10 Region Information. X = Number of sectors in bank 63h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 11 Region Information. X = Number of sectors in bank June 14, 2004 S29WSxxxN_00C0 Description Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01=Supported S29WSxxxN MirrorBitTM Flash Family 39 P r e l i m i n a r y Table 19. Primary Vendor-Specific Extended Query (Continued) Addresses Data Description 64h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 12 Region Information. X = Number of sectors in bank 65h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 13 Region Information. X = Number of sectors in bank 66h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 14 Region Information. X = Number of sectors in bank 67h 0013h (WS256N) 000Bh (WS128N) 0007h (WS064N) Bank 15 Region Information. X = Number of sectors in bank Table 20. Bank Bank 0 40 WS256N Sector & Memory Address Map Sector Sector Size A23-A14 (x16) Address Range SA0 16 Kwords 0000000000 000000h-003FFFh SA1 16 Kwords 0000000001 004000h-007FFFh SA2 16 Kwords 0000000010 008000h-00BFFFh SA3 16 Kwords 0000000011 00C000h-00FFFFh SA4 64 Kwords 00000001XX 010000h-01FFFFh SA5 64 Kwords 00000010XX 020000h-02FFFFh SA6 64 Kwords 00000011XX 030000h-03FFFFh SA7 64 Kwords 00000100XX 040000h-04FFFFh SA8 64 Kwords 00000101XX 050000h-05FFFFh SA9 64 Kwords 00000110XX 060000h-06FFFFh SA10 64 Kwords 00000111XX 070000h-07FFFFh SA11 64 Kwords 00001000XX 080000h-08FFFFh SA12 64 Kwords 00001001XX 090000h-09FFFFh SA13 64 Kwords 00001010XX 0A0000h-0AFFFFh SA14 64 Kwords 00001011XX 0B0000h-0BFFFFh SA15 64 Kwords 00001100XX 0C0000h-0CFFFFh SA16 64 Kwords 00001101XX 0D0000h-0DFFFFh SA17 64 Kwords 00001110XX 0E0000h-0EFFFFh SA18 64 Kwords 00001111XX 0F0000h-0FFFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 20. Bank Bank 1 Bank 2 June 14, 2004 S29WSxxxN_00C0 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA19 64 Kwords 00010000XX 100000h-10FFFFh SA20 64 Kwords 00010001XX 110000h-11FFFFh SA21 64 Kwords 00010010XX 120000h-12FFFFh SA22 64 Kwords 00010011XX 130000h-13FFFFh SA23 64 Kwords 00010100XX 140000h-14FFFFh SA24 64 Kwords 00010101XX 150000h-15FFFFh SA25 64 Kwords 00010110XX 160000h-16FFFFh SA26 64 Kwords 00010111XX 170000h-17FFFFh SA27 64 Kwords 00011000XX 180000h-18FFFFh SA28 64 Kwords 00011001XX 190000h-19FFFFh SA29 64 Kwords 00011010XX 1A0000h-1AFFFFh SA30 64 Kwords 00011011XX 1B0000h-1BFFFFh SA31 64 Kwords 00011100XX 1C0000h-1CFFFFh SA32 64 Kwords 00011101XX 1D0000h-1DFFFFh SA33 64 Kwords 00011110XX 1E0000h-1EFFFFh SA34 64 Kwords 00011111XX 1F0000h-1FFFFFh SA35 64 Kwords 00100000XX 200000h-20FFFFh SA36 64 Kwords 00100001XX 210000h-21FFFFh SA37 64 Kwords 00100010XX 220000h-22FFFFh SA38 64 Kwords 00100011XX 230000h-23FFFFh SA39 64 Kwords 00100100XX 240000h-24FFFFh SA40 64 Kwords 00100101XX 250000h-25FFFFh SA41 64 Kwords 00100110XX 260000h-26FFFFh SA42 64 Kwords 00100111XX 270000h-27FFFFh SA43 64 Kwords 00101000XX 280000h-28FFFFh SA44 64 Kwords 00101001XX 290000h-29FFFFh SA45 64 Kwords 00101010XX 2A0000h-2AFFFFh SA46 64 Kwords 00101011XX 2B0000h-2BFFFFh SA47 64 Kwords 00101100XX 2C0000h-2CFFFFh SA48 64 Kwords 00101101XX 2D0000h-2DFFFFh SA49 64 Kwords 00101110XX 2E0000h-2EFFFFh SA50 64 Kwords 00101111XX 2F0000h-2FFFFFh S29WSxxxN MirrorBitTM Flash Family 41 P r e l i m i n a r y Table 20. Bank Bank 3 Bank 4 42 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA51 64 Kwords 00110000XX 300000h-30FFFFh SA52 64 Kwords 00110001XX 310000h-31FFFFh SA53 64 Kwords 00110010XX 320000h-32FFFFh SA54 64 Kwords 00110011XX 330000h-33FFFFh SA55 64 Kwords 00110100XX 340000h-34FFFFh SA56 64 Kwords 00110101XX 350000h-35FFFFh SA57 64 Kwords 00110110XX 360000h-36FFFFh SA58 64 Kwords 00110111XX 370000h-37FFFFh SA59 64 Kwords 00111000XX 380000h-38FFFFh SA60 64 Kwords 00111001XX 390000h-39FFFFh SA61 64 Kwords 00111010XX 3A0000h-3AFFFFh SA62 64 Kwords 00111011XX 3B0000h-3BFFFFh SA63 64 Kwords 00111100XX 3C0000h-3CFFFFh SA64 64 Kwords 00111101XX 3D0000h-3DFFFFh SA65 64 Kwords 00111110XX 3E0000h-3EFFFFh SA66 64 Kwords 00111111XX 3F0000h-3FFFFFh SA67 64 Kwords 01000000XX 400000h-40FFFFh SA68 64 Kwords 01000001XX 410000h-41FFFFh SA69 64 Kwords 01000010XX 420000h-42FFFFh SA70 64 Kwords 01000011XX 430000h-43FFFFh SA71 64 Kwords 01000100XX 440000h-44FFFFh SA72 64 Kwords 01000101XX 450000h-45FFFFh SA73 64 Kwords 01000110XX 460000h-46FFFFh SA74 64 Kwords 01000111XX 470000h-47FFFFh SA75 64 Kwords 01001000XX 480000h-48FFFFh SA76 64 Kwords 01001001XX 490000h-49FFFFh SA77 64 Kwords 01001010XX 4A0000h-4AFFFFh SA78 64 Kwords 01001011XX 4B0000h-4BFFFFh SA79 64 Kwords 01001100XX 4C0000h-4CFFFFh SA80 64 Kwords 01001101XX 4D0000h-4DFFFFh SA81 64 Kwords 01001110XX 4E0000h-4EFFFFh SA82 64 Kwords 01001111XX 4F0000h-4FFFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 20. Bank Bank 5 Bank 6 June 14, 2004 S29WSxxxN_00C0 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA83 64 Kwords 01010000XX 500000h-50FFFFh SA84 64 Kwords 01010001XX 510000h-51FFFFh SA85 64 Kwords 01010010XX 520000h-52FFFFh SA86 64 Kwords 01010011XX 530000h-53FFFFh SA87 64 Kwords 01010100XX 540000h-54FFFFh SA88 64 Kwords 01010101XX 550000h-55FFFFh SA89 64 Kwords 01010110XX 560000h-56FFFFh SA90 64 Kwords 01010111XX 570000h-57FFFFh SA91 64 Kwords 01011000XX 580000h-58FFFFh SA92 64 Kwords 01011001XX 590000h-59FFFFh SA93 64 Kwords 01011010XX 5A0000h-5AFFFFh SA94 64 Kwords 01011011XX 5B0000h-5BFFFFh SA95 64 Kwords 01011100XX 5C0000h-5CFFFFh SA96 64 Kwords 01011101XX 5D0000h-5DFFFFh SA97 64 Kwords 01011110XX 5E0000h-5EFFFFh SA98 64 Kwords 01011111XX 5F0000h-5FFFFFh SA99 64 Kwords 01100000XX 600000h-60FFFFh SA100 64 Kwords 01100001XX 610000h-61FFFFh SA101 64 Kwords 01100010XX 620000h-62FFFFh SA102 64 Kwords 01100011XX 630000h-63FFFFh SA103 64 Kwords 01100100XX 640000h-64FFFFh SA104 64 Kwords 01100101XX 650000h-65FFFFh SA105 64 Kwords 01100110XX 660000h-66FFFFh SA106 64 Kwords 01100111XX 670000h-67FFFFh SA107 64 Kwords 01101000XX 680000h-68FFFFh SA108 64 Kwords 01101001XX 690000h-69FFFFh SA109 64 Kwords 01101010XX 6A0000h-6AFFFFh SA110 64 Kwords 01101011XX 6B0000h-6BFFFFh SA111 64 Kwords 01101100XX 6C0000h-6CFFFFh SA112 64 Kwords 01101101XX 6D0000h-6DFFFFh SA113 64 Kwords 01101110XX 6E0000h-6EFFFFh SA114 64 Kwords 01101111XX 6F0000h-6FFFFFh S29WSxxxN MirrorBitTM Flash Family 43 P r e l i m i n a r y Table 20. Bank Bank 7 Bank 8 44 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA115 64 Kwords 01110000XX 700000h-70FFFFh SA116 64 Kwords 01110001XX 710000h-71FFFFh SA117 64 Kwords 01110010XX 720000h-72FFFFh SA118 64 Kwords 01110011XX 730000h-73FFFFh SA119 64 Kwords 01110100XX 740000h-74FFFFh SA120 64 Kwords 01110101XX 750000h-75FFFFh SA121 64 Kwords 01110110XX 760000h-76FFFFh SA122 64 Kwords 01110111XX 770000h-77FFFFh SA123 64 Kwords 01111000XX 780000h-78FFFFh SA124 64 Kwords 01111001XX 790000h-79FFFFh SA125 64 Kwords 01111010XX 7A0000h-7AFFFFh SA126 64 Kwords 01111011XX 7B0000h-7BFFFFh SA127 64 Kwords 01111100XX 7C0000h-7CFFFFh SA128 64 Kwords 01111101XX 7D0000h-7DFFFFh SA129 64 Kwords 01111110XX 7E0000h-7EFFFFh SA130 64 Kwords 01111111XX 7F0000h-7FFFFFh SA131 64 Kwords 10000000XX 800000h-80FFFFh SA132 64 Kwords 10000001XX 810000h-81FFFFh SA133 64 Kwords 10000010XX 820000h-82FFFFh SA134 64 Kwords 10000011XX 830000h-83FFFFh SA135 64 Kwords 10000100XX 840000h-84FFFFh SA136 64 Kwords 10000101XX 850000h-85FFFFh SA137 64 Kwords 10000110XX 860000h-86FFFFh SA138 64 Kwords 10000111XX 870000h-87FFFFh SA139 64 Kwords 10001000XX 880000h-88FFFFh SA140 64 Kwords 10001001XX 890000h-89FFFFh SA141 64 Kwords 10001010XX 8A0000h-8AFFFFh SA142 64 Kwords 10001011XX 8B0000h-8BFFFFh SA143 64 Kwords 10001100XX 8C0000h-8CFFFFh SA144 64 Kwords 10001101XX 8D0000h-8DFFFFh SA145 64 Kwords 10001110XX 8E0000h-8EFFFFh SA146 64 Kwords 10001111XX 8F0000h-8FFFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 20. Bank Bank 9 Bank 10 June 14, 2004 S29WSxxxN_00C0 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA147 64 Kwords 10010000XX 900000h-90FFFFh SA148 64 Kwords 10010001XX 910000h-91FFFFh SA149 64 Kwords 10010010XX 920000h-92FFFFh SA150 64 Kwords 10010011XX 930000h-93FFFFh SA151 64 Kwords 10010100XX 940000h-94FFFFh SA152 64 Kwords 10010101XX 950000h-95FFFFh SA153 64 Kwords 10010110XX 960000h-96FFFFh SA154 64 Kwords 10010111XX 970000h-97FFFFh SA155 64 Kwords 10011000XX 980000h-98FFFFh SA156 64 Kwords 10011001XX 990000h-99FFFFh SA157 64 Kwords 10011010XX 9A0000h-9AFFFFh SA158 64 Kwords 10011011XX 9B0000h-9BFFFFh SA159 64 Kwords 10011100XX 9C0000h-9CFFFFh SA160 64 Kwords 10011101XX 9D0000h-9DFFFFh SA161 64 Kwords 10011110XX 9E0000h-9EFFFFh SA162 64 Kwords 10011111XX 9F0000h-9FFFFFh SA163 64 Kwords 10100000XX A00000h-A0FFFFh SA164 64 Kwords 10100001XX A10000h-A1FFFFh SA165 64 Kwords 10100010XX A20000h-A2FFFFh SA166 64 Kwords 10100011XX A30000h-A3FFFFh SA167 64 Kwords 10100100XX A40000h-A4FFFFh SA168 64 Kwords 10100101XX A50000h-A5FFFFh SA169 64 Kwords 10100110XX A60000h-A6FFFFh SA170 64 Kwords 10100111XX A70000h-A7FFFFh SA171 64 Kwords 10101000XX A80000h-A8FFFFh SA172 64 Kwords 10101001XX A90000h-A9FFFFh SA173 64 Kwords 10101010XX AA0000h-AAFFFFh SA174 64 Kwords 10101011XX AB0000h-ABFFFFh SA175 64 Kwords 10101100XX AC0000h-ACFFFFh SA176 64 Kwords 10101101XX AD0000h-ADFFFFh SA177 64 Kwords 10101110XX AE0000h-AEFFFFh SA178 64 Kwords 10101111XX AF0000h-AFFFFFh S29WSxxxN MirrorBitTM Flash Family 45 P r e l i m i n a r y Table 20. Bank Bank 11 Bank 12 46 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA179 64 Kwords 10110000XX B00000h-B0FFFFh SA180 64 Kwords 10110001XX B10000h-B1FFFFh SA181 64 Kwords 10110010XX B20000h-B2FFFFh SA182 64 Kwords 10110011XX B30000h-B3FFFFh SA183 64 Kwords 10110100XX B40000h-B4FFFFh SA184 64 Kwords 10110101XX B50000h-B5FFFFh SA185 64 Kwords 10110110XX B60000h-B6FFFFh SA186 64 Kwords 10110111XX B70000h-B7FFFFh SA187 64 Kwords 10111000XX B80000h-B8FFFFh SA188 64 Kwords 10111001XX B90000h-B9FFFFh SA189 64 Kwords 10111010XX BA0000h-BAFFFFh SA190 64 Kwords 10111011XX BB0000h-BBFFFFh SA191 64 Kwords 10111100XX BC0000h-BCFFFFh SA192 64 Kwords 10111101XX BD0000h-BDFFFFh SA193 64 Kwords 10111110XX BE0000h-BEFFFFh SA194 64 Kwords 10111111XX BF0000h-BFFFFFh SA195 64 Kwords 11000000XX C00000h-C0FFFFh SA196 64 Kwords 11000001XX C10000h-C1FFFFh SA197 64 Kwords 11000010XX C20000h-C2FFFFh SA198 64 Kwords 11000011XX C30000h-C3FFFFh SA199 64 Kwords 11000100XX C40000h-C4FFFFh SA200 64 Kwords 11000101XX C50000h-C5FFFFh SA201 64 Kwords 11000110XX C60000h-C6FFFFh SA202 64 Kwords 11000111XX C70000h-C7FFFFh SA203 64 Kwords 11001000XX C80000h-C8FFFFh SA204 64 Kwords 11001001XX C90000h-C9FFFFh SA205 64 Kwords 11001010XX CA0000h-CAFFFFh SA206 64 Kwords 11001011XX CB0000h-CBFFFFh SA207 64 Kwords 11001100XX CC0000h-CCFFFFh SA208 64 Kwords 11001101XX CD0000h-CDFFFFh SA209 64 Kwords 11001110XX CE0000h-CEFFFFh SA210 64 Kwords 11001111XX CF0000h-CFFFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 20. Bank Bank 13 Bank 14 June 14, 2004 S29WSxxxN_00C0 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA211 64 Kwords 11010000XX D00000h-D0FFFFh SA212 64 Kwords 11010001XX D10000h-D1FFFFh SA213 64 Kwords 11010010XX D20000h-D2FFFFh SA214 64 Kwords 11010011XX D30000h-D3FFFFh SA215 64 Kwords 11010100XX D40000h-D4FFFFh SA216 64 Kwords 11010101XX D50000h-D5FFFFh SA217 64 Kwords 11010110XX D60000h-D6FFFFh SA218 64 Kwords 11010111XX D70000h-D7FFFFh SA219 64 Kwords 11011000XX D80000h-D8FFFFh SA220 64 Kwords 11011001XX D90000h-D9FFFFh SA221 64 Kwords 11011010XX DA0000h-DAFFFFh SA222 64 Kwords 11011011XX DB0000h-DBFFFFh SA223 64 Kwords 11011100XX DC0000h-DCFFFFh SA224 64 Kwords 11011101XX DD0000h-DDFFFFh SA225 64 Kwords 11011110XX DE0000h-DEFFFFh SA226 64 Kwords 11011111XX DF0000h-DFFFFFh SA227 64 Kwords 11100000XX E00000h-E0FFFFh SA228 64 Kwords 11100001XX E10000h-E1FFFFh SA229 64 Kwords 11100010XX E20000h-E2FFFFh SA230 64 Kwords 11100011XX E30000h-E3FFFFh SA231 64 Kwords 11100100XX E40000h-E4FFFFh SA232 64 Kwords 11100101XX E50000h-E5FFFFh SA233 64 Kwords 11100110XX E60000h-E6FFFFh SA234 64 Kwords 11100111XX E70000h-E7FFFFh SA235 64 Kwords 11101000XX E80000h-E8FFFFh SA236 64 Kwords 11101001XX E90000h-E9FFFFh SA237 64 Kwords 11101010XX EA0000h-EAFFFFh SA238 64 Kwords 11101011XX EB0000h-EBFFFFh SA239 64 Kwords 11101100XX EC0000h-ECFFFFh SA240 64 Kwords 11101101XX ED0000h-EDFFFFh SA241 64 Kwords 11101110XX EE0000h-EEFFFFh SA242 64 Kwords 11101111XX EF0000h-EFFFFFh S29WSxxxN MirrorBitTM Flash Family 47 P r e l i m i n a r y Table 20. Bank Bank 15 WS256N Sector & Memory Address Map (Continued) Sector Sector Size A23-A14 (x16) Address Range SA243 64 Kwords 11110000XX F00000h-F0FFFFh SA244 64 Kwords 11110001XX F10000h-F1FFFFh SA245 64 Kwords 11110010XX F20000h-F2FFFFh SA246 64 Kwords 11110011XX F30000h-F3FFFFh SA247 64 Kwords 11110100XX F40000h-F4FFFFh SA248 64 Kwords 11110101XX F50000h-F5FFFFh SA249 64 Kwords 11110110XX F60000h-F6FFFFh SA250 64 Kwords 11110111XX F70000h-F7FFFFh SA251 64 Kwords 11111000XX F80000h-F8FFFFh SA252 64 Kwords 11111001XX F90000h-F9FFFFh SA253 64 Kwords 11111010XX FA0000h-FAFFFFh SA254 64 Kwords 11111011XX FB0000h-FBFFFFh SA255 64 Kwords 11111100XX FC0000h-FCFFFFh SA256 64 Kwords 11111101XX FD0000h-FDFFFFh SA257 64 Kwords 11111110XX FE0000h-FEFFFFh SA258 16 Kwords 1111111100 FF0000h-FF3FFFh SA259 16 Kwords 1111111101 FF4000h-FF7FFFh SA260 16 Kwords 1111111110 FF8000h-FFBFFFh SA261 16 Kwords 1111111111 FFC000h-FFFFFFh Table 21. Bank Bank 0 Bank 1 48 WS128N Sector & Memory Address Map Sector Sector Size A22-A14 (x16) Address Range SA0 16 Kwords 000000000 000000h-003FFFh SA1 16 Kwords 000000001 004000h-007FFFh SA2 16 Kwords 000000010 008000h-00BFFFh SA3 16 Kwords 000000011 00C000h-00FFFFh SA4 64 Kwords 0000001XX 010000h-01FFFFh SA5 64 Kwords 0000010XX 020000h-02FFFFh SA6 64 Kwords 0000011XX 030000h-03FFFFh SA7 64 Kwords 0000100XX 040000h-04FFFFh SA8 64 Kwords 0000101XX 050000h-05FFFFh SA9 64 Kwords 0000110XX 060000h-06FFFFh SA10 64 Kwords 0000111XX 070000h-07FFFFh SA11 64 Kwords 0001000XX 080000h-08FFFFh SA12 64 Kwords 0001001XX 090000h-09FFFFh SA13 64 Kwords 0001010XX 0A0000h-0AFFFFh SA14 64 Kwords 0001011XX 0B0000h-0BFFFFh SA15 64 Kwords 0001100XX 0C0000h-0CFFFFh SA16 64 Kwords 0001101XX 0D0000h-0DFFFFh SA17 64 Kwords 0001110XX 0E0000h-0EFFFFh SA18 64 Kwords 0001111XX 0F0000h-0FFFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 21. Bank Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 June 14, 2004 S29WSxxxN_00C0 WS128N Sector & Memory Address Map (Continued) Sector Sector Size A22-A14 (x16) Address Range SA19 64 Kwords 0010000XX 100000h-10FFFFh SA20 64 Kwords 0010001XX 110000h-11FFFFh SA21 64 Kwords 0010010XX 120000h-12FFFFh SA22 64 Kwords 0010011XX 130000h-13FFFFh SA23 64 Kwords 0010100XX 140000h-14FFFFh SA24 64 Kwords 0010101XX 150000h-15FFFFh SA25 64 Kwords 0010110XX 160000h-16FFFFh SA26 64 Kwords 0010111XX 170000h-17FFFFh SA27 64 Kwords 0011000XX 180000h-18FFFFh SA28 64 Kwords 0011001XX 190000h-19FFFFh SA29 64 Kwords 0011010XX 1A0000h-1AFFFFh SA30 64 Kwords 0011011XX 1B0000h-1BFFFFh SA31 64 Kwords 0011100XX 1C0000h-1CFFFFh SA32 64 Kwords 0011101XX 1D0000h-1DFFFFh SA33 64 Kwords 0011110XX 1E0000h-1EFFFFh SA34 64 Kwords 0011111XX 1F0000h-1FFFFFh SA35 64 Kwords 0100000XX 200000h-20FFFFh SA36 64 Kwords 0100001XX 210000h-21FFFFh SA37 64 Kwords 0100010XX 220000h-22FFFFh SA38 64 Kwords 0100011XX 230000h-23FFFFh SA39 64 Kwords 0100100XX 240000h-24FFFFh SA40 64 Kwords 0100101XX 250000h-25FFFFh SA41 64 Kwords 0100110XX 260000h-26FFFFh SA42 64 Kwords 0100111XX 270000h-27FFFFh SA43 64 Kwords 0101000XX 280000h-28FFFFh SA44 64 Kwords 0101001XX 290000h-29FFFFh SA45 64 Kwords 0101010XX 2A0000h-2AFFFFh SA46 64 Kwords 0101011XX 2B0000h-2BFFFFh SA47 64 Kwords 0101100XX 2C0000h-2CFFFFh SA48 64 Kwords 0101101XX 2D0000h-2DFFFFh SA49 64 Kwords 0101110XX 2E0000h-2EFFFFh SA50 64 Kwords 0101111XX 2F0000h-2FFFFFh SA51 64 Kwords 0110000XX 300000h-30FFFFh SA52 64 Kwords 0110001XX 310000h-31FFFFh SA53 64 Kwords 0110010XX 320000h-32FFFFh SA54 64 Kwords 0110011XX 330000h-33FFFFh SA55 64 Kwords 0110100XX 340000h-34FFFFh SA56 64 Kwords 0110101XX 350000h-35FFFFh SA57 64 Kwords 0110110XX 360000h-36FFFFh SA58 64 Kwords 0110111XX 370000h-37FFFFh S29WSxxxN MirrorBitTM Flash Family 49 P r e l i m i n a r y Table 21. Bank Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 50 WS128N Sector & Memory Address Map (Continued) Sector Sector Size A22-A14 (x16) Address Range SA59 64 Kwords 0111000XX 380000h-38FFFFh SA60 64 Kwords 0111001XX 390000h-39FFFFh SA61 64 Kwords 0111010XX 3A0000h-3AFFFFh SA62 64 Kwords 0111011XX 3B0000h-3BFFFFh SA63 64 Kwords 0111100XX 3C0000h-3CFFFFh SA64 64 Kwords 0111101XX 3D0000h-3DFFFFh SA65 64 Kwords 0111110XX 3E0000h-3EFFFFh SA66 64 Kwords 0111111XX 3F0000h-3FFFFFh SA67 64 Kwords 1000000XX 400000h-40FFFFh SA68 64 Kwords 1000001XX 410000h-41FFFFh SA69 64 Kwords 1000010XX 420000h-42FFFFh SA70 64 Kwords 1000011XX 430000h-43FFFFh SA71 64 Kwords 1000100XX 440000h-44FFFFh SA72 64 Kwords 1000101XX 450000h-45FFFFh SA73 64 Kwords 1000110XX 460000h-46FFFFh SA74 64 Kwords 1000111XX 470000h-47FFFFh SA75 64 Kwords 1001000XX 480000h-48FFFFh SA76 64 Kwords 1001001XX 490000h-49FFFFh SA77 64 Kwords 1001010XX 4A0000h-4AFFFFh SA78 64 Kwords 1001011XX 4B0000h-4BFFFFh SA79 64 Kwords 1001100XX 4C0000h-4CFFFFh SA80 64 Kwords 1001101XX 4D0000h-4DFFFFh SA81 64 Kwords 1001110XX 4E0000h-4EFFFFh SA82 64 Kwords 1001111XX 4F0000h-4FFFFFh SA83 64 Kwords 1010000XX 500000h-50FFFFh SA84 64 Kwords 1010001XX 510000h-51FFFFh SA85 64 Kwords 1010010XX 520000h-52FFFFh SA86 64 Kwords 1010011XX 530000h-53FFFFh SA87 64 Kwords 1010100XX 540000h-54FFFFh SA88 64 Kwords 1010101XX 550000h-55FFFFh SA89 64 Kwords 1010110XX 560000h-56FFFFh SA90 64 Kwords 1010111XX 570000h-57FFFFh SA91 64 Kwords 1011000XX 580000h-58FFFFh SA92 64 Kwords 1011001XX 590000h-59FFFFh SA93 64 Kwords 1011010XX 5A0000h-5AFFFFh SA94 64 Kwords 1011011XX 5B0000h-5BFFFFh SA95 64 Kwords 1011100XX 5C0000h-5CFFFFh SA96 64 Kwords 1011101XX 5D0000h-5DFFFFh SA97 64 Kwords 1011110XX 5E0000h-5EFFFFh SA98 64 Kwords 1011111XX 5F0000h-5FFFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 21. Bank Bank 12 Bank 13 Bank 14 Bank 15 June 14, 2004 S29WSxxxN_00C0 WS128N Sector & Memory Address Map (Continued) Sector Sector Size A22-A14 (x16) Address Range SA99 64 Kwords 1100000XX 600000h-60FFFFh SA100 64 Kwords 1100001XX 610000h-61FFFFh SA101 64 Kwords 1100010XX 620000h-62FFFFh SA102 64 Kwords 1100011XX 630000h-63FFFFh SA103 64 Kwords 1100100XX 640000h-64FFFFh SA104 64 Kwords 1100101XX 650000h-65FFFFh SA105 64 Kwords 1100110XX 660000h-66FFFFh SA106 64 Kwords 1100111XX 670000h-67FFFFh SA107 64 Kwords 1101000XX 680000h-68FFFFh SA108 64 Kwords 1101001XX 690000h-69FFFFh SA109 64 Kwords 1101010XX 6A0000h-6AFFFFh SA110 64 Kwords 1101011XX 6B0000h-6BFFFFh SA111 64 Kwords 1101100XX 6C0000h-6CFFFFh SA112 64 Kwords 1101101XX 6D0000h-6DFFFFh SA113 64 Kwords 1101110XX 6E0000h-6EFFFFh SA114 64 Kwords 1101111XX 6F0000h-6FFFFFh SA115 64 Kwords 1110000XX 700000h-70FFFFh SA116 64 Kwords 1110001XX 710000h-71FFFFh SA117 64 Kwords 1110010XX 720000h-72FFFFh SA118 64 Kwords 1110011XX 730000h-73FFFFh SA119 64 Kwords 1110100XX 740000h-74FFFFh SA120 64 Kwords 1110101XX 750000h-75FFFFh SA121 64 Kwords 1110110XX 760000h-76FFFFh SA122 64 Kwords 1110111XX 770000h-77FFFFh SA123 64 Kwords 1111000XX 780000h-78FFFFh SA124 64 Kwords 1111001XX 790000h-79FFFFh SA125 64 Kwords 1111010XX 7A0000h-7AFFFFh SA126 64 Kwords 1111011XX 7B0000h-7BFFFFh SA127 64 Kwords 1111100XX 7C0000h-7CFFFFh SA128 64 Kwords 1111101XX 7D0000h-7DFFFFh SA129 64 Kwords 1111110XX 7E0000h-7EFFFFh SA130 16 Kwords 111111100 7F0000h-7F3FFFh SA131 16 Kwords 111111101 7F4000h-7F7FFFh SA132 16 Kwords 111111110 7F8000h-7FBFFFh SA133 16 Kwords 111111111 7FC000h-7FFFFFh S29WSxxxN MirrorBitTM Flash Family 51 P r e l i m i n a r y Table 22. Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 52 WS064N Sector & Memory Address Map Sector Sector Size A21-A14 (x16) Address Range SA0 16 Kwords 00000000 000000h-003FFFh SA1 16 Kwords 00000001 004000h-007FFFh SA2 16 Kwords 00000010 008000h-00BFFFh SA3 16 Kwords 00000011 00C000h-00FFFFh SA4 64 Kwords 000001XX 010000h-01FFFFh SA5 64 Kwords 000010XX 020000h-02FFFFh SA6 64 Kwords 000011XX 030000h-03FFFFh SA7 64 Kwords 000100XX 040000h-04FFFFh SA8 64 Kwords 000101XX 050000h-05FFFFh SA9 64 Kwords 000110XX 060000h-06FFFFh SA10 64 Kwords 000111XX 070000h-07FFFFh SA11 64 Kwords 001000XX 080000h-08FFFFh SA12 64 Kwords 001001XX 090000h-09FFFFh SA13 64 Kwords 001010XX 0A0000h-0AFFFFh SA14 64 Kwords 001011XX 0B0000h-0BFFFFh SA15 64 Kwords 001100XX 0C0000h-0CFFFFh SA16 64 Kwords 001101XX 0D0000h-0DFFFFh SA17 64 Kwords 001110XX 0E0000h-0EFFFFh SA18 64 Kwords 001111XX 0F0000h-0FFFFFh SA19 64 Kwords 010000XX 100000h-10FFFFh SA20 64 Kwords 010001XX 110000h-11FFFFh SA21 64 Kwords 010010XX 120000h-12FFFFh SA22 64 Kwords 010011XX 130000h-13FFFFh SA23 64 Kwords 010100XX 140000h-14FFFFh SA24 64 Kwords 010101XX 150000h-15FFFFh SA25 64 Kwords 010110XX 160000h-16FFFFh SA26 64 Kwords 010111XX 170000h-17FFFFh SA27 64 Kwords 011000XX 180000h-18FFFFh SA28 64 Kwords 011001XX 190000h-19FFFFh SA29 64 Kwords 011010XX 1A0000h-1AFFFFh SA30 64 Kwords 011011XX 1B0000h-1BFFFFh SA31 64 Kwords 011100XX 1C0000h-1CFFFFh SA32 64 Kwords 011101XX 1D0000h-1DFFFFh SA33 64 Kwords 011110XX 1E0000h-1EFFFFh SA34 64 Kwords 011111XX 1F0000h-1FFFFFh SA35 64 Kwords 100000XX 200000h-20FFFFh SA36 64 Kwords 100001XX 210000h-21FFFFh SA37 64 Kwords 100010XX 220000h-22FFFFh SA38 64 Kwords 100011XX 230000h-23FFFFh S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 22. Bank Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 Bank 14 Bank 15 June 14, 2004 S29WSxxxN_00C0 WS064N Sector & Memory Address Map (Continued) Sector Sector Size A21-A14 (x16) Address Range SA39 64 Kwords 100100XX 240000h-24FFFFh SA40 64 Kwords 100101XX 250000h-25FFFFh SA41 64 Kwords 100110XX 260000h-26FFFFh SA42 64 Kwords 100111XX 270000h-27FFFFh SA43 64 Kwords 101000XX 280000h-28FFFFh SA44 64 Kwords 101001XX 290000h-29FFFFh SA45 64 Kwords 101010XX 2A0000h-2AFFFFh SA46 64 Kwords 101011XX 2B0000h-2BFFFFh SA47 64 Kwords 101100XX 2C0000h-2CFFFFh SA48 64 Kwords 101101XX 2D0000h-2DFFFFh SA49 64 Kwords 101110XX 2E0000h-2EFFFFh SA50 64 Kwords 101111XX 2F0000h-2FFFFFh SA51 64 Kwords 110000XX 300000h-30FFFFh SA52 64 Kwords 110001XX 310000h-31FFFFh SA53 64 Kwords 110010XX 320000h-32FFFFh SA54 64 Kwords 110011XX 330000h-33FFFFh SA55 64 Kwords 110100XX 340000h-34FFFFh SA56 64 Kwords 110101XX 350000h-35FFFFh SA57 64 Kwords 110110XX 360000h-36FFFFh SA58 64 Kwords 110111XX 370000h-37FFFFh SA59 64 Kwords 111000XX 380000h-38FFFFh SA60 64 Kwords 111001XX 390000h-39FFFFh SA61 64 Kwords 111010XX 3A0000h-3AFFFFh SA62 64 Kwords 111011XX 3B0000h-3BFFFFh SA63 64 Kwords 111100XX 3C0000h-3CFFFFh SA64 64 Kwords 111101XX 3D0000h-3DFFFFh SA65 64 Kwords 111110XX 3E0000h-3EFFFFh SA66 16 Kwords 11111100 3F0000h-3F3FFFh SA67 16 Kwords 11111101 3F4000h-3F7FFFh SA68 16 Kwords 11111110 3F8000h-3FBFFFh SA69 16 Kwords 11111111 3FC000h-3FFFFFh S29WSxxxN MirrorBitTM Flash Family 53 P r e l i m i n a r y Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definition Summary section defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. See "AC Characteristics--Synchronous" and "AC Characteristics--Asynchronous" for timing diagrams. Reading Array Data The device is automatically set to reading asynchronous array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. See Erase Suspend/Erase Resume Commands for more information. After the device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank. See Program Suspend/Program Resume Commands for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See Reset Command for more information. If DQ1 goes high during Write Buffer Programming, the system must issue the Write Buffer Abort Reset command. See also Requirements for Asynchronous (Non-Burst) Read Operation and Requirements for Synchronous (Burst) Read Operation for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 14, and Figure 18 show the timings. Set Configuration Register Command Sequence The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active (see Figure 26 for details). The configuration register must be set before the device will enter burst mode. On power up or reset, the device is set in asynchronous read mode and the configuration register is reset. The configuration register is not reset after deasserting CE#. The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address 000h. Once the data has been programmed into the configuration register, a software reset command is required to set the device into the correct state. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter 54 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock). Read Configuration Register Command Sequence The configuration register can be read with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C6h and address bits should be 555h. During the fourth cycle, the configuration code should be read out of the data bus with the address bus set to address 000h. Once the data has been read from the configuration register, a software reset command is required to set the device into the array read mode. Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1) Synchronous Read Mode Only Figure 1. Synchronous/Asynchronous State Diagram Read Mode Setting This setting allows the system to enable or disable burst mode during system operations. Configuration Bit CR15 determines this setting: "1' for asynchronous mode, "0" for synchronous mode. Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Configuration Bit CR13-CR11 determine the setting (see Table 23). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 55 P r e l i m i n a r y Table 23. Programmable Wait State Settings CR13 CR12 CR11 Total Initial Access Cycles 0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 7 (default) 1 1 0 Reserved 1 1 1 Reserved Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Programmable Wait State If the device is equipped with the handshaking option, the host system should set CR13-CR11 to 010 for a clock frequency of 54 MHz, to 011 for a clock frequency of 66 MHz, or to 100 for a clock frequency of 80 MHz for the system/device to execute at maximum speed. Table 24 describes the typical number of clock cycles (wait states) for various conditions. Boundary Crossing Latency If the device is operating above 66 MHz, an additional wait state must be inserted to account for boundary crossing latency. This is done by setting CR14 to a `1' (default). If the device is operating at or below 66 MHz, the additional wait state for boundary crossing is not needed. Therefore the CR14 can be changed to a `0' to remove boundary crossing latency. Table 24. Wait States for Handshaking Typical No. of Clock Cycles after AVD# Low Conditions at Address Initial address (VIO = 1.8 V) 54 MHz 66 MHz 80 MHz 4 5 6 Handshaking For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. See Autoselect Command Sequence for more information. Burst Length Configuration The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or without wrap around modes. A continuous sequence (de- 56 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y fault) begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 25 shows the CR2-CR0 and settings for the four read modes. Table 25. Burst Length Configuration Address Bits Burst Modes CR2 CR1 CR0 Continuous 0 0 0 8-word linear 0 1 0 16-word linear 0 1 1 32-word linear 1 0 0 Note: Upon power-up or hardware reset the default setting is continuous. Burst Wrap Around By default, the device will perform burst wrap around with CR3 set to a `1'. Changing the CR3 to a `0' disables burst wrap around. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. CR8 determines this setting; "1" for RDY active (default) with data, "0" for RDY active one clock cycle before valid data. RDY Polarity By default, the RDY pin will always indicate that the device is ready to handle a new transaction with CR10 set to a `1'. In this case, the RDY pin is active high. Changing the CR10 to a `0' sets the RDY pin to be active low. In this case, the RDY pin will always indicate that the device is ready to handle a new transaction when low. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 57 P r e l i m i n a r y Configuration Register Table 26 shows the address bits that determine the configuration register settings for various device functions. Table 26. CR Bit Function CR15 Set Device Read Mode CR14 Boundary Crossing CR13 Configuration Register Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) 000 = Data is valid on the 2nd active CLK edge after addresses are latched 001 = Data is valid on the 3rd active CLK edge after addresses are latched 010 = Data is valid on the 4th active CLK edge after addresses are latched CR12 Programmable Wait State 011 = Data is valid on the 5th active CLK edge after addresses are latched 100 = Data is valid on the 6th active CLK edge after addresses are latched 101 = Data is valid on the 7th active CLK edge after addresses are latched (default) CR11 110 = Reserved 111 = Reserved 0 = RDY signal is active low CR10 RDY Polarity CR9 Reserved CR8 RDY CR7 Reserved 1 = default CR6 Reserved 1 = default CR5 Reserved 0 = default CR4 Reserved 0 = default CR3 Burst Wrap Around CR2 1 = RDY signal is active high (default) 1 = default 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst CR1 Burst Length 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) CR0 Note: Device will be in the default state upon power-up or hardware reset. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writ- 58 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y ing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend and program-suspend-read mode if that bank was in Program Suspend). Note: If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command will not work. See Table 17 for details on this command sequence. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The Command Definition Summary shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. Autoselect does not support simultaneous operations nor burst mode. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. Read commands to other banks will return data from the array. Writes to other banks is not allowed. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address. The device ID is read in three cycles. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 59 P r e l i m i n a r y Table 27. Description Autoselect Addresses Address Read Data Manufacturer ID (BA) + 00h 0001h Device ID, Word 1 (BA) + 01h 227Eh Device ID, Word 2 (BA) + 0Eh 2230 (WS256N) 2232 (WS064N) 2231 (WS128N) Device ID, Word 3 (BA) + 0Fh 2200 DQ15 - DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake Indicator Bits (BA) + 03h DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot Sectors. 01, 10, 11 = Reserved DQ2 = Reserved DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option), 0 = Locked (default) DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed, 0 = Erase disabled Sector Block Lock/ Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend). Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. See Command Definition Summary for address and data requirements for both command sequences. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin (see Figure 2). When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program 60 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. Programming to the same word address multiple times without intervening erases is limited. For such application requirements, please contact your local Spansion representative. A "0" cannot be programmed back to a "1." Attempting to do so will cause the device to set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Command Definition Summary for program command sequence. Figure 2. Word Program Operation Write Buffer Programming Command Sequence Write Buffer Programming Command Sequence allows for faster programming compared to the standard Program Command Sequence. Write Buffer Programming allows the system to write 32 words in one programming operation. See Write Buffer Programming Operation section for the program command sequence. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 61 P r e l i m i n a r y Table 28. Sequence Unlock Command 1 Unlock Command 2 Write Buffer Command Sequence Address Data 555 00AA Not required in the Unlock Bypass mode Comment Same as above 2AA 0055 Write Buffer Load Starting Address 0025h Specify the Number of Program Locations Starting Address Word Count Load 1st data word Starting Address Program Data All addresses must be within write-buffer-page boundaries, but do not have to be loaded in any order Write Buffer Location Program Data Same as above Load next data word ... Load last data word Write Buffer Program Confirm Number of locations to program minus 1 (must be 32 - 1 = 31) ... ... Same as above Write Buffer Location Program Data Same as above Sector Address 0029h This command must follow the last write buffer location loaded, or the operation will ABORT Device goes busy Status monitoring through DQ pins (Perform Data Bar Polling on the Last Loaded Address) 62 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Write "Write to Buffer" command and Sector Address Part of "Write to Buffer" Command Sequence Write number of addresses to program minus 1 and Sector Address Write first address/data Yes WC = 0 ? No Abort Write to Buffer Operation? Write to a different sector address Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. No Write next address/data pair WC = WC - 1 Write program buffer to flash sector address Read DQ15 - DQ0 at Last Loaded Address DQ7 = Data? No Yes No No DQ1 = 1? DQ5 = 1? Yes Yes Read DQ15 - DQ0 with address = Last Loaded Address DQ7 = Data? Yes No FAIL or ABORT Figure 3. June 14, 2004 S29WSxxxN_00C0 PASS Write Buffer Programming Operation S29WSxxxN MirrorBitTM Flash Family 63 P r e l i m i n a r y Unlock Bypass Command Sequence The unlock bypass feature allows faster programming than the standard word program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. See Command Definition Summary for the unlock bypass command sequences requirements. During the unlock bypass mode, only the Read, Unlock Bypass Program, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. See Command Definition Summary for chip erase command sequence address and data requirements. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. See Erase/Program Timing Operations for parameters and timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. See Command Definition Summary for sector erase command sequence address and data requirements. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. 64 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase Timer.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. See Erase/Program Timing Operations for parameters and timing diagrams. START Write Erase Command Sequence Data Poll from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. 2. See Command Definition Summary for erase command sequence. See the section on DQ3 for information on the sector erase timer. Figure 4. June 14, 2004 S29WSxxxN_00C0 Erase Operation S29WSxxxN MirrorBitTM Flash Family 65 P r e l i m i n a r y Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written during the sector erase operation, the device requires tSEL (erase suspend latency) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 32 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. See Write Buffer Programming Operation and the Autoselect Command Sequence for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation or a "Write to Buffer" programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. Addresses are "don't-cares" when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in Program Suspend mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, 66 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y and is ready for another valid operation. See "Autoselect Command Sequence" for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system must write the Program Resume command (address bits are "don't care") to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. Lock Register Command Set Definitions The Lock Register Command Set permits the user to program the SecSi Sector Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection Mode Lock Bit one time. The Lock Command Set also allows for the reading of the SecSi Sector Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection Mode Lock Bit. The Lock Register Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. Lock Register Program Command Lock Register Read Command Lock Register Exit Command Note that issuing the Lock Register Command Set Entry command disables reads and writes for Bank 0. Reads from other banks excluding Bank 0 are allowed. The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the device to read mode, and re-enables reads and writes for Bank 0. Note that if the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are programmed at the same time, neither will be programmed. Password Protection Command Set Definitions The Password Protection Command Set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. The Password Protection Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. Password Program Command Password Read Command Password Unlock Command Note that issuing the Password Protection Command Set Entry command disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64 bits June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 67 P r e l i m i n a r y long. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program Algorithm with the cell remaining as a "0". The password is all "1"s when shipped from the factory. All 64bit password combinations are valid as a password. The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all "1"s onto the DQ data bus. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 1 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long. A1 and A0 are used for matching. Writing the Password Unlock command does not need to be address order specific. An example sequence is starting with the lower address A1-A0= 00, followed by A1-A0= 01, A1-A0= 10, and A1-A0= 11. Approximately 1 Sec is required for unlocking the device after the valid 64-bit password is given to the device. It is the responsibility of the microprocessor to keep track of the 64-bit password as it is entered with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to re-lock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued. The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode, otherwise the device will hang. Note that issuing the Password Protection Command Set Exit command re-enables reads and writes for Bank 0. Non-Volatile Sector Protection Command Set Definitions The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits (PPBs), erase all of the Persistent Protection Bits (PPBs), and read the logic state of the Persistent Protection Bits (PPBs). The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. PPB Program Command All PPB Erase Command PPB Status Read Command 68 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Note that issuing the Non-Volatile Sector Protection Command Set Entry command disables reads and writes for the bank selected. Reads within that bank will return the PPB status for that sector. Reads from other banks are allowed; writes are not allowed. All Reads must be performed using the Asynchronous mode. The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program command will not execute and the command will time-out without programming the PPB. The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. The device will preprogram all PPBs prior to erasing when issuing the All PPB Erase command. Also note that the total number of PPB program/erase cycles has the same endurance as the flash memory array. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device. The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and writes for Bank 0. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 69 P r e l i m i n a r y Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA Read Byte. Addr = SA0 Read Byte. Addr = SA0 No DQ6 = Toggle? Yes DQ5 = 1? Yes Read Byte Twice. Addr = SA0 DQ6 = Toggle? No Read Byte. Addr = SA Yes No DQ0 = '1' (Erase) '0' (Pgm.)? FAIL Yes Issue Reset Command PASS Exit PPB Command Set Figure 5. 70 PPB Program/Erase Algorithm S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Global Volatile Sector Protection Freeze Command Set The Global Volatile Sector Protection Freeze Command Set permits the user to set the PPB Lock Bit and read the logic state of the PPB Lock Bit. The Volatile Sector Protection Freeze Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution: PPB Lock Bit Set Command PPB Lock Bit Status Read Command Reads from all remaining 15 banks are allowed. The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear (for Persistent Sector Protection Mode) or the Password Unlock command is executed (for Password Sector Protection Mode). If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read Command to the device. The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Volatile Sector Protection Command Set The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. DYB Set Command DYB Clear Command DYB Status Read Command Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes for the bank selected with the command. Reads within that bank will return the DYB status for that sector. Writes within that bank will set the DYB for that sector. Reads for other banks excluding that bank are allowed; writes are not allowed. All Reads must be performed using the Asynchronous mode. The DYB Set/Clear command is used to set or clear a DYB for a given sector. The high order address bits (A23-A14 for the WS256N, A22-A14 for the WS128N, A21-A14 for the WS064N) are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. The programming state of the DYB for a given sector can be verified by writing a DYB Status Read Command to the device. The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 71 P r e l i m i n a r y mode. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes for Bank 0. SecSi Sector Entry Command The SecSi Sector Entry Command allows the following commands to be executed Read from SecSi Sector Program to SecSi Sector Sector 0 is remapped from memory array to SecSi Sector array. Reads can be performed using the Asynchronous or Synchronous mode. Burst mode reads within SecSi Sector will wrap from address FFh back to address 00h. Reads outside of sector 0 will return memory array data. Continuous burst read past the maximum address is undefined. Simultaneous operations are allowed except for Bank 0. Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command has to be issued to exit SecSi Sector Mode. 72 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Command Definition Summary Autoselect (8) Command Sequence (Notes) Asynchronous Read (6) Reset (7) Manufacturer ID Device ID (9) Cycles Table 29. 1 1 4 6 First Addr Data RA RD XXX F0 555 AA 555 AA Memory Array Commands Second Addr Data Bus Cycles (Notes 1-5) Third Fourth Addr Data Addr Data 2AA 2AA 55 55 [BA]555 [BA]555 90 90 [BA]X00 [BA]X01 0001 227E Data BA+X0F 2200 PD WC PA PD WBL PD 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 X00 X00 CR CR 88 A0 PA PD 90 XXX 00 555 AA 2AA 55 [BA]555 90 [BA]X03 Data Program Write to Buffer (11) Program Buffer to Flash Write to Buffer Abort Reset (12) Chip Erase Sector Erase Erase/Program Suspend (13) Erase/Program Resume (14) Set Configuration Register (18) Read Configuration Register CFI Query (15) Entry Program (16) CFI (16) 4 6 1 3 6 6 1 1 4 4 1 3 2 1 555 555 SA 555 555 555 BA BA 555 555 [BA]555 555 XXX XXX AA AA 29 AA AA AA B0 30 AA AA 98 AA A0 98 2AA 2AA 55 55 555 PA A0 25 PA PA 2AA 2AA 2AA 55 55 55 555 555 555 F0 80 80 2AA 2AA 55 55 555 555 D0 C6 2AA PA 55 PD 555 20 Reset 2 XXX 90 XXX 00 Entry Program (17) Read (17) 3 4 1 555 555 00 AA AA Data 2AA 2AA 55 55 555 555 Exit (17) 4 555 AA 2AA 55 555 SecSi Sector Unlock Bypass Mode 4 Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. 4. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 6. No unlock or command cycles required when bank is reading array data. 7. Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The system must provide the bank address. See Autoselect Command Sequence section for more information. 9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231 (WS128N). 10. See Table 27 for indicator bit values. June 14, 2004 S29WSxxxN_00C0 Sixth Addr Data BA+X0E Indicator Bits (10) Legend: X = Don't care. RA = Read Address. RD = Read Data. PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. Fifth Addr Data SA = Sector Address. WS256N = A23-A14; WS128N = A22-A14; WS064N = A21-A14. BA = Bank Address. WS256N = A23-A20; WS128N = A22-A20; WS064N = A21-A18. CR = Configuration Register data bits D15-D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. 11. Total number of cycles in the command sequence is determined by the number of words written to the write buffer. The number of cycles in the command sequence is 37 for full page programming (32 words). Less than 32 word programming is not recommended. 12. Command sequence resets device for next command after writeto-buffer operation. 13. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Address will equal 55h on all future devices, but 555h for WS256N/128N/064N. 16. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data. 17. Requires Entry command sequence prior to execution. SecSi Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. Requires reset command to configure the Configuration Register. S29WSxxxN MirrorBitTM Flash Family 73 Command Sequence (Notes) Command Set Entry (5) Lock Program (6) Register Read (6) Bits Command Set Exit (7) Command Set Entry (5) Program [0-3] (8) Password Read (9) Protection Unlock Command Set Exit (7) Command Set Entry (5) PPB Program (10) Non-Volatile Sector All PPB Erase (10, 11) Protection (PPB) PPB Status Read Command Set Exit (7) Global Command Set Entry (5) Volatile Sector PPB Lock Bit Set Protection PPB Lock Bit Status Read Freeze Command Set Exit (7) (PPB Lock) Volatile Sector Protection (DYB) Command Set Entry (5) DYB Set DYB Clear DYB Status Read Command Set Exit (7) Cycles P r e l i m i n a r y 3 2 1 2 3 2 4 7 2 3 2 2 1 2 3 2 1 Table 30. Sector Protection Commands First Addr Data 555 AA XX A0 77 data XX 90 555 AA XX A0 0...00 PWD0 00 25 XX 90 555 AA XX A0 XX 80 SA RD(0) XX 90 555 AA XX A0 BA RD(0) Second Addr Data 2AA 55 77 data XX 00 2AA 55 555 60 00 PWD[0-3] 0...01 PWD1 0...02 PWD2 00 03 00 PWD0 XX 00 2AA 55 [BA]555 C0 SA 00 00 30 XX 2AA XX 00 55 00 2 XX 90 XX 00 3 2 2 1 2 555 XX XX SA XX AA A0 A0 RD(0) 90 2AA SA SA 55 00 01 XX 00 Legend: X = Don't care. RA = Address of the memory location to be read. PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to `0' for protection while PD(2), bit[2] must be left as `1'. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to `0' for protection while PD(1), bit[1] must be left as `1'. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Sector Address. WS256N = A23-A14; WS128N = A22-A14; WS064N = A21-A14. Notes: 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 74 Bus Cycles (Notes 1-4) Third Fourth Fifth Addr Data Addr Data Addr Data 555 40 [BA]555 50 [BA]555 E0 0...03 PWD3 01 PWD1 02 PWD2 Sixth Addr Data 03 PWD3 Seventh Addr Data 00 29 BA = Bank Address. WS256N = A23-A20; WS128N = A22-A20; WS064N = A21-A18. PWD3-PWD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1, DQ2 = 1. 6. 7. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation will abort and return the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses will equal 00h, but are currently 77h for WS256N, WS128N, and WS064N. See Table 14 for explanation of lock bits. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is required for reading password. 10. See Figure 5 for details. 11. "All PPB Erase" command will pre-program all PPBs before erasure to prevent over-erasure. S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. Table 32 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles. Table 32 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm. Figure 24 in "AC Characteristics--Asynchronous" shows the Data# Polling timing diagram. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 75 P r e l i m i n a r y START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL Figure 6. PASS Data# Polling Algorithm DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP (all sectors protected toggle time), then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, 76 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 7, DQ6: Toggle Bit I, Figure 25 (toggle bit timing diagram), and Table 31. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 77 P r e l i m i n a r y START Read Byte (DQ0-DQ7) Address = VA Read Byte (DQ0-DQ7) Address = VA DQ6 = Toggle? No Yes No DQ5 = 1? Yes Read Byte Twice (DQ 0-DQ7) Adrdess = VA DQ6 = Toggle? No Yes FAIL PASS Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the 78 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 31 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 7; DQ6: Toggle Bit I; and Figure 25. Table 31. DQ6 and DQ2 Indications If device is and the system reads then DQ6 and DQ2 programming, at any address, toggles, does not toggle. at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. The system can read from any sector not selected for erasure. at any address, toggles, is not applicable. actively erasing, erase suspended, programming in erase suspend Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7- DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 7 for more details. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 79 P r e l i m i n a r y The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 32 shows the status of DQ3 relative to the other status bits. DQ1: Write to Buffer Abort DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a `1'. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details. 80 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 32. Write Operation Status Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) DQ1 (Note 4) Standard Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A Program Suspend Mode (Note 3) Reading within Program Suspended Sector INVALID INVALID INVALID INVALID INVALID INVALID (Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed) Data Data Data Data Data Data Erase Suspended Sector 1 No toggle 0 N/A Toggle N/A Non-Erase Suspended Sector Data Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle 0 N/A N/A N/A BUSY State DQ7# Toggle 0 N/A N/A 0 Exceeded Timing Limits DQ7# Toggle 1 N/A N/A 0 ABORT State DQ7# Toggle 0 N/A N/A 1 Erase Suspend Mode Write to Buffer (Note 5) Reading within Non-Program Suspended Sector Erase-SuspendRead Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. Data are invalid for addresses in a Program Suspended sector. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITEBUFFER ADDRESS location. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 81 P r e l i m i n a r y Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VIO + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +9.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns +0.8 V 20 ns VCC +2.0 V VCC +0.5 V -0.5 V -2.0 V 1.0 V 20 ns Figure 8. 20 ns Maximum Negative Overshoot Waveform Figure 9. 20 ns Maximum Positive Overshoot Waveform Operating Ranges Wireless (W) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltages VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Contact local sales office for VIO = 1.35 to +1.70 V.) +1.70 V to +1.95 V Notes: Operating ranges define those limits between which the functionality of the device is guaranteed. 82 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y DC Characteristics CMOS Compatible Parameter Description (Notes) Test Conditions (Notes 1, 2, 9) Min Typ Max Unit A ILI Input Load Current VIN = VSS to VCC, VCC = VCCmax 1 ILO Output Leakage Current (3) VOUT = VSS to VCC, VCC = VCCmax 1 A CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous IIO1 ICC1 VIO Non-active Output 54 MHz 27 54 mA 66 MHz 28 60 mA 80 MHz 30 66 mA 54 MHz 28 48 mA 66 MHz 30 54 mA 80 MHz 32 60 mA 54 MHz 29 42 mA 66 MHz 32 48 mA 80 MHz 34 54 mA 54 MHz 32 36 mA 66 MHz 35 42 mA mA 80 MHz 38 48 20 30 A 10 MHz 27 36 mA 5 MHz 13 18 mA 1 MHz 3 4 mA OE# = VIH VCC Active Asynchronous Read Current (4) CE# = VIL, OE# = VIH, WE# = VIH VCC Active Write Current (5) CE# = VIL, OE# = VIH, ACC = VIH VACC 1 5 A VCC 19 52.5 mA ICC3 VCC Standby Current (6, 7) CE# = RESET# = VCC 0.2 V VACC 1 5 A VCC 20 40 A ICC4 VCC Reset Current (7) RESET# = VIL, CLK = VIL 70 150 A ICC5 VCC Active Current (Read While Write) (7) CE# = VIL, OE# = VIH, ACC = VIH 50 60 mA ICC6 VCC Sleep Current (7) 2 40 A 6 20 mA 20 mA ICC2 CE# = VIL, OE# = VIH VACC Accelerated Program Current (8) CE# = VIL, OE# = VIH, VACC = 9.5 V VIL Input Low Voltage VIO = 1.8 V -0.5 0.4 V VIH Input High Voltage VIO = 1.8 V VIO - 0.4 VIO + 0.4 V 0.1 V IACC 14 VCC VOL Output Low Voltage IOL = 100 A, VCC = VCC min = VIO VOH Output High Voltage IOH = -100 A, VCC = VCC min = VIO VHH Voltage for Accelerated Program 8.5 9.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V VIO - 0.1 V Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Maximum ICC specifications are tested with VCC = VCCmax. VCC= VIO. CE# must be set high when measuring the RDY pin. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH. ICC active while Embedded Erase or Embedded Program is in progress. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. VIH = VCC 0.2 V and VIL > -0.1 V. Total current during accelerated programming is the sum of VACC and VCC currents. VACC = VHH on ACC input. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 83 P r e l i m i n a r y Test Conditions Device Under Test CL Figure 10. Table 33. Test Setup Test Specifications Test Condition All Speed Options Unit Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 3.0 @ 54, 66 MHz ns 2.5 @ 80 MHz Input Pulse Levels 0.0-VIO V Input timing measurement reference levels VIO/2 V Output timing measurement reference levels VIO/2 V Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) Switching Waveforms All Inputs and Outputs VIO Input VIO/2 Measurement Level VIO/2 Output 0.0 V Figure 11. 84 Input Waveforms and Measurement Levels S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y VCC Power-up Parameter Description Test Setup Speed Unit tVCS VCC Setup Time Min 1 ms Note: 1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100s 2. VCC ramp rate <1V / 100s, a Hardware Reset will be required. tVCS VCC VIO RESET# Figure 12. June 14, 2004 S29WSxxxN_00C0 VCC Power-up Diagram S29WSxxxN MirrorBitTM Flash Family 85 P r e l i m i n a r y AC Characteristics--Synchronous CLK Characterization Parameter Description 54 MHz 66 MHz 80 MHz Unit fCLK CLK Frequency Max 54 66 80 MHz tCLK CLK Period Min 18.5 15.1 12.5 ns tCH CLK High Time tCL CLK Low Time Min 7.4 6.1 5.0 ns tCR CLK Rise Time tCF CLK Fall Time Max 3 3 2.5 ns tCLK tCH CLK tCF tCR Figure 13. 86 tCL CLK Characterization S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Synchronous/Burst Read Parameter JEDEC Standard Description 54 MHz 66 MHz 80 MHz 69 Unit tIACC Latency Max ns tBACC Burst Access Time Valid Clock to Output Delay Max 13.5 tACS Address Setup Time to CLK (Note 1) Min 5 4 ns tACH Address Hold Time from CLK (Note 1) Min 7 6 ns tBDH Data Hold Time from Next Clock Cycle Min 4 3 ns tCR Chip Enable to RDY Valid Max 13.5 tOE Output Enable to Output Valid Max 13.5 tCEZ Chip Enable to High Z (Note 2) Max 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 ns tCES CE# Setup Time to CLK Min 4 ns tRDYS RDY Setup Time to CLK Min 5 4 3.5 ns tRACC Ready Access Time from CLK Max 13.5 11.2 9 ns tAAS Address Setup Time to AVD# (Note 1) Min 5 4 ns tAAH Address Hold Time to AVD# (Note 1) Min 7 6 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 4 ns tAVD AVD# Pulse Min 8 ns 11.2 9 11.2 9 11.2 ns ns ns Notes: 1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. 2. Not 100% tested. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 87 P r e l i m i n a r y Timing Diagrams 5 cycles for initial access shown. tCES tCEZ 18.5 ns typ. (54 MHz) CE# 1 2 3 4 5 6 7 CLK tAVC AVD# tAVD tACS Addresses Aa tBACC tACH Hi-Z Data (n) tIACC Da Da + 1 Da + 2 Da + 3 Da + n tOEZ tBDH OE# tRACC tOE RDY (n) Hi-Z Hi-Z tCR tRDYS Hi-Z Data (n + 1) Da RDY (n + 1) Da + 1 Da + 2 Da + 2 Da + n Hi-Z Hi-Z Hi-Z Data (n + 2) Da RDY (n + 2) Da + 1 Da + 1 Da + 1 Da + n Hi-Z Hi-Z Hi-Z Data (n + 3) Da RDY (n + 3) Da Da Da Da + n Hi-Z Hi-Z Notes: 1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode. Figure 14. 88 CLK Synchronous Burst Mode Read S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y tCES 7 cycles for initial access shown. CE# 1 2 3 4 5 6 7 CLK tAVC AVD# tAVD tACS Addresses Ac tBACC tACH Data tIACC DC DD DE DF D8 DB tBDH OE# tCR RDY tRACC tOE tRACC Hi-Z tRDYS Note: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode with wrap around. 4. D8-DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (8-F). Figure 15. tCES 7 8-word Linear Burst with Wrap Around cycles for initial access shown. CE# 1 2 3 4 5 6 7 CLK tAVC AVD# tAVD tACS Addresses Ac tBACC tACH Data tIACC DC DD DE DF D10 D13 tBDH OE# tCR RDY tOE tRACC tRACC Hi-Z tRDYS Note: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in asynchronous mode with out wrap around. 4. DC-D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (c-13). Figure 16. June 14, 2004 S29WSxxxN_00C0 8-word Linear Burst without Wrap Around S29WSxxxN MirrorBitTM Flash Family 89 P r e l i m i n a r y tCES 6 tCEZ wait cycles for initial access shown. CE# 1 2 3 4 5 6 CLK tAVC AVD# tAVD tACS Addresses Aa tBACC tACH Hi-Z Data tIACC Da Da+1 Da+2 Da+3 tBDH tRACC OE# tCR RDY Da + n tOEZ tOE Hi-Z Hi-Z tRDYS Note: 1. Figure assumes 6 wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one cycle before valid data. Figure 17. 90 Linear Burst with RDY Set One Cycle Before Data S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y AC Characteristics--Asynchronous Asynchronous Mode Read Parameter JEDEC Standard Description 54 MHz 66 MHz 80 MHz Unit tCE Access Time from CE# Low Max 70 ns tACC Asynchronous Access Time Max 70 ns tAVDP AVD# Low Time Min 8 ns tAAVDS Address Setup Time to Rising Edge of AVD# Min 4 ns tAAVDH Address Hold Time from Rising Edge of AVD# Min 7 6 ns tOE Output Enable to Output Valid Max 13.5 11.2 ns tOEH Output Enable Hold Time tOEZ tCAS Read Min 0 ns Toggle and Data# Polling Min 10 ns Output Enable to High Z (see Note) Max 10 ns CE# Setup Time to AVD# Min 0 ns Note: Not 100% tested. Timing Diagrams CE# tOE OE# tOEH WE# tCE tOEZ Data Valid RD tACC RA Addresses tAAVDH tCAS AVD# tAVDP tAAVDS Note: RA = Read Address, RD = Read Data. Figure 18. June 14, 2004 S29WSxxxN_00C0 Asynchronous Mode Read with Latched Addresses S29WSxxxN MirrorBitTM Flash Family 91 P r e l i m i n a r y CE# tOE OE# tOEH WE# tCE Data tOEZ Valid RD tACC RA Addresses AVD# Note: RA = Read Address, RD = Read Data. Figure 19. Asynchronous Mode Read Hardware Reset (RESET#) Parameter JEDEC Std. Description All Speed Options Unit tRP RESET# Pulse Width Min 30 s tRH Reset High Time Before Read (See Note) Min 200 ns Note: Not 100% tested. CE#, OE# tRH RESET# tRP Figure 20. 92 Reset Timings S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Erase/Program Timing Operations Parameter JEDEC Standard tAVAV tWC tAVWL tWLAX tAS tAH Description 54 MHz Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) Min Synchronous Asynchronous Synchronous Asynchronous Min 66 MHz 80 MHz ns 5 ns 0 ns 9 Min Unit 70 ns 20 tAVDP AVD# Low Time Min tDVWH tDS Data Setup Time Min 8 tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL 45 ns 20 ns Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 ns tWHWL tWPH Write Pulse Width High Min 20 ns tSR/W Latency Between Read and Write Operations Min 0 ns tELWL tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 s tVCS VCC Setup Time Min 50 s tCS CE# Setup Time to WE# Min 5 ns tAVSW AVD# Setup Time to WE# Min 5 ns tAVHW AVD# Hold Time to WE# Min 5 ns tAVSC AVD# Setup Time to CLK Min 5 ns tAVHC AVD# Hold Time to CLK Min 5 ns tCSW Clock Setup Time to WE# Min 5 ns tWEP Noise Pulse Margin on WE# Max 3 ns tSEA Sector Erase Accept Time-out Max 50 s tESL Erase Suspend Latency Max 20 s tPSL Program Suspend Latency Max 20 s tASP Toggle Time During Sector Protection Typ 100 s tPSP Toggle Time During Programming Within a Protected Sector Typ 1 s Notes: 1. 2. 3. 4. 5. Not 100% tested. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. See the "Erase and Programming Performance" section for more information. Does not include the preprogramming time. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 93 P r e l i m i n a r y Program Command Sequence (last two cycles) Read Status Data VIH CLK VIL tAVSW tAVHW tAVDP AVD tAS tAH Addresses 555h VA PA Data A0h VA In Progress PD Complete tDS tCAS tDH CE# tCH OE# tWP WE# tWHWH1 tCS tWPH tWC tVCS VCC Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A23-A14 for the WS256N (A22-A14 for the WS128N, A21-A14 for the WS064N) are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 21. 94 Asynchronous Program Operation Timings: WE# Latched Addresses S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Program Command Sequence (last two cycles) Read Status Data tAVCH CLK tAS tAH tAVSC AVD tAVDP Addresses VA PA 555h Data In Progress PD A0h VA Complete tDS tDH tCAS CE# OE# tCH tCSW tWP WE# tWHWH1 tWPH tWC tVCS VCC Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A23-A14 for the WS256N (A22-A14 for the WS128N, A21-A14 for the WS064N) are don't care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 22. June 14, 2004 S29WSxxxN_00C0 Synchronous Program Operation Timings: CLK Latched Addresses S29WSxxxN MirrorBitTM Flash Family 95 P r e l i m i n a r y CE# AVD# WE# Addresses PA Data Don't Care OE# tVIDS ACC A0h Don't Care PD Don't Care VID tVID VIL or VIH Note: Use setup and hold times from conventional program operation. Figure 23. Accelerated Unlock Bypass Programming Timing AVD# tCEZ tCE CE# tCH tOEZ tOE OE# tOEH WE# tACC Addresses VA High Z VA High Z Data Status Data Status Data Notes: 1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. Figure 24. Data# Polling Timings (During Embedded Algorithm) 96 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y AVD# tCEZ tCE CE# tCH tOEZ tOE OE# tOEH WE# tACC Addresses VA High Z VA High Z Data Status Data Status Data Notes: 1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. Figure 25. Toggle Bit Timings (During Embedded Algorithm) CE# CLK AVD# Addresses VA VA OE# tIACC tIACC Data Status Data Status Data RDY Notes: 1. 2. 3. The timings are similar to synchronous read timings. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle before data. Figure 26. June 14, 2004 S29WSxxxN_00C0 Synchronous Data Polling Timings/ Toggle Bit Timings S29WSxxxN MirrorBitTM Flash Family 97 P r e l i m i n a r y Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Complete Erase Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 27. DQ2 vs. DQ6 Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 C125 C126 7C 7D 7E C127 C127 C128 C129 7F 7F 80 81 C130 C131 CLK Address (hex) AVD# RDY(1) tRACC latency tRACC RDY(2) OE#, CE# 83 (stays high) tRACC Data 82 tRACC latency D124 D125 D126 D127 D128 D129 D130 (stays low) Notes: 1. RDY active with data (D8 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (D8 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. 4. Figure shows the device not crossing a bank in the process of performing an erase or program. 5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0 Figure 28. 98 Latency with Boundary Crossing when Frequency > 66 MHz S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 C125 C126 7C 7D 7E C127 C127 CLK Address (hex) AVD# 7F 7F (stays high) tRACC tRACC RDY(1) latency tRACC RDY(2) latency Data OE#, CE# tRACC D124 D125 D126 D127 Read Status (stays low) Notes: 1. RDY active with data (D8 = 0 in the Configuration Register). 2. 3. 4. 5. RDY active one clock cycle before data (D8 = 1 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0 Figure 29. June 14, 2004 S29WSxxxN_00C0 Latency with Boundary Crossing into Program/Erase Bank S29WSxxxN MirrorBitTM Flash Family 99 P r e l i m i n a r y Data D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data AVD# total number of clock cycles following addresses being latched OE# 1 2 3 0 1 4 5 6 7 3 4 5 CLK 2 number of clock cycles programmed Wait State Configuration Register Setup: D13, D13, D13, D13, D13, D13, D13, D13, D12, D12, D12, D12, D12, D12, D12, D12, D11 D11 D11 D11 D11 D11 D11 D11 = = = = = = = = "111" "110" "101" "100" "011" "010" "001" "000" Reserved Reserved 5 programmed, 7 total 4 programmed, 6 total 3 programmed, 5 total 2 programmed, 4 total 1 programmed, 3 total 0 programmed, 2 total Note: Figure assumes address D0 is not at an address boundary, and wait state is set to "101". Figure 30. 100 Example of Wait States Insertion S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Read status (at least two cycles) in same bank and/or array data from other bank Last Cycle in Program or Sector Erase Command Sequence tWC tRC Begin another write or program command sequence tRC tWC CE# OE# tOE tOEH tGHWL WE# tWPH Data tWP tDS tOEZ tACC tOEH tDH RD RD PD/30h AAh tSR/W Addresses PA/SA RA RA 555h tAS AVD# tAH Note: Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information. Figure 31. June 14, 2004 S29WSxxxN_00C0 Back-to-Back Read/Write Cycle Timings S29WSxxxN MirrorBitTM Flash Family 101 P r e l i m i n a r y Erase and Programming Performance Parameter Sector Erase Time Typ (Note 1) Max (Note 2) 64 Kword VCC 0.6 3.5 16 Kword VCC <0.15 2 154 (WS256N) 308 (WS256N) 154 (WS128N) 78 (WS064N) VCC 39 (WS064N) Chip Erase Time 131 (WS256N) 33 (WS064N) VCC 40 400 ACC 24 240 Effective Word Programming Time utilizing Program Write Buffer VCC 9.4 94 ACC 6 60 Total 32-Word Buffer Programming Time VCC 300 3000 ACC 192 1920 157.3 (WS256N) 39.3 (WS064N) 314.6 (WS256N) 157.3 (WS128N) 78.6 (WS064N) 100.7 (WS256N) 50.3 (WS128N) 25.2 (WS064N) 201.3 (WS256N) 100.7 (WS128N) 50.3 (WS064N) VCC Chip Programming Time (Note 3) ACC 66 (WS128N) 78.6 (WS128N) Comments s s 262 (WS256N) 132 (WS128N) 66 (WS064N) ACC Single Word Programming Time (Note 8) 77 (WS128N) Unit Excludes 00h programming prior to erasure (Note 4) s s s s Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 1.70 V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. Based upon single word programming, not page programming. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Command Definition Summary for further information on command definitions. 6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. 7. Refer to Application Note "Erase Suspend/Resume Timing" for more details. 8. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 102 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Physical Dimensions (256 Mb and 128 Mb) VBH084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package 0.05 C (2X) D D1 A e 10 9 e 7 8 SE 7 6 E1 E 5 4 3 2 1 M A1 CORNER INDEX MARK L K B 10 H G F E SD 6 0.05 C (2X) J D C B A A1 CORNER 7 NXb 0.08 M C TOP VIEW 0.15 M C A B BOTTOM VIEW 0.10 C A2 A A1 C 0.08 C SEATING PLANE SIDE VIEW NOTES: PACKAGE VBH 084 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 11.60 mm x 8.00 mm NOM PACKAGE SYMBOL MIN NOM MAX A --- --- 1.00 A1 0.18 --- --- A2 0.62 --- 0.76 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE OVERALL THICKNESS BALL HEIGHT 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. BALL FOOTPRINT BALL FOOTPRINT E1 7.20 BSC. MD 12 ROW MATRIX SIZE D DIRECTION ME 10 ROW MATRIX SIZE E DIRECTION N 84 TOTAL BALL COUNT 0.33 --- 0.43 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT (A2-A9, B10-L10, M2-M9, B1-L1) DEPOPULATED SOLDER BALLS e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D b 4. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3339 \ 16-038.25b Note: BSC is an ANSI standard for Basic Space Centering June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 103 P r e l i m i n a r y Physical Dimensions (64 Mb) TBD--80-ball Fine-Pitch Ball Grid Array (FBGA) 7x9 mm MCP Compatible Package TBD Note: BSC is an ANSI standard for Basic Space Centering 104 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Revision Summary Revision A (February 2, 2004) Initial release. Revision A + 1 (March 12, 2004) Performance Characteristics Removed the Clock Divider section. Security Features Removed Burst Suspend/Resume section. Removed all document-wide references to this feature. Ordering Information Package type designations were corrected to show proper lead (Pb) characteristics. Process Technology was corrected to 110nm. Word Program Command Sequence New information added. Section completely re-written. Revision B (May 24, 2004) Global Changed document status to Preliminary. Deleted references to 1.5 V VIO option. Distinctive Characteristics MCP-Compatible Packages: Changed ball count and dimensions for 128Mb BGA package to 84-ball, 8 x 11.6 mm. High Performance: Changed typical word programming time to <6 s. General Description Corrected maximum wireless temperature range maximum to +85C. Deleted paragraph referring to clock polarity. Connection Diagrams Changed diagram for 128 Mb package to 84-ball layout, changed A23 input to RFU. Added note to 64 Mb connection diagram. Ordering Information Reformatted layout for easier reference. Changed valid combinations for 128 Mb density to match package change (80-ball to 84-ball; 8 x 10 mm to 8 x 11.6 mm). Table 1, Device Bus Operations Corrected symbols for AVD# during the Load Starting Burst Address and Terminate Current Burst Read Cycle and Start New Burst Read Cycle operations to active rising edge. Write Buffer Programming Operation Changed "Sector Address" to "starting address" in the first paragraph. Table 17, System Interface String Deleted note and references in table. Read Configuration Register Command Burst Active Clock Edge Configuration: Deleted reference to active falling edge settings. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 105 P r e l i m i n a r y Table 26, Configuration Register Changed 01b setting definition for CR6 to reserved for future use. Tables 29-30, Command Definitions Tables Reformatted for easier reference. Added Notes 10 and 11 to Table 30. Corrected definition for SecSi Sector Program command sequence. DC Characteristics Table Added Note 9 to Test Conditions column heading. Added Note 7 reference to ICC4, ICC5, and ICC6 specifications. Changed maximum specifications for ICC3 at VCC, ICC4, and ICC6. Added Notes 7 and 8. VCC Power-up Table and Figure 12, VCC Power-up Diagram Deleted tVIOS from table and diagram. Moved beginning of tVCS period from VCC low to VCC high. Figure 13, CLK Characterization Deleted CLK Divider waveform from figure. Synchronous Burst Read Operations table Deleted tRCC from table. Changed Note 1 to indicate only rising edge of CLK. Synchronous Burst Mode Read figure. Deleted figure. Hardware Reset (RESET#) table Deleted references to Embedded Algorithms. Deleted alternate definition of tRH (not during Embedded Algorithms). Erase/Program Operations table Changed specifications for tAH at 54 and 80 MHz speed options. Changed specification for tWHWH1. Modified Note 3 to indicate rising edge of CLK only. Erase and Programming Performance Table Changed cycles in Note 1 and VCC voltage in Note 2. Added Note 7. Changed typical and maximum values for Effective Word Programming Time utilizing Program Write Buffer (at ACC), Total 32-Word Buffer Programming Time (at ACC), Chip Programming Time (at ACC and VCC). Physical Dimensions Deleted 80-ball, 8 x 10 mm package drawing. Revision C (June 14, 2004) Global Changed all 1.65 V VCC and VIO specifications to 1.70 V. Deleted references to 1.8 V VIO. Distinctive Characteristics SecSi Sector region: Added "non-erasable region" subbullet. MCP-compatible packages: Deleted "recommended for all new designs". Read access times: Changed specifications for synchronous initial latency and asynchronous random access times for 80 MHz speed option. Program and Erase Performance: Changed heading text. Deleted "less than" symbols in front of specification values. Changed typical sector erase time for 64 Kword sectors. 106 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Power dissipation: Deleted CL condition. Deleted "less than" symbols in front of specification values. Changed all specifications listed to new values. Deleted Hardware Reset input and CMOS compatible input bullets. ACC input: Added "erase" to bullet text. General Description Modified description in third sentence of first paragraph. Changed initial latency specification for 80 MHz speed option. Modified description of Write Buffer Programming, Program Suspend/Program Resume, Erase Suspend/Erase Resume paragraphs. In 15th paragraph, added "memory array' to first sentence, and changed description of DQ3. In last paragraph, deleted reference to Fowler-Nordheim tunneling. Product Selector Guide Changed specifications for 80 MHz speed option. Block Diagram Deleted VSSIO input. Connection Diagrams Deleted note below diagrams. Multi-Chip Compatible Packages: Deleted references to Am29BDS products. MCP Look-Ahead Connection Diagram: Added section. Input/Output Descriptions Deleted VIO and VSSIO. Corrected CE#f1 name. Deleted voltage range for VCC. Added description for RFU. Ordering Information Changed reel size for packing types 2, 3. Corrected model numbers for 64 Mb device. Added Note 3 to all ordering information charts. Deleted BAI and added BFW to package & temperature valid combinations. Modified DYB power-up state description. Table 1, Device Bus Operations Deleted note. Changed active edge symbol in AVD# column for all operations. Changed active edge symbol in CLK column for synchronous write operation. Requirements for Asynchronous (Non-Burst) Read Operation Deleted last sentence of first paragraph. Deleted reference to addresses in second sentence of second paragraph. Requirements for Synchronous (Burst) Read Operation Modified first sentence of second paragraph. Deleted third paragraph. Modified Tables 2-11 and rearranged table sequence. 8-, 16-, and 32-Word Linear Burst with Wrap Around: Clarified first sentence in first paragraph. Modified first and second sentences in second paragraph. 8-, 16-, and 32-Word Linear Burst without Wrap Around: Added last sentence to first paragraph. Deleted second paragraph. Configuration Register Deleted "active clock edge" from paragraph. Accelerated Program/Chip Erase Operations Clarified heading title. Modified first sentence of second paragraph. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 107 P r e l i m i n a r y Write Buffer Programming Operation Modified note from first paragraph. Moved partial text from last paragraph to previous paragraph, deleted ramaining text. Password Sector Protection Replaced OTP reference in last paragraph with "non-erasable". Lock Register Modified first paragraph. Hardware Data Protection Mode Modified second, third, and last paragraphs. Write Pulse "Glitch" Protection Modified description. Standby Mode Modified second paragraph. RESET#: Hardware Reset Input Modified second paragraph. Deleted fourth paragraph. SecSiTM (Secured Silicon) Sector Flash Memory Region Modified second paragraph. SecSi Sector Protection Bit Deleted section. Common Flash Memory Interface (CFI) Added table reference to second paragraph. Deleted third paragraph. Table 16, CFI Query Identification String: Changed data for addresses 1Fh, 21h, and 25h. Table 17, System Interface String: Changed data for addresses 2Ah. Table 18, Device Geometry Definition: Changed data and description for addresses 45h. Table 21, WS128N Sector & Memory Address Map: Corrected address range and sector address bit range for SA66. Set Configuration Register Command Sequence Deleted reference to active clock edge. Programmable Wait State Modified paragraph. Set Internal Clock Frequency, Burst Sequence, Burst Active Clock Edge Configuration Deleted sections. Table 23, Programmable Wait State Settings Added 80 MHz column. RDY Configuration Deleted last sentence of paragraph. Table 25, Burst Length Configuration Changed function and settings descriptions for CR9, CR7, CR6. Added CR5, CR4 to table. 108 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Table 26, Configuration Register Changed read data for DA15-DQ0 and DQ2 indicator bits (BA) + 03h. Added row for Sector Block Lock/Unlock codes. Word Program Command Sequence Modified first sentence of third paragraph. Modified fourth sentence of last paragraph. Moved Figure 2 to this section. Figure 3, Write Buffer Programming Operation Deleted WS=31 from second box in figure. Unlock Bypass Command Sequence Deleted next to last sentence in first paragraph. Modified first sentence in second paragraph. Deleted third and fourth paragraphs. Chip Erase Command Sequence Modified first sentence in first paragraph. Deleted fourth paragraph. Sector Erase Command Sequence Modified first sentence in first paragraph. Modified third paragraph: added tSEA, description, deleted sixth and seventh and ninth (last) sentences. Deleted seventh paragraph. Erase Suspend/Erase Resume Commands Added tSEA to first paragraph. Added tESL to second paragraph. Program Suspend/Program Resume Commands Added tPSL to first paragraph. Lock Register Command Set Definitions Modified third paragraph; combined with fifth paragraph. Deleted fourth paragraph. Password Protection Command Set Definitions Clarified fifth and sixth paragraphs. Non-Volatile Sector Protection Command Set Definitions Modified third paragraph. Added Figure 5 to section. Volatile Sector Protection Command Set Clarified statement after bulleted list. Table 29, Memory Array Commands Added Note 18 to table. Deleted sector erase and erase rows from Unlock Bypass section of table. Added note reference to Set Configuration Register command. Table 30, Sector Protection Commands Deleted "Non" from Global Non-Volatile Sector Protection Freeze Command heading in table. Modified Note 10. Write Operation Status Added tPSP to second paragraph and tASP to fourth paragraph. RDY: Ready Moved subsection to Device Bus Operations section. Modified first sentence, and deleted last sentence in first paragraph. Deleted second paragraph. DQ6: Toggle Bit I Added tASP to third paragraph. Added tPAP to fifth paragraph. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 109 P r e l i m i n a r y DQ3: Sector Erase Timer Added tSEA to first paragraph. Operating Ranges Changed VCC and VIO supply voltage range specifications. DC Characteristics Changed Note 7. Changed specifications for ICCB, ICC1, ICC2, ICC3, ICC4, ICC6. Removed "less than" symbol from ICC5 and IACC. Synchronous/Burst Read Changed specifications for tIACC, tOE, tCEZ, tOEZ, tCES, tAVC, tAVD. Deleted tCKA, tCKZ, tOES. Changed Note 2. Figure 14, CLK Synchronous Burst Mode Read and Figure 15, 8-word Linear Burst with Wrap Around Modified Addresses waveform. Changed Note 4. Hardware Reset (RESET#) table Changed specifications for tRP and tRH. Asynchronous Mode Read table Changed specifications for tCE, tACC, tAVDP, tAAVDS, tOE, tOEH, tOEZ. Added note. Erase/Program Timing Operations table Changed specifications for tWC, tAS, tAH, tAVDP, tWP, tCS, tASW, tAVHW, tAVSC, tAVHC. Added tWEP, tSEA, tESL, tPSL, tASP, tPSP. Deleted tWHWH1 and tWHWH2. Figure 22, Synchronous Program Operation Timings: CLK Latched Addresses Modified AVD waveform. Figure 23, Accelerated Unlock Bypass Programming Timing Deleted tVIDS value from OE# waveform. Figure 29, Latency with Boundary Crossing into Program/Erase Bank Modified note. Erase and Programming Performance Deleted Erase Suspend/Erase Resume Latency, and Program Suspend/Program Resume Latency specifications from table. Changed specifications for all except Chip Programming Time. Removed "less than" symbol for Chip Programming Times. Added Single Word Programming Time specifications. Added Note 8. 110 S29WSxxxN MirrorBitTM Flash Family S29WSxxxN_00C0 June 14, 2004 P r e l i m i n a r y Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 Spansion LLC. All rights reserved. SpansionTM, the SpansionTM logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. June 14, 2004 S29WSxxxN_00C0 S29WSxxxN MirrorBitTM Flash Family 111