INTEGRATED CIRCUITS DATA SHEET PCF85xxC-2 family 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface Product specification File under Integrated Circuits, IC12 1997 Feb 13 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 DEVICE SELECTION 6 BLOCK DIAGRAM 7 PINNING 7.1 7.2 7.3 Pin description PCF8582C-2 Pin description PCF8594C-2 Pin description PCF8598C-2 8 I2C-BUS PROTOCOL 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.5.1 Bus conditions Data transfer Device addressing Write operations Byte/word write Page write Remark Read operations Remark 1997 Feb 13 2 PCF85xxC-2 family 9 LIMITING VALUES 10 CHARACTERISTICS 11 I2C-BUS CHARACTERISTICS 12 WRITE CYCLE LIMITS 13 EXTERNAL CLOCK TIMING 14 PACKAGE OUTLINES 15 SOLDERING 15.1 15.2 15.2.1 15.2.2 15.3 15.3.1 15.3.2 15.3.3 Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family FEATURES * High reliability by using a redundant storage code * Low power CMOS: * Endurance: 1000000 Erase/Write (E/W) cycles at Tamb = 22 C 1 - maximum operating current: 2.0 mA (PCF8582C-2) 2.5 mA (PCF8594C-2) 4.0 mA (PCF8598C-2) * 10 years non-volatile data retention time * Pin and address compatible to: PCF8570, PCF8571, PCF8572 and PCF8581. - maximum standby current 10 A (at 6.0 V), typical 4 A 2 * Non-volatile storage of: The PCF85xxC-2 is a family of floating gate Electrically Erasable Programmable Read Only Memories (EEPROMs) with 2, 4 and 8 kbits (256, 512 and 1024 x 8-bit). By using an internal redundant storage code it is fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. - 2 kbits organized as 256 x 8-bit (PCF8582C-2) - 4 kbits organized as 512 x 8-bit (PCF8594C-2) - 8 kbits organized as 1024 x 8-bit (PCF8598C-2) * Single supply with full operation down to 2.5 V * On-chip voltage multiplier * Serial input/output I2C-bus * Write operations: As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Up to eight PCF85xxC-2 devices may be connected to the I2C-bus. Chip select is accomplished by three address inputs (A0, A1 and A2). - byte write mode - 8-byte page write mode (minimizes total write time per byte) * Read operations: - sequential read Timing of the E/W cycle is carried out internally, thus no external components are required. Pin 7 (PTC) must be connected to either VDD or left open-circuit. There is an option of using an external clock for timing the length of an E/W cycle. - random read * Internal timer for writing (no external components) * Power-on-reset 3 GENERAL DESCRIPTION QUICK REFERENCE DATA SYMBOL PARAMETER VDD supply voltage IDDR supply current read IDDW supply current E/W CONDITIONS PCF8598C-2 1997 Feb 13 UNIT 2.5 6.0 V VDD = 2.5 V - 60 A VDD = 6 V - 200 A VDD = 2.5 V - 0.6 mA VDD = 6 V - 2.0 mA VDD = 2.5 V - 0.8 mA VDD = 6 V - 2.5 mA VDD = 2.5 V - 1.0 mA fSCL = 100 kHz PCF8594C-2 standby supply current MAX. fSCL = 100 kHz PCF8582C-2 IDD(stb) MIN. VDD = 6 V - 4.0 mA VDD = 2.5 V - 3.5 A VDD = 6 V - 10 A 3 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface 4 PCF85xxC-2 family ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 SO8 plastic small outline package; 8 leads (straight); body width 3.9 mm SOT96-1 SO8 plastic small outline package; 8 leads; body width 7.5 mm SOT176-1 PCF8582C-2P PCF8594C-2P PCF8598C-2P PCF8582C-2T PCF8594C-2T PCF8598C-2T 5 DEVICE SELECTION Table 1 Device selection code SELECTION Bit Device DEVICE CODE CHIP ENABLE b7(1) b6 b5 b4 b3 b2 b1 b0 1 0 1 0 A2 A1 A0 R/W Note 1. The Most Significant Bit (MSB) `b7' is sent first. 1997 Feb 13 R/W 4 1997 Feb 13 5 3 2 1 5 6 4 VSS ADDRESS SWITCH n 8 BYTE LATCH (8 bytes) 3 BYTE COUNTER POWER-ON-RESET TEST MODE DECODER SHIFT REGISTER INPUT FILTER ADDRESS POINTER PCF85xxC-2 EEPROM Fig.1 Block diagram. 8 ADDRESS HIGH REGISTER 4 I2C-BUS CONTROL LOGIC EE CONTROL OSCILLATOR TIMER ( 16) SEQUENCER DIVIDER ( 128) MGD927 7 PTC 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface The pin numbers in this block diagram refer to the PCF8582C-2. For PCF8594C-2 and PCF8598C-2 please see Chapter 7. A0 A2 A1 SDA SCL 6 handbook, full pagewidth VDD Philips Semiconductors Product specification PCF85xxC-2 family BLOCK DIAGRAM Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface 7 PCF85xxC-2 family PINNING 7.1 Pin description PCF8582C-2 SYMBOL PIN DESCRIPTION A0 1 address input 0 A1 2 address input 1 A2 3 address input 2 VSS 4 negative supply voltage SDA 5 serial data input/output (I2C-bus) SCL 6 serial clock input (I2C-bus) PTC 7 programming time control output VDD 8 positive supply voltage 7.2 A0 8 V DD 1 7 PTC A2 3 6 SCL VSS 4 5 SDA A1 2 PCF8582C-2 MGD928 Fig.2 Pin configuration PCF8582C-2. Pin description PCF8594C-2 SYMBOL PIN DESCRIPTION WP 1 write-protection input A1 2 address input 1 A2 3 address input 2 VSS 4 negative supply voltage SDA 5 serial data input/output (I2C-bus) SCL 6 serial clock input (I2C-bus) PTC 7 programming time control output VDD 8 positive supply voltage 7.3 handbook, halfpage handbook, 2 columns WP 8 V DD 1 7 PTC A2 3 6 SCL VSS 4 5 SDA A1 2 PCF8594C-2 MGL001 Fig.3 Pin configuration PCF8594C-2. Pin description PCF8598C-2 SYMBOL PIN DESCRIPTION WP 1 write-protection input n.c. 2 not connected A2 3 address input 2 VSS 4 negative supply voltage SDA 5 serial data input/output (I2C-bus) SCL 6 serial clock input (I2C-bus) PTC 7 programming time control output VDD 8 positive supply voltage 1997 Feb 13 handbook, halfpage WP 8 V DD 1 7 PTC A2 3 6 SCL VSS 4 5 SDA n.c. 2 PCF8598C-2 MGL002 Fig.4 Pin configuration PCF8598C-2. 6 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface 8 Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit. I2C-BUS PROTOCOL The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA), and one for clock signals (SCL). Within the I2C-bus specifications a low-speed mode (2 kHz clock rate) and a high speed mode (100 kHz clock rate) are defined. The PCF85xxC-2 operates in both modes. Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. By definition a device that sends a signal is called a `transmitter', and the device which receives the signal is called a `receiver'. The device which controls the signal is called the `master'. The devices that are controlled by the master are called `slaves'. The following protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. 8.1 Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Bus conditions The following bus conditions have been defined: The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. * Bus not busy: both data and clock lines remain HIGH. * Start data transfer: a change in the state of the data line, from HIGH-to-LOW, while the clock is HIGH, defines the START condition. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. * Stop data transfer: a change in the state of the data line, from LOW-to-HIGH, while the clock is HIGH, defines the STOP condition. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master generation of the STOP condition. * Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. 8.2 Data transfer Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes, transferred between the START and STOP conditions is limited to 7 bytes in the E/W mode and 8 bytes in the page E/W mode. 1997 Feb 13 PCF85xxC-2 family 7 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface 8.3 After this STOP condition the E/W cycle starts and the bus is free for another transmission. Its duration is 10 ms per byte. Device addressing Following a START condition the bus master must output the address of the slave it is accessing. The 4 MSBs of the slave address are the device type identifier (see Fig.5). For the PCF85xxC-2 this is fixed to `1010'. During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus. The next three significant bits address a particular device or memory page (page = 256 bytes of memory). A system could have up to eight PCF8582C-2 (or four PCF8594C-2 containing two memory pages each or two PCF8598C-2 containing four memory pages each, respectively) devices on the bus. The eight addresses are defined by the state of the A0, A1 and A2 inputs. 8.4.2 Address bits must be connected to either VDD or VSS. 1 0 1 0 A2 A1 After the receipt of each data byte the three low order bits of the word address are internally incremented. The high order five bits of the address remain unchanged. The slave acknowledges the reception of each data byte with an ACK. The I2C-bus data transfer is terminated by the master after the 8th byte with a STOP condition. If the master transmits more than eight bytes prior to generating the STOP condition, no acknowledge will be given on the ninth (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles. A0 R/W MBC793 Fig.5 Slave address. 8.4 8.4.1 Write operations BYTE/WORD WRITE 8.4.3 For a write operation the PCF85xxC-2 requires a second address field. This address field is a word address providing access to the 256 words of memory. Upon receipt of the word address the PCF85xxC-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master can now terminate the transfer by generating a STOP condition or transmit up to six more bytes of data and then terminate by generating a STOP condition. 1997 Feb 13 PAGE WRITE The PCF85xxC-2 is capable of an eight-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transmit eight data bytes within one transmission. After receipt of each byte the PCF85xxC-2 will respond with an acknowledge. The typical E/W time in this mode is 9 x 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms and sequential writing of these 8 bytes another typical 28 ms. The last bit of the slave address defines the operation to be performed. When set to logic 1 a read operation is selected. handbook, halfpage PCF85xxC-2 family REMARK A write to the EEPROM is always performed if the pin WP is LOW (not on PCF8582C-2). If WP is HIGH, then the upper half of the EEPROM is write-protected and no acknowledge will be given by the PCF85xxC-2 when one of the upper 256 EEPROM bytes (PCF8594C-2) or 512 EEPROM bytes (PCF8598C-2) is addressed. However, an acknowledge will be given after the slave address and the word address. 8 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface S acknowledge from slave acknowledge from slave handbook, full pagewidth 0 A SLAVE ADDRESS PCF85xxC-2 family WORD ADDRESS A acknowledge from slave DATA acknowledge from slave DATA A A P R/W auto increment word address auto increment word address MBA701 Fig.6 Auto increment memory word address; two byte write. handbook, full pagewidth S acknowledge from slave SLAVE ADDRESS 0 A acknowledge from slave WORD ADDRESS acknowledge from slave DATA N A A acknowledge from slave DATA N + 1 A R/W auto increment word address auto increment word address acknowledge from slave DATA N + 7 1 A P last byte MBA702 Fig.7 Page write operation; eight bytes. 1997 Feb 13 9 auto increment word address Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface 8.5 Read operations 8.5.1 Read operations are initiated in the same manner as write operations with the exception that the LSB of the slave address is set to logic 1. S acknowledge from slave acknowledge from slave SLAVE ADDRESS 0 A REMARK The lower 8 bits of the word address are incremented after each transmission of a data byte (read or write). The MSB of the word address, which is defined in the slave address, is not changed when the word address count overflows. Thus, the word address overflows from 255 to 0 and from 511 to 256. There are three basic read operations; current address read, random read and sequential read sequential read. handbook, full pagewidth PCF85xxC-2 family WORD ADDRESS R/W A acknowledge from slave SLAVE ADDRESS S at this moment master transmitter becomes master receiver and EEPROM slave receiver becomes slave transmitter 1 A R/W acknowledge from master DATA A n bytes auto increment word address no acknowledge from master DATA 1 P last byte auto increment word address MBA703 - 1 Fig.8 Master reads PCF85xxC-2 slave after setting word address (write word address; read data). acknowledge from master acknowledge from slave handbook, full pagewidth S SLAVE ADDRESS 1 A R/W DATA A n bytes no acknowledge from master DATA 1 P last bytes auto increment word address auto increment word address MBA704 - 1 Fig.9 Master reads PCF85xxC-2 immediately after first byte (read mode). 1997 Feb 13 10 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDD supply voltage VI input voltage on any input pin II CONDITIONS MIN. -0.3 MAX. UNIT +6.5 V VSS - 0.8 +6.5 V input current on any input pin - 1 mA IO output current - 10 mA Tstg storage temperature -65 +150 C Tamb operating ambient temperature -40 +85 C Zi > 500 10 CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supplies VDD supply voltage IDDR supply current read IDDW supply current E/W PCF8582C-2 PCF8594C-2 PCF8598C-2 IDD(stb) standby supply current 2.5 6.0 V VDD = 2.5 V - 60 A VDD = 6.0 V - 200 A VDD = 2.5 V - 0.6 mA VDD = 6.0 V - 2.0 mA VDD = 2.5 V - 0.8 mA VDD = 6.0 V - 2.5 mA VDD = 2.5 V - 1.0 mA VDD = 6.0 V fSCL = 100 kHz fSCL = 100 kHz - 4.0 mA VDD = 2.5 V - 3.5 A VDD = 6.0 V - 10 A V PTC output (pin 7) VIL LOW level input voltage -0.8 0.1VDD VIH HIGH level input voltage 0.9VDD VDD + 0.8 V SCL input (pin 6) VIL LOW level input voltage -0.8 0.3VDD V VIH HIGH level input voltage 0.7VDD +6.5 V ILI input leakage current fSCL clock input frequency CI input capacitance 1997 Feb 13 VI = VDD or VSS VI = VSS 11 - 1 A 0 100 kHz - 7 pF Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface SYMBOL PARAMETER PCF85xxC-2 family CONDITIONS MIN. MAX. UNIT SDA input/output (pin 5) VIL LOW level input voltage -0.8 0.3VDD V VIH HIGH level input voltage 0.7VDD +6.5 V VOL LOW level output voltage IOL = 3 mA; VDD(min) - 0.4 V ILO output leakage current VOH = VDD - 1 A CI input capacitance VI = VSS - 7 pF Tamb = 55 C 10 - years Data retention time tS data retention time 11 I2C-BUS CHARACTERISTICS All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing from VSS to VDD; see Fig.10. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT fSCL clock frequency 0 100 kHz tBUF bus free time between a STOP and START condition 4.7 - s tHD;STA START condition hold time after which first clock pulse is generated 4.0 - s tLOW LOW level clock period 4.7 - s tHIGH HIGH level clock period 4.0 - s tSU;STA set-up time for STARt condition 4.7 - s tHD;DAT data hold time repeated start for bus compatible masters for bus devices note 1 5 - s 0 - ns tSU;DAT data set-up time 250 - ns tr SDA and SCL rise time - 1 s tf SDA and SCL fall time - 300 ns tSU;STO set-up time for STOP condition 4.0 - s Note 1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. 1997 Feb 13 12 1997 Feb 13 P t BUF S t HD;STA t LOW tr 13 t HIGH handbook, full pagewidth t SU;DAT t SU;STO t SU;STA MBA705 P t HD;STA S Fig.10 Timing requirements for the I2C-bus. t HD;DAT tf 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface P = STOP condition; S = START condition. SCL SDA Philips Semiconductors Product specification PCF85xxC-2 family Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family 12 WRITE CYCLE LIMITS Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT E/W cycle timing tE/W E/W cycle time internal oscillator - 7 - ms external clock 4 - 10 ms Tamb = -40 to +85 C 100000 - - cycles Tamb = 22 C - 1000000 - cycles Endurance NE/W E/W cycle per byte 13 EXTERNAL CLOCK TIMING td handbook, full pagewidth tr PTC t HIGH tf t LOW 1 2 257 SDA SCL STOP MBA697 Fig.11 One byte E/W cycle. td handbook, full pagewidth tr t HIGH tf t LOW n x 256 + 1 PTC 1 2 SDA SCL STOP MBA698 Fig.12 n bytes E/W cycle (n = 2 to 7). 1997 Feb 13 14 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface tr td t HIGH tf PCF85xxC-2 family t LOW handbook, full pagewidth PTC 1 2 1153 SDA SCL STOP MBA699 Fig.13 Page mode. handbook, full pagewidth SLAVE ADDRESS 2 I C-bus S HIGH PTC LOW WORD ADDRESS 0A A DATA A DATA A P (1) undefined undefined 1 1 1 negative edge SCL 8-bit td 2 2 2 257 513 1153 clock (2) clock (3) clock (4) 0 MBA700 (1) If an external clock is chosen, this information is latched internally by setting pin 7 (PTC) LOW after transmission of the eighth bits of the word address (negative edge of SCL). Thus the state of pin 7 may be previously undefined. Leaving pin 7 LOW causes a higher standby current. (2) 1-byte programming. (3) 2-byte programming. (4) One page (8 bytes) programming. Fig.14 External clock. 1997 Feb 13 15 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family 14 PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.020 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT97-1 050G01 MO-001AN 1997 Feb 13 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 16 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0098 0.014 0.0075 0.20 0.19 0.16 0.15 0.050 0.24 0.23 0.039 0.028 0.041 0.016 0.024 inches 0.0098 0.057 0.069 0.0039 0.049 0.01 0.01 0.028 0.004 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Feb 13 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 17 o 8 0o Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family SO8: plastic small outline package; 8 leads; body width 7.5 mm SOT176-1 D E A X c y HE v M A Z 8 5 Q A2 A (A 3) A1 pin 1 index Lp L 1 4 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 7.65 7.45 7.6 7.4 1.27 10.65 10.00 1.45 1.1 0.45 1.1 1.0 0.25 0.25 0.1 2.0 1.8 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.30 0.29 0.30 0.29 0.050 0.42 0.39 0.057 0.043 0.018 0.043 0.039 0.01 0.01 0.004 0.079 0.071 inches 0.10 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 91-08-13 95-02-25 SOT176-1 1997 Feb 13 EUROPEAN PROJECTION 18 o 8 0o Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. 15 SOLDERING 15.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 15.3.2 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 15.2.1 * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 15.3 15.3.1 15.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Feb 13 WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 15.2.2 PCF85xxC-2 family 19 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface PCF85xxC-2 family 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Feb 13 20 Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface NOTES 1997 Feb 13 21 PCF85xxC-2 family Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface NOTES 1997 Feb 13 22 PCF85xxC-2 family Philips Semiconductors Product specification 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface NOTES 1997 Feb 13 23 PCF85xxC-2 family Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417067/1200/01/pp24 Date of release: 1997 Feb 13 Document order number: 9397 750 01773 Select & Go... Go to Philips Semiconductors' home page Start part Catalog & Datasheets Information as of 2000-08-25 Catalog by Function Discrete semiconductors Audio Clocks and Watches Data communications Microcontrollers Peripherals Standard analog Video Wired communications Wireless communications Catalog by System Automotive Consumer Multimedia Systems Communications PC/PC-peripherals Cross reference PCF85xxC-2 family; 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface * Description * Features * Datasheet * Blockdiagram * Products, packages, availability and ordering * Find similar products Subscribe to eNews To be kept informed on PCF85xxC-2 family, subscribe to eNews. * Description The PCF85xxC-2 is a family of floating gate Electrically Erasable Programmable Read Only Memories (EEPROMs) with 2, 4 and 8 kbits (256, 512 and 1024 x 8-bit). By using an internal redundant storage code it is fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. Models Packages Application notes Selection guides Other technical documentation As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Up to eight PCF85xxC-2 devices may be connected to the I2C-bus. Chip select is accomplished by three address inputs (A0, A1 and A2). Timing of the E/W cycle is carried out internally, thus no external components are required. Pin 7 (PTC) must be connected to either VDD or left open-circuit. There is an option of using an external clock for timing the length of an E/W cycle. End of Life information Datahandbook system Features Relevant Links About catalog tree About search About this site Subscribe to eNews Catalog & Datasheets Search PCF85xxC-2 family PCF85xxC-2 family l l l l l l Low power CMOS: - maximum operating current: 2.0 mA (PCF8582C-2) 2.5 mA (PCF8594C-2) 4.0 mA (PCF8598C-2) - maximum standby current 10 A (at 6.0 V), typical 4 A Non-volatile storage of: - 2 kbits organized as 256 x 8-bit (PCF8582C-2) - 4 kbits organized as 512 x 8-bit (PCF8594C-2) - 8 kbits organized as 1024 x 8-bit (PCF8598C-2) Single supply with full operation down to 2.5 V On-chip voltage multiplier Serial input/output I2C-bus Write operations: - byte write mode l l l l l l l - 8-byte page write mode (minimizes total write time per byte) Read operations: - sequential read - random read Internal timer for writing (no external components) Power-on-reset High reliability by using a redundant storage code Endurance: 1000000 Erase/Write (E/W) cycles at Tamb =22C 10 years non-volatile data retention time Pin and address compatible to: PCF8570, PCF8571, PCF8572 and PCF8581. Datasheet Type nr. Title PCF85xxC-2 family 256 to 1024 x 8-bit CMOS EEPROMs with I2C-bus interface Publication release date 13-Feb-97 Datasheet status Product Specification Page count 24 File size (kB) 179 Datasheet Download Blockdiagram Blockdiagram of PCF8598C-2P Products, packages, availability and ordering Partnumber PCF8582C2P/03 PCF8582C2T/03 PCF8594C2P/02 PCF8594C2T/02 PCF8598C2P/02 North American Partnumber Order code (12nc) marking/packing package device status PCF8582C2N 9351 916 70112 Standard Marking * Tube SOT97 Full production PCF8582C2D 9351 917 10112 Standard Marking * Tube SOT96 Full production PCF8582C2D-T 9351 917 10118 SOT96 Full production PCF8594C2N 9351 955 10112 Standard Marking * Tube SOT97 Full production PCF8594C2D 9351 955 50112 Standard Marking * Tube SOT96 Full production PCF8594C2D-T 9351 955 50118 SOT96 Full production PCF8598C2N 9351 823 50112 Standard Marking * Tube SOT97 Full production Standard Marking * Reel Pack, SMD, 13" Standard Marking * Reel Pack, SMD, 13" buy online 2P/02 PCF8598C2T/02 PCF8598C2N 9351 823 50112 Standard Marking * Tube SOT97 PCF8598C2D 9351 823 90112 Standard Marking * Tube SOT176 Full production PCF8598C2D-T 9351 823 90118 Standard Marking * Reel Pack, SMD, 13" Full production SOT176 Full production Please read information about some discontinued variants of this product. Find similar products: PCF85xxC-2 family links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. Copyright (c) 2000 Royal Philips Electronics All rights reserved. Terms and conditions.