TC74VHCT573AF/AFW/AFT
2006-02-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT573AF,TC74VHCT573AFW,TC74VHCT573AFT
Octal D-Type Latch with 3-State Output
The TC74VHCT573A is an advanced high speed CMOS OCTAL
LATCH with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type latch is controlled by a latch enable input
(LE) and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output (Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: Output in off-state
Features
• High speed: tpd = 7.7 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
• Compatible with TTL outputs: VIL = 0.8 V (max)
V
IH = 2.0 V (min)
• Power down protection is provided on all inputs and outputs.
• Balanced propagation delays: tpLH ∼
−tpHL
• Low noise: VOLP = 1.6 V (max)
• Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 573 type.
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHCT573AF
TC74VHCT573AFW
TC74VHCT573AFT
Weight
SOP20-P-300-1.27A : 0.22 g (typ.)
SOP20-P-300-1.27 : 0.22 g (typ.)
SOL20-P-300-1.27 : 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
TC74VHCT573AF/AFW/AFT
2006-02-01
2
Pin Assignment IEC Logic Symbol
Trut h Table
Inputs
OE LE D
Output
H X X Z
L L X Qn
L H L L
L H H H
X: Don’t care
Z: High impedance
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
OE
LE
11
2
19
L Q
D
Q1
D1
18
L Q
D
Q2
D2
17
L Q
D
Q3
D3
16
L Q
D
Q4
D4
15
L Q
D
Q5
D5
14
L Q
D
Q6
D6
13
L Q
D
Q7
D7
12
L Q
D
Q0
D0
3 456789
1
D
(8)
(6)
(7)
(11)
(1)
(2)
(4)
(3)
D1
1D
D3
D2
(5)
D5
D4
(19)
(17)
(15)
Q1
Q3
Q5
(18)
(16)
(14)
Q2
Q4
Q6
EN
C1
LE
OE
D6
(9)
D7
(13)
Q7
(12)
Q0
D0
VCC
16
Q2
Q3
Q4 15
14
13
12
11
20
OE 1
2
3
4
5
6
7
D4
D5
D6
D7
D0
Q5
8
Q1
19
Q6
Q0
D2
D3
18
9
D1
GND 10 LE
17
Q7
(top view)
TC74VHCT573AF/AFW/AFT
2006-02-01
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to 7.0 V
−0.5 to 7.0 (Note 2)
DC output voltage VOUT
−0.5 to VCC + 0.5 (Note 3)
V
Input diode current IIK −20 mA
Output diode current IOK ±20 (Note 4) mA
DC output current IOUT ±25 mA
DC VCC/ground current ICC ±75 mA
Power dissipation PD 180 mW
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Note 2: Output in off-state
Note 3: High or low state. IOUT absolute maximum rating must be observed.
Note 4: VOUT < GND, VOUT > VCC
Recomm end ed Operating Condi tions (No t e 1)
Characteristics Symbol Rating Unit
Supply voltage VCC 4.5 to 5.5 V
Input voltage VIN 0 to 5.5 V
0 to 5.5 (Note 2)
Output voltage VOUT
0 to VCC (Note 3)
V
Operating temperature Topr −40 to 85 °C
Input rise and fall time dt/dV 0 to 20 ns/V
Note 1: The recommended operating conditions are required to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 2: Output in off-state
Note 3: High or low state
TC74VHCT573AF/AFW/AFT
2006-02-01
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH ― 4.5 to 5.5 2.0 ― ― 2.0 ― V
Low-level input
voltage VIL ― 4.5 to 5.5 ― ― 0.8 ― 0.8 V
IOH = −50 µA 4.5 4.40 4.50 ― 4.40 ―
High-level output
voltage VOH
VIN
= VIH or
VIL IOH = −8 mA 4.5 3.94 ― ― 3.80 ―
V
IOL = 50 µA 4.5 ― 0.0 0.1 ― 0.1
Low-level output
voltage VOL
VIN
= VIH or
VIL IOL = 8 mA 4.5 ― ― 0.36 ― 0.44
V
3-state output
off-state current IOZ
VIN = VIH or VIL
VOUT = VCC or GND
5.5 ― ― ±0.25 ― ±2.50 µA
Input leakage
current IIN VIN = 5.5 V or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 µA
ICC V
IN = VCC or GND 5.5 ― ― 4.0 ― 40.0 µA
Quiescent supply
current ICCT Per input: VIN = 3.4 V
Other input: VCC or GND
5.5 ― ― 1.35 ― 1.50 mA
Output leakage
current IOPD VOUT = 5.5 V 0 ― ― 0.5 ― 5.0 µA
Timing Requirements (input: tr = tf = 3 ns)
Test Condition Ta = 25°C
Ta =
−40 to
85°C
Characteristics Symbol
VCC (V) Typ. Limit Max
Unit
Minimum pulse width
(LE)
tw (H) ― 5.0 ± 0.5 ― 6.5 8.5 ns
Minimum set-up time ts ― 5.0 ± 0.5 ― 1.5 1.5 ns
Minimum hold time th ― 5.0 ± 0.5 ― 3.5 3.5 ns
TC74VHCT573AF/AFW/AFT
2006-02-01
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AC Characteristics (input: tr = tf = 3 ns)
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
VCC (V) CL (pF) Min Typ. Max Min Max
Unit
15 ― 7.7 12.3 1.0 13.5
Propagation delay
time
(LE-Q)
tpLH
tpHL
― 5.0 ± 0.5
50 ― 8.5 13.3 1.0 14.5
ns
15 ― 5.1 8.5 1.0 9.5
Propagation delay
time
(D-Q)
tpLH
tpHL
― 5.0 ± 0.5
50 ― 5.9 9.5 1.0 10.5
ns
15 ― 6.3 10.9 1.0 12.5
3-state output enable
time
tpZL
tpZH
RL = 1 kΩ 5.0 ± 0.5
50 ― 7.1 11.9 1.0 13.5
ns
3-state output disable
time
tpLZ
tpHZ
RL = 1 kΩ 5.0 ± 0.5 50 ― 8.8 11.2 1.0 12.0 ns
Output to output skew tosLH
tosHL
(Note 1) 5.0 ± 0.5 50 ― ― 1.0 ― 1.0 ns
Input capacitance CIN ― ― 4 10 ― 10 pF
Output capacitance COUT ― ― 9 ― ― ― pF
Power dissipation
capacitance CPD (Note 2) ― 25 ― ― ― pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per latch)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 14 + 11·n
Noise Characteristics (input: tr = tf = 3 ns) (Note)
Test Condition Ta = 25°C
Characteristics Symbol
VCC (V) Typ. Max
Unit
Quiet output maximum dynamic VOL V
OLP CL = 50 pF 5.0 1.1
(1.2)
1.5
(1.6)
V
Quiet output minimum dynamic VOL V
OLV CL = 50 pF 5.0
−1.1
(−1.2)
−1.5
(−1.6)
V
Minimum high level dynamic input voltage VIHD CL = 50 pF 5.0 ― 2.0 V
Maximum low level dynamic input voltage VILD CL = 50 pF 5.0 ― 0.8 V
Note: The value in ( ) only applies to JEDEC SOP (FW) devices.
TC74VHCT573AF/AFW/AFT
2006-02-01
6
Package Dimensions
Weight: 0.22 g (typ.)
TC74VHCT573AF/AFW/AFT
2006-02-01
7
Package Dimensions
Weight: 0.22 g (typ.)
TC74VHCT573AF/AFW/AFT
2006-02-01
8
Package Dimensions (Note)
Note: This package is not available in Japan.
Weight: 0.46 g (typ.)
TC74VHCT573AF/AFW/AFT
2006-02-01
9
Package Dimensions
Weight: 0.08 g (typ.)
TC74VHCT573AF/AFW/AFT
2006-02-01
10
Note: Lead (Pb)-Free Packages
SOP20-P-300-1.27A TSSOP20-P-0044-0.65A
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