SDAS210C − DECEMBER 1982 − REVISED JULY 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DSingle Down/Up Count-Control Line
DLook-Ahead Circuitry Enhances Speed of
Cascaded Counters
DFully Synchronous in Count Modes
DAsynchronously Presettable With Load
Control
DPackage Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’ALS191A are synchronous 4-bit reversible
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincidentally with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is lo w, the counter
counts up, and when D/U is high, the counter
counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD
input and entering the desired data at the data inputs. The output changes to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on
(current required by) clock drivers, for long parallel words.
Copyright 1996, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
QB
QA
CTEN
D/U
QC
QD
GND
VCC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54ALS191A ...J PACKAGE
SN74ALS191A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS191A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
QA
CTEN
NC
D/U
QC
B
NC
D
CA
Q
GND
NC
DQ
B
VCC
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
description (continued)
Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The
latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of
the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output
(RCO) produces a low-level output pulse under those same conditions, but only while the clock input is low. The
counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter
if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count
(MAX/MIN) output can be used to accomplish look ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ALS191A is characterized for operation from 0°C to 70°C.
logic symbol†
1,2− / 1,3+
CTRDIV16
M2 [DOWN]
5
M3 [UP]
14
CLK G4
C5
11
MAX/MIN
12
2(CT=0)Z6
3(CT=15)Z6
13
6,1,4
3
2
6
7
5D
15
A1
B10
C9
D
G1
4
[1]
[2]
[4]
[8]
CTEN
D/U
QA
QB
QC
QD
LOAD
RCO
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic diagram (positive logic)
15
4
11
14
5
CLK
A
1
10
9
B
C
D
CTEN
D/U
LOAD
QB
QC
QD
2
6
7
MAX/
MIN
QA
12
13
3
RCO
SC1
1D
R
SC1
1D
R
SC1
1D
R
SC1
1D
R
Pin numbers shown are for the D, J, and N packages.
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
typical load, count, and inhibit sequences
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
2
A
B
C
D
CLK
D/U
MAX/MIN
QA
QD
QC
QB
Load
Count Up Inhibit Count Down
13 14 15 0 1 2210151413
Data
Inputs
RCO
CTEN
LOAD
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS191A −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS191A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS191A SN74ALS191A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
fclock Clock frequency 0 20 0 30 MHz
tw
Pulse duration
CLK high or low 20 16.5
ns
twPulse duration LOAD low 25 20 ns
Data before LOAD↑25 20
tsu
Setup time
CTEN before CLK↑45 20
ns
tsu Setup time D/U before CLK↑30 20 ns
LOAD inactive before CLK↑20 20
Data after LOAD↑5 5
thHold time CTEN after CLK↑0 0 ns
D/U after CLK↑0 0
ns
TAOperating free-air temperature −55 125 0 70 °C
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS191A SN74ALS191A
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = −18 mA −1.5 −1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = −0.4 mA VCC −2 VCC −2
VOL
VCC = 4.5 V
IOL = 4 mA 0.25 0.4 0.25 0.4 V
VOL VCC = 4.5 V IOL = 8 mA 0.35 0.5
V
IIVCC = 5.5 V, VI = 7 V 0.2 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL
CTEN or CLK
VCC = 5.5 V,
VI = 0.4 V
−0.2 −0.2
mA
IIL All others VCC = 5.5 V, VI = 0.4 V −0.2 −0.1 mA
IO‡VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA
ICC VCC = 5.5 V, All inputs at 0 12 22 12 22 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER FROM
(OUTPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX§UNIT
PARAMETER
(OUTPUT)
(OUTPUT)
SN54ALS191A SN74ALS191A
UNIT
MIN MAX MIN MAX
fmax 20 30 MHz
tPLH
LOAD
Any Q
7 37 7 30
ns
tPHL LOAD Any Q 8 34 8 30 ns
tPLH
A, B, C, D
Any Q
3 25 3 21
ns
tPHL A, B, C, D Any Q 4 25 4 21 ns
tPLH
CLK
RCO
5 24 5 20
ns
tPHL CLK RCO 5 25 5 20 ns
tPLH
CLK
Any Q
3 26 3 18
ns
tPHL CLK Any Q 3 22 3 18 ns
tPLH
CLK
MAX/MIN
8 37 8 31
ns
tPHL CLK MAX/MIN 8 34 8 31 ns
tPLH
D/U
RCO
8 45 8 37
ns
tPHL D/U RCO 10 36 10 28 ns
tPLH
D/U
MAX/MIN
8 35 8 25
ns
tPHL D/U MAX/MIN 8 30 8 25 ns
tPLH
CTEN
RCO
4 21 4 18
ns
tPHL
CTEN
RCO
4 23 4 18
ns
§For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SDAS210C − DECEMBER 1982 − REVISED JULY 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B) [0 V
VOH
VOL
[3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-86840012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8684001EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-8684001FA ACTIVE CFP W 16 1 TBD Call TI Call TI
SN54ALS191AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN74ALS191AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS191ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS191ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS191ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS191ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS191ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS191AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS191ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54ALS191AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54ALS191AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54ALS191AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS191A, SN74ALS191A :
•Catalog: SN74ALS191A
•Military: SN54ALS191A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS191ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS191ADR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2010
Pack Materials-Page 2
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