SDAS210C - DECEMBER 1982 - REVISED JULY 1996 D Single Down / Up Count-Control Line D Look-Ahead Circuitry Enhances Speed of SN54ALS191A . . . J PACKAGE SN74ALS191A . . . D OR N PACKAGE (TOP VIEW) Cascaded Counters D Fully Synchronous in Count Modes D Asynchronously Presettable With Load D B QB QA CTEN D/U QC QD GND Control Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLK RCO MAX/MIN LOAD C D description SN54ALS191A . . . FK PACKAGE (TOP VIEW) QB B NC VCC A The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. QA CTEN NC D/U QC 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 CLK RCO NC MAX/MIN LOAD QD GND NC D C The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, the counter counts down. 4 NC - No internal connection These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditions meeting the stable setup and hold times. These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1 SDAS210C - DECEMBER 1982 - REVISED JULY 1996 description (continued) Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output (RCO) produces a low-level output pulse under those same conditions, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count (MAX/MIN) output can be used to accomplish look ahead for high-speed operation. The SN54ALS191A is characterized for operation over the full military temperature range of -55C to 125C. The SN74ALS191A is characterized for operation from 0C to 70C. logic symbol CTEN D/U CLK LOAD A B C D 4 5 14 11 15 1 G1 CTRDIV16 M2 [DOWN] 2(CT=0)Z6 3(CT=15)Z6 M3 [UP] 1,2- / 1,3+ G4 6,1,4 13 MAX/MIN RCO C5 [1] 5D [2] 10 [4] 9 [8] This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 2 12 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 3 2 6 7 QA QB QC QD SDAS210C - DECEMBER 1982 - REVISED JULY 1996 logic diagram (positive logic) 12 CTEN D/U CLK LOAD A MAX/ MIN 4 13 RCO 5 14 11 15 3 S QA C1 1D R B 1 2 S QB C1 1D R C 10 6 S C1 QC 1D R D 9 7 S QD C1 1D R Pin numbers shown are for the D, J, and N packages. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 3 SDAS210C - DECEMBER 1982 - REVISED JULY 1996 typical load, count, and inhibit sequences The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 LOAD A B Data Inputs C D CLK D/U CTEN QA QB QC QD MAX/MIN RCO 13 14 15 0 1 2 2 Count Up 2 Inhibit Load 4 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1 0 15 14 Count Down 13 SDAS210C - DECEMBER 1982 - REVISED JULY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS191A . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C SN74ALS191A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS191A VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock Low-level output current tw Pulse duration tsu High-level input voltage NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 High-level output current th Hold time TA Operating free-air temperature 2 0 V -0.4 mA 20 0 20 16.5 25 20 Data before LOAD 25 20 CTEN before CLK 45 20 D/U before CLK 30 20 LOAD inactive before CLK 20 20 Data after LOAD 5 5 CTEN after CLK 0 0 0 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * V -0.4 LOAD low -55 V 0.8 CLK high or low D/U after CLK UNIT 0.7 4 Clock frequency Setup time SN74ALS191A MIN 8 mA 30 MHz ns ns ns 0 125 0 70 C 5 SDAS210C - DECEMBER 1982 - REVISED JULY 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54ALS191A TYP MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = - 18 mA IOH = - 0.4 mA VOL VCC = 4.5 V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V -1.5 VCC - 2 All others VCC = 5.5 V, UNIT -1.5 V 0.25 0.4 V 0.35 0.5 VCC - 2 0.25 0.4 0.2 CTEN or CLK IIL SN74ALS191A TYP MAX MIN VI = 0.4 V 0.1 mA A 20 20 -0.2 -0.2 -0.2 -0.1 mA IO VCC = 5.5 V, VO = 2.25 V -20 -112 -30 - 112 mA ICC VCC = 5.5 V, All inputs at 0 12 22 12 22 mA All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (OUTPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX SN54ALS191A MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH MAX 20 LOAD Any Q A, B, C, D Any Q CLK RCO CLK Any Q CLK MAX/MIN D/U RCO D/U MAX/MIN UNIT SN74ALS191A MIN MAX 30 MHz 7 37 7 30 8 34 8 30 3 25 3 21 4 25 4 21 5 24 5 20 5 25 5 20 3 26 3 18 3 22 3 18 8 37 8 31 8 34 8 31 8 45 8 37 10 36 10 28 8 35 8 25 8 30 8 25 4 21 4 CTEN RCO tPHL 4 23 4 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 18 tPHL tPLH tPHL tPLH 6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 18 ns ns ns ns ns ns ns ns SDAS210C - DECEMBER 1982 - REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point From Output Under Test LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ 3.5 V Input tPHZ 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output VOL 0.3 V 1.3 V 1.3 V VOL tPLH tPHL VOH 1.3 V 1.3 V [3.5 V 1.3 V tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOH Out-of-Phase Output (see Note C) 0.3 V [0 V 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 7 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 5962-86840012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-8684001EA ACTIVE CDIP J 16 1 TBD Call TI Call TI 5962-8684001FA ACTIVE CFP W 16 1 TBD Call TI Call TI SN54ALS191AJ ACTIVE CDIP J 16 1 TBD A42 SN74ALS191AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS191ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS191ADG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS191ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS191ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS191ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM N / A for Pkg Type SN74ALS191AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) SN74ALS191ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type SNJ54ALS191AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54ALS191AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type SNJ54ALS191AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN54ALS191A, SN74ALS191A : * Catalog: SN74ALS191A * Military: SN54ALS191A NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALS191ADR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS191ADR SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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