ispLSI® 2032VE Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue select devices
in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line Ordering Part Number Product Status Reference PCN
ispLSI 2032VE-110LJ44
ispLSI 2032VE-135LJ44
ispLSI 2032VE-180LJ44
ispLSI 2032VE-225LJ44
ispLSI 2032VE-110LT44
ispLSI 2032VE-135LT44
ispLSI 2032VE-180LT44
ispLSI 2032VE-225LT44
ispLSI 2032VE-300LT44
ispLSI 2032VE-180LT44I
ispLSI 2032VE-110LT48
ispLSI 2032VE-135LT48
ispLSI 2032VE-180LT48
ispLSI 2032VE-225LT48
ispLSI 2032VE-300LT48
Active / Orderable
ispLSI 2032VE-110LB49
ispLSI 2032VE-135LB49
ispLSI 2032VE-180LB49
ispLSI 2032VE-225LB49
ispLSI 2032VE-300LB49
Discontinued PCN#09-10
ispLSI 2032VE-110LTN44
ispLSI 2032VE-135LTN44
ispLSI 2032VE-180LTN44
ispLSI 2032VE-300LTN44
ispLSI 2032VE-180LTN44I
ispLSI 2032VE-110LTN48
ispLSI 2032VE-135LTN48
ispLSI 2032VE-180LTN48
ispLSI 2032VE
ispLSI 2032VE-300LTN48
Active / Orderable
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispLSI® 2032VE
3.3V In-System Programmable
High Density SuperFAST™ PLD
2032ve_11 1
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2032V Devices
• 3.3V LOW VOLTAGE 2032 ARCHITECTURE
— Interfaces With Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 300 MHz Maximum Operating Frequency
—tpd = 3.0 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability Using Boundary
Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Functional Block Diagram
Description
The ispLSI 2032VE is a High Density Programmable
Logic Device that can be used in both 3.3V and 5V
systems. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides
complete interconnectivity between all of these elements.
The ispLSI 2032VE features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VE offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 2032VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Lead-
Free
Package
Options
Available!
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2 GLB
Logic
Array
DQ
DQ
DQ
DQ
0139Bisp/2000
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
2
Functional Block Diagram
Figure 1. ispLSI 2032VE Functional Block Diagram
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. Device pins
can be safely driven to 5 Volt signal levels to support
mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORPs. Each
ispLSI 2032VE device contains one Megablock.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock
can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is the totem-pole configu-
ration. The open-drain/totem-pole option is selectable
through the Lattice design tools.
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
A7
A6
A5
A4
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
Note: *Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
TDI/IN 0
TDO/IN 1
I/O 4
I/O 5
Y0
Y1*
TCK/Y2
BSCAN
TMS/NC
0139B/2032VE
Generic Logic
Blocks (GLBs)
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
3
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature.............................. -65 to +150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
C
SYMBOL
Table 2-0006/2032VE
C
PARAMETER
I/O Capacitance 6
UNITSTYPICAL TEST CONDITIONS
1
2
8Dedicated Input Capacitance
pf
pf
V = 3.3V, V = 0.0V
V = 3.3V, V = 0.0V
CC
CC I/O
IN
CClock Capacitance 10
3
pf V = 3.3V, V = 0.0V
CC Y
TA = 0°C to + 70°C
TA = -40°C to + 85°C
SYMBOL
Table 2-0005/2032VE
VCC
VIH
VIL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
3.0
3.0
2.0
V – 0.5
3.6
3.6
5.25
0.8
V
V
V
V
SS
Commercial
Industrial
Erase Reprogram Specifications
Table 2-0008A/2032VE
PARAMETER MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 10,000 – Cycles
Capacitance (TA=25°C, f=1.0 MHz)
DC Recommended Operating Condition
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
4
Switching Test Conditions
Input Pulse Levels
Table 2-0003/2032VE
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
≤ 1.5 ns
Output Load Conditions (see Figure 2)
DC Electrical Characteristics
Over Recommended Operating Conditions
Figure 2. Test Load
+ 3.3V
R1
R2CL*
Device
Output
Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213A/2032VE
TEST CONDITION R1 R2 CL
A 316Ω348Ω35pF
B
∞
348Ω35pF
316Ω348Ω35pF
Active High
Active Low
C
316Ω348Ω5pF
∞
348Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004A/2032VE
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at V = 3.3V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to Power Consumption section
of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I .
5. Unused inputs at V = 0V.
Table 2-0007/2032VE
1
V
OH
I
IH
I
IL
I
IL-isp
PARAMETER
I
IL-PU
I
OS
2, 4, 5
I
CC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
V ≤ V ≤ 5.25V
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1MHz
OL
OH
IN IL
IN
IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
80-300/-225
0.4
–
10
-10
10
-150
-150
-100
V
V
μA
μA
μA
μA
μA
mA
mA
CC
IL
A
OUT
–
–Others mA–
65
CC
IN
CC
CC
(V - 0.2)V ≤ V ≤ V
CC
IN
CC
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
5
USE 2032VE-300 FOR
NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2032VE
v.0.1
1
3
2
1
tsu2 + tco1
( )
DESCRIPTION#PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass ns
tpd2 A 2 Data Propagation Delay ns
fmax A 3 Clock Frequency with Internal Feedback MHz
fmax (Ext.) – 4 Clock Frequency with External Feedback MHz
fmax (Tog.) – 5 Clock Frequency, Max. Toggle MHz
tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ns
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns
tsu2 – 9 GLB Reg. Setup Time before Clock ns
tco2 A 10 GLB Reg. Clock to Output Delay ns
th2 – 11 GLB Reg. Hold Time after Clock ns
tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass ns
trw1 – 13 Ext. Reset Pulse Duration ns
tptoeen B 14 Input to Output Enable ns
tptoedis C 15 Input to Output Disable ns
tgoeen B 16 Global OE Output Enable ns
tgoedis C 17 Global OE Output Disable ns
twh – 18 External Synchronous Clock Pulse Duration, High ns
twl – 19 External Synchronous Clock Pulse Duration, Low ns
-225
MIN. MAX.
– 4.0
–
225 –
–
–
–
–
0.0
3.5
–
0.0
–
3.5
–
–
–
–
2.0 –
2.0 –
154
250
2.5
3.0
–
–
4.0
–
5.0
–
7.0
7.0
3.5
3.5
6.0
-300
MIN. MAX.
– 3.0
–
300 –
–
–
–
–
0.0
2.8
–
0.0
–
3.0
–
–
–
–
1.5 –
1.5 –
208
333
2.0
2.0
–
–
2.5
–
4.5
–
5.0
5.0
3.0
3.0
4.5
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
6
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-135
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2032VE
v.0.1
1
3
2
1
tsu2 + tco1
( )
-110
MIN.MAX. MAX.
DESCRIPTION#PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns
t
pd2 A 2 Data Propagation Delay – – ns
f
max A 3 Clock Frequency with Internal Feedback 135 – 111 – MHz
f
max (Ext.) – 4 Clock Frequency with External Feedback – – MHz
f
max (Tog.) – 5 Clock Frequency, Max. Toggle – – MHz
t
su1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
t
co1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – – ns
t
h1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
t
su2 – 9 GLB Reg. Setup Time before Clock 5.5 – ns
t
co2 A 10 GLB Reg. Clock to Output Delay – – ns
t
h2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns
t
r1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass – – ns
t
rw1 – 13 Ext. Reset Pulse Duration 5.0 – ns
t
ptoeen B 14 Input to Output Enable – – ns
t
ptoedis C 15 Input to Output Disable – – ns
t
goeen B 16 Global OE Output Enable – – ns
t
goedis C 17 Global OE Output Disable – – ns
t
wh – 18 External Synchronous Clock Pulse Duration, High 3.0 – – ns
t
wl – 19 External Synchronous Clock Pulse Duration, Low 3.0 – – ns
100
167
4.0
4.5
–
–
5.5
–
9.0
–
12.0
12.0
6.0
6.0
10.0
77.0
125
5.5
0.0
7.5
0.0
6.5
4.0
4.0
13.0
5.0
6.5
12.5
14.5
14.5
7.0
7.0
-180
MIN. MAX.
– 5.0
–
180 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
118
200
3.0
0.0
4.0
0.0
4.0
2.5
2.5
7.5
4.0
5.0
6.0
10.0
10.0
5.0
5.0
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
7
USE 2032VE-300 FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032VE
v.0.1
Inputs
UNITSDESCRIPTION#2
PARAMETER
20 Input Buffer Delay ns
tdin 21 Dedicated Input Delay ns
tgrp 22 GRP Delay ns
GLB
t1ptxor 25 1 Product Term/XOR Path Delay ns
t20ptxor 26 20 Product Term/XOR Path Delay ns
txoradj 27 XOR Adjacent Path Delay ns
tgbp 28 GLB Register Bypass Delay ns
tgsu 29 GLB Register Setup Time before Clock ns
tgh 30 GLB Register Hold Time after Clock ns
tgco 31 GLB Register Clock to Output Delay ns
3
tgro 32 GLB Register Reset to Output Delay ns
tptre 33 GLB Product Term Reset to Register Delay ns
tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns
tptck 35 GLB Product Term Clock Delay ns
ORP
tob 38 Output Buffer Delay ns
tsl 39 Output Slew Limited Delay Adder ns
GRP
t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns
t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns
torp 36 ORP Delay ns
torpbp 37 ORP Bypass Delay ns
Outputs
toen 40 I/O Cell OE to Output Enabled ns
todis 41 I/O Cell OE to Output Disabled ns
tgoe 42 Global Output Enable ns
tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
tgr 45 Global Reset to GLB ns
Global Reset
-225
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
1.3
0.7
–
–
2.2
2.2
2.2
0.0
1.2
1.2
0.8
1.7
0.7
1.3
3.2
4.2
0.5 2.8
–
–
1.3
0.3
1.2
2.0
–
–
1.5
1.5
–2.0
0.8
1.0
0.8
1.0
–2.2
-300
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.4
1.0
0.6
–
–
1.9
1.9
1.9
0.0
0.9
1.1
0.5
1.5
0.3
1.3
2.5
3.0
0.4 2.3
–
–
0.6
0.1
1.0
2.0
–
–
1.0
1.0
–2.0
0.6
0.8
0.6
0.8
–2.1
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
8
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032VE
v.0.1
Inputs
UNITS
-135
MIN.
-110
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay – – 1.3 ns
t
din 21 Dedicated Input Delay – – 2.5 ns
t
grp 22 GRP Delay – – 1.2 ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay – – 5.4 ns
t
20ptxor 26 20 Product Term/XOR Path Delay – – 5.4 ns
t
xoradj 27 XOR Adjacent Path Delay – – 5.4 ns
t
gbp 28 GLB Register Bypass Delay – – 1.4 ns
t
gsu 29 GLB Register Setup Time before Clock – 1.4 – ns
t
gh 30 GLB Register Hold Time after Clock – 4.1 – ns
t
gco 31 GLB Register Clock to Output Delay – – 1.0 ns
3
t
gro 32 GLB Register Reset to Output Delay – – 2.7 ns
t
ptre 33 GLB Product Term Reset to Register Delay – – 7.1 ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay – – 8.6 ns
t
ptck 35 GLB Product Term Clock Delay 2.5 4.4 ns
ORP
t
ob 38 Output Buffer Delay – – 1.8 ns
t
sl 39 Output Slew Limited Delay Adder – – 2.0 ns
0.8
1.7
GRP
0.9
t
4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – – 4.8 ns
t
4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – – 3.4 ns
4.4
4.4
4.4
1.0
3.9
2.9
1.1
2.9
0.9
1.8
6.1
6.9
1.7 4.1
t
orp 36 ORP Delay – – 1.9 ns
t
orpbp 37 ORP Bypass Delay – – 0.9 ns
1.5
0.5
Outputs
1.4
2.0
t
oen 40 I/O Cell OE to Output Enabled – – 3.4 ns
t
odis 41 I/O Cell OE to Output Disabled – – 3.4 ns
3.4
3.4
t
goe 42 Global Output Enable – – 3.6 ns
2.6
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.7 1.8 1.8 ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.9 2.0 2.0 ns
Clocks
1.7
1.9
t
gr 45 Global Reset to GLB – – 7.1 ns
Global Reset
5.3
-180
MIN. MAX.
– 0.8
– 1.5
–0.7
– 3.1
– 3.1
– 3.1
– 0.2
0.9 –
2.1 –
– 0.8
– 1.3
– 4.0
– 5.7
1.4 3.6
– 1.3
–2.0
– 1.8
– 2.1
– 1.4
– 0.4
– 2.8
– 2.8
– 2.2
1.5 1.5
1.7 1.7
–3.0
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
9
ispLSI 2032VE Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0 #42
#40, 41
0491/2000
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of tsu, th and tco from the Product Term Clock
=
=
=
=
t
su
2.0ns
1.9ns
5.2ns
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.4 + 0.6 + 1.9) + (0.5) - (0.4 + 0.6 + 0.4)
=
=
=
=
t
h Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.4 + 0.6 + 2.3) + (1.5) - (0.4 + 0.6 + 1.9)
=
=
=
=
t
co Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.4 + 0.6 + 2.3) + (0.3) + (0.6 + 1.0)
Table 2-0042/2032VE
Note: Calculations are based on timing specifications for the ispLSI 2032VE-300L.
SELECT DEVICES
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Specifications ispLSI 2032VE
10
Power Consumption
Power consumption in the ispLSI 2032VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. Figure 3 shows the relationship between power
and operating speed.
Figure 3. Typical Device Power Consumption vs fmax
0127A/2032VE
ICC can be estimated for the ispLSI 2032VE using the following equation:
For ispLSI 2032VE-300 and -225: ICC(mA) = 4.5 + (# of PTs * 1.29) + (# of nets * Fmax * 0.0068)
For ispLSI 2032VE-180 and slower: ICC(mA) = 4.5 + (# of PTs * 1.05) + (# of nets * Fmax * 0.0068)
Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
Notes: Configuration of two 16-bit counters
Typical current at 3.3V, 25° C
ispLSI 2032VE-300 and -225
ispLSI 2032VE-180
and slower
75
125
025
50 75 100 125 150 175 200 225 250 275 300
f
max (MHz)
I
CC (mA)
150
100
25
50
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Specifications ispLSI 2032VE
11
Signal Descriptions
GOE 0 Global Output Enable input pin
Y0 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the
device.
RESET/Y1 This pin performs two functions: (1) Active Low (0) Reset pin which resets all of the registers in the
device. (2) Dedicated Clock input.
BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. (2) When BSCAN is high, it functions as a dedicated input
pin.
TMS/NC1Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, this pin is not to be connected to any
active signals, VCC or GND.
TDO/IN 1 Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
TCK/Y2 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a Dedicated Clock input.
GND Ground (GND)
VCC Vcc
NC1No Connect
I/O Input/Output pins – These are the general purpose I/O pins used by the logic array.
Signal Name Description
GOE 0 40 2 43 A4
Y0 5 11 5 C1
RESET/Y1 29 35 31 D7
BSCAN 7137D1
TDI/IN 0 8 14 8 E2
TMS/NC130 36 32 C6
TDO/IN 1 18 24 19 G4
TCK/Y2 27 33 29 E7
GND 17, 39 1, 23 18, 42 C4, E4
VCC 6, 28 12, 34 6, 30 D3, D5
NC1— — 12, 24, 36, 48 A1, A7, D4, G1, G7
Signal 44-Pin TQFP 44-Pin PLCC 48-Pin TQFP 49-Ball caBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
I/O Locations
Signal 44-Pin TQFP 44-Pin PLCC 48-Pin TQFP 49-Ball caBGA
I/O 0 - I/O 6 9, 10, 11, 12, 13, 14, 15 15, 16, 17, 18, 19, 20, 21 9, 10, 11, 13, 14, 15, 16 E1, F2, F1, E3, F3, G2, F4
I/O 7 - I/O 13 16, 19, 20, 21, 22, 23, 24 22, 25, 26, 27, 28, 29, 30 17, 20, 21, 22, 23, 25, 26 G3, F5, G5, F6, G6, E5, E6
I/O 14 - I/O 20 25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40, 41 27, 28, 33, 34, 35, 37, 38 F7, D6, C7, B6, B7, C5, B5
I/O 21 - I/O 27 36, 37, 38, 41, 42, 43, 44 42, 43, 44, 3, 4, 5, 6 39, 40, 41, 44, 45, 46, 47 A6, B4, A5, B3, A3, B2, A2
I/O 28 - I/O 31 1, 2, 3, 4 7, 8, 9, 10 1, 2, 3, 4 C3, C2, B1, D2
SELECT DEVICES
DISCONTINUED
Specifications ispLSI 2032VE
12
Pin Configuration
ispLSI 2032VE 44-Pin PLCC Pinout Diagram (0.5in Lead Pitch/0.65 x 0.65in Body Size)
Pin Configuration
ispLSI 2032VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/10.0 x 10.0mm Body Size)
I/O 18
I/O 17
I/O 16
TMS/NC1
RESET/Y1
VCC
TCK/Y2
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
TDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
7
8
9
10
12
11
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
18
5
19
4
20
3
21
2
22
1
23
44
24
43
25
42
26
41
27
40
28
1. NC pins are not to be connected to any active signals, VCC or GND.
ispLSI 2032VE
Top View
0123/2032VE
I/O 18
I/O 17
I/O 16
TMS/NC
1
RESET/Y1
VCC
TCK/Y2
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
TDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 2032VE
Top View
1
2
3
4
6
5
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
0851/2032VE
1. NC pins are not to be connected to any active signals, VCC or GND.
SELECT DEVICES
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Specifications ispLSI 2032VE
13
Signal Configuration
ispLSI 2032VE 49-Ball caBGA Signal Diagram (0.8mm Lead Pitch/7.0 x 7.0mm Body Size)
7654321
A
B
C
D
E
F
G
A
B
C
D
E
F
G
7654321
I/O
21
I/O
23
I/O
25
I/O
27 NC
1
NC
1
I/O
16
I/O
18
TMS/
NC
1
TCK/
Y2
I/O
19
I/O
29
I/O
28 Y0
GND
I/O
11
I/O
9
TDO/
IN1
I/O
5
I/O
7
1. NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
I/O
14
I/O
10
I/O
8
I/O
6
I/O
4
I/O
1
I/O
2
49-BGA/2032VE
RESET/
Y1
VCC VCC
I/O
15
I/O
31
NC
1
I/O
13
I/O
12
I/O
3
I/O
0
TDI/
IN0
GOE
0
BSCAN
I/O
22
I/O
20
I/O
17
I/O
24
I/O
26
I/O
30
NC
1
NC
1
GND
Bottom View
ispLSI 2032VE
Pin Configuration
ispLSI 2032VE 48-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/7.0 x 7.0mm Body Size)
I/O 18
I/O 17
I/O 16
TMS/NC2
RESET/Y11
VCC
TCK/Y21
I/O 15
I/O 14
I/O 13
I/O 12
I/O 28
I/O 29
I/O 30
I/O 31
Y0
VCC
BSCAN
1TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 27
I/O 26
I/O 25
I/O 24
GOE 0
GND
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1TDO/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
ispLSI 2032VE
Top View
1
2
3
4
6
5
7
8
9
10
11
35
34
33
32
31
30
29
28
27
26
25
47
13
46
14
45
15
44
16
43
17
42
18
41
19
40
20
39
21
38
22
37
23
48TQFP/2032VE
2NC 12
2NC
24
NC2
36
NC2
48
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
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Specifications ispLSI 2032VE
14
Part Number Description
ispLSI 2032VE Ordering Information
135 44-Pin TQFP7.5 ispLSI 2032VE-135LT44
135 48-Pin TQFP7.5 ispLSI 2032VE-135LT48
135 44-Pin PLCC7.5 ispLSI 2032VE-135LJ44
135 49-Ball caBGA7.5 ispLSI 2032VE-135LB49
110 10 44-Pin PLCCispLSI 2032VE-110LJ44
110 10 49-Ball caBGAispLSI 2032VE-110LB49
110 10 44-Pin TQFPispLSI 2032VE-110LT44
110 10 48-Pin TQFPispLSI 2032VE-110LT48
Table 2-0041A/2032VE
180 5.0 44-Pin PLCCispLSI 2032VE-180LJ44
180 5.0 49-Ball caBGAispLSI 2032VE-180LB49
ispLSI
180 44-Pin TQFP5.0 ispLSI 2032VE-180LT44
180 48-Pin TQFP5.0 ispLSI 2032VE-180LT48
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
225 44-Pin PLCC4.0 ispLSI 2032VE-225LJ44
225 49-Ball caBGA4.0 ispLSI 2032VE-225LB49*
225 44-Pin TQFP4.0 ispLSI 2032VE-225LT44*
225 48-Pin TQFP4.0 ispLSI 2032VE-225LT48*
300 49-Ball caBGA3.0 ispLSI 2032VE-300LB49
300 44-Pin TQFP3.0 ispLSI 2032VE-300LT44
300 48-Pin TQFP3.0 ispLSI 2032VE-300LT48
COMMERCIAL
*2032VE-300 recommended for new designs
Table 2-0041B/2032VE
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI 180 44-Pin TQFP5.0 ispLSI 2032VE-180LT44I
INDUSTRIAL
Conventional Packaging
Device Number
2032VE
ispLSI 2032VE – XXX X XXXX
Grade
Blank = Commercial
I = Industrial
X
Speed
300 = 300 MHz fmax
225 = 225 MHz fmax
180 = 180 MHz fmax
135 = 135 MHz fmax
110 = 110 MHz fmax
Power
L = Low
Package
T44 = 44-Pin TQFP
T48 = 48-Pin TQFP
J44 = 44-Pin PLCC
B49 = 49-Ball caBGA
TN44 = Lead-Free 44-Pin TQFP
TN48 = Lead-Free 48-Pin TQFP
Device Family
SELECT DEVICES
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Specifications ispLSI 2032VE
15
ispLSI 2032VE Ordering Information (Cont.)
Lead-Free Packaging
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI 180 Lead-Free 44-Pin TQFP5.0 ispLSI 2032VE-180LTN44I
INDUSTRIAL
ispLSI
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
110 Lead-Free 44-Pin TQFP10 ispLSI 2032VE-110LTN44
135 Lead-Free 44-Pin TQFP7.5 ispLSI 2032VE-135LTN44
300 Lead-Free 44-Pin TQFP3.0 ispLSI 2032VE-300LTN44
180 Lead-Free 44-Pin TQFP5.0 ispLSI 2032VE-180LTN44
COMMERCIAL
110 Lead-Free 48-Pin TQFP10 ispLSI 2032VE-110LTN48
135 Lead-Free 48-Pin TQFP7.5 ispLSI 2032VE-135LTN48
300 Lead-Free 48-Pin TQFP3.0 ispLSI 2032VE-300LTN48
180 Lead-Free 48-Pin TQFP5.0 ispLSI 2032VE-180LTN48
Revision History
Date Version
11
10
August 2006
—
Change Summary
Updated for 48-pin TQFP lead-free package option.
Previous Lattice release.
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