SMP100LC TrisilTM for telecom equipment protection Features Bidirectional crowbar protection Voltage range from 8 V to 400 V Low capacitance from 20 pF to 45 pF @ 2 V Low leakage current: IR = 2 A max Holding current: IH = 150 mA min. Repetitive peak pulse current: IPP = 100 A (10/1000 s) SMB (JEDEC DO-214AA) Benefits Trisils are not subject to ageing and provide a fail safe mode in short circuit for better protection. Helps equipment meet main standards such as UL60950, IEC 950 / CSA C22.2 and UL1459. Epoxy meets UL94, V0. Package is JEDEC registered (DO-214AA). Description Complies with the following standards GR-1089 Core ITU-T-K20/K21 IEC 61000-4-5 IEC 61000-4-2 level 4 TIA/EIA IS-968 UL497B recognized, UL file E136224 The SMP100LC is a series of low capacitance transient surge arrestors designed for the protection of high data rate communication equipment. The low capacitance of the devices avoids any distortion of the signal and is compatible with digital transmission line cards (xDSL, ISDN...). SMP100LC series tested and confirmed compatible with Cooper Bussmann Telecom Circuit Protector TCP 1.25A. Applications Any sensitive equipment requiring protection against lightning strikes and AC power faults. These devices are dedicated to central office protection as they comply with the most stressful standards. Their low capacitances make them suitable for xDSL. The SMP100LC-xxx with the fuse TCP1.25A or TCP2A is compliant with Telcordia GR1089 (lightning and AC power fault tests), ITU-T K20/K21 (lightning and AC power fault tests), TIA/EIA-IS-968 (formerly FCC Part 68 lightning tests), and UL60950 (AC power fault tests). The use of the TCP1.25A allows the SMP100LC-xxx to be safe for the 2nd level (B criteria) AC power fault tests. TM: Trisil is a trademark of STMicroelectronics February 2012 Doc ID 7050 Rev 14 1/13 www.st.com 13 Characteristics 1 SMP100LC Characteristics Table 1. 2/13 In compliance with the following standards Standard Peak surge voltage (V) GR-1089 Core First level Required Waveform peak current voltage (A) Current waveform Minimum serial resistor to meet standard () 2500 1000 2/10 s 10/1000 s 500 100 2/10 s 10/1000 s 0 0 GR-1089 Core Second level 5000 2/10 s 500 2/10 s 0 GR-1089 Core Intra-building 1500 2/10 s 100 2/10 s 0 ITU-T-K20/K21 6000 1500 10/700 s 150 37.5 5/310 s 0 0 ITU-T-K20 (IEC61000-4-2) 8000 15000 1/60 ns ESD contact discharge ESD air discharge 0 0 IEC61000-4-5 4000 4000 10/700 s 1.2/50 s 100 100 5/310 s 8/20 s 0 0 TIA/EIA IS-968, lightning surge type A 1500 800 10/160 s 10/560 s 200 100 10/160 s 10/560 s 0 0 TIA/EIA IS-968, lightning surge type B 1000 9/720 s 25 5/320 s 0 Doc ID 7050 Rev 14 SMP100LC Characteristics Table 2. Absolute ratings (Tamb = 25 C) Symbol Parameter Value Unit 100 400 140 150 200 400 500 A IPP Repetitive peak pulse current (see Figure 2) 10/1000 s 8/20 s 10/560 s 5/310 s 10/160 s 1/20 s 2/10 s IFS Fail-safe mode: maximum current (1) 8/20 s 5 kA t = 0.2 s t=1s t=2s t = 15 mn 24 15 12 4 A t = 16.6 ms t = 20 ms 20 21 A2s ITSM I2t Tstg Non repetitive surge peak on-state current (sinusoidal) I2t value for fusing Storage temperature range -55 to 150 Tj Operating junction temperature range -40 to 150 TL Maximum lead temperature for soldering during 10 s. C 260 C Value Unit 1. In fail safe mode, the device acts as a short circuit. Table 3. Thermal resistances Symbol Parameter Rth(j-a) Junction to ambient (with recommended footprint) 100 C/W Rth(j-l) Junction to leads 20 C/W Figure 1. Electrical characteristics - definitions (Tamb = 25 C) Symbol VRM VBO IRM IPP IBO IH VR IR C Parameter Stand-off voltage Breakover voltage Leakage current Peak pulse current Breakover current Holding current Continuous reverse voltage Leakage current at VR Capacitance Doc ID 7050 Rev 14 IPP I IBO IH IRM V VRM VR VBO 3/13 Characteristics SMP100LC Table 4. Electrical characteristics - values (Tamb = 25 C) IRM @ VRM Order code max. A IR @ VR Static Dynamic VBO (1) VBO @ IBO (2) max. V A C(4) C(5) max. max. max. min. typ. typ. V V V mA mA pF pF 50 (typ.) NA 75 SMP100LC-8 6 8 25 15 SMP100LC-25 22 25 40 35 NA 65 SMP100LC-35 32 35 55 55 NA 55 SMP100LC-65 55 65 85 85 45 90 SMP100LC-90 81 90 120 125 40 80 SMP100LC-120 108 120 155 150 35 75 140 180 175 30 65 30 65 SMP100LC-140 2 126 5 800 150 SMP100LC-160 144 160 205 200 SMP100LC-200 180 200 255 250 30 60 SMP100LC-230 207 230 295 285 30 60 SMP100LC-270 243 270 345 335 30 60 SMP100LC-320 290 320 400 390 25 50 SMP100LC-360 325 360 460 450 25 50 SMP100LC-400 360 400 540 530 20 45 1. See Figure 16: Test circuit 1 for Dynamic IBO and VBO parameters 2. See Figure 17: Test circuit 2 for IBO and VBO parameters 3. See Figure 18: Test circuit 3 for dynamic IH parameter 4. VR = 50 V bias, VRMS =1 V, F = 1 MHz 5. VR = 2V bias, VRMS =1 V, F = 1 MHz 4/13 IH (3) Doc ID 7050 Rev 14 SMP100LC Figure 2. Characteristics Pulse waveform %IPP Figure 3. ITSM(A) Repetitive peak pulse current 70 tr = rise time (s) tp = pulse duration time (s) 100 Non repetitive surge peak on-state current versus overload duration F=50Hz Tj initial = 25C 60 50 40 50 30 20 10 0 tr Figure 4. t(s) t tp 0 1E-2 On-state voltage versus on-state current (typical values) 1E-1 Figure 5. IT(A) 1E+0 1E+1 1E+2 1E+3 Relative variation of holding current versus junction temperature IH[Tj] / IH[Tj=25C] 100 2.0 Tj initial = 25C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 VT(V) Tj(C) 0.0 10 -25 0 1 Figure 6. 2 3 4 5 6 7 0 25 50 75 100 125 8 Relative variation of breakover voltage versus junction temperature Figure 7. VBO[Tj] / VBO[Tj=25C] Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj=25C] 1.08 2000 1000 1.06 1.04 100 1.02 1.00 10 0.98 Tj(C) Tj(C) 1 0.96 -25 0 25 50 75 100 125 25 Doc ID 7050 Rev 14 50 75 100 125 5/13 Application information Figure 8. SMP100LC Variation of thermal impedance junction to ambient versus pulse duration Figure 9. Relative variation of junction capacitance versus reverse voltage applied (typical values) C [VR] / C [VR=2V] Zth(j-a)/Rth(j-a) 1 1.4 Printed circuit board - FR4, copper thickness = 35m, recommended pad layout F =1MHz VRMS = 1V Tj = 25C 1.2 1.0 0.8 0.1 0.6 0.4 0.2 tp(s) VR(V) 0.01 1E-3 2 0.0 1E-2 1E-1 1E+0 1E+1 1E+2 1 5E+2 5 2 10 20 50 100 300 Application information In wire line applications, analog or digital, both central office and subscriber sides have to be protected. This function is assumed by a combined series / parallel protection stage. Figure 10. Examples of protection stages for line cards Line Ex. Analog line card Protection stage Line Protection stage Ring relay Ex. xDSL line card or terminal In such a stage, parallel function is assumed by one or several Trisil, and is used to protect against short duration surge (lightning). During this kind of surges the Trisil limits the voltage across the device to be protected at its break over value and then fires. The fuse assumes the series function, and is used to protect the module against long duration or very high current mains disturbances (50/60Hz). It acts by safe circuit opening. Lightning surge and mains disturbance surges are defined by standards like GR1089, TIA/EIA IS-968, ITU-T K20. Figure 11. Typical circuits Fuse TCP 1.25A Tip L Tip S Fuse TCP 1.25A SMP100LC-xxx T1 SMP100LC-xxx Gnd Gnd SMP100LC-xxx T2 Fuse TCP 1.25A Ring L Typical circuit for subscriber side 6/13 Doc ID 7050 Rev 14 Ring S Typical circuit for central office side SMP100LC Application information Figure 12. Test method of the board with fuse and Trisil I surge Surge Generator Line side Device to be protected Test board V Oscilloscope Current probe Voltage probe These topologies, using SMP100LC from ST and TCP1.25A from Cooper Bussmann, have been functionally validated with a Trisil glued on the PCB. Following example was performed with SMP100LC-270 Trisil. For more information, see Application Note AN2064. Figure 13. Trisil turns on during lightning strike I surge (100A/div) V (50V/div) Test conditions: 2/10 s + and - 2.5 and 5 kV, 500 A (10 pulses of each polarity), Tamb = 25 C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements. Doc ID 7050 Rev 14 7/13 Application information SMP100LC Figure 14. Trisil action while fuse remains operational I surge (2A/div) V (100V/div) Test conditions: 600 V, 3 A, 1.1 s (first level), Tamb = 25 C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements. Figure 15. High current AC power test: the fuse acts like a switch by opening the circuit I surge (10A/div) V (100V/div) Test conditions: 277 V, 25 A (second level), Tamb = 25 C Test result: Fuse safely opened and Trisil OK after test in accordance with GR1089 requirements. 8/13 Doc ID 7050 Rev 14 SMP100LC Application information Figure 16. Test circuit 1 for Dynamic IBO and VBO parameters 100 V / s, di /dt < 10 A / s, Ipp = 100 A 2 83 45 10 F U 66 46 H 0.36 nF 470 KeyTek 'System 2' generator with PN246I module 1 kV / s, di /dt < 10 A / s, Ipp = 10 A 250 26 H 60 F U 47 46 H 12 KeyTek 'System 2' generator with PN246I module Figure 17. Test circuit 2 for IBO and VBO parameters K ton = 20ms R1 = 140 R2 = 240 220V 50Hz DUT Vout VBO measurement 1/4 IBO measurement TEST PROCEDURE Pulse test duration (tp = 20ms): for Bidirectional devices = Switch K is closed for Unidirectional devices = Switch K is open VOUT selection: Device with VBO < 200V VOUT = 250 VRMS, R1 = 140 Device with VBO 200V VOUT = 480 VRMS, R2 = 240 Doc ID 7050 Rev 14 9/13 Ordering information scheme SMP100LC Figure 18. Test circuit 3 for dynamic IH parameter R Surge generator D.U.T VBAT = - 48 V This is a GO-NOGO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE 1/ Adjust the current level at the IH value by short circuiting the AK of the D.U.T. 2/ Fire the D.U.T. with a surge current IPP = 10A, 10/1000s. 3/ The D.U.T. will come back off-state within 50ms maximum. 3 Ordering information scheme Figure 19. Ordering information scheme SMP Trisil surface mount Repetitive peak pulse current 100 = 100 A Capacitance LC = Low capacitance Voltage 65 = 65 V 10/13 Doc ID 7050 Rev 14 100 LC - xxx SMP100LC 4 Package information Package information Epoxy meets UL94, V0 Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Table 5. SMB dimensions Dimensions Ref. Millimeters Inches E1 D Min. Max. Min. Max. A1 1.90 2.45 0.075 0.096 A2 0.05 0.20 0.002 0.008 b 1.95 2.20 0.077 0.087 c 0.15 0.40 0.006 0.016 E 5.10 5.60 0.201 0.220 E1 4.05 4.60 0.159 0.181 D 3.30 3.95 0.130 0.156 L 0.75 1.50 0.030 0.059 E A1 A2 C L b Figure 20. Footprint dimensions in mm (inches) 1.62 2.60 (0.064) (0.102) Figure 21. Marking layout(1) 1.62 (0.064) Cathode bar ( unidirectional devices only ) 2.18 (0.086) 5.84 (0.23) e x x x z y ww e: ECOPACK compliance XXX: Marking Z: Manufacturing location Y: Year WW: week 1. Marking layout can vary according to assembly location. Doc ID 7050 Rev 14 11/13 Ordering information 5 SMP100LC Ordering information Table 6. Ordering information Order code 6 SMP100LC-8 PL8 SMP100LC-25 L25 SMP100LC-35 L35 SMP100LC-65 L06 SMP100LC-90 L09 SMP100LC-120 L12 SMP100LC-140 L14 SMP100LC-160 L16 SMP100LC-200 L20 SMP100LC-230 L23 SMP100LC-270 L27 SMP100LC-320 L32 SMP100LC-360 L36 SMP100LC-400 L40 Package Weight Base qty Delivery mode SMB 98 mg 2500 Tape and reel Revision history Table 7. 12/13 Marking Document revision history Date Revision Changes 09-Nov-2004 9 Absolute ratings values, table 3 on page 2, updated. 07-Dec-2004 10 SMP100LC-320, SMP100LC-360 and SMP100LC-400 addition. 20-Jun-2005 11 Telecom Circuit Protector added in Description. 05-Mar-2007 12 Reformatted to current standards. SMB Package information updated. Standards compliance paragraphs added to Description. 05-Jan-2010 13 Corrected vertical axis labelling in Figure 8. 09-Feb-2012 14 Added UL statement in Complies with the following standards. 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