Data Sheet
No vember 2001
L9217A/G Low-Cost Line Interface
with Reverse Battery and PPM
Features
■Basic forward/reverse battery SLIC functionality at
a low cost
■Pin compatible with Agere Systems Inc. L9218/
L9219 SLIC
■Low active power (typical 154 mW during on-hook
transmission)
■Low-power scan mode for low-power, on-hook
power dissipation (57 mW typical)
■Distortion-free, on-hook transmission
■Convenient operating states:
— Forward powerup
— Reverse powerup
— Low-power scan
— Disconnect (high impedance)
— PPM operational states
■Minimal external components required
■Two gain options to optimize the codec interface
■Adjustable sup ervision functions:
— Off-hook detector with hysteresis
— Ring trip detector
■Adjustable loop current limit
■Adjustable overhead voltage
■Ramped rate of battery reversal
■Periodic pulse metering (PPM) compatible
■Thermal protection with thermal shutdown indica-
tion
Description
This general-purpose electronic subscriber loop
interface circuit (SLIC) is optimized for low cost, while
still providing a satisfactory set of features. This part
is a pin-for-pin replacement for the Agere L9218/
L9219 SLIC.
The L9217 requires a 5 V power supply and single
battery to operate. This device offers forward and
reverse battery operation. The rate of battery rever-
sal may be ramped to meet international require-
ments. Additionally , a low-power scan mode, wherein
all circuitry except the off-hook supervision is shut
down to conserve power, is available.
The dc current limit may be programmed via a single
external resistor. Both the loop supervision and ring
trip supervision functions are offered with user-
controlled thresholds via external resistors. Over-
head is adequate for 3.14 dBm into 900 Ω of on-hook
transmission.
The device is periodic pulse metering (PPM) compat-
ible, offering a convenient point for meter pulse injec-
tion and filter point for rejection of the meter pulse
signal. In the PPM active modes, overhead voltage is
automatically increased to accommodate on-hook
transmission of meter pulse signals. The level that
the overhead is increased to is set by a single exter-
nal resistor . In this way , the L9217 can accommodate
high-voltage meter pulse signals.
The L9217 is offered with a receive gain that is opti-
mized to interface to a first-generation type codec
(L9217A). It is also offered with a gain option that is
optimized to interface to a third- or fourth-generation
type codec (L9217G). In both cases, minimizing
external components is required at this interface.
Data control is via a parallel data control scheme.
The device is available in a 28-pin PLCC package. It
is built by using a 90 V complementary bipolar
(CBIC) pr oces s.
2Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Features ......................................................................1
Description...................................................................1
Pin Information ............................................................4
Functional Description.................................................6
Absolute Maximum Ratings (at TA = 25 °C)................7
Recommen ded Oper ating Cond iti ons ... ....... ...... ....... .. 7
Electrical Characteristics.............................................8
Ring Trip Requirements..........................................12
Test Configurations ...................................................13
Applications...............................................................15
dc Applications........................................................19
Battery Feed.........................................................19
Overhead Voltage ................................................19
Rate of Battery Reversal......................................20
Loop Range..........................................................20
Off-Hook Detection...............................................20
Ring Trip Detection...............................................21
Longitudinal Balance...............................................21
Periodic Pulse Metering (PPM)...............................22
ac Design................................................................23
Codec Types........................................................23
ac Interface Network ........................ ....... ...... .......23
Receive Interface .................................................23
Examp le 1: Real Termination (Fi rst-
Generation Codec)...............................................24
Example 2: Complex Termination (First-
Generation Codec)...............................................26
Power Derating .......................................................28
Pin-for-Pin Compatibility with L9218/L9219............28
PCB Layout Information ............................................28
Outline Diagram.........................................................29
28-Pin PLCC.............. ...... ...... ....... ...... .................... 29
Ordering Information..................................................30
Figures Page
Figure 1. Functional Diagram...................................3
Figure 2. 28-Pin PLCC.............................................4
Figure 3. Ring Trip Circuits....................................12
Figure 4. L9217 Basic Test Circuit.........................13
Figure 5. Metallic PSRR.........................................13
Figure 6. Longitudinal PSRR .................................13
Figure 7. Longitudinal Balance ..............................14
Figure 8. RFI Rejection..........................................14
Figure 9. Longitudinal Impedance..........................14
Figure 10. ac Gains..................................................14
Figure 11. Basic Loop Start Application
Circuit Using T7504-Type Codec............15
Figure 12. Basic Loop Start Application
Circuit Using T8536-Type Codec............17
Figure 13. Loop Current vs. Loop Voltage.............. 19
Figure 14. Off-Hook Detection Circuit..................... 20
Figure 15. Ring Trip Equivalent Circuit
and Equivalent Application .................... 21
Figure 16. ac Equivalent Circuit.............................. 24
Figure 17. Interface Circuit Using First-
Generation Codec (±5 V Codec) ........... 27
Figure 18. Interface Circuit Using First-
Generation Codec (5 V Only Codec)..... 27
Tables Page
Table 1. Pin Descriptions ..................................... 4
Table 2. Input State Coding .................................. 6
Table 3. Supervision Coding ................................. 6
Table 4. Power Supply .......................................... 8
Table 5. 2-Wire Port .............................................. 9
Table 6. Analog Pin Characteristics .................... 10
Table 7. PPM ...................................................... 10
Table 8. ac Feed Characteristics ........................ 11
Table 9. Logic Inputs and Outputs ...................... 12
Table 10. Parts List for Loop Start Application
Circuit Using T7504-Type Codec .......... 16
Table 11. 900 W Termination, 850 W + 50 nF
Hybrid First -Gen er ation C ode c Desi gn
Parameters ........................................... 17
Table 12. Parts List for Loop Start Application
Circuit Using T8536-Type Codec .......... 18
Table 13. FB1/FB2 Values vs. Typical Ramp
Time ...................................................... 20
Table of Contents
Contents Page Figures Page
Agere Systems Inc. 3
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Description (continued)
Figure 1. Functional Diagram
–
+
–
+
+
–
A = 1
A = –1
POWER CONDITIONING AND REFERENCE
BGND
AGND
IPROG
VCC
CF2
PT
PR
RTSN
RTSP
LCTH
RING TRIP DETECTOR
LOOP CLOSURE DETECTOR
BATTERY FEED
STATE CONTROL
B0
RCVP
RCVN
B1
NSTAT
FB2
+
+
–
–
TIP/RING
CURRENT
SENSE
B2
A VERSION GAIN = 3.93
G VERSION GAIN = 1
FORWARD AND REVERSE BATTERY
DCOUT
VTX
TG
TXI
VITR
–
+AX
RECTIFIER 3
AAC
β = 9.66
β = 41 V/A
CF1
FB1
PPMOUT
PPMIN
OVH
β = 5
PPM
12-3557 (F)
4Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Pin Information
Figure 2. 28-Pin PLCC
Table 1. Pin Descriptions
PLCC Symbol Type Description
1 IPROG ICurrent-Limit Program Input. A resistor to DCOUT sets the dc current limit of the
device.
2FB2 —Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of bat-
tery reversal.
3FB1 —Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of bat-
tery reversal.
4 VCC —5 V Power Supply.
5RCVP IReceive ac Signal Input (Noninverting). This high-impedance input controls the ac
differential volta ge on tip and ring.
6RCVN IReceive ac Signal Input (Inverting). This high-impedance input controls the ac differ-
ential voltage on tip and ring.
VTX
TXI
VITR
NSTAT
PPMIN
RTSP
RCVN
DCOUT
VBAT
PR
5
6
7
8
9
10
11
42128273
12 14 15 16 17 1813
25
24
23
22
21
20
19
IPROG
B0
CF1
PT
BGND
B1
B2
AGND
28-PIN PLCC
LCTH
RCVP
CF2 RTSN
OVH
PPMOUT
FB2
FB1
VCC
26
TG
28-PIN PLCC
12-3558 (F).c
Agere Systems Inc. 5
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Pin Information (continued)
Table 1. Pin Descriptions (continued)
PLCC Symbol Type Description
7LCTH ILoop Closure Threshold Input. Connect a resistor to DCOUT to set off-hook
threshold.
8DCOUT Odc Output Voltage. This output is a voltage that is directly proportional to the abso-
lute value of the differential tip/ring current.
9 VBAT —Battery Supply. Negative high-voltage power supply.
10 PR I/O Protected Ring. The output of the ring driver amplifier and input to loop sensing cir-
cuitry. Connect to the loop through overvoltage protection.
11 CF2 —Filter Capacitor 2. Connect a 0.1 µF capacitor from this pin to AGND.
12 CF1 —Filter Capacitor 1. Connect a 0.47 µF capacitor from this pin to pin CF2.
13 B2 IState Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B2 has internal pull-down.
14 B1 IState Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B1 has internal pull-down.
15 B0 IState Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2.
Pin B0 has internal pull-down.
16 AGND —Analog Signal Ground.
17 BGND —Battery Ground. Ground return for the battery supply.
18 PT I/O Protected Tip. The output of the tip driver amplifier and input to loop sensing cir-
cuitry. Connect to loop through overvoltage protection.
19 RTSN IRing Trip Sense Negative. Connect this pin to the ringing generator signal through a
high-value resistor.
20 RTSP IRing Trip Sense Positive. Connect this pin to the ring relay and the ringer series
resistor through a high-value resistor.
21 PPMIN IReceive PPM Signal Input. This high-impedance input controls the PPM differential
voltage on tip and ring. The PPM signal may be present at this pin at all times: how-
ever, PPM will only be transmitted to tip and ring if the appropriate PPM state is cho-
sen. ac couple the PPM signal to this node.
22 NSTAT ORing Trip Detector Output/Loop Detector Output. When low, this logic output indi-
cates that ringing is tripped or that an off-hook condition exists.
23 VITR Oac Output Voltage. The voltage at this point is directly proportional to the differential
tip/ ring cu rren t.
24 TXI Iac/dc Separation. Connect a 0.1 µF capacitor from this point to VTX.
25 VTX Oac Output Voltage. This output is a voltage that is directly proportional to the differ-
ential tip/ring current.
26 TG —Transmit Gain. Connect an 8.06 kΩ from TG to VTX to set the transmit gain of the
SLIC.
27 OVH IPPM Over head . Connect a resistor from this node to ground to set the overhead volt-
age during PPM high overhead modes.
28 PPMOUT OPPM Signal Output. Connect a resistor from this node to TG for hybrid cancellation
of the periodic pulse metering (PPM) signal.
6Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Functional Description
Table 2. Input State Coding
Table 3. Supervision Coding
B0 B1 B2 State/Definition
111Powerup, Forward Battery, Normal Overhead. Normal talk and battery feed state. Pin PT is
positive with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is un-
affected by resistor OVH and is adequate for 3.14 dBm overload into 900 Ω.
101Powerup, Reverse Battery, Normal Overhead. Normal talk and battery feed state. Pin PT is
negative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is un-
affected by resistor OVH and is adequate for 3.14 dBm overload into 900 Ω.
110Powerup, Forward Battery, High Overhead. Normal talk and battery feed state. Pin PT is posi-
tive with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is in-
creased via resistor OVH.
100Powerup, Reverse Battery, High Overhead. Normal talk and battery feed state. Pin PT is neg-
ative with respect to PR. On-hook transmission is enabled. PPM is not active. Overhead is in-
creased via resistor OVH.
011Low-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin
PT is positive with respect to pin PR. On-hook transmission is disabled.
001Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance
state (>100 kΩ). Supervision outputs read on hook. Device will power up in this state.
000Powerup, Reverse Battery, High Overhead with PPM. Normal talk and battery feed state. Pin
PT is negative with respect to PR. On-hook transmission is enabled. PPM is active. Overhead is
increased via resistor OVH.
010Powerup, Forward Battery, High Overhead with PPM. Normal talk and battery feed state. Pin
PT is positive with respect to PR. On-hook transmission is enabled. PPM is active. Overhead is
increased via resistor OVH.
NSTAT
0 = off-hook or ring trip.
1 = on-hook and no ring trip.
Agere Systems Inc. 7
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Absolute Maximum Ratings (at TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. Some of the known examples of conditions that cause such potentials during powerup are the following:
1. An inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters.
2. Inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
5 V Power Supply VCC — — 7.0 V
Battery (Talking) Supply VBAT — — –75 V
Logic Input Voltage —–0.5 —7.0 V
Analog Input Voltage —–7.0 —7.0 V
Maximum Junction Temperature TJ150 — — °C
Storage Temperature Range Tstg –40 —125 °C
Relative Humidity Range RH5 — 95 %
Ground Potential Difference (BGND to AGND) — — ±3 — V
PT or PR Fault Voltage (dc) VPT, VPR VBAT – 5 — 3 V
PT or PR Fault Voltage (10 x 1000 µs) VPT, VPR VBAT – 15 —15 V
Current into Ring Trip Inputs IRTSP, IRTSN —±240 —µA
Parameter Min Typ Max Unit
Ambient Temperature –40 —85 °C
VCC Supply Voltage 4.75 5.0 5.25 V
VBAT Supply Voltage –24 –48 –70 V
8Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics
Minimum and maximum values are testing requirements in the temperature range of 25 °C to 85 °C and battery
range of –24 V to –70 V. These minimum and maximum values are guaranteed to –40 °C based on component
simulations and design verification of samples, but devices are not tested to –40 °C in production. The test circuit
shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device.
Typical values are characteristics of the device design at 25 °C based on engineering evaluations and are not part
of the test requirements. Supply values used for typical characterization are VCC = 5.0 V, VBAT = –48 V, unless oth-
erwise note d.
Table 4. Power Supply
1. T his parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
Parameter Min Typ Max Unit
Power Supply—Powerup, No Loop Current:
ICC
IBAT (VBAT = –48 V)
Power Dissipation (VBAT = –48 V)
—
—
—
5.2
–2.66
154
6.5
–2.95
175
mA
mA
mW
Power Supply—Scan, No Loop Current:
ICC
IBAT (VBAT = –48 V)
Power Dissipation (VBAT = –48 V)
—
—
—
3.4
–0.9
57
4.3
–1
70
mA
mA
mW
Power Supply—Disconnect, No Loop Current:
ICC
IBAT (VBAT = –48 V)
Power Dissipation (VBAT = –48 V)
—
—
—
1.9
–0.1
14
—
—
—
mA
mA
mW
Power Supply Rejection 500 Hz to 3 kHz
(See Figures 5, 6, 16, and 17.)1:
VCC
VBAT
30
36 —
——
—dB
dB
Thermal Protection Shutdown (Tjc)1150 165 —°C
Thermal Resistance Still Air, Junction to Ambient (θJA)1, 2:
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
—
—
—
—
30
43
27
36
—
—
—
—
°C/W
°C/W
°C/W
°C/W
Agere Systems Inc. 9
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Table 5. 2-Wire Port
1. The longitudinal current is independent of dc loop current.
2. Current-limit ILIM is programmed by a resistor , R PROG, from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting
begins (see Figure 13).
3. This parameter is not tested in production. It is guaranteed by design and device characterization.
4. Specification is reduced to |VBAT1 + 10.5 V| minimum when VBAT1 = –70 V at 85 °C.
5. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. More information is available in
the Applications section of this document.
Parameter Min Typ Max Unit
Tip or Ring Drive Current = dc + Longitudinal + Signal
Currents 80 — — mA
Signal Current 15 — — mArms
Longitudinal Current Capability per Wire18.5 15 —mArms
dc Loop Current Limit2:
Allowed Range Including Tolerance3
Accuracy (RLOOP = 100 Ω, VBAT = –48 V) 15
——
±545
—mA
%
Powerup Open Loop Voltage Levels (PPMOFF):
Common-mode Voltage
Differential Voltage VBAT = –48 V4 (Gain = 2)
Differential Voltage VBAT = – 48 V4 (Gain = 7.86)
—
|VBAT + 7.5|
|VBAT + 8.0|
VBAT/2
|VBAT + 6.5|
|VBAT + 6.5|
—
|VBAT + 5.9|
|VBAT + 5.9|
V
V
V
Powerup Open Loop Voltage Levels (PPMON)
Minimum Programmed Overhead:
Differential Voltage VBAT = –48 V (Gain = 7.86) — — |VBAT + 18.6 7| V
Disconnect State:
Leakage —10 150 µA
dc Feed Resistance (for ILOOP below regulation level)
(does not include protection resistor) —72 100 Ω
Loop Resistance Range (–3.17 dBm overload into
900 Ω; not including protection):
ILOOP = 20 mA at VBAT = –48 V 1800 — — Ω
Longitudinal to Metallic Balance—
IEEE
® Std. 455
(See Figure 7.)5:
200 Hz to 3400 Hz 58 61 —dB
Metallic to Longitudinal Balance (open loop):
200 Hz to 4 kHz 40 — — dB
RFI Rejection (See Figure 8.)3, 0.5 Vrms, 50 Ω Source,
30% AM Mod 1 kHz:
500 kHz to 100 MHz —
——
–55 —
–45 —
dBV
10 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Table 6. Analog Pin Characteristics
1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT. The programming equation or relationship between
off-hook threshold and resistor value is different for active mode versus scan mode (see Applications section for more details).
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. IN is the sourcing current at RTSN. Guaranteed if IN is within 5 µA to 30 µA.
Table 7. PPM
* PPM signal should be ac-coupled into PPMIN.
Parameter Min Typ Max Unit
Differential PT/PR Current Sense (DCOUT):
Gain (PT/PR to DCOUT)
Offset Voltage at ILOOP = 0 121
–100 125
—129
100 V/A
mV
Loop Closure Detector Threshold (RLCTH = 22.1 kΩ)1:
On- to Off-hook Threshold (scan mode)
Off- to On-hook Threshold (active mode) 8.8
6.0 —
—13.6
10.2 mA
mA
Ring Trip Comparator:
Input Offset Voltage2
Internal Voltage Source
Current at Input RTSP3
—
–9.1
IN – 0.5
±10
–8.6
IN
—
–8.1
IN + 0.5
mV
V
µA
RCVN, RCVP:
Input Bias Current
Input Resistance —
—–0.2
1–1
—µA
MΩ
Parameter Min Typ Max Unit
PPM S ourc e*:
Frequency (f1)
Frequency (f2)
Input Signal
11.88
15.80
0
12
16
—
12.12
16.20
0.525
kHz
kHz
Vrms
Signal Gain (from PPMIN to amplifier outputs) 9 10 11 —
Harmoni c Distor ti on — 5 — %
Isolation 50 — — dB
Agere Systems Inc. 11
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Table 8 . ac Feed Char acterist ics
1. Wit h a first-generation codec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 Ω and
1300 Ω can be synthesized. With a third-generation codec, this parameter is set by a codec or by a combination of a codec and an external
network.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. Use this gain option with an Agere first-generation or third-generation codec.
4. Use this gain option with an Agere third-generation codec.
Parameter Min Typ Max Unit
ac Termination Impedance1150 —1300 Ω
Longitudinal Impedance at PT/PR2 — 0 — Ω
Total Harmonic Distortion—200 Hz to 4 kHz2:
Off-hook
On-hook —
——
—0.3
1.0 %
%
Transmit Gain, f = 1 kHz (PT/PR to VITR) (current limit) –391 –403 –415 V/A
L9217A, Open Loop:
Receive + Gain, f = 1 kHz (RCVP to PT/PR)3
Receive – Gain, f = 1 kHz (RCVN to PT/PR)3
L9217G, Open Loop:
Receive + Gain, f = 1 kHz (RCVP to PT/PR)4
Receive – Gain, f = 1 kHz (RCVN to PT/PR)4
7.62
–7.62
1.94
–1.94
7.86
–7.86
2.00
–2.00
8.09
–8.09
2.06
–2.06
—
—
—
—
Gain vs. Frequency (transmit and receive)
(600 Ω termination; reference 1 kHz2):
200 Hz to 300 Hz
300 Hz to 3.4 kHz
3.4 kHz to 16 kHz
16 kHz to 266 kHz
–1.00
–0.3
–3.0
—
0.0
0.0
–0.1
—
0.05
0.05
0.3
2.5
dB
dB
dB
dB
Gain vs. Level (transmit and receive)(reference 0 dBV2):
–55 dB to +3 dB –0.05 00.05 dB
2-Wire Idle-channel Noise (600 Ω termination):
Psophometric2
C-message
3 kHz Flat2
—
—
—
–87
2
10
–77
12
20
dBmp
dBrnC
dBrn
Transmit Idle-channel Noise:
Psophometric2
C-message
3 kHz Flat2
—
—
—
–82
7
15
–77
12
20
dBmp
dBrnC
dBrn
1212 Agere Systems Inc.
Data Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Electrical Characteristics (continued)
Table 9. Logic Inputs and Outputs
All outputs are open collectors with internal, 30 kΩ pull-up resistor. Input pins have internal pull-down or some
method to power up in the disconnect state.
Ring Trip Requirements
■Ringing signal:
— Voltage, minimum 35 Vrms, maximum 100 Vrms.
— Frequency, 17 Hz to 33 Hz.
— Crest factor, 1.2 to 1.6.
■Ring trip:
— ≤100 ms (typical).
■Pretrip:
— Th e circuits in Figure 3 will not cause ring trip. Figure 3. Ring Trip Circuits
Parameter Symbol Min Typ Max Unit
Input Voltages:
Low Level (permissible range)
High Level (p er miss ib le ra nge ) VIL
VIH –0.5
2.0 0.4
2.4 0.7
VCC V
V
Input Currents:
Low Level (VCC = 5.25 V, VI = 0.4 V)
High Level (VCC = 5.25 V, VI = 2.4 V) IIL
IIH 0
10 4
24 10
50 µA
µA
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 4.75 V, IOL = 200 µA)
High Level (VCC = 4.75 V, IOH = –20 µA) VOL
VOH 0
2.4 0.2
—0.4
VCC V
V
RING
RING
100 Ω
10 kΩ
TIP
TIP 2 µF
8 µF
12-2572 (F).f
Agere Systems Inc. 13
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Test Configurations
Figure 4. L9217 Basic Test Circuit
Figure 5. Metallic PSRR Figure 6. Longitudinal PSRR
VBAT VCC
0.1 µF0.1
µF
0.47 µF
0.1 µF
RLOOP
43.2 kΩ
22.1 kΩ
B1
NSTAT
VBAT BGND VCC AGND
IPROG
LCTH
RTSP
RTSN
VITR
RCVP
B0
CF1
CF2
L9217
SLIC
TG 8.06 kΩ
100 Ω/600 Ω
2 MΩ
274 kΩ
2 MΩ
402 Ω
VBAT
50 Ω
50 Ω
RING
TIP XMT
75 kΩ
RCV
RCVN 46 kΩ
19.4 kΩ
DCOUT
B2
VTX
TXI 0.1 µF
PPMIN
OVH
V
PPMOUT 6.19 kΩ
12-3559 (F).E m
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
VT/R
VBAT
OR VCC
TIP
RING
BASIC
TEST CIRCUIT
+
–
PSRR = 20log VS
VT/R
900 Ω
BYPASS CAPACITOR
12-2582 (F).b
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
BYPASS CAPACITOR
56.3 Ω
VBAT
OR VCC
TIP
RING
BASIC
TEST CIRCUIT
PSRR = 20log VS
VM
67.5 Ω
10 µF
10 µF
67.5 Ω
VM
+
–
12-2583 (F).b
14 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Test Configurations (continued)
Figure 7. Longitudinal Balance
VS = 0.5 Vrms 30% AM 1 kHz modulation,
f = 500 kHz—1 MHz
device in powerup mode, 600 Ω termination.
Figure 8. RFI Rejection
Figure 9. Longitudinal Impedance
Figure 10. ac Gains
TIP
RING
BASIC
TEST CIRCUIT
LONGITUDINAL BALANCE = 20 log VS
VM
368 Ω
100 µF
100 µF
368 Ω
VM
+
–
VS
12-2584 (F).c
BASIC TEST
CIRCUIT
TIP
RING
VBAT
0.01 µF
0.01 µF
600 Ω
2.15 µF
82.5 Ω
82.5 Ω
HP
® 4935A
TIMS
50 Ω12
4
6, 7 L7591
VS
5-6756 (F).bm
TIP
RING
BASIC
TEST CIRCUIT
+
–
+
–
ILONG
ILONG
VPT
VPR
ZLONG = OR
∆ VPT
∆ ILONG ∆ VPR
∆ILONG
12-2585 (F).a
TIP
RING
BASIC
TEST CIRCUIT
600 ΩVT/R
+
–
GXMT =VXMT
VT/R
GRCV =VT/R
VRCV
XMT
RCV
VS
12-2587 (F).e
Agere Systems Inc. 15
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications
A basic loop start reference circuit, using bused ringing with the L9217 SLIC and the T7504 first-generation codec,
is shown in Figure 11. This circuit is designed for a 900 Ω termination impedance and an 850 Ω + 50 nF transhy-
brid. Transmit gain is set at 0 dBm and receive gain is set at –7 dBm.
* Placeholder for potential resistor to form filter against PPM generator noise if necessary.
Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec
Table 10 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted
to program these values are also shown.
Table 10. 900 Ω Termination, 850 Ω + 50 nF Hybrid First-Generation Codec Design Parameters
Design Parameter Param eter Value Components Adjusted
Loop Closure Threshold 10 mA RLCTH
dc Loop Current Limit 20 mA RPROG
ac Termin ati on Impe danc e 900 ΩRT1, RGP, RRCV, RGP1
Hybrid Balance Line Impedance 850 Ω + 50 nF CHB, RHB, RHB1
Tran sm it Gain 0 dBm RT2, RX, RN1, RN2, CN
Receive Gain –7 dBm RRCV, RGP, RT1
2797 (F)
R
PROG
35.7 k
Ω
R
LCTH
2 2 .1 k
Ω
R
PT
50
Ω
L7591
R
PR
PT
18
1
7LCTH
8DCOUT
50
Ω
PR
10
RTSP
20
R
TS1
402
Ω
RTSN
19
R
TSN
3.32 M
Ω
V
RING
V
BAT
CF2
11 CF1
12
C
F1
0.47
µ
F
AGND
16 BGND
17
I
PROG
V
BAT
9
C
BAT
0.1
µ
F
RCVP
RCVN
5
6
R
GP
R
T1
33.2 k
Ω
R
T2
45.3 k
Ω
R
RCV
63.4 k
Ω
R
HB1
97.6 k
Ω
R
X
86.6 k
Ω
GSX
VF
R
O
DX
DR
FSX
FSR
MCLK
1/4 T7504
CODEC
PCM
HIGHWAY
CONTROL
AND
CLOCK
–
+
L9217
SLIC
C
RTS1
0.015
µ
F
R
TSP
2.94 M
Ω
C
F2
0.1
µ
F
V
BAT
+ 2 .4 V
C
B2
0.47
µ
F
22
SUPERVISION
B1
B0 14
15
CONTROL
INPUTS
NSTAT
B2 13
VITR 23
TXI 24
VTX 25
TG 26
C
B
0.1
µ
F
R
GP1
8.06 k
Ω
TIP
RING
EMR
C
B1
0.47
µ
F
R
HB
86.6 k
Ω
C
HB
0.47 nF
14.7 k
Ω
C
PPM
0.01
µ
F
PPMIN
R
PPM
6.19 k
Ω
R
GN
9.76 k
Ω
PPMIN PPMOUT
2821
OUTPUT
V
CC
4
C
CC
0.1
µ
F
V
CC
R
OVH
49.9 k
Ω
27 OV H (for 2.5 Vrms P PM )
LCAS
C
HY
4.7 nF
OPEN
R
FLT
*
16 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Table 11. Parts List for Loop Start Application Circuit Using T7504-Type Codec
Name Value Function
Integrated Circuits
SLIC L92 17 Subscriber loop int erface circuit (SL IC).
Protector Agere L7591 Secondary protection.
Ringing Relay Agere L7581/2/3 or EMR Switches ringing signals.
Codec T7504 First-generation codec.
Overvolt age Protection
RPT 50 Ω, Fusible Protection resistor.
RPR 50 Ω, Fusible Protection resistor.
Power Supply
CBAT1 0.1 µF, 20%, 100 V VBAT filter capacitor.
CCC 0.1 µF, 20%, 10 V VCC filter capacitor.
CF1 0.47 µF, 20%, 100 V With CF2, improves idle- c hann el noise .
CF2 0.1 µF, 20%, 100 V With CF1, improves idl e- c hann el noise .
dc Characteristics
RPROG 35.7 kΩ, 1%, 1/16 W Set low current limit.
ac Characteristics
CB1 0.47 µF, 20%, 10 V ac/ dc se parati on capacit or.
CB2 0.47 µF, 20%, 10 V ac/ dc se parati on capacit or.
CB0.1 µF, 20%, 10 V dc blocking capacitor.
RT1 33.2 kΩ, 1%, 1/16 W With RGP and RRCV, sets ac termination impedance.
RRCV 63.4 kΩ, 1%, 1/16 W With RGP and RT1, sets receive gain.
RGP 14.7 kΩ, 1%, 1/16 W With RT1 and RRCV, sets ac termination impedance
and receive gain.
RT2 45.3 kΩ, 1%, 1/16 W With RX, sets transmit gain in codec.
RX86.6 kΩ, 1%, 1/16 W With RT2, se ts tr ansmit gain in codec.
RHB1 97.6 kΩ, 1%, 1/16 W Sets hybrid balance.
CHB 0.47 nF, 10%, 10 V With RGS provides gain shaping for hybrid.
RHB 86.6 kΩ, 1%, 1/16 W With CGS provides gain shaping for hybrid.
RGP1 8.06 kΩ, 1%, 1/16 W Sets dc transmit gain of SLIC.
RGN 9.76 kΩ, 1%, 1/16 W dc offset.
Meter Pulse
CHY 4.7 nF, 20%, 10 V Meter pulse rejection.
CPPM 0.01 µF, 20%, 10 V Meter pulse injection.
RPPM 6.19 kΩ, 1%, 1/16 W Meter pulse rejection.
ROVH 49.9 kΩ, 1%, 1/16 W Increases PPM overhead mode.
Supervision
RLCTH 22.1 kΩ, 1%, 1/16 W Sets loop closure (off-hook) threshold.
RTS1 402 Ω, 5%, 2 W Ringing source series resistor.
CRTS1 0.015 µF, 20%, 10 V With RTSN, RTSP, forms filter pole.
RTSN 3.32 MΩ, 1%, 1/16 W With R TSP, sets threshold.
RTSP 2.94 MΩ, 1%, 1/16 W With CRTS1, RTSN, sets threshold.
Agere Systems Inc. 17
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
A basic loop start reference circuit, using bused ringing with the L9217 SLIC and the T8536 third-generation codec,
is shown in Figure 12.
* Placeho lder for potential resistor to form filter against PPM generator noise if necessary.
Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec
RPROG
35.7 kΩ
RLCTH
22.1 kΩ
RPT
50 Ω
L7591
RPR
PT
18
1
7LCTH
8DCOUT
50 ΩPR
10
RTSP
20
RTS1
510 ΩRTSN
19
RTSN
3.4 MΩ
VRING
VBAT
CF2
11 CF1
12
CF1
0.47 µF
AGND
16 BGND
17
L9217
SLIC
CRTS1
0.015 µF
RTSP
2.94 MΩ
CF2
0.1 µF
RCVN
NSTAT
6DR2
FS
BCLK
1/4 T8536 PCM
HIGHWAY
CONTROL
AND
CLOCK
B0
B1
15
14
RCVP 5
VFRON
VFXI
VFROP
SLIC0a
SLIC3a
SLIC2a
DGND
DX1
DX2
DR1
CVDD
0.1 µF
VDD
CODEC
B2 13 SLIC4a
22
VITR 23
TIP
RING
EMR
TXI 24
VTX 25
TG 26
CB
0.1 µF
RGP1
8.06 kΩ
CB1 0.1 µF
TXI
IPROG
RPPM
6.19 kΩ
CPPM
0.01 µF
PPMIN
PPMIN PPMOUT
2821
VBAT
9
CBAT
0.1 µF
VBAT
VCC
4
CCC
0.1 µF
VCC
ROVH
61.9 kΩ
27 OVH (for 3.5 Vrms PPM)
RCIN
20 MΩ
LCAS
CHY
4.7 nF
OPEN
RFLT*
2798 (F)
18 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Table 12. Parts List for Loop Start Application Circuit Using T8536-Type Codec
Name Value Function
Integrated Circuits
SLIC L92 17 Subscriber loop int erface circuit (SL IC).
Protector Agere L7591 Secondary protection.
Ringing Relay Agere L7581/2/3 or EMR Switches ringing signals.
Codec T8536 Third- ge nerati on co dec .
Overvolt age Protection
RPT 50 Ω, Fusible Protection resistor.
RPR 50 Ω, Fusible Protection resistor.
Power Supply
CBAT1 0.1 µF, 20%, 100 V VBAT filter capacitor.
CCC 0.1 µF, 20%, 10 V VCC filter capacitor.
CF1 0.47 µF, 20%, 100 V With CF2, improves idle- c hann el noise .
CF2 0.1 µF, 20%, 100 V With CF1, improves idl e- c hann el noise .
dc Characteristics
RPROG 35.7 kΩ, 1%, 1/16 W Set low current limit.
ac Characteristics
CB1 0.1 µF, 20%, 10 V ac/dc separation capacitor.
CB0.1 µF, 20%, 10 V dc blocking capacitor.
RGP1 8.06 kΩ, 1%, 1/16 W Sets dc transmit gain of SLIC.
RCIN 20 MΩ, 5%, 1 /16 W dc bias.
Supervision
RLCTH 22.1 kΩ, 1%, 1/16 W Sets loop closure (off-hook) threshold.
RTS1 510 Ω, 5%, 2 W Ringing source series resistor.
CRTS1 0.015 µF, 20%, 10 V With RTSN and RTSP, forms second 2 Hz filter pole.
RTSN 3.4 MΩ, 1%, 1/16 W With RTSP, sets threshold.
RTSP 2.94 MΩ, 1%, 1/16 W With R TSN, sets threshold.
Meter Pulse
CHY 4.7 nF, 20%, 10 V Meter pulse rejection.
CPPM 0.01 µF, 20%, 10 V Meter pulse injection.
RPPM 6.19 kΩ, 1%, 1/16 W Meter pulse rejection.
ROVH 61.9 kΩ, 1%, 1/16 W Increases PPM overhead mode.
Agere Systems Inc. 19
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
dc Applica t ions
Battery Feed
The dc feed characteristic can be described by:
where:
IL = dc loop current.
VT/R = dc loop voltage.
|VBAT| = battery voltage magnitude.
VOH = overhead voltage. This is the difference between
the battery voltage and the open loop tip/ring
voltage.
RL = loop resistance, not including protection resistors.
RP = protection resistor value.
Rdc = SLIC internal dc feed resistance.
Note: VBAT = –48 V; ILIM = 22 mA; Rdc1 = 115 Ω.
Figure 13. Loop Current vs. Loop Voltage
Starting from the on-hook condition and going through
to a short circuit, the curve passes through the follow-
ing two regions:
Region 1: On-hook and low-loop currents. The slope
corresponds to the dc resistance of the SLIC, Rdc1
(default is 72 Ω typical). The open circuit voltage is
the battery voltage minus the overhead voltage of the
device, VOH (default is 6.5 V typical). These values are
suitable for most applications but can be adjusted if
needed.
Region 2: Current limit. The dc current is limited to a
starting value determined by external resistor RPROG,
an internal current source, and the gain from tip/ring to
pin VITR. Current limit with a 100 Ω load is set by the
following equation:
0.637 RPROG (kΩ) + 2 mA = ILIM x (mA)
Overhead Voltage
In order to drive an on-hook ac signal, the SLIC must
set up the tip and ring voltage to a value less than the
battery voltage. The amount that the open loop voltage
is decreased relative to the battery is referred to as the
overhead voltage. This is expressed as the following
equation:
VOH = |VBAT| – (VPT – VPR)
Without this buffer voltage, amplifier saturation will
occur and the signal will be clipped. In modes without
PPM, the L9217 is set to allow undistorted on-hook
transmission of a 3.17 dBm signal into a 900 Ω loop
impedance. A minimum 11.1 V overhead is needed to
pass 3.5 Vrms meter pulse.
In high overhead and PPM modes, overhead is auto-
matically increased to accommodate on-hook trans-
mission of meter pulse signals. The increase in
overhead is set by a resistor from pin OVH to ground.
This is expressed as the following equation:
VOVH (V) = 6.37 + 0.09535 x ROVH (kΩ)
ILVBAT VOH
–
RL2RPRdc
++
----------------------------------
=
VT/R VBAT VOH
–
()
R
×L
RL2RPRdc
++
---------------------------------------------
=
01020 50
0
20
30
40
50
LOOP VO LTAGE (V)
30 40
10
LOOP CURRENT (mA)
1
12.5 kΩ
–1
Rdc1
ILIM TESTED ILIM ONSET
12-3050 (F).i
2020 Agere Systems Inc.
Data Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
dc Applications (continued)
Rate of Battery Reversal
The rate of battery reversal is controlled or ramped by
capacitors FB1 and FB2. A chart showing FB1/FB2 val-
ues versus typical ramp rate is given below. Leave
FB1/FB2 open if it is not desired to ramp the rate of
battery re ve rsal .
Table 13. FB1/FB2 Values vs. Typical Ramp Time
Loop Range
The equation below can be rearranged to provide the
loop range for a required loop current:
Off-Hook Detection
The loop closure detection threshold is set by resistor
RLCTH. The supervision output bit NSTAT is high in an
on-hook condition. The of f-hook comparator goes low
during an off-hook condition:
Figure 14. Off-Hook Detection Circuit
CFB1/CFB2 Transition Time
0.01 µF 20 ms
0.1 µF 220 ms
0.22 µF 440 ms
0.47 µF 900 ms
1.0 µF 1.8 s
1.22 µF2.25 s
1.3 µF 2.5 s
1.4 µF 2.7 s
1.6 µF 3.2 s
RLVBAT VOH
–
IL
---------------------------- 2RP
–RDC
–=
ITR (mA) = 0.4167 RLTCH (kΩ) –1.9 mA
ACTIVE off-hook to on-hook
ITR (mA) = 0.4167 RLTCH (kΩ) + 2.7 mA
SCAN on-hook to off-hook
RLITR
RP
RP
RING
–
+
–
+
DCOUT
RLCTH
LCTH
NSTAT
TIP
0.125 V/mA
0.05 mA
12-2553 (F)
Agere Systems Inc. 21
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
dc Applications (continued)
Ring Trip Detection
The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent
circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing.
Figure 15. Ring Trip Equivalent Circuit and Equivalent Application
Ring trip detection threshold is given by the following equation:
ITH (mA) =
Longitudinal Balance
The SLIC is graded to certain longitudinal balance specifications. The numbers are guaranteed by testing (Figure 5
and Figure 8). However, for specific applications, the longitudinal balance may also be determined by termination
impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This
can be illustrated by the following equation:
LB = 20 x log
where:
LB: longitudinal balance.
RP: protection resistor value in Ω.
ZT: magnitude of the termination impedance in Ω.
ε: protection resistor mismatch in Ω.
∆: SLIC internal tip/ring sensing mismatch.
The ∆ can be calculated using the above equation with these exceptions: ε = 0, ZT = 600 Ω, RP = 100 Ω, and the
longitudinal balance specification on a specific code.
Now with ∆ available, the equation will predict the actual longitudinal balance for RP, ZT, and ε.
Be aware that ZT may vary with frequency for complex impedance applications.
+
–
RTSP
RLOOP
15 kΩ
8.6 V
IP = IN
RTSN
3.32 MΩ/3.40 MΩ
CRTS1
0.015 µF
PHONE
HOOK SWITCH
RC PHONE
VRING
VBAT
NSTAT
RTSP
IN
RTSN
–
+
2.94 MΩ
RS
402 Ω/510 Ω
2799 (F)
RTSN MΩ
()
0.015 RTSP MΩ
()
–+
[]
VBAT 8.6
–
[]×1000
×
RTSN MΩ
()
0.015
+
[]
RS
×
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
368 RP
+
()
368 ZT RP
–+
()×
3682ZT2
–RP
×[]×∆ε
+
×()×
-------------------------------------------------------------------------------------------
22 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Periodi c Pul se Metering (PPM)
Periodic pulse metering (PPM), also referred to as
TTX, is input to the PPMIN input of the L9217. Upon
application of appropriate logic control, this signal is
presented to the tip/ring subscriber loop. The state of
the L9217 may be changed while applying PPM sig-
nals. The L9217 assumes that a shaped PPM signal is
applied to the PPMIN input.
Sufficient drive current is available in the tip and ring
drive amplifiers to support 3.5 V rms PPM signals into a
200 Ω load with a 45 mA dc current limit.
PPM signals are input to a separate PPMIN input. This
input is controlled via the logic table. PPMIN is off dur-
ing all states except the forward/reverse PPM active
state. Thus, PPM signals may be present at all times,
even during non-PPM active times. To apply PPM to
tip/ring, from a normal overhead state first switch to a
high overhead state without PPM; the overhead volt-
age at tip/ring will increase to 7 V to 13 V. The ramp up
time of the overhead increase is on the order of hun-
dreds of milliseconds. Thus, wait 1 s before applying
the PPM signal by going to a PPM active high over-
head state. Once in a high overhead, there is no timing
requirement in switching in and out of a PPM active
mode. Without the initial 1 s delay, AT/AR will get into
saturation and PPM signal at T/R will get distorted, pro-
ducing crosstalk in the handset.
PPM input signals may be a maximum 0.525 Vrms at
PPMIN. The gain from PPMIN tip/ring is 10. Thus, for
2.5 Vrms at tip and ring, apply a 0.375 Vrms signal at
PPMIN. The PPM signal should be ac coupled to
PPMIN through a 0.01 µF capacitor.
When applied to tip and ring, the PPM signal will also
be returned through the SLIC and will appear at the
SLIC VITR output. The concern is that this high-voltage
signal can overload the codec input and cause distor-
tion of the (desired) ac signal. Therefore, some sort of
PPM rejection scheme must be employed, see Figure
1. The L9217 outputs on the PPMOUT pin, which is the
output of the PPM input amplifier . Connecting a resis-
tor , RPPM, from P PMOU T to n ode TG wil l pr ovide a pat h
for a hybrid reject of the returned meter pulse signal.
The return path from tip and ring to VITR for the PPM
signal is through the internal AX amplifier. TG is the
input to this amplifier. Through RPPM, by applying a
PPM signal equal in magnitude, but 180 degrees out of
phase to the returned PPM signal at TG, the PPM sig-
nal is cancelled, preventing overload at the codec
input. Even if the cancellation is not perfect, the idea is
to reduce the PPM signal so as not to overload the
codec. Codecs typically have a low-pass filter at their
input to reject any residual meter pulse signal.
The value of RPPM is selected by:
RPPM = [{(VPPMIN x 10)/(RPPMLOAD + RDC + 2RP)}/201.2]–1
For undistorted transmission of meter pulse signals,
increase the overhead as described in the Overhead
Voltage section of this data sheet.
Agere Systems Inc. 23
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design
Codec Types
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. There are four key ac
design parameters. Termination impedance is the
impedance looking into the 2-wire port of the line card.
It is set to match the impedance of the telephone loop
in order to minimize echo return to the telephone set.
Transmit gain is measured from the 2-wire port to the
PCM highway , while receive gain is done from the PCM
highway to the transmit port. Finally , the hybrid balance
network cancels the unwanted amount of the receive
signal that appears at the transmit port.
Below is a brief codec feature summary.
First-Generation Codecs. These perform the basic fil-
tering, A/D (transmit), D/A (receive), and µ-law/A-law
companding. They all have an op amp in front of the
A/D converter for transmit gain setting and hybrid bal-
ance (cancellation at the summing node). Depending
on the type, some have differential analog input stages,
differential analog output stages, 5 V only or ±5 V op e r -
ation, and µ-law/A- la w sele cta bili ty. These are av ail-
able in single and quad designs. This type of codec
requires continuous time analog filtering via external
resistor/capacitor networks to set the ac design param-
eters. An example of this type of codec is the Agere
T7504 quad 5 V only codec.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Furthermore, ac parameters are fixed by the external
R/C network, so software control of ac parameters is
difficult.
Third-Generation Codecs. This class of devices
includes all ac parameters set digitally under micropro-
cessor control. Depending on the device, it may or may
not have data control latches. Additional functionality
sometimes offered includes tone plant generation and
reception, TTX generation, test algorithms, and echo
cancellation. Again, this type of codec may be 5 V
only or ±5 V operation, single quad or 16-channel, and
µ-law/A-law or 16-bit linear coding selectable. Exam-
ples of this type of codec are the Agere T8535/6 (5 V
only, quad, standard features), T8533/4 (5 V only , quad
with echo cancellation), and the T8531/36 (5 V only
16-channel with self-test).
ac Interface Network
The ac interface network between the L9217 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9217 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set dig-
itally, internal to the codec; thus, the interface between
the L9217 and this type of codec is designed to avoid
overload at the codec input in the transmit direction,
and to optimize signal-to-noise ratio (S/N) in the
receive direction.
Receive Interface
Because the design requirements are very different
with a first- or third-generation codec, the L9217 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9217
and the codec.
With a first-generation codec, the termination imped-
ance is set by providing gain shaping through a feed-
back network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9217 provides a t ranscon-
ductance from T/R to VITR in the transmit direction and
a single ended to differential gain in the receive direc-
tion from either RCVN or RCVP to T/R. Assuming a
short from VITR to RCVN or RCVP, the maximum
impedance that is seen looking into the SLIC is the
product of the SLIC transconductance times the SLIC
receive gain, plus the protection resistors. The various
specified termination impedance can range over the
voice band as low as 300 Ω up to over 1000 Ω. Thus, if
the SLIC gains are too low, it will be impossible to syn-
thesize the higher termination impedances. Further-
more, the termination that is achieved will be far less
than what is calculated by assuming a short for SLIC
output to SLIC input. In the receive direction, in order to
control echo, the gain is typically a loss, which requires
a loss network at the SLIC RCVN/RCVP inputs, which
will reduce the amount of gain that is available for ter-
mination impedance. For this reason a high-gain SLIC
is required with a first-generation codec.
2424 Agere Systems Inc.
Data Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Receive Interface (continued)
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination imped-
ance, hybrid balances, and transmission level points
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voice band frequency, must ensure that the
codec is not overloaded. With a given TLP and a given
SLIC gain (if the signal will cause a codec overload),
the designer must insert some sort of loss, typically a
resistor divider, between the SLIC output and codec
input.
In the receive direction, the issue is to optimize S/N.
Again, the designer must consider all the considered
TLPs. The idea is, for all desired TLPs, to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember noise floor is
constant, so the hotter the signal from the codec, the
better the
S/N. The problem is, if the codec is feeding a high-gain
SLIC, either an external resistor divider is needed to
knock the gain down to meet the TLP requirements, or
the codec is not operating near maximum signal levels,
thus compromising the S/N.
It appears the solution is to have a SLIC with a low
gain, especially in the receive direction. This will allow
the codec to operate near its maximum output signal
(to optimize S/N), without an external resistor divider
(to minimize cost).
Note also that some third-generation codecs require
the designer to provide an inherent resistive termina-
tion via external networks. The codec will then provide
gain shaping, as a function of frequency to meet the
return loss requirements. Further stability issues may
add external components or excessive ground plane
requirements to the design.
To meet the unique requirements of both types of
codecs, the L9217 offers two receive gain choices.
These receive gains are mask programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9217A
is offered with a receive gain of 7.86. For interface with
a third-generation codec, the L9217G is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction, or the transmit gain is 403 Ω.
Example 1: Real Termination (First-Generation Codec)
ac equivalent circuits for real termination using a T7504 codec is shown in Figure 15.
Figure 16. ac Equivalent Circuit
RP
ZT+
–
RP
VT/R
IT/R
VS
ZT/R
+
–
RING AV = –1
AV = 1
VITR
–
+
+
–
CURRENT
SENSE
TIP
+
–
RT1
RRCV
RHB1
RT2
RCVN
RCVP
RXVGSX
VFXIN
VFR
1/4 T7504 CODEC
RG
2.4 V
–0.403 V/mA
AV =
L9217 SLIC
VFXIP
3.93
12-3581 (F).Cm
Agere Systems Inc. 25
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Example 1: Real Termination (First-Generation Codec) (continued)
The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination imped-
ance.
Termination Impedance:
ZT =
Receive Gain:
grcv =
grcv =
Transmit Gain:
gtx =
gtx = x
Hybrid Balance:
hbal = 20log
To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0.
The following expressions assume the test network is the same as the termination impedance:
RHB =
hbal = 20log
VTR
⁄
ITR
⁄
–
--------------
ZT2RP3168
1RT3
RGP
---------RT3
RRCV
------------
++
-----------------------------------
+=
VTR
⁄
Vfr
--------------
7.86
1RRCV
RT3
--------------- RRCV
RGP
---------------
++
1ZT
ZT/R
-------------
+
-------------------------------------------------------------------------------------
VGSX
VTR
⁄
---------------
RX
RT6
---------- 403
ZT
-----------
VGSX
VTR
⁄
---------------
RX
gtx grcv
×
-------------------------
RX
RHB
------------gtx
–grcv
×
26 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (continued)
Example 2: Complex Termination (First-Generation Codec)
Below are design equations for complex termination (see Figure 17 and Figure 18).
RTGP || RTGS
RTGP || RTGS
gtx =
grcv =
hbal = 20log
where:
ZT/R = R1 + R2 || C
ZTG = RTGP || (RTGS + CG)
RTGP = 8.06 kΩ
RTGS = RTGP
CG = x C
and
CNRN2 = CG RTGP
RN1 = RN2
The equations above do not include the blocking capacitors.
RT1 2RP7.86
201.2
------------1
1RT3
RGP
---------RT3
RRCV
------------
++
----------------------------------- 1
1RN1
RN2
--------
+
------------------
–
•
+=
RT2 7.86
201.2
------------ RTGP RTGS
⁄
1RT3
RGP
---------RT3
RRCV
------------
++
----------------------------------- 1
1RN1
RN2
--------
+
------------------
+
+=
1
CT
------- 7.86
201.2
---------------- 1
CN1
-----------RN2
RN1 RN2
+
()
2
-------------------------------------RTGP RTGS
|| 1
CTG
-----------RTGP
RTGP RTGS
+
-------------------------------------
2•• 1
1RT3
RGP
------------RT3
RRCV
---------------
++
---------------------------------------------- 1
1RN1
RN2
-----------
+
---------------------
–
+
=
RX
RT6
---------- 1
201.2
---------------- ZTG
ZT
-----------
7.86
1RRCV
RT3
--------------- RRCV
RGP
---------------
++
------------------------------------------------1
1ZT
ZTR
⁄
-------------
+
------------------------
×
RX
RHB
------------gtx
–grcv
×
R1
R2
-------
R22
RTGP R1R2
+
()
------------------------------------------
2RP
3167
-------------
3167
2RP
-------------RTGS
RTGP
--------------
1–
Agere Systems Inc. 27
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
ac Design (contin ued)
Example 2: Complex Terminati on (First-Generation Codec) (continued)
Figure 17. Interface Circuit Using First-Generation Codec (±5 V Codec)
Figure 18. Interface Circuit Using First-Generation Codec (5 V Only Codec)
RTGS
RTGP = 8.06 kΩRT6
RX
RT3
CODEC
OP AMP
–
+
CN
RN1
RN2 RGP
RRCV
RCVN
RCVP
–IT/R
201.2
CGS
CB1
RTGS
RT6
RT3
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
CN
RN1
RRCV
RCVN
RCVP
–IT/R
CGS
AX
5-6401 (F).l
RTGS
CB1
RTGP = 8.06 kΩRT6
Rx
RT3
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
CN
RN1
RN2
RGP
RRCV
RCVN
RCVP
–IT/R
201.2
CG
AX
–2.4 V
CB2
5-6400 (F).o
28 Agere Systems Inc.
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Applications (continued)
Power Dera tin g
Operating temperature range, maximum current limit,
maximum battery voltage, minimum dc loop, and pro-
tection resistor values will influence the overall th ermal
performance. This section shows the relevant design
equations and considerations in evaluating the SLIC
thermal perfor m anc e.
Consider the L9217 SLIC in a 28-pin PLCC package.
The thermal resistance on a 2-layer board with natural
convection is 43 °C/W.
The SLIC will enter the thermal shutdown state at a
minimum of 150 °C. The thermal shutdown design
should ensure that the SLIC temperature does not
reach 150 °C under normal operating conditions.
Assume a maximum ambient operating temperature of
85 °C, a design current limit of 25 mA, and a maximum
battery of –52 V. Furthermore, assume a (worst-case)
minimum dc loop of 200 Ω, and that 50 Ω protection
resistors are used at both tip and ring.
1. TTSD – TAMBIENT(max) = allowed thermal rise.
150 °C – 85 °C = 65 °C
2. Allowed thermal rise = package thermal
impedance • SLIC power dissipation.
65 °C = 43 °C/W • SLIC power dissipation
SLIC power dissipation (PDISS) = 1.51 W
Thus, if the total power dissipated in the SLIC is less
than 1.51 W, it will not enter the thermal shutdown
state. Total SLIC power is calculated as:
Total PDISS = Maximum battery • maximum
current limit (including effects of accuracy)
+ SLIC quiescent power
For the L9217, SLIC quiescent power (PQ) is maximum
at 0.175 W. Thus,
Total PDISS = (–52 V • [25 mA • 1.08]) + 0.175 W
Total PDISS = 1.404 W + 0.175 W
Total PDISS = 1.579 W
The power dissipated in the SLIC is the total power dis-
sipation minus the power that is dissipated in the loop.
SLIC PDISS = Total power – loop power
Loop power = (ILIM)2 • (RdcLOOP min + 2RP)
Loop power = (25 mA • 1.08)2 •
(200 Ω + 100 Ω)
Loop power = 0.219 W
SLIC power = 1.579 W – 0.219 W = 1.36
SLIC power = 1.36 W < 1.51 W
Thus, in this example, the thermal design ensures that
the SLIC will not enter the thermal shutdown state.
Pin-for-Pin Compatibility with L9218/L9219
The L9217 can be a pin-for-pin replacement for the
L9218/L9219. The exceptions are as follows: L9217
has three logic control inputs: B0, B1, and B2. The
L9218 has only two logic control inputs: B0 and B1. Pin
13 in L9218 is NC, so a connection between the con-
troller and pin 13 will not affect L9218 operation. In
L9217, pin 28 is PPMOUT, pin 21 is PPMIN, and pin 27
is OVH. In L9218/9, pin 28 is NC, pin 21 is NC, and pin
27 is TSD
PCB Layout Information
Make the leads to BGND and VBAT as wide as possible
for thermal and electrical reasons. Also, maximize the
amount of PCB copper in the area of (and specifically
on) the leads connected to this device for the lowest
operating temperature.
When poweri ng the devic e, mak e certa in that no exte r-
nal potential creates a voltage on any pin of the device
that exceeds the device ratings. In this application,
some of the conditions that cause such potentials dur-
ing powerup are the following:
1. An inductor connected to PT and PR (this can force
an overvoltage on VBAT through the protection
devices if the VBAT connection chatters).
2. Inductance in the VBAT lead (this could resonate
with the VBAT filter capacitor to cause a destructive
overvoltage).
This device is normally used on a circuit card that is
subjected to hot plug-in, meaning the card is plugged
into a biased backplane connector. In order to prevent
damage to the IC, all ground connections must be
applied before, and removed after, all other connec-
tions.
Agere Systems Inc. 29
Data Sheet
November 20 01 with Re verse Battery and PPM
L9217A/G Low-Cost Line Interface
Outline Diagram
28-Pin PLCC
Dimensions are in millimeters.
1.27 TYP
0.330/0.533
0.10
SEATING PLA NE
0.51 MIN
TYP
4.572
MAX
12 18
11
5
4126
25
19
12.446 ± 0.127
PIN #1 IDENTIFIER
ZONE
11.506 ± 0.076
11.506
± 0.076
12.446
± 0.127
5-2506 (F) r.8
Dat a Sheet
November 2001
with Reverse Battery and PPM
L9217A/G Low-Cost Line Interface
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
November 2001
DS02-038ALC (Replaces DS02-002ALC)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA , A llentown, PA 18109-3286
1-800-372-2447, FAX 61 0-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), ( 86) 10- 6 522-55 66 (Beijing), (86) 755-695-7224 (Shenz hen)
JAPAN: (81) 3-54 21-1600 (Tokyo), KOREA: ( 82) 2- 767-1850 (Seou l), SIN G APORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Ordering Information
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
HP
is a registered trademark of Hewlett-Packard Company.
Device Package Comcode
LUCL9217AAR-DT 28-Pin PLCC
(Tape & Reel, Dry-bagged)
Gain of 8
108760737
LUCL9217AAR-D 28-Pin PLCC
(Dry-bagged)
Gain of 8
108760729
LUCL9217GAR-DT 28-Pin PLCC
(Tape & Reel, Dry-bagged)
Gain of 2
108760760
LUCL9217GAR-D 28-Pin PLCC
(Dry-bagged)
Gain of 2
108760752
