This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.02 / Jun.01 Hynix Semiconductor
HY62UF08401C Series
256Kx16bit full CMOS SRAM
Document Title
512K x 8bit 2.7 ~ 3.3V Super low Power FCMOS Slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Draft Dec.18.2000 Final
01 Changed Logo Mar.23.2001 Final
02 Changed Isb1 values Jun.07.2001 Final
HY62UF08401C Series
Rev.02 / Jun.01 2
DESCRIPTION
The HY62UF08401C is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
512K words by 8bits. The HY62UF08401C uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup
-. 1.2V(min) data retention
• Standard pin configuration
-. 32 - sTSOP - 8X13.4(Standard)
Standby
Current(uA) Product No. Voltage
(V) Speed (ns) Operation
Current/Icc(mA)
LL SL
Temperature
(°C)
HY62UF08401C-I
2.7~3.3
55/70 5 15 6 -40~85
Note 1. I : Industrial
2. Current value is max.
PIN CONNECTION BLOCK DIAGRAM
PIN DESCRIPTION
Pin Name Pin Function Pin Name Pin Function
/CS Chip Select I/O1 ~ I/O8 Data Input/Output
/WE Write Enable Vcc Power (2.7V~3.3V)
/OE Output Enable Vss Ground
A0 ~ A18 Address Input
MEMORY ARRAY
512K x 8
ROW
DECODER
SENSE AMP
WRITE DRIVER
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT
BUFFER
A0
A18
/OE
/WE
/CS
I/O1
I/O8
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-sTSOP Forward
HY62UF08401C Series
Rev.02 / Jun.01 2
ORDERING INFORMATION
Part No. Speed Power
Temp.
Package
HY62UF08401C-DS(I) 55/70 LL-part I sTSOP
HY62UF08401C-SS(I) 55/70 SL-part I sTSOP
Note 1. I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter Rating Unit Remark
VIN, VOUT Input/Output Voltage -0.3 to 3.6 V
Vcc Power Supply -0.3 to 4.6 V
TA Operating Temperature -40 to 85 °C HY62UF08401C-I
TSTG Storage Temperature -55 to 150 °C
PD Power Dissipation 1.0 W
TSOLDER Ball Soldering Temperature & Time 260 • 10 °C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
/WE
/OE
MODE I/O OPERATION Supply Current
H X X Deselected High-Z Standby
H Output Disabled
High-Z Active
H L Read Dout
L L X Write Din Active
Note:
1. H=VIH, L=VIL, X=don't care (VIL or VIH)
HY62UF08401C Series
Rev.02 / Jun.01 3
RECOMMENDED DC OPERATING CONDITION
Symbol Parameter Min. Typ Max. Unit
Vcc Supply Voltage 2.7 3.0 3.3 V
Vss Ground 0 0 0 V
VIH Input High Voltage 2.2 - Vcc+0.3 V
VIL Input Low Voltage -0.31. - 0.6 V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C
Sym
Parameter Test Condition Min
Typ1.
Max
Unit
ILI Input Leakage Current Vss < VIN < Vcc -1 - 1 uA
ILO Output Leakage Current Vss < VOUT < Vcc,
/CS = VIH or
/OE = VIH or /WE = VIL
-1 - 1 uA
Icc Operating Power Supply Current /CS = VIL,
VIN = VIH or VIL, II/O = 0mA 5 mA
/CS = VIL,
VIN = VIH or VIL, Cycle Time = Min,
100% Duty, II/O = 0mA
40 mA
ICC1 Average Operating Current /CS < 0.2V,
VIN < 0.2V or VIN > Vcc-0.2V,
Cycle Time = 1us,
100% Duty, II/O = 0mA
5 mA
ISB Standby Current (TTL Input) /CS = VIH or VIN = VIH or VIL 0.5
mA
SL 0.2 6 uA
ISB1 Standby Current (CMOS Input) /CS > Vcc - 0.2V or
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V LL 0.2 15 uA
VOL Output Low IOL = 2.1mA - - 0.4
V
VOH Output High IOH = -1.0mA 2.4
- - V
Note
1. Typical values are at Vcc = 3.0V TA = 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol Parameter Condition Max. Unit
CIN Input Capacitance (Add, /CS, /WE, /OE) VIN = 0V 8 pF
COUT Output Capacitance (I/O) VI/O = 0V 10 pF
Note : These parameters are sampled and not 100% tested
HY62UF08401C Series
Rev.02 / Jun.01 4
AC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified 55ns 70ns
# Symbol
Parameter Min.
Max.
Min.
Max.
Unit
1 tRC Read Cycle Time 55 - 70 - ns
2 tAA Address Access Time - 55 - 70 ns
3 tACS Chip Select Access Time - 55 - 70 ns
4 tOE Output Enable to Output Valid - 30 - 35 ns
5 tCLZ Chip Select to Output in Low Z 10 - 10 - ns
6 tOLZ Output Enable to Output in Low Z 5 - 5 - ns
7 tCHZ Chip Deselection to Output in High Z 0 30 0 30 ns
8 tOHZ Out Disable to Output in High Z 0 30 0 30 ns
9 tOH Output Hold from Address Change 10 - 10 - ns
10
tWC Write Cycle Time 55 - 70 - ns
11
tCW Chip Selection to End of Write 50 - 60 - ns
12
tAW Address Valid to End of Write 50 - 60 - ns
13
tAS Address Set-up Time 0 - 0 - ns
14
tWP Write Pulse Width 45 - 50 - ns
15
tWR Write Recovery Time 0 - 0 - ns
16
tWHZ Write to Output in High Z 0 20 0 20 ns
17
tDW Data to Write Time Overlap 25 - 30 - ns
18
tDH Data Hold from Write Time 0 - 0 - ns
19
tOW Output Active from End of Write 5 - 5 - ns
AC TEST CONDITIONS
TA = -40°C to 85°C, unless otherwise specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW CL = 5pF + 1TTL Load Output Load
Others CL = 30pF + 1TTL Load
AC TEST LOADS
D
OUT
1728 Ohm
CL(1)
1029 Ohm
V
TM=2.8V
Note
1. Including jig and scope capacitance
READ CYCLE
WRITE CYCLE
HY62UF08401C Series
Rev.02 / Jun.01 5
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
READ CYCLE 2 (Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,2,4)
/CS
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
ADDR
tRC
/CS
tAA
tACS
tOH
Data Valid
High-Z
Data
Out
/OE
tOE
tCLZ(3)
tOLZ(3)
tCHZ(3)
tOHZ(3)
HY62UF08401C Series
Rev.02 / Jun.01 6
WRITE CYCLE 1(1,4,8) (/WE Controlled)
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
Data Valid
ADDR
Data
Ou
t
/CS
/WE
tWC
tCW
tWR(2)
tAW
tWP
Data In
High-Z
tAS
tWHZ(3,8)
tDW tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/CS
/WE
tWC
tCW
tWR(2)
tAW
tWP
Data In
tDW
tDH
High-Z
High-Z
tAS
HY62UF08401C Series
Rev.02 / Jun.01 7
Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occurs simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = -40°C to 85°C
Symbol
Parameter Test Condition Min Typ1.
Max
Unit
VDR Vcc for Data Retention /CS > Vcc - 0.2V,
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
1.2 - 3.3 V
SL - 0.1 3 uA
Iccdr Data Retention Current
Vcc=1.5V,
/CS > Vcc - 0.2V or
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V LL - 0.1 10 uA
tCDR Chip Deselect to Data
Retention Time 0 - - ns
tR Operating Recovery Time See Data Retention Timing Diagram tRC - - ns
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical value are sampled and not 100% tested
DATA RETENTION TIMING DIAGRAM
/CS
VDR
/CS >VCC-0.2V
tCDR tR
VSS
VCC
2.7V
VIH
DATA RETENTION MODE
HY62UF08401C Series
Rev.02 / Jun.01 8
PACKAGE INFORMATION
32pin 8x13.4mm Smaller Thin Small Outline Package Standard(ST)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.024(0.6)
0.016(0.4)
0.008(0.2)
0.004(0.1) 0.020(0.50)
0.007(0.17)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
#1
#32
#16
#17
0.011(0.27)
HY62UF08401C Series
Rev.02 / Jun.01 9
MARKING INFORMATION
Package Marking Example
Index
•HY62UF08401C : Part Name
•c: Power Consumption
-D: Low Low Power
-S: Super Low Power
•S: Package Type
-S: sTSOP
•ss : Speed -55 : 55ns
-70 : 70ns
•t: Temperature
-I: Industrial ( -40 ~ 85 °C)
•yy : Year ( ex : 00 = year 2000, 01 = year 2001 )
•ww : work week ( ex : 12 = ww12 )
•p: Process Code
•KOR : Origin Country
Note
-Capital Letter : Fixed Item
-Small Letter : Non-fixed Item
HY6 2 UF0840
1C-cSs s t
y y w w pKOR
sTSOP
Package Marking Example
Index
•HY62UF08401C : Part Name
•c: Power Consumption
-D: Low Low Power
-S: Super Low Power
•S: Package Type
-S: sTSOP
•ss : Speed -55 : 55ns
-70 : 70ns
•t: Temperature
-I: Industrial ( -40 ~ 85 °C)
•yy : Year ( ex : 00 = year 2000, 01 = year 2001 )
•ww : work week ( ex : 12 = ww12 )
•p: Process Code
•KOR : Origin Country
Note
-Capital Letter : Fixed Item
-Small Letter : Non-fixed Item
HY6 2 UF0840
1C-cSs s t
y y w w pKOR
HY6 2 UF0840
1C-cSs s t
y y w w pKOR
sTSOP