AK4414EQ - AKM Semiconductor

[AK4414]

MS1476-E-01 2013/01

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GENERAL DESCRIPTION

AK4414 is a 32-bit DAC, which corresponds to BD systems. An internal circuit includes newly developed

32bit Digital Filter for better sound quality achieving low distortion characteristics and wide dynamic

range. The AK4414 has full differential SCF outputs, removing the need for AC coupling capacitors and

increasing performance for systems with excessive clock jitter. The AK4414 accepts 216kHz PCM data

and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD.

FEATURES

• 128x Over sampling

• Sampling Rate: 30kHz ∼ 216kHz

• 32Bit 8x Digital Filter

- Ripple: ±0.005dB, Attenuation: 80dB

- High Quality Sound Short Delay Option; GD=7/fs and GD=5.5/fs

- Sharp Roll-Off Filter

- Slow Roll-Off Filter

• High Tolerance to Clock Jitter

• Low Distortion Differential Output

• DSD data input

• Digital De-emphasis for 32, 44.1, 48kHz sampling

• Soft Mute

• Digital Attenuator (255 levels and 0.5dB step)

• Stereo Mode

• THD+N: -107dB

• DR, S/N: 120dB (Stereo mode: 123dB)

• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD, TDM

• Master Clock:

30kHz ~ 32kHz: 1152fs

30kHz ~ 54kHz: 512fs or 768fs

30kHz ~ 108kHz: 256fs or 384fs

108kHz ~ 216kHz: 128fs or 192fs

• Power Supply: DVDD=AVDD=2.7 ∼ 3.6V, VDD1/2=4.75 ∼ 5.25V

• Digital Input Level: CMOS

• Package: 44pin LQFP

AK4414

High Performance 120dB 32-Bit 4ch DAC

[AK4414]

MS1476-E-01 2013/01

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■ Block Diagram

MCLK

SDTI1/DSDL1

LRCK/DSDR2

CSN/SMUTE

BICK/DCLK

CCLK/DEM0

CDTI/DEM1

ACKS/DZF2

VSS1

VDD1

PDN AVDD

Clock

Divider

DVSS DVDD

CAD0/SD CAD1/DIF0

PSN DZF1/DIF1 DIF

VSS2

AOUTRN1

VREFH1

VREFL1

AVSS

AOUTLP1

AOUTLN1

AOUTRP1

PCM

Data

Interface

DSD

Data

Interface

8X

Interpolator

Control

Register

SCF

AOUTRN2

VREFH2

VREFL2

AOUTLP2

AOUTLN2

AOUTRP2

Δ

Σ

Modulator

Vref

VDD2

VCOM2

VCOM1

TDM0

SDTI2/DSDL2

TDM1/DSDR1

8X

Interpolator

DATT

Soft Mute

SCF

Δ

Σ

Modulator

Vref

DATT

Soft Mute

Bias

SLOW

Block Diagram

[AK4414]

MS1476-E-01 2013/01

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■ Ordering Guide

AK4414EQ −10 ∼ +70°C 44pin LQFP (0.8mm pitch)

AKD4414 Evaluation Board for AK4414

■ Pin Layout

VDD1

VSS1

34

AOUTL1N

33

35

AOUTL1P 36

VCM1 37

TSTO1 38

TSTO2 39

AVDD 40

AVSS 41

MCLK 42

DVSS 43

DVDD 44

VREFL1 32

VREFH 1 31

AOUTR1N

30

AOUTR1P

29

NC

28

AOUTL 2P

27

AOUTL 2N

26

VREFH2

25

VREFL2 24

VSS2 23

PDN 1

TDM1/DSDR1

2

BICK/DCL

K

3

SDATA1/DSDL1

4

LRCK/DSDR2

5

SMUTE/CSN

6

SD/CAD0

7

DEM0/CCL

K

8

DEM1/CDTI

9

DIF0/CAD1

10

11

22

21

20

19

18

17

16

15

14

13

12

VDD2

A

OUTR2N

A

OUTR2P

VCM2

TEST

SLOW

TDM0

A

CKS/DZF2

PSN

DIF2

DIF1/DZF1

AK4414

Top View

SDATA2/DSDL2

[AK4414]

MS1476-E-01 2013/01

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PIN/FUNCTION

No. Pin Name I/O Function

1 PDN I

Power-Down Mode

When at “L”, the AK4414 is in power-down mode and is held in reset.

The AK4414 should always be reset upon power-up.

BICK I Audio Serial Data Clock in PCM Mode

2 DCLK DSD Clock Pin in DSD mode

SDATA1 I Audio Serial Data Input in PCM Mode

3 DSDL1 I Audio Serial Data Input in DSD Mode

SDATA2 I Audio Serial Data Input in PCM Mode

4 DSDL2 I Audio Serial Data Input in DSD Mode

TDM1 I TDM I/F Format Mode in PCM Mode

5 DSDR1 I Audio Serial Data Input in DSD Mode

LRCK I L/R Clock in PCM Mode

6 DSDR2 Audio Serial Data Input in DSD Mode

SMUTE I

Soft Mute in Parallel Control Mode

When this pin goes to “H”, soft mute cycle is initiated.

When returning to “L”, the output mute releases.

7

CSN I Chip Select in Serial Control Mode

SD Digital Filter setting pin in Parallel Control mode

8 CAD0 I Chip Address 0 in Serial Control Mode (Internal pull-down pin)

DEM0 I De-emphasis Enable 0 in Parallel Control Mode

9 CCLK I Control Data Clock in Serial Control Mode

DEM1 I De-emphasis Enable 1 in Parallel Control Mode

10 CDTI I Control Data Input in Serial Control Mode

DIF0 I Digital Input Format 0 in PCM Mode

11 CAD1 I Chip Address 1 in Serial Control Mode

DIF1 I Digital Input Format 1 in PCM Mode

12 DZF1 O Zero Input Detect in Serial Control Mode

13 DIF2 I Digital Input Format 2 in PCM Mode

14 PSN I Parallel/Serial Select (Internal pull-up pin)

“L”: Serial Control Mode, “H”: Parallel Control Mode

ACKS I

Auto Clock Setting Mode in Parallel Control mode

“L”: Manual Setting Mode, “H”: Auto Setting Mode

15

DZF2 O Zero Input Detect in Serial Control Mode

16 TDM0 I TDM I/F Format Mode in Parallel Control mode

17 SLOW I Digital filter setting pin

18 TEST - No internal bonding.

Connect to DVSS.

19 VCM2 - Common Voltage 2

Normally connected to VSS with a 10uF electrolytic cap.

20 AOUTR2P O Right Channel Positive Analog Output 2

21 AOUTR2N O Right Channel Negative Analog Output 2

22 VDD2 - Analog Power Supply, 4.75 to 5.25V

23 VSS2 - Ground (connected to DVSS, AVSS, VSS1 ground)

24 VREFL2 I Low Level Voltage Reference Input 2

25 VREFH2 I High Level Voltage Reference Input 2

26 AOUTL2N O Left Channel Negative Analog Output 2

27 AOUTL2P O Left Channel Positive Analog Output 2

28 NC - No internal bonding.

Connect to GND.

[AK4414]

MS1476-E-01 2013/01

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No. Pin Name I/O Function

29 AOUTR1P O Right Channel Positive Analog Output 1

30 AOUTR1N O Right Channel Negative Analog Output 1

31 VREFH1 I High Level Voltage Reference Input 1

32 VREFL1 I Low Level Voltage Reference Input 1

33 VSS1 - Connected to DVSS, AVSS, VSS2 Ground

34 VDD1 - Analog Power Supply Pin, 4.75 ∼ 5.25V

35 AOUTL1N O Left Channel Negative Analog Output 1

36 AOUTL1P O Left Channel Positive Analog Output 1

37 VCM1 - Common Voltage 1

Normally connected to VSS with a 10uF electrolytic cap.

38 TSTO1 I Test Output pin. “Hi-Z” at Normal Operation.

Connect to AVSS.

39 TSTO2 I Test Output pin. “Hi-Z” at Normal Operation.

Connect to AVSS.

40 AVDD - Analog Power Supply, 2.7 to 3.6V

41 AVSS - Analog Ground Pin

42 MCLK I Master Clock Input

43 DVSS - Digital Ground Pin

44 DVDD - Digital Power Supply, 3.0 ∼ 3.6V

Note: All input pins except internal pull-up/down pins should not be left floating.

[AK4414]

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■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

(1) Parallel Mode (PCM Mode only)

Classification Pin Name Setting

AOUTL1P, AOUTL1N These pins must be open.

AOUTR1P, AOUTR1N These pins must be open.

AOUTL2P, AOUTL2N These pins must be open.

Analog

AOUTR2P, AOUTR2N These pins must be open.

Analog TSTO1,TSTO2 This pin must be connected to AVSS

Digital TEST This pin must be connected to DVSS

(2) Serial Mode

1. PCM Mode

Classification Pin Name Setting

AOUTL1P, AOUTL1N These pins must be open.

AOUTR1P, AOUTR1N These pins must be open.

AOUTL2P, AOUTL2N These pins must be open.

Analog

AOUTR2P, AOUTR2N These pins must be open.

Analog TSTO1,TSTO2 This pin must be connected to AVSS

DIF2,PSN,TDM0,SLOW,TEST This pin must be connected to DVSS

Digital DZF1, DZF2 These pins must be open.

2. DSD Mode

Classification Pin name Setting

AOUTL1P, AOUTL1N These pins must be open.

AOUTR1P, AOUTR1N These pins must be open.

AOUTL2P, AOUTL2N These pins must be open.

Analog

AOUTR2P, AOUTR2N These pins must be open.

Analog TSTO1,TSTO2 This pin must be connected to AVSS

DIF2,PSN,TDM0,SLOW,TEST This pin must be connected to DVSS

Digital DZF1, DZF2 These pins must be open.

[AK4414]

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ABSOLUTE MAXIMUM RATINGS

(VSS1-2=AVSS =DVSS =0V; Note 1)

Parameter Symbol min max Unit

Power Supplies:

Analog

Digital

|AVSS − DVSS|

AVDD

VDD1/2

DVDD

ΔGND

−0.3

-

4.6

6.0

4.6

0.3

V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Digital Input Voltage VIND −0.3 DVDD+0.3 V

Ambient Temperature (Power applied) Ta −10 70 °C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. AVSS, VSS1/2, DVSS must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1-2=AVSS =DVSS =; Note 1)

Parameter Symbol min typ max Unit

Power Supplies

(Note 3)

Analog

Digital

AVDD

VDD1/2

DVDD

2.7

4.75

2.7

3.0

5.0

3.0

3.6

5.25

3.6

V

Voltage

Reference

(Note 4)

“H” voltage reference

“L” voltage reference

VREFH1

VREFH2

VREFL1

VREFL2

VDD1−0.5

VDD2-0.5

-

AVSS

VDD1

VDD2

-

V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD, VDD1/2 and DVDD is not critical.

Note 4. The analog output voltage scales with the voltage of (VREFH1/2 − VREFL1/2).

Connect a resistor of 20ohm or less and a capacitor of 100uF or more to the VREFH1/2 pin. (Figure 24)

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH1/2 − VREFL1/2)/5.

* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

[AK4414]

MS1476-E-01 2013/01

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ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=DVDD=3.0V, VDD1/2=5.0V; AVSS=VSS1/2=DVSS=0V; VREFH1/2=VDD1/2, VREFL1/2=

AVSS; Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;

Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 27; unless otherwise specified.)

Parameter min typ max Unit

Resolution - - 24 Bits

Dynamic Characteristics (Note 5)

fs=44.1kHz

BW=20kHz

0dBFS

−60dBFS

-

-107

-57

-98

-

dB

fs=96kHz

BW=40kHz

0dBFS

−60dBFS

-

-104

-54

-

dB

THD+N

fs=192kHz

BW=40kHz

BW=80kHz

0dBFS

−60dBFS

-104

-54

-51

-

dB

Dynamic Range (−60dBFS with A-weighted) (Note 6) 113 120 dB

S/N (A-weighted) (Note 7) 113 120 dB

Interchannel Isolation (1kHz) 100 110 dB

DC Accuracy

Interchannel Gain Mismatch - 0 0.3 dB

Gain Drift (Note 8) - 20 - ppm/°C

Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Vpp

Load Capacitance - - 10 pF

Load Resistance (Note 10) 1 - - kΩ

Power Supplies

Power Supply Current

Normal operation (PDN pin = “H”)

VDD1+VDD2

AVDD

DVDD (fs ≤ 44.1kHz)

DVDD (fs=96kHz)

DVDD (fs = 192kHz)

-

41

1

7

12

18

60

1.5

11

18

27

mA

Power down (PDN pin = “L”) (Note 11)

AVDD+VDD1/2+DVDD

-

10

100

μA

Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.

Note 6. Figure 27 External LPF Circuit Example 2. 100dB for 16-bit data.

Note 7. Figure 27 External LPF Circuit Example 2. S/N does not depend on input data size.

Note 8. The voltage on (VREFH1/2 − VREFL1/2) is held +5V externally.

Note 9. Full scale voltage (0dB). Output voltage scales with the voltage of (VREFH1/2 − VREFL1/2).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH1/2 − VREFL1/2)/5.

Note 10. Regarding Load Resistance, AC load is 1kΩ (min) with a DC cut capacitor (Figure 27). DC load is 1.5 kΩ (min)

without a DC cut capacitor (Figure 26). The load resistance value is with respect to ground. Analog

characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load

must be minimized.

Note 11. In the power down mode. The PSN pin = DVDD, and all other digital input pins including clock pins

(MCLK, BICK and LRCK) are held DVSS.

[AK4414]

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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

22.05

20.0

-

kHz

Stopband (Note 12) SB 24.1 - kHz

Passband Ripple PR -0.0032 - 0.0032 dB

Stopband Attenuation SA 80 - - dB

Group Delay (Note 13) GD - 29 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz -0.2 - 0.2 dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

48.0

43.5

-

kHz

Stopband (Note 12) SB 52.5 - kHz

Passband Ripple PR -0.0032 - 0.0032 dB

Stopband Attenuation SA 80 - - dB

Group Delay (Note 13) GD - 29 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz -0.3 - 0.3 dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”.

SD bit=“0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

96.0

87.0

-

kHz

Stopband (Note 12) SB 105 - kHz

Passband Ripple PR -0.0032 - 0.0032 dB

Stopband Attenuation SA 80 - - dB

Group Delay (Note 13) GD - 29 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz -1 - 0.1 dB

Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs, SB=0.546×fs.

Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24/32bit data

of both channels to input register to the output of analog signal.

[AK4414]

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SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”,

SD bit = “0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 14)

±0.04dB

−3.0dB

PB

0

-

18.2

8.1

-

kHz

Stopband (Note 14) SB 39.2 - kHz

Passband Ripple PR -0.043 - 0.043 dB

Stopband Attenuation SA 73 - - dB

Group Delay (Note 13) GD - 6 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz -5 - 0.1 dB

SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode DEM=OFF; SLOW bit=“1”,

SD bit = “0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 14)

±0.04dB

−3.0dB

PB

0

-

39.6

17.7

-

kHz

Stopband (Note 14) SB 85.3 - - kHz

Passband Ripple PR -0.043 - 0.043 dB

Stopband Attenuation SA 73 - - dB

Group Delay (Note 13) GD - 6 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz -4 - 0.1 dB

SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”,

SD bit = “0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 14)

±0.04dB

−3.0dB

PB

0

-

79.1

35.5

-

kHz

Stopband (Note 14) SB 171 - - kHz

Passband Ripple PR -0.043 - 0.043 dB

Stopband Attenuation SA 73 - - dB

Group Delay (Note 13) GD - 6 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz -5 - 0.1 dB

Note 14. The passband and stopband frequencies scale with fs. For example, PB=0.185×fs, SB=0.888×fs.

[AK4414]

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SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

22.05

20.0

-

kHz

Stopband (Note 12) SB 24.1 - - kHz

Passband Ripple PR -0.0031 - 0.0031 dB

Stopband Attenuation SA 80 - - dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 20.0kHz -0.2 - 0.2 dB

SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

48.0

43.5

-

kHz

Stopband (Note 12) SB 52.5 - - kHz

Passband Ripple PR -0.0031 - 0.0031 dB

Stopband Attenuation SA 80 - - dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 40.0kHz -0.3 - 0.3 dB

SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

96.0

87.0

-

kHz

Stopband (Note 12) SB 105 - - kHz

Passband Ripple PR -0.0031 - 0.0031 dB

Stopband Attenuation SA 80 - - dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 80.0kHz -1 - 0.1 dB

[AK4414]

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SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “1”,

SD bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

22.3

11.1

-

kHz

Stopband (Note 12) SB 38.1 - - kHz

Passband Ripple PR -0.05 - 0.05 dB

Stopband Attenuation SA 82 - - dB

Group Delay (Note 13) GD - 5.5 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 20.0kHz -5 - 0.1 dB

SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “1”,

SD bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

44.6

24.2

-

kHz

Stopband (Note 12) SB 83.0 - - kHz

Passband Ripple PR -0.05 - 0.05 dB

Stopband Attenuation SA 82 - dB

Group Delay (Note 13) GD - 5.5 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 40.0kHz -5 - 0.1 dB

SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”,

SD bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 12)

±0.01dB

−6.0dB

PB

0

-

89.2

48.4

-

kHz

Stopband (Note 12) SB 165.9 - - kHz

Passband Ripple PR -0.05 - 0.05 dB

Stopband Attenuation SA 82 - - dB

Group Delay (Note 13) GD - 5.5 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 80.0kHz -5 - 0.1 dB

[AK4414]

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DC CHARACTERISTICS

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V)

Parameter Symbol min typ max Unit

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

70%DVDD

-

30%DVDD

V

High-Level Output Voltage (Iout=−100μA)

Low-Level Output Voltage (Iout=100μA)

VOH

VOL

DVDD−0.5

-

0.5

V

Input Leakage Current (Note 15) Iin - - ±10 μA

Note 15. The PSN pin has an internal pull-up device nominally 100kΩ. Therefore the PSN pin is not included.

[AK4414]

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SWITCHING CHARACTERISTICS

(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V)

Parameter Symbol min typ max Unit

Master Clock Timing

Frequency

Duty Cycle

fCLK

dCLK

2.048

40

41.472

60

MHz

%

LRCK Frequency (Note 16)

Normal Mode (TDM0= “L”, TDM1= “L”)

1152fs, 512fs or 768fs

256fs or 384fs

128fs or 192fs

Duty Cycle

fsn

fsd

fsq

Duty

8

54

108

45

54

108

216

55

kHz

%

TDM256 mode (TDM0= “H”, TDM1= “L”)

Normal Speed Mode High time

Low time

fsn

tLRH

tLRL

8

1/256fs

54

kHz

ns

TDM128 mode (TDM0= “H”, TDM1= “H”)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

High time

Low time

fsn

fsd

fsq

tLRH

tLRL

8

54

108

1/128fs

54

108

216

kHz

ns

PCM Audio Interface Timing

Normal Mode (TDM0= “L”, TDM1= “L”)

BICK Period

1152fs, 512fs or 768fs

256fs or 384fs

128fs or 192fs

BICK Pulse Width Low

BICK Pulse Width High

BICK “↑” to LRCK Edge (Note 17)

LRCK Edge to BICK “↑” (Note 17)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fsn

1/64fsd

1/64fsq

14

5

ns

TDM256 mode (TDM0= “H”, TDM1= “L”)

BICK Period

Normal Speed Mode

BICK Pulse Width Low

BICK Pulse Width High

BICK “↑” to LRCK Edge (Note 17)

LRCK Edge to BICK “↑” (Note 17)

SDATA1/2 Hold Time

SDATA1/2 Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/256fsn

14

5

ns

[AK4414]

MS1476-E-01 2013/01

- 15 -

TDM128 mode (TDM0= “H”, TDM1= “H”)

BICK Period

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

BICK Pulse Width Low

BICK Pulse Width High

BICK “↑” to LRCK Edge (Note 17)

LRCK Edge to BICK “↑” (Note 17)

SDATA1/2 Hold Time

SDATA1/2 Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fsn

1/128fsd

1/128fsq

14

5

ns

DSD Audio Interface Timing

DCLK Period

DCLK Pulse Width Low

DCLK Pulse Width High

DCLK Edge to DSDL1/R1/L2/R2 (Note 18)

tDCK

tDCKL

tDCKH

tDDD

-

160

−20

1/64fs

-

20

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

50

150

50

ns

Reset Timing

PDN Pulse Width (Note 19)

tPD

150

ns

Note 16. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4414 should be reset by the

PDN pin or RSTN bit.

Note 17. BICK rising edge must not occur at the same time as LRCK edge.

Note 18. DSD data transmitting device must meet this time.

Note 19. The AK4414 can be reset by bringing the PDN pin “L” to “H” upon power-up.

[AK4414]

MS1476-E-01 2013/01

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■ Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

dCLK=tCLKH x fCLK, tCLKL x fCLK

1/fs

VIH

LRCK VIL

tLRLtLRH Dut

y

=tL

R

H x fs, tL

R

L x fs

tBCK

tBCKL

VIH

tBCKH

BICK VIL

Clock Timing

tLRB

LRCK

VIH

BICK VIL

tSDS

VIH

SDATA1/2 VIL

tSDH

VIH

VIL

tBLR

Audio Interface Timing (PCM Mode)

[AK4414]

MS1476-E-01 2013/01

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VIH

DCLK VIL

tDDD

VIH

DSDL 1/2

DSDR1/2 VIL

tDCKHtDCKL

tDCK

tDDD

VIH

DSDL1 /2

DSDR1/2 VIL

Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)

VIH

DCLK VIL

tDDD

VIH

DSDL 1/2

DSDR1/2 VIL

tDCKHtDCKL

tDCK

tDDD

VIH

DSDL1 /2

DSDR1/2 VIL

tDDD

Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

[AK4414]

MS1476-E-01 2013/01

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tCSS

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

WRITE Data Input Timing

tPD

PDN VIL

Power Down & Reset Timing

[AK4414]

MS1476-E-01 2013/01

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OPERATION OVERVIEW

■ D/A Conversion Mode

In serial mode, the AK4414 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls

PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,

PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4414

should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4414 performs for

only PCM data.

DP bit Interface

0 PCM

1 DSD

Table 1. PCM/DSD Mode Control

■ System Clock

[1] PCM Mode

The external clocks, which are required to operate the AK4414, are MCLK, BICK and LRCK. MCLK should be

synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the

delta-sigma modulator.

The AK4414 is automatically placed in reset state when MCLK and LRCK are stopped during a normal operation (PDN

pin =“H”), and the analog output becomes AVDD/2 (typ). When MCLK and LRCK are input again, the AK4414 exit

reset state and starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the

AK4414 is in power-down mode until MCLK and LRCK are supplied.

(1) Parallel Mode (PSN pin = “H”)

1. Manual Setting Mode

In manual setting mode (ACKS pin = “L”) only Normal Speed mode is supported with the sample rate range shown in

Table 2. The AK4414 automatically configures itself to operate with the supported MCLK frequencies which are required

to be provided as input and are shown in Table 3.

Sampling Rate (fs)

Normal Speed Mode 8kHz ∼ 54kHz

Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)

LRCK MCLK (MHz) BICK

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz

Table 3. System Clock Example (Manual Setting Mode @Parallel Mode), (N/A: Not available)

[AK4414]

MS1476-E-01 2013/01

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2. Auto Setting Mode (ACKS pin = “H”)

In this mode, sampling speed and MCLK frequency are detected automatically (Table 4). The MCLK must be supplied at

correct frequency according to the Table 5.

MCLK Sampling Speed

1152fs Normal (fs≤32kHz)

512fs 768fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz N/A N/A (8.1920*) (12.2880*) 16.3840 24.5760 36.8640

44.1kHz N/A N/A (11.2896*) (16.9344*) 22.5792 33.8688 N/A

48.0kHz N/A N/A (12.2880*) (18.4320*) 24.5760 36.8640 N/A

Normal/

(Double*)

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

Double

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Quad

Table 5. System Clock Example (Auto Setting Mode @Parallel Mode), (N/A: Not available)

MCLK= 256fs/384fs supports sampling rate of 32kHz~96kHz (Table 6). However, when the sampling rate is

32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

ACKS pin MCLK DR,S/N

L 256fs/384fs/512fs/768fs 120dB

H 256fs/384fs 117dB

H 512fs/768fs 120dB

Table 6. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)

3. Digital Filter Setting

SD pin SLOW pin Mode

0 0 Sharp roll-off filter

0 1 Slow roll-off filter

1 0 Short delay sharp roll-off

1 1 Short delay slow roll-off

Table 7. Digital Filter Setting (Parallel Mode)

[AK4414]

MS1476-E-01 2013/01

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(2) Serial Mode (PSN pin = “L”)

1. Manual Setting Mode (ACKS bit = “0”)

MCLK frequency is detected automatically and the sampling rate is set by DFS1-0 bits (Table 8). The MCLK frequency

corresponding to each sampling speed should be provided externally (Table 9). The AK4414 is set to Manual Setting

Mode at power-up (PDN pin = “L” →“H”). When DFS1-0 bits are changed, the AK4414 should be reset by RSTN bit.

DFS1 bit DFS0 bit Sampling Rate (fs)

0 0 Normal Speed Mode 30kHz ∼ 54kHz

0 1 Double Speed Mode 54kHz ∼ 108kHz

1 0 Quad Speed Mode

120kHz ∼ 216kHz

(default)

Table 8. Sampling Speed (Manual Setting Mode @Serial Mode)

LRCK MCLK (MHz) BICK

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz

88.2kHz 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A 5.6448MHz

96.0kHz 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A 6.1440MHz

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A 11.2896MHz

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A 12.2880MHz

Table 9. System Clock Example (Manual Setting Mode @Serial Mode)

2. Auto Setting Mode (ACKS bit = “1”)

MCLK frequency and the sampling speed are detected automatically (Table 10) and DFS1-0 bits are ignored. The MCLK

frequency corresponding to each sampling speed should be provided externally (Table 11).

MCLK Sampling Speed

1152fs Normal (fs≤32kHz)

512fs 768fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 10. Sampling Speed (Auto Setting Mode @Serial Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz N/A N/A (8.1920*) (12.2880*) 16.3840 24.5760 36.8640

44.1kHz N/A N/A (11.2896*) (16.9344*) 22.5792 33.8688 N/A

48.0kHz N/A N/A (12.2880*) (18.4320*) 24.5760 36.8640 N/A

Normal/

(Double*)

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

Double

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Quad

Table 11. System Clock Example (Auto Setting Mode @Serial Mode)

[AK4414]

MS1476-E-01 2013/01

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MCLK= 256fs/384fs supports sampling rate of 32kHz~96kHz (Table 12). However, when the sampling rate is

32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

ACKS pin MCLK DR,S/N

L 256fs/384fs/512fs/768fs 120dB

H 256fs/384fs 117dB

H 512fs/768fs 120dB

Table 12. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)

3. Digital Filter Setting

SD bit SLOW bit Mode

0 0 Sharp roll-off filter

0 1 Slow roll-off filter

1 0 Short delay sharp roll-off (default)

1 1 Short delay slow roll-off

Table 13. Digital Filter Setting (Serial Mode)

[2] DSD Mode

The external clocks, which are required to operate the AK4414, are MCLK and DCLK. MCLK should be synchronized

with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.

The AK4414 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),

and the analog output becomes AVDD/2 voltage (typ).

DCKS bit MCLK Frequency DCLK Frequency

0 512fs 64fs (default)

1 768fs 64fs

Table 14. System Clock (DSD Mode)

[AK4414]

MS1476-E-01 2013/01

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■ Audio Interface Format

[1] PCM Mode

(1) Parallel Control Mode (PSN pin = “H”)

Twenty formats are selectable by DIF1-0 and TDM2-0 pins (Table 15). In this mode, register settings are ignored. In all

formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used

for 20 and 16 MSB justified formats by zeroing the unused LSBs.

If TDM1-0 pins = “LH” the audio interface is TDM256 mode (Table 15) and all eight channels of DAC data are input to

the SDTI1 pin. The input data to the SDTI2 pin is ignored. BICK is fixed to 256fs, “H” time and “L” time of LRCK should

be 1/256fs at least. The data format is MSB first, 2’s complement and the SDTI1 is latched on the rising edge of BICK.

Only the first four channels of DAC data may be selected to be converted into four channels of DAC analog output.

If TDM1-0 pins = “HH” the audio interface is TDM128 mode (Table 15) and the serial data of DAC (four channels: L1,

R1, L2, R2) is input to the SDTI1 pin.

Mode TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK BICK

0 0 0 0 16-bit LSB justified H/L ≥32fs

1 0 0 1 20-bit LSB justified H/L

≥40fs

2 0 1 0 24-bit MSB justified H/L ≥48fs

3 0 1 1 24-bit I2S compatible L/H ≥48fs

4 1 0 0 24-bit LSB justified H/L

≥48fs

5 1 0 1 32-bit LSB justified H/L

≥64fs

6 1 1 0 32-bit MSB justified H/L ≥64fs

Normal

7

- 0

1 1 1 32-bit I2S compatible L/H ≥64fs

0 0 0 N/A

0 0 1 N/A

8 0 1 0 24-bit MSB justified ↑ 256fs

9 0 1 1 24-bit I2S compatible ↓ 256fs

10 1 0 0 24-bit LSB justified

↑ 256fs

11 1 0 1 32-bit LSB justified

↑ 256fs

12 1 1 0 32-bit MSB justified ↑ 256fs

TDM256

13

0 1

1 1 1 32-bit I2S compatible ↓ 256fs

0 0 0 N/A

0 0 1 N/A

14 0 1 0 24-bit MSB justified ↑ 128fs

15 0 1 1 24-bit I2S compatible ↓ 128fs

16 1 0 0 24-bit LSB justified

↑ 128fs

17 1 0 1 32-bit LSB justified

↑ 128fs

18 1 1 0 32-bit MSB justified ↑ 128fs

TDM128

19

1 1

1 1 1 32-bit I2S compatible ↓ 128fs

Table 15. Audio Interface Format (Parallel mode)

[AK4414]

MS1476-E-01 2013/01

- 24 -

(2) Serial Control Mode (PSN pin = “L”)

Twenty formats are selected by setting DIF2-0 and TDM1-0 bits (Table 16). The initial setting of DIF2-0 bits is “010”. In

this mode, the DIF1 pin setting is ignored.

The audio I/F format is TDM256 mode (Table 16) and all the serial data of eight DAC channels are input to the SDTI1 pin

(Figure 15). The input data to the SDTI2 pin is ignored. BICK is fixed to 256fs, high and low amplitude of LRCK is

1/256fs (min). The data format is MSB first, 2’s complement and the SDTI1 is latched on the rising edge of BICK. The

eight channels of DAC data may be mapped to two pieces of AK4414 (Table 17).

In TDM128 mode, the serial data of DAC (four channels: L1, R1, L2, R2) is input to the SDTI1 pin and other serial data

of DAC (four channels: L3, R3, L4, R4) are input to the SDTI2 pin (Figure 14). BICK is fixed to 128fs. The data format is

MSB first and 2’s complement and the input data to SDTI1-2 pins are latched on the rising edge of BICK. The eight

channels of DAC data may be mapped to two pieces of AK4414 (Table 17).

Mode TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK BICK

0 0 0 0 16-bit LSB justified H/L

≥32fs

1 0 0 1 20-bit LSB justified H/L

≥40fs

2 0 1 0 24-bit MSB justified H/L ≥48fs

3 0 1 1 24-bit I2S compatible L/H ≥48fs

4 1 0 0 24-bit LSB justified H/L

≥48fs

5 1 0 1 32-bit LSB justified H/L

≥64fs

6 1 1 0 32-bit MSB justified H/L ≥64fs

Normal

7

- 0

1 1 1 32-bit I2S compatible L/H ≥64fs

0 0 0 N/A

0 0 1 N/A

8 0 1 0 24-bit MSB justified ↑ 256fs

9 0 1 1 24-bit I2S compatible ↓ 256fs

10 1 0 0 24-bit LSB justified

↑ 256fs

11 1 0 1 32-bit LSB justified

↑ 256fs

12 1 1 0 32-bit MSB justified ↑ 256fs

TDM256

13

0 1

1 1 1 32-bit I2S compatible ↓ 256fs

0 0 0 N/A

0 0 1 N/A

14 0 1 0 24-bit MSB justified ↑ 128fs

15 0 1 1 24-bit I2S compatible ↓ 128fs

16 1 0 0 24-bit LSB justified

↑ 128fs

17 1 0 1 32-bit LSB justified

↑ 128fs

18 1 1 0 32-bit MSB justified ↑ 128fs

TDM128

19

1 1

1 1 1 32-bit I2S compatible ↓ 128fs

Table 16. Audio Interface Format (Serial mode)

[AK4414]

MS1476-E-01 2013/01

- 25 -

SDATA1/2

BICK

LRCK

SDATA1/2 15 14 6 5 4

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3 2 1 0 15 14

(

32fs

)

(

64fs

)

0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1

15 14 0 15 14 0

Mode 0 D o n ’ t care Don’t care

15 :MSB, 0 :L SB

Mode 0 15 14 6 5 4 3 2 1 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

SDATA1/2

LRCK

BICK

(64fs)

0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

Mode 1 Do n’t care Don’t care

19:MSB, 0:LSB

SDATA1/2

Mode 4 23:MSB , 0:LSB

20 19 0 20 19 0 Don’t care Don’ t care

22 21 22 21

Lch D ata Rch Data

8

23 23

8

Figure 2. Mode 1/4 Timing

LRCK

BICK

(64fs)

SDATA1/2

0 22 1 2 24 31 0 1 31 0 1

23:MSB , 0:LSB

22 1 0 Don’t care 23

Lch D ata Rch Data

23 30 2222423 30

22 1 0 Don’t care 23 2223

Figure 3. Mode 2 Timing

[AK4414]

MS1476-E-01 2013/01

- 26 -

LRCK

BICK

(

64fs

)

SDATA1/2

0 3 1 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t car e 23

Lch Data Rch Da ta

23 25 32 24 23 25

22 1 0 Don’t care 23 23

Figure 4. Mode 3 Timing

LRCK

BICK

(

64fs

)

SDATA1/2

0 22 1 2 24 31 0 1 31 0 1

32:MSB , 0:LSB

30 1 031

Lch D ata Rch Data

23 30 2222423 30

30 1 0 31 3031

Mode 5,6

Figure 5. Mode 5/6 Timing

LRCK

BICK

(

64fs

)

SDATA1/2

0 31 2 24 31 0 1 31 0 1

32:MSB , 0:LSB

30 1 031

Lch Data Rc h Data

23 25 3 2 2423 25

30 1 0 31 3031

Figure 6. Mode 7 Timing

[AK4414]

MS1476-E-01 2013/01

- 27 -

23

LRCK

BICK (256fs)

22 0

L1

32 BICK

256 BICK

22 0

R1

32 BICK

2223 2322 0

L2

32 BICK

22 0

R2

32 BICK

23 23

SDATA1

31 30 0 303131 30 0 31 30 031 30 0

SDATA1

Mode8

Mode11,12

23 22 0

L3

32 BICK

22 0

R3

32 BICK

23 22 0

L4

32 BICK

22 0

R4

32 BICK

23 23

31 30 031 30 031 30 0 31 30 0

Figure 7. Mode 8/11/12 Timing

LRCK

BICK (256fs)

23 0

L1

32 BICK

256 BICK

23 0

R1

32 BICK

2323 0

L2

32 BICK

23 0

R2

32 BICK

SDATA1

Mode9

31 0 3130 31 0 30 31 030 31 030

SDATA1

Mode13

23 0

L3

32 BICK

23 0

R3

32 BICK

23 0

L4

32 BICK

23 0

R4

32 BICK

31 030 31 030 31 0 30 31 030

Figure 8. Mode 9/13 Timing

LRCK

BICK(256fs)

SDATA

256 BICK

22 0

L1

32 BICK

22 0

R1

32 BICK

22 0

L2

32 BICK

22 0

R2

32 BICK

23 23 23 23 23

22 0

L3

32 BICK

22 0

R3

32 BICK

22 0

L4

32 BICK

22 0

R4

32 BICK

23 23 23 23

Figure 9. Mode 10 Timing

[AK4414]

MS1476-E-01 2013/01

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LRCK

BICK(128fs)

128 BICK

L1

32 BICK R1

32 BICK

L2

32 B ICK R2

32 BICK

SDATA 22 0 22 022 022 0 23 23 23 23 2223

Mode14

SDATA 30 0 30 030 030 031 31 31 31 3031

Mode17,18

Figure 10. Mode 14/17/18 Timing

LRCK

BICK(128fs)

128 BICK

L1

32 B ICK R1

32 BICK L2

32 BICK R2

32 BICK

SDATA1 22 0 22 022 022 0 23 23 23 23 23

SDATA1

Mode15

Mode19 30 0 30 030 030 0

31 31 31 31 331

Figure 11. Mode 15/19 Timing

LRCK

BICK(128fs)

128 BIC K

L1

32 BICK R1

32 BICK L2

32 BICK R2

32 BICK

SDATA 22 0 22 022 022 023 23 23 23 23

Figure 12. Mode 16 Timing

[AK4414]

MS1476-E-01 2013/01

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One data cycle of SDATA1 and SDATA2 for each format are defined as below. SDS2-1 bits control playback channel of

each DAC.

LRCK

SDATA1 R1L1

SDATA2

R

2L2

Figure 13. Data Slot in Normal Mode

SDATA1 R1L1

SDATA2

LRCK

128 BICK

R

2 L2

R3

L3

R

4 L4

Figure 14. Data Slot in TDM128 Mode

SDATA1 R1 L1

LRCK

256 BICK

R2L2 R3L3 R4 L4

Figure 15. Data Slot in TDM256 Mode

AK4414 Data Select

DAC1 DAC2

SDS1 SDS2 Lch Rch Lch Rch

0 0 L1 R1 L2 R2

0 1 L1 R1 L1 R1

1 0 L2 R2 L2 R2

Normal

1 1 L2 R2 L1 R1

0 0 L1 R1 L2 R2

0 1 L1 R1 L4 R4

1 0 L3 R3 L2 R2

TDM128

1 1 L3 R3 L4 R4

0 0 L1 R1 L2 R2

0 1 L1 R1 L4 R4

1 0 L3 R3 L2 R2

TDM256

1 1 L3 R3 L4 R4

Table 17. Data Select

[AK4414]

MS1476-E-01 2013/01

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[2] DSD Mode

In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can

invert the polarity of DCLK.

DCLK (64fs)

DCKB=1

DCLK (64fs)

DCKB=0

DSDL,DSDR

Normal

DSDL,DSDR

Phase M odulation

D1

D0 D1 D2

D0 D2 D3

D1 D2 D3

Figure 16. DSD Mode Timing

■ D/A Conversion Mode Switching Timing

RSTN bit

D/A Data

D/A Mode

≥4/fs

≥0

PCM Data DSD Data

P CM M ode DSD Mode

Figure 17. D/A Mode Switching Timing (PCM to DSD)

RSTN bit

D/A Data

D/A Mode

≥4/fs

DSD Data PCM Da ta

DSD Mode PCM Mode

Figure 18. D/A Mode Switching Timing (DSD to PCM)

Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty

range at the SACD format book (Scarlet Book).

[AK4414]

MS1476-E-01 2013/01

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■ De-emphasis Filter

A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or

disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is

always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are

switched.

[1] Parallel Mode

The DEM1 and DEM0 pins control de-emphasis mode of DAC1 and DAC2. This setting is common for both of DAC’s.

In parallel mode, the filter setting cannot be applied independently.

DEM1 DEM0 Mode

L L 44.1kHz

L H OFF (default)

H L 48kHz

H H 32kHz

Table 18. De-emphasis Control (Parallel Mode)

[2] Serial Mode

DEM1-0 bits and DEM3-2 bits control de-emphasis mode of DAC1 and DAC2, respectively. DEM3-0 bits settings are

invalid in DSD mode. The register settings are maintained when switching the mode between PCM and DSD modes.

DEM1 DEM0 Mode

0 0 44.1kHz

0 1 OFF (default)

1 0 48kHz

1 1 32kHz

Table 19. DAC1 De-emphasis Control (Serial Mode)

DEM3 DEM2 Mode

0 0 44.1kHz

0 1 OFF (default)

1 0 48kHz

1 1 32kHz

Table 20. DAC2 De-emphasis Control (Serial Mode)

■ Output Volume

The AK4414 includes channel independent digital output volumes (ATT) with 255 levels at 0.5dB step including MUTE.

This volume control is in front of the DAC and it can attenuate the input data from 0dB to –127dB and mute. When

changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions. It

takes 7424/fs from FFH (0dB) to 00H (Mute). The attenuation level is reset to FFH (0dB) by initial reset. By RSTN bit =

“0”, the attenuation level is initialized to FFH, and the attenuation level returns to the setting value by RSTN bit = “1”.

Transition Time

Sampling Speed 0dB to MUTE

fs=44.1kHz 168.3ms

fs=96kHz 77.3ms

fs=192kHz 38.6ms

Table 21. ATT Transition Time

[AK4414]

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■ Zero Detection (PCM mode, DSD mode)

The AK4414 has channel-independent zeros detect function. When the input data at each channel is continuously zeros

for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to “L”

if the input data of each channel is not zero. If the RSTN bit is “0”, the DZF pins of both channels go to “H”. The DZF pins

of both channels go to “L” after 4 ~ 5/fs when RSTN bit returns to “1”. The DZFB bit can invert the polarity of the DZF

pin. In parallel control mode, the zero detect function is disabled.

Pin Comment

DZF1 Zero Detection flag output of the channels set by register 08H.

DZF2 Zero Detection flag output of the channels set by register 09H.

Table 22. DZF pin function

■ Mono Output

Input and output signal combination of the AK4414 can be set by MONO bit and SELLR bit. Monaural output mode is

enabled when MONO bit = “1”. The output signal phase of DAC is controlled by INVL and INVLR bits. These settings

are available for any audio format.

(L1/2 is the output signal of the AOUTL1N/2N and AOUTL1P/2P pins. R1/2 is the output signal of AOUTR1N/2N and

AOUTR1P/2P pins)

MONO bit SELLR1 bit INVL1 bit INVR1 bit L1

(AOUTL1N, AOUTL1P pins)

R1

(AOUTR1N, AOUTR1P pins)

0 0 L1 R1

1 0 L1 Invert R1

0 1 L1 R1 Invert

0 0

1 1 L1 Invert R1 Invert

0 0 R1 L1

1 0 R1 Invert L1

0 1 R1 L1 Invert

0 1

1 1 R1 Invert L1 Invert

0 0 L1 L1

1 0 L1 Invert L1

0 1 L1 L1ch In Invert

1 0

1 1 L1 Invert L1 Invert

0 0 R1 R1

1 0 R1 Invert R1

0 1 R1 R1 Invert

1 1

1 1 R1 Invert R1 Invert

Table 23. Output Select for DAC1

[AK4414]

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MONO bit SELLR2 bit INVL2 bit INVR2 bit L2

(AOUTL2N, AOUTL2P pins) R2

(AOUTR2N, AOUTR2P pins)

0 0 L2 R2

1 0 L2 Invert R2

0 1 L2 R2 Invert

0 0

1 1 L2 Invert R2 Invert

0 0 R2 L2

1 0 R2 Invert L2

0 1 R2 L2 Invert

0 1

1 1 R2 Invert L2 Invert

0 0 L2 L2

1 0 L2 Invert L2

0 1 L2 L2 Invert

1 0

1 1 L2 Invert L2 Invert

0 0 R2 R2

1 0 R2 Invert R2

0 1 R2 R2 Invert

1 1

1 1 R2 Invert R2 Invert

Table 24. Output Select for DAC2

[AK4414]

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■ Soft Mute Operation

The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,

the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the

SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation

gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before

attenuating −∞, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for

changing the signal source without stopping the signal transmission.

SM U T E pin or

SMU TE bit

A

ttenuation

D ZF pin

ATT_Level

-∞

A

OUT

8192/fs

GD GD

(1)

(2)

(3)

(4)

(1)

(2)

Notes:

(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in

Normal Speed Mode.

(2) The analog output corresponding to the digital input has group delay (GD).

(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued

and returned to ATT level by the same cycle.

(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel

goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.

Figure 19. Soft Mute Function

■ System Reset

The AK4414 should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register settings of the

device. The AK4414 exits this system reset (power-down mode) by MCLK after the PDN pin = “H”, and the analog block

exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK for 4/fs.

[AK4414]

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■ Power ON/OFF timing

The AK4414 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. The analog

outputs are floating (Hi-Z). Since a click noise occurs at the edge of the PDN pin signal, the analog output should be

muted externally if the click noise influences system application.

The DAC can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding

analog outputs go to VCM1/2. Since a click noise occurs at the edge of RSTN signal, the analog output should be muted

externally if click noise aversely affect system performance.

PDN pin

Power

Reset

Normal Operation

Clock In

MCLK,LRCK,BICK

DAC In

(Digital)

DAC Out

(Analog)

Ex ternal

Mute Mute ON

(6)

DZFL/DZFR

Don’t care

“0”data

GD

(2)

(4)

(5)

(7)

GD

(4)

Mute O N

“0”data

Don’t care

Internal

State

(3) (3)

(1)

Notes:

(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.

(2) The analog output corresponding to digital input has group delay (GD).

(3) Analog outputs are floating (Hi-Z) in power-down mode.

(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.

(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).

(6) Mute the analog output externally if click noise (3) adversely affect system performance

The timing example is shown in this figure.

(7) DZF1/2 pins are “L” in the power-down mode (PDN pin = “L”).

Figure 20. Power-down/up Sequence Example

[AK4414]

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■ Reset Function

(1) RESET by RSTN bit = “0”

When the RSTN bit = “0”, the AK4414’s digital block is powered down, but the internal register values are not initialized.

In this time, the analog outputs go to VCM1/2 voltage and DZF1/2 pins are “H”. Figure 21 shows an example of reset by

RSTN bit.

Internal

State

RSTN bit

Digital Bl ock

P

d

N ormal Operat ion

GD GD

“0 ” data

D/A Out

(Analog)

D/A I n

(Digital) (1) (3)

DZF

(3) (1)

(2)

Norm al Operation

2/fs(4)

Internal

RSTN bit

2~3/fs (5)3~4/fs (5)

(6)

Notes:

(1) The analog output corresponding to digital input has group delay (GD).

(2) Analog outputs settle to VCOM voltage.

(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”

data is input.

(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes

“1”.

(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the

internal RSTN bit “1”.

(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance

Figure 21. Reset Sequence Example 1

[AK4414]

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(2) RESET by MCLK or LRCK Stop

The AK4414 is automatically placed in reset state when MCLK or LRCK is stopped during PCM mode (RSTN pin

=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4414 exits reset state

and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4414 is in

reset state when MCLK is stopped.

Normal O per ati on

Internal

State Di gital Ci rc ui t Power -d own Normal Ope ra tion

GD GD

D/A Out

(Analog)

D/A In

(Digital)

Cl ock In

MCLK, LRCK

(2)

(3)

External

MUTE (6)

(5)

(2)

MC LK , LR C K St o p

RSTB pin

Power-down

(4) (4)

(4)

Hi-Z

(6)

(5)

(1)

AVDD pin

DVDD pin

(6)

Notes:

(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.

(2) The analog output corresponding to digital input has group delay (GD).

(3) The digital data can be stopped. Click noise after MCLK and LRCK are input again can be reduced by inputting

“0” data during this period.

(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This

noise occurs even when “0” data is input.

(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).

(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown

in this figure.

Figure 22. Reset Sequence Example 2

[AK4414]

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■ Register Control Interface

Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4414. In parallel control

mode, the register setting is ignored, and in serial control mode the pin settings are ORed if the pin is not repurposed.

When the state of the PSN pin is changed, the AK4414 should be reset by the PDN pin. The serial control interface is

enabled by the PSN pin = “L”. In this mode, pin settings must be all “L”. Internal registers may be written to

through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits,

C1/0), Read/Write (1-bit; fixed to “1”), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The

AK4414 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data

is valid when CSN “↑”. The clock speed of CCLK is 5MHz (max).

Function Parallel mode Serial mode

Auto Setting Mode Y Y

Manual Setting Mode Y Y

Audio Format Y Y

De-emphasis Y Y

SMUTE Y Y

TDM Mode Y (4-ch only) Y

Digital Filter Option Y Y

DSD Mode - Y

Zero Detection - Y

Digital Attenuator - Y

Table 25. Function List1 (Y: Available, -: Not available)

Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is

reset by the RSTN bit, but the registers are not initialized.

CDTI

CCLK

C1

012345678 9 10 11 12 13 14 15

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

CSN

C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)

R/W: READ/WRITE (Fixed to “1”, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 23. Control I/F Timing

* The AK4414 does not support the read command.

* When the AK4414 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control

registers is prohibited.

* The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is

“L”.

[AK4414]

MS1476-E-01 2013/01

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Function List

Function Default Address Bit PCM DSD

Attenuation Level 0dB

03H

04H

06H

07H

ATT7-0 Y Y

Audio Data Interface Modes 24bit MSB Justified 00H DIF2-0 Y -

Data Zero Detect Enable Disable 08H

09H L1/R1/L2/R2 Y Y

Minimum delay Filter Enable Y -

Slow Rolloff Filter Enable Y -

Short delay Filter Enable

Sharp roll-off filter 01H

02H

SD

SLOW Y -

De-emphasis Response OFF 01H

0AH DEM3-0 Y -

Soft Mute Enable Normal Operation 01H SMUTE Y Y

DSD/PCM Mode Select PCM mode 02H D/P Y Y

Master Clock Frequency Select at

DSD mode 512fs 02H DCKS - Y

MONO mode Stereo mode select Stereo 02H MONO Y Y

Inverting Enable of DZF “H” active 02H DZFB Y Y

The data selection of L channel and

R channel R channel 02H

05H SELLR1/2 Y Y

The data selection of DAC1 and

DAC2 Normal 0AH SDS1/2 Y -

Data Invert Mode OFF 05H INVL1/L2/R1/R2 Y Y

Table 26. Function List2 (Y: Available, -: Not available)

[AK4414]

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■ Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN

01H Control 2 0 0 SD DFS1 DFS0 DEM1 DEM0 SMUTE

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR1 SLOW

03H L1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H R1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 0 0

06H L2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

07H R2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

08H DZF1 Control L1 R1 L2 R2 0 0 0 0

09H DZF2 Control L1 R1 L2 R2 0 0 0 0

0AH Control 5 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM3 DEM2

Notes:

Data must not be written into addresses from 0BH to 1FH.

When the PDN pin goes to “L”, the registers are initialized to their default values.

When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default

values.

When the state of the PSN pin is changed, the AK4414 should be reset by the PDN pin.

■ Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN

Default 0 0 0 0 0 1 0 1

RSTN: Internal Timing Reset

0: Reset. All registers are not initialized.

1: Normal Operation (default)

Internal clock timings are reset but registers are not reset.

DIF2-0: Audio Data Interface Modes (Table 16)

Initial value is “010” (Mode 2: 24-bit MSB justified).

ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)

0: Disable : Manual Setting Mode (default)

1: Enable : Auto Setting Mode

When ACKS bit = “1”, the sampling frequency and MCLK frequency are detected automatically.

[AK4414]

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 0 0 SD DFS1 DFS0 DEM1 DEM0 SMUTE

Default 0 0 1 0 0 0 1 0

SMUTE: Soft Mute Enable

0: Normal Operation (default)

1: DAC outputs soft-muted.

DEM1-0: DAC1 De-emphasis Response (Table 19)

Initial value is “01” (OFF).

SD: Short delay Filter Enable. This setting is ORed with the pin setting.

0: Sharp roll-off filter

1: Short delay filter (default)

SD SLOW Mode

0 0 Sharp roll-off filter

0 1 Slow roll-off filter

1 0 Short delay sharp roll-off (default)

1 1 Short delay slow roll-off

Table 27. Digital Filter setting

DFS1-0: Sampling Speed Control (Table 8)

The default values are “00”. A click noise occurs when changing DFS1-0 bits.

[AK4414]

MS1476-E-01 2013/01

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR1 SLOW

Default 0 0 0 0 0 0 0 0

SLOW: Slow Roll-off Filter Enable. This setting is ORed with the pin setting.

0: (default)

1: Slow roll-off filter

SD SLOW Mode

0 0 Sharp roll-off filter

0 1 Slow roll-off filter

1 0 Short delay sharp roll-off (default)

1 1 Short delay slow roll-off

Table 28. Digital Filter setting

SELLR1: The data selection of L channel and R channel, when MONO mode

0: All channel output L channel data, when MONO mode. (default)

1: All channel output R channel data, when MONO mode.

It is enabled when MONO bit is “1”, and outputs Lch date to both channels when “0”,outputs Rch data to

both channels when “1”.

DZFB: Inverting Enable of DZF

0: DZF pin goes “H” at Zero Detection (default)

1: DZF pin goes “L” at Zero Detection

MONO: MONO mode Stereo mode select

0: Stereo mode (default)

1: MONO mode

When MONO bit is “1”, MONO mode is enabled.

DCKB: Polarity of DCLK (DSD Only)

0: DSD data is output from DCLK falling edge. (default)

1: DSD data is output from DCLK rising edge.

DCKS: Master Clock Frequency Select at DSD mode (DSD only)

0: 512fs (default)

1: 768fs

DP: DSD/PCM Mode Select

0: PCM Mode (default)

1: DSD Mode

When D/P bit is changed, the AK4414 should be reset by RSTN bit.

[AK4414]

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H L1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H R1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Default 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

255 levels, 0.5dB step

Data Attenuation

FFH 0dB

FEH -0.5dB

FDH -1.0dB

: :

02H -126.5dB

01H -127.0dB

00H MUTE (-∞)

The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from

FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH

when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is

independent of soft mute function.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 0 0

Default 0 0 0 0 0 0 0 0

SELLR2: The data selection of AOUTL2-R2, when MONO mode

0: AOUTL2-R2 output L channel data, when MONO mode. (default)

1: AOUTL2-R2 output R channel data, when MONO mode.

When MONO bit is set to “1”, Lch data is output by SELLR2 bit = “0” and Rch data is output by SELLR2

bit = “1”.

INVR2: AOUTR2 output phase invert bit

0: Disable (default)

1: Enable

INVL2: AOUTL2 output phase invert bit

0: Disable (default)

1: Enable

INVR1: AOUTR1 output phase invert bit

0: Disable (default)

1: Enable

INVL1: AOUTL1 output phase invert bit

0: Disable (default)

1: Enable

[AK4414]

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

06H L2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

07H R2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Default 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

255 levels, 0.5dB step

Data Attenuation

FFH 0dB

FEH -0.5dB

FDH -1.0dB

: :

02H -126.5dB

01H -127.0dB

00H MUTE (-∞)

The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from

FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH

when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is

independent of soft mute function.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

08H DZF1 Control L1 R1 L2 R2 0 0 0 0

09H DZF2 Control L1 R1 L2 R2 0 0 0 0

Default 0 0 0 0 0 0 0 0

L1-2, R1-2: Zero Detect Flag Enable Bit for the DZF1-2 pins

0: Disable

1: Enable

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

0AH Control 5 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM3 DEM2

Default 0 0 0 0 1 1 0 1

DEM3-2: DAC2 De-emphasis Response (Table 20)

Initial value is “01” (OFF).

PW2-1: Power Down control for DAC

PW2: Power management for DAC2

0: DAC2 power OFF

1: DAC2 power ON (default)

PW1: Power management for DAC1

0: DAC1 power OFF

1: DAC1 power ON (default)

SDS1-2: DAC1and DAC2 data select

0: Normal Operation

1: Outputs other slot data

Refer to Table 17 for details.

TDM0-1: TDM Mode Select

Mode TDM1 TDM0 BICK SDTI Sampling Speed

Normal 0 0 32fs∼ 1-2 Normal, Double, Quad Speed

TDM256 0 1 256fs fixed 1 Normal Speed

TDM128 1 1 128fs fixed 1-2 Normal, Double, Quad Speed

[AK4414]

MS1476-E-01 2013/01

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SYSTEM DESIGN

Figure 24 shows the system connection diagram. Figure 26, Figure 27 and Figure 28 show the analog output circuit

examples. The evaluation board (AKD4414) demonstrates the optimum layout, power supply arrangements and

measurement results.

Analog 5.0V

Cer amic Capaci tor

+Electrol

y

t ic Capacito

r

R1ch

LPF R1ch

Mute R1ch Out

Digital 3.0V

+

0.1u

10u

PDN

DVDD

1

BICK

44

2

SDATA1 3

SDATA2 4

TDM1

5

LRCK 6

SMUTE 7

SD8

DEM0

9

DEM1 10

DIF0 11

DIF1 12

33

VSS1

AK4414EQ

13

14

15

16

17

18

19

20

21

22

DFI2

P/S

A

CKS

TDM0

SLOW

TEST

VCM2

A

OUTR2P

A

OUTR2N

VDD2

32VREFL1

31VREFH1

30

AOUTR1P

29

AOUTR1N

28NC

27

AOUTL2N

26

AOUTL2P

25VREFH2

24VREFL2

23

VSS2

DVSS 43

MCL

K

42

AVSS 41

AVDD 40

TSTO 2 39

TSTO1 38

VCM1 37

A

OUTL1P 36

A

OUTL1N 35

VDD1 34

Analog 3.0V

0.1u

10u

DSP

Micro-

Controller

+

0.1u

100u

10u

R=10

+

0.1u

10u

100u

R=10

L2ch

LPF L2ch

Mute L2 ch Ou t

L1ch

LPF L1ch

Mute L1 ch Ou t

R2ch

LPF R2ch

Mute R2ch Out

0.1u

A

nalog

Ground

Digital

G

round

Notes:

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.

- VSS1-2, DVSS and AVSS must be connected to the same analog ground plane.

- When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the

capacitive load.

- All input pins except pull-down/pull-up pins should not be allowed to float.

Figure 24. Typical Connection Diagram (AVDD=3.0V, VDD1/2=5V, DVDD=3.0V, Serial Control Mode)

[AK4414]

MS1476-E-01 2013/01

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Analog Ground Digital Ground

System

Controller

PDN

DV DD

1

BICK

44

2

SDATA1

3

SDATA24

TDM1

5

LRCK 6

SMUTE7

SD 8

DEM0

9

DEM1 10

DIF0 11

DIF1 12

33

VSS1

AK 4414EQ

13

14

15

16

17

18

19

20

21

22

DFI2

P/S

A

CK S

TDM0

SLOW

TEST

VCM2

A

OUTR2P

A

OUTR2N

VDD2

32 VREFL1

31 VREFH1

30

AOUTR1N

29

AOUTR1

P

28 NC

27

AOUTL2

P

26

AOUTL2N

25 VREFH2

24 VREFL2

23

VSS2

DVSS 43

MCLK 4

2

AVSS 41

AVDD 40

TSTO2 39

TSTO1 38

VCM1 3

7

A

OUTL1P 36

A

OUTL1N 3

5

VDD1 34

Figure 25. Ground Layout

1. Grounding and Power Supply Decoupling

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDD1/2 and DVDD

respectively. AVDD and VDD1/2 are supplied from analog supply in system and DVDD is supplied from digital supply in

system. Power lines of AVDD, VDD1/2 and DVDD should be distributed separately from the point with low impedance of

regulator etc. The power up sequence between AVDD, VDD1/2 and DVDD is not critical. VSS1-2, DVSS and AVSS

must be connected to the same analog ground pl ane. Decoupling capacitors for high frequency should be placed

as near as possible to the supply pin.

2. Voltage Reference

The differential voltage between VREFH1/2 and VREFL1/2 sets the analog output range. The VREFH1/2 pin is normally

connected to AVDD, and the VREFL1/2 pin is normally connected to VSS1/VSS2/AVSS. VREFH1/2 and VREFL1/2

should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency

noise. No load current may be drawn from VCM1/2 pin. All signals, especially clocks, should be kept away from the

VREFH1/2 and VREFL1/2 pins in order to avoid unwanted noise coupling into the AK4414.

3. Analog Outputs

The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH1/2 − VREFL1/2 = 5V) centered around AVDD/2.

The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If the

summing gain is 1, the output range is 5.6Vpp (typ, VREFH1/2 − VREFL1/2 = 5V). The bias voltage of the external

summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive

full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for

000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio

passband.

Figure 26 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 27 shows an example of differential outputs and LPF circuit example by three op-amps.

[AK4414]

MS1476-E-01 2013/01

- 47 -

2.4k 2.4k

150

2.4k 150

2.4k 680p

+Vop

680p

-Vop

AOUT-

AOU T+

3.3n Analog

Out

A

K4414

Figure 26. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)

Frequency Response Gain

20kHz −0.036dB

40kHz −0.225dB

80kHz −1.855dB

Table 29. Frequency Response of External LPF Circuit Example 1 for PCM

330

100u 180

A

OUTL-

10k

3.9

n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1u 10u

10u

NJM5534D

330

100u 180

A

OUTL+

10k

3.9n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1

u

10u

NJM5534D 0.1u

+

NJM5534D

0.1u 10u

100

4

3

2

1.0n

620

560

7

+

-

+

-

+

-

+

1.0n

Lch

-15

+15

6

560

Figure 27. External LPF Circuit Example 2 for PCM

1

st Stage 2nd Stage Total

Cut-off Frequency 182kHz 284kHz -

Q 0.637 - -

Gain +3.9dB -0.88dB +3.02dB

20kHz -0.025 -0.021 -0.046dB

40kHz -0.106 -0.085 -0.191dB

Frequency

Response 80kHz -0.517 -0.331 -0.848dB

Table 30. Frequency Response of External LPF Circuit Example 2 for PCM

[AK4414]

MS1476-E-01 2013/01

- 48 -

It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass

filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4414 can achieve this filter

response by combination of the internal filter (Table 31) and an external filter (Figure 28).

Frequency Gain

20kHz −0.4dB

50kHz −2.8dB

100kHz −15.5dB

Table 31. Internal Filter Response at DSD Mode

1.8k 4.3k

1.0k

1.8k 1.0k

4.3k 270p

+Vop

270p

-Vop

AOU T-

AOUT+

3300p Analo

g

Out

2.0k

2200

p

-

+

2.4Vpp

5.42Vpp

2.4Vpp

Figure 28. External 3rd Order LPF Circuit Example for DSD

Frequency Gain

20kHz −0.05dB

50kHz −0.51dB

100kHz −16.8dB

DC gain = 1.07dB

Table 32. 3rd Order LPF (Figure 28) Response

4. Measurement Example

Figure 29 shows the relationship between THD+N and Frequency.

Measurement condition

Ta=25°C; AVDD=DVDD=3.3V, VDD1/2=5.0V; AVSS=VSS1/2=DVSS=0V; VREFH1/2=VDD1/2, VREFL1/2= AVSS;

Mono bit = “1”; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz

Measured by Audio Precision System Two.

Figure 29. THD+N vs. Frequency

C

=

10

00

uF

C

=

2200

uF

C

=

470

uF

C

=

220

uF

C

=

10uF

[AK4414]

MS1476-E-01 2013/01

- 49 -

PACKAGE

0.10

0.145

±

0.055

0.37

10.0

1.60max

1 11

23

33

44pin LQFP (Unit: mm)

10.0

12.0

34

44

0.80

22

12

12.0

0.10

±

0.05

0°∼7°

0.6

±

0.15

1.40

±

0.05

0.20 M

+0.08

–0.07

S

1.00

■ Material & Lead finish

Package molding compound: Epoxy, Halogen (bromine and chlorine) free

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

[AK4414]

MS1476-E-01 2013/01

- 50 -

MARKING

AK4414EQ

XXXXXXX

A

KM

1

1) Pin #1 indication

2) AKM Logo

3) Date Code: XXXXXXX(7 digits)

4) Marking Code: AK4414

5) Audio 4 pro Logo

Date (Y/M/D) Revision Reason Page Contents

12/11/16 00 First Edition

13/01/15 01 Error

Correction

41 ■ Register Definitions

DEM1-0: The table number was corrected.

44 A0H, Control 5

D3: The default value was changed. (0 → 1)

D0: The default value was changed. (0 → 1)

DEM3-2: Description was changed.

PW2-1: Description was added.

48 SYSTEM DESIGN

4. Measurement Example

Measurement Condition was changed.

REVISION HISTORY

[AK4414]

MS1476-E-01 2013/01

- 51 -

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

z Descriptions of external circuits, application circuits, software and other related information contained in this

document are provided only to illustrate the operation and application examples of the semiconductor products. You

are fully responsible for the incorporation of these external circuits, application circuits, software and other related

information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third

parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,

intellectual property, or other rights in the application or use of such information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,

or strategic materials.

z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or

other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform

may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places

the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer

or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all

claims arising from the use of said product in the absence of such notification.