1. General description
The ISP1582 is a cost-optim ized and feature-optimized Hi-Speed Universal Serial Bus
(USB) peripheral controller. It fully complies with Ref. 1 “Universal Serial Bus S pecification
Rev. 2.0, supporting data transfer at high -speed (480 Mbit/s) and full-speed (12 Mbit/s).
The ISP1582 provides high-speed USB communication capacity to systems based on
microcontrollers or microprocessors. It communicates with a microcontroller or
microprocessor of a system through a high-speed general-purpose parallel interface.
The ISP1582 supports automatic detection of Hi-Speed USB system operation. Original
USB fall-back mode allows the device to remain operational under full-speed conditions. It
is designed as a generic USB peripheral controller so that it can fit into all existing device
classes, such as imaging class, mass storage devices, communication devices, printing
devices and human interface devices.
The internal generic Direct Memory Access (DMA) blo ck allows easy integration into data
streaming applications.
The modular approach to implementing a USB peripheral contro ller allows the designer to
select the optimum system microcontroller from the wide variety available. The ability to
reuse existing architecture and firmware shortens the development time, eliminates risk
and reduces cost. The result is fast and efficient development of the most cost-effective
USB peripheral solution.
The ISP1582 also incorporates features such as SoftConnect1, a reduced freq uency
crystal oscillator, and integrated termination resistors. These features allow significant
cost savings in system design and easy implementation of advanced USB functionality
into PC peripherals.
2. Features
Complies fully with:
Ref. 1 “Universal Serial Bus Specification Rev. 2.0
Most device class specifications
ACPI, OnNow and USB power management requirements
Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)
High performance USB peripheral controller with integrated Serial Interface Engine
(SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver
Automatic Hi-Spee d USB mode detection and Original USB fall-back mode
Supports sharing mode
ISP1582
Hi-Speed USB peripheral controller
Rev. 09 — 29 September 2009 Product data sheet
1. SoftConnect is a trademark of ST-Ericsson.
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 2 of 64
ISP1582
Hi-Speed USB peripheral controller
Supports VBUS sensing
Supports Generic DMA (GDMA) slave mode
High-speed DMA interface
Fully autonomous and multi-configuration DMA operation
Seven IN endpoints, seven OUT endpoints, and a fixed control IN and OUT endpoint
Integrated physical 8 kB of multi-configuration FIFO memory
Endpoints with double buffering to increase throughput and ease real-time data
transfer
Bus-independent interface with most microcontrollers and microprocessors
12 MHz crystal oscillator with integrated PLL for low EMI
Software-controlled co nn e ctio n to the USB bus (SoftConnect)
Low-power consumption in operation and power-down modes; suitable for use in
bus-powered USB devices
Support s Session Request Protocol (SRP) that adheres to Ref. 2 “On-The-Go
Supplement to the USB Specification Rev. 1.3
Internal powe r- on and lo w- vo ltage rese t circuits; also supports software reset
Operation over the extended USB bus voltage range (DP, DM and VBUS)
5 V tolerant I/O pads
Operating temperature range from 40 °C to +85 °C
Available in HVQFN56 halogen-free and lead-free package
3. Applications
Personal digital assistant
Digital video camera
Digital still camera
3G mobile phone
MP3 player
Communication device, for example: router and mode m
Printer
Scanner
4. Ordering information
Table 1. Ordering information
Commercial
product code Package descrip tion Packing Minimum sellable
quantity
ISP1582BSUM HVQFN56; 56 terminals; body 8 × 8 × 0.85 mm 13 inch tape and reel dry pack 2000 pieces
ISP1582BSGA HVQFN56; 56 terminals; body 8 × 8 × 0.85 mm sing le tray dry pack 260 pieces
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xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
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ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 3 of 64
ISP1582
Hi-Speed USB peripheral controller
5. Block diagram
Fig 1. Block diagram
1.5 kΩ
12.0 kΩ
VCC
004aaa199
ISP1582
MEMORY
MANAGEMENT
UNIT
INTEGRATED
RAM
(8 kB)
SYSTEM
CONTROLLER
VOLTAGE
REGULATORS
POWER-ON
RESET
HI-SPEED USB
TRANSCEIVER
internal
reset
SoftConnect
analog supply
digital
supply I/O pad
supply
MICRO-
CONTROLLER
HANDLER
MICRO-
CONTROLLER
INTERFACE
OTG SRP
MODULE
DMA
REGISTERS
DMA
HANDLER DMA
INTERFACE
ST-ERICSSON
SIE/PIE
INT
DATA
[15:0]
A[7:0]
8
DACK
3.3 V
VCC1V8 SUSPEND WAKEUPAGNDDGND
3.3 V
RD_N
EOT
VCC(I/O)
16
1, 5
2
7
8
DREQ DIOR
DIOW
9101112
13, 26,
29, 41
14
CS_N
WR_N
15
16
17
18 to 20,
22 to 25,
27
21, 34, 4828, 50
30 to 33,
35 to 40,
42 to 47
12 MHz
XTAL2XTAL1
to or from USB
DMDP VBUS
43495251
53, 54
5556
6
RPU
RREF
RESET_N
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 4 of 64
ISP1582
Hi-Speed USB peripheral controller
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration HVQFN56 (top view)
004aaa536
ISP1582BSUM
ISP1582BSGA
Transparent top view
DGND
DGND
INT
DATA0
DIOW DATA1
DIOR DATA2
DACK DATA3
DREQ VCC(I/O)
EOT DATA4
RESET_N DATA5
RREF DATA6
AGND DATA7
DM DATA8
DP DATA9
RPU DGND
AGND DATA10
CS_N
RD_N
WR_N
A0
A1
A2
VCC(I/O)
A3
A4
A5
A6
DGND
A7
VCC1V8
SUSPEND
WAKEUP
VCC
VCC
XTAL1
XTAL2
VCC1V8
VBUS
VCC(I/O)
DATA15
DATA14
DATA13
DATA12
DATA11
14 29
13 30
12 31
11 32
10 33
9 34
8 35
7 36
6 37
5 38
4 39
3 40
2 41
1 42
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
terminal 1
index area
Table 2. Pin description
Symbol[1] Pin Type[2] Description
AGND 1 - analog ground
RPU 2 A pull-up resistor connection; connect to the external pull-up
resistor for pin DP; must be connected to 3.3 V through a 1.5 kΩ
resistor
DP 3 A USB D+ line connection (analog)
DM 4 A USB D line connection (analog)
AGND 5 - analog ground
RREF 6 A external bias resistor connection; connect to the external bias
resistor; must be connected to ground through a 12 .0 kΩ± 1%
resistor
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 5 of 64
ISP1582
Hi-Speed USB peripheral controller
RESET_N 7 I reset input (500 μs); a LOW level produces an asynchronous
reset; connect to VCC for power-on reset (internal POR circuit)
When the RESET_N pin is LOW, ensure that the W AKEUP pin
does not go from LOW to HIGH; otherwise the device will enter
test mode.
TTL; 5 V tolerant
EOT 8 I end-of-transfer input (programmable pol arity); when not in use,
connect this pin to VCC(I/O) through a 10 kΩ resistor
input pad; TTL; 5 V tolerant
DREQ 9 O DMA request (programmable polarity) output; when not in use,
connect this pin to ground through a 10 kΩ resistor; see
Table 51 and Table 52
TTL; 4 ns slew-rate control
DACK 10 I DMA acknowledge input (programmable polarity); when not in
use, connect this pin to VCC(I/O) through a 10 kΩ resistor; see
Table 51 and Table 52
TTL; 5 V tolerant
DIOR 11 I DMA read strobe input (programmable polarity); when not in
use, connect this pin to VCC(I/O) through a 10 kΩ resistor; see
Table 51 and Table 52
TTL; 5 V tolerant
DIOW 12 I DMA write strobe input (programmable polarity); when not in
use, connect this pin to VCC(I/O) through a 10 kΩ resistor; see
Table 51 and Table 52
TTL; 5 V tolerant
DGND 13 - digital ground
INT 14 O interrupt output; programmable polarity (active HIGH or LOW)
and signaling (edge or level triggered)
CMOS output; 8 mA drive
CS_N 15 I chip select input
input pad; TTL; 5 V tolerant
RD_N 16 I read strobe input
input pad; TTL; 5 V tolerant
WR_N 17 I write strobe input
input pad; TTL; 5 V tolerant
A0 18 I bit 0 of the address bus
input pad; TTL; 5 V tolerant
A1 19 I bit 1 of the address bus
input pad; TTL; 5 V tolerant
A2 20 I bit 2 of the address bus
input pad; TTL; 5 V tolerant
VCC(I/O)[3] 21 - supply voltage; used to supply voltage to the I/O pads; see
Section 7.15
A3 22 I bit 3 of the address bus
input pad; TTL; 5 V tolerant
Table 2. Pin description …continued
Symbol[1] Pin Type[2] Description
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 6 of 64
ISP1582
Hi-Speed USB peripheral controller
A4 23 I bit 4 of the address bus
input pad; TTL; 5 V tolerant
A5 24 I bit 5 of the address bus
input pad; TTL; 5 V tolerant
A6 25 I bit 6 of the address bus
input pad; TTL; 5 V tolerant
DGND 26 - digital ground
A7 27 I bit 7 of the address bus
input pad; TTL; 5 V tolerant
VCC1V8[3] 28 - regulator output voltage (1.8 V ± 0.15 V); tapped out voltage
from the internal regulator; this regulated voltage cannot drive
external devices; decouple this pin using a 0.1 μF capacitor; see
Section 7.15
DGND 29 - digital ground
DATA0 30 I/O bit 0 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA1 31 I/O bit 1 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA2 32 I/O bit 2 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA3 33 I/O bit 3 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
VCC(I/O)[3] 34 - supply voltage; used to supply voltage to the I/O pads; see
Section 7.15
DATA4 35 I/O bit 4 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA5 36 I/O bit 5 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA6 37 I/O bit 6 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA7 38 I/O bit 7 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA8 39 I/O bit 8 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA9 40 I/O bit 9 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DGND 41 - digital ground
DATA10 42 I/O bit 10 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA11 43 I/O bit 11 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA12 44 I/O bit 12 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
Table 2. Pin description …continued
Symbol[1] Pin Type[2] Description
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 7 of 64
ISP1582
Hi-Speed USB peripheral controller
[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.
[2] All outputs and I/O pins can source 4 mA, unless otherwise specified.
[3] Add a decoupling capacitor (0.1 μF) to all the supply pins. For better EMI results, add a 0.01 μF capaci tor in
parallel to the 0.1 μF.
DATA13 45 I/O bit 13 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA14 46 I/O bit 14 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
DATA15 47 I/O bit 15 of bidirectional data bus
bidirectional pad; 4 ns slew-ra te control ; TTL; 5 V tolerant
VCC(I/O)[3] 48 - supply voltage; used to supply voltage to the I/O pads; see
Section 7.15
VBUS 49 A USB bus power sensing input — Used to detect whether the
host is connected or not; connect a 1 μF electrolytic or tantalum
capacitor, and a 1 MΩ pull-down resistor to ground; see
Section 7.13
VBUS pulsing output — In OTG mode; connect a 1 μF
electrolytic or tantalum capacitor, and a 1 MΩ pull-down resistor
to ground; see Section 7.13
5V tolerant
VCC1V8[3] 50 - voltage regulator output (1.8 V ± 0.15 V); tapped out voltage
from the internal regulator; this regulated voltage cannot drive
external devices; deco uple this pin using 4.7 μF and 0.1 μF
capacitors; see Section 7.15
XTAL2 51 O crystal oscillator output (12 MHz); connect a fundamental
parallel-resonant crystal; leave this pin open when using an
external clock source on pin XTAL1; see Table 79
XTAL1 52 I crystal oscillator input (12 MHz); conne ct a fundamental
parallel-resonant crystal or an external clock source (leaving
pin XTAL2 unconnected); see Table 79
VCC[3] 53 - supply voltage (3.3 V ± 0.3 V); this pin supplies the internal
voltage regulator and the analog circuit; see Section 7.15
VCC[3] 54 - supply voltage (3.3 V ± 0.3 V); this pin supplies the internal
voltage regulator and the analog circuit; see Section 7.15
WAKEUP 55 I wake-up input; when this pin is at the HIGH level, the chip is
prevented from getting into the suspen d state and wake-up the
chip when already in suspend mode; when not in use, connect
this pin to ground through a 10 kΩ resistor
When the RESET_N pin is LOW, ensure that the W AKEUP pin
does not go from LOW to HIGH; otherwise the device will enter
test mode.
input pad; TTL; 5 V tolerant
SUSPEND 56 O suspend state indicator output; used as a power switch control
output to power-off or power-on external devices when going
into suspend mode or recovering from suspend mode
CMOS output; 8 mA drive
GND exposed
die pad - ground supply; down bonded to the exposed die pad (heat sink);
to be connected to DGND during PCB layout
Table 2. Pin description …continued
Symbol[1] Pin Type[2] Description
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 8 of 64
ISP1582
Hi-Speed USB peripheral controller
7. Functional description
The ISP1582 is a high-speed USB peripheral controller. It implements the Hi-Speed USB
or the Original USB physical layer, and the packet protocol layer. It concurrently maint ains
up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT
configurable) along with end point EP0 setup, which accesses the set-up buf fer . The Ref. 1
Universal Serial Bus Specification Rev. 2.0, Chapte r 9 protocol handling is execu te d
using the external firmware.
For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer
data to or from external memory or devices. The DMA interface can be configured by
writing to proper DMA registers (see Section 8.4).
The ISP1582 supports Hi-Speed USB and Original USB signaling. The USB signaling
speed is automatically detected.
The ISP1582 has 8 kB of internal FIFO memory, which is shared among enabled USB
endpoints, including control IN and control OUT endpoints, and set-up token buffer.
There are seven IN and seven OUT configurable endpoints, and two fixed control
endpoin ts that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be
separately enabled or disabled. The endpoint type (interrupt, isochrono us or bulk) and
packet size of these endpoints can be individu ally configured, depending on the
requirements of the application. Optional double buffering increases the data throughput
of these data endpoints.
The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an intern al
1.8 V regulator to power the digital logic.
Table 3. Endpoint access and pr ogrammability
Endpoint
identifier Maximum packet
size Double buffering Endpoint type Direction
EP0SETUP 8 bytes (fixed) no set-up token OUT
EP0RX 64 bytes (fixed) no control OUT OUT
EP0TX 64 bytes (fixed) no control IN IN
EP1RX programmable yes programmable OUT
EP1TX programmable yes programmable IN
EP2RX programmable yes programmable OUT
EP2TX programmable yes programmable IN
EP3RX programmable yes programmable OUT
EP3TX programmable yes programmable IN
EP4RX programmable yes programmable OUT
EP4TX programmable yes programmable IN
EP5RX programmable yes programmable OUT
EP5TX programmable yes programmable IN
EP6RX programmable yes programmable OUT
EP6TX programmable yes programmable IN
EP7RX programmable yes programmable OUT
EP7TX programmable yes programmable IN
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 9 of 64
ISP1582
Hi-Speed USB peripheral controller
The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40 × PLL clock
multiplier generates the internal sampling clock of 480 MHz.
7.1 DMA interface, DMA handler and DMA registers
The DMA block can be subdivided into two blocks: DMA handler and DMA interface.
The firmware writes to the DMA Command register to st art a DMA transfe r (see Table 44).
The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On
receiving the DMA command, the DMA hand ler directs the da ta from the end point FIFO to
the external DM A dev ice or fro m th e ext er nal DMA de vic e to th e en dpoint FIFO .
The DMA interface configures the timing and the DMA handshake. Data can be
transferred usin g eith er the DIOR an d DIO W str ob es or by the DACK an d DREQ
handshakes. DMA configurations are set up by writing to the DMA Configuration register
(see Table 49 and Table 50).
Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.
For details on DMA registers, see Section 8.4.
7.2 Hi-Speed USB transceiver
The analog transceiver directly interfaces to the USB cab le through integrated termin ation
resistors. The high-speed transceiver requires an external resistor (12.0 kΩ± 1%)
between pin RREF and ground to ensure an accurate current mirror that gen erates the
Hi-S peed USB current drive. A full-speed tra nsceiver is integrated as we ll. This makes the
ISP1582 compliant to Hi-Speed USB and Original USB, supporting both the high-speed
and full-speed physical layers. After automatic speed detection, the ST-Ericsson Serial
Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed
signaling.
7.3 MMU and integrated RAM
The Memory Manage ment Unit (MMU) manag es the access to the integrated RAM that is
shared by the USB, microcontrolle r handler and DMA handler. Data from the USB bus is
stored in the integrated RAM, which is cleared only when the microcon troller has read the
corresponding endpoint, or the DMA controller has written all data from the RAM of the
correspond in g en dpoint to the DM A bus . Th e OU T en dpoint bu ffer can also be forcibly
cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is
available for buffering.
7.4 Microcontroller interface and microcontroller handler
The microcontroller handler allows the external microcontroller or microprocessor to
access the register set in the ST-Ericsson SIE, as well as the DMA handler. The
initialization of the DMA configuration is done through the microcontroller handler.
7.5 OTG SRP module
The OTG supplement defines a Session Request Protocol (SRP), which allows a
B-device to request the A-device to turn on VBUS and st art a session. This pro tocol allows
the A-device, which may be battery-powered, to conserve power by turning off V BUS when
there is no bus activity while still providing a means for the B-device to initiate bus activity.
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 10 of 64
ISP1582
Hi-Speed USB peripheral controller
Any A-device, including a PC or laptop, can respo nd to SRP. Any B-device, including a
standard USB peripheral, can initiate SRP.
The ISP1582 is a device that can initia te SRP.
7.6 ST-Ericsson high-speed transceiver
7.6.1 ST-Ericsson Parallel Interface Engine (PIE)
In the High-Speed (HS) transceiver, the ST-Ericsson PIE interface uses a 16-bit parallel
bidirectional data interface. The functions of the HS module also include bit-stuffing or
de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.
7.6.2 Peripheral circuit
To maintain a constant current driver for HS transmit circuits and to bias other analog
circuits, an internal band gap reference circuit and an RREF resistor form the reference
current. This circuit requires an external precision resistor (12.0 kΩ± 1 %) conn ected to
the analog ground.
7.6.3 HS detection
The ISP1582 hand les more than one electrical st ate, Full-S peed (FS) or High-S peed (HS),
under the USB specification. When the USB cable is connected fr om the periphera l to the
host controller, the ISP1582 default s to the FS st ate, until it sees a bus r eset from the host
controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the host
controller supports Hi-Speed USB or Original USB. If the HS handshake shows that th ere
is an HS host connected, then the ISP1582 switches to the HS state.
In the HS state, the ISP1582 must observe the bus for periodic activity. If the bus remains
inactive for 3 ms, the peripheral switches to the FS state to ch eck for a Single-Ended Zero
(SE0) condition on th e USB bus. If an SE0 condition is detected for the designated time
(100 μs to 875 μs; refer to Ref. 1 “Universal Serial Bus Specification Rev. 2.0,
Section 7.1.7.6), the ISP1582 switches to the HS chirp state to perform an HS detection
handshake. Otherwise , the ISP1582 remains in the FS state, adhering to the bus-suspend
specification.
7.6.4 Isolation
Ensure that the DP and DM lines are maintained in a clean state, without any residual
voltage or glitches. Once the ISP1582 is reset and the clock is available, ensure that ther e
are no errone ous p ulses or glitch es e ven of very small amplitude on the DP and DM lines.
Remark: If there are an y erroneo us unwanted pulses or glitches de tected by the ISP1582
DP and DM lines, there is a possibility of the ISP1582 clocking this state into the internal
core, causing unknown behaviors.
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 11 of 64
ISP1582
Hi-Speed USB peripheral controller
7.7 ST-Ericsson Serial Interface Engine (SIE)
The ST -Ericsson SIE implements the full USB protocol layer . It is completely hardwired for
speed and needs no firmware intervention. The functions of this block includ e:
synchronization pattern recognition, p arallel or serial conversion, bit-stuffing or de-stuf fing,
CRC checking or generation, Packet IDentifier (PID) verification or generation, address
recognition, handshake evaluation or generation.
7.8 SoftConnect
The USB connection is established by pulling pin DP (for full-speed devices) to HIGH
through a 1.5 kΩ pull-up resistor. In the ISP1582, an external 1.5 kΩ pull-up resistor must
be connected between pin RPU and 3.3 V. Pin RPU connects the pull-up resistor to pin
DP, when bit SOFTCT in the Mode register is set (see Table 18 and Table 19). After a
hardware reset, the pull-up resistor is disconnected by default (b it SOFTCT = 0). The USB
bus reset does not change the value of bit SOFTCT.
When VBUS is not present, the SOFTCT bit must be set to logic 0 to comply with the
back-drive voltage.
7.9 Reconfiguring endpoints
The ISP1582 endpoints have a limitation when implementing a composite device with at
least two functionalities that require the support of alternate settings, for example, the
video class and audio class devices. The ISP1582 endpoin ts cannot be reconfigured on
the fly because it is implemented as a FIFO base. The internal RAM partition will be
corrupted if there is a need to reconfigure endpoints on the fly because of alternate
settings request, causing data corruption.
For det ails and workaround, refer to Ref. 3 “Using ISP1582/3 in a composite device
application with alternate settings (AN10071).
7.10 System controller
The system controller implements the USB power-down capabilities of the ISP1582.
Registers are protected against data corruption during wake-up following a resume (from
the suspend state) by locking the write access, until an unlock code is written in the
Unlock Device register (see Table 69 and Table 70).
7.11 Pins status
Table 4 illustrates the behavior of ISP1582 pins with VCC(I/O) and VCC in various operating
conditions.
[1] Dead: The USB cable is plugged out, and VCC(I/O) is not available.
Table 4. ISP1582 pin status
VCC VCC(I/O) State Pin
Input Output I/O
0 V 0 V dead[1] unknown unknown unknown
3.3 V VCC reset state depends on how the pin is driven output high-Z
3.3 V VCC after reset state depends on how the pin is driven output state depends on how the pin is configured
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 12 of 64
ISP1582
Hi-Speed USB peripheral controller
Table 5 illustrates the behavior of output pins with VCC(I/O) and VCC in various operating
conditions.
[1] Dead: The USB cable is plugged out, and VCC(I/O) is not available.
[2] X: Don’t care.
7.12 Interrupt
7.12.1 Interrupt output pin
The Interrupt Config uration register of the ISP1582 contro ls the behavior of the INT output
pin. The polarity an d signaling mode of pin INT can be programmed by setting bits
INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see Table 22. Bit
GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT. Default settings
afte r reset are active LOW and level mode. Whe n pulse mode is selected, a pulse of 60 ns
is generated when the OR-ed combination of all interrupt bits changes from logic 0 to
logic 1.
Figure 3 shows the relationship between interrupt events and pin INT.
Each of the indicated USB and DMA events is logged in a status bit of the Interrupt
register and the DMA Interrupt Reason register, respectively. Corresponding bits in the
Interrupt Enable register and the DMA Interrupt Enable register determine whether an
event will generate an interrupt.
Interrupts can be masked globally by means of bit GLINTENA of the Mode register; see
Table 19.
Field CDBGMOD[1:0] of the Interrupt Configuration register contr ols the generation of INT
signals for the control pip e. Field DDBGMODIN[1:0] of the Interrupt Configuration register
controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the
Interrupt Configuration register controls the generation of INT signals for the OUT pipe;
see Table 23.
Table 5. ISP1582 output status
VCC VCC(I/O) State INT SUSPEND
0V 0V dead
[1] X[2] X[2]
3.3 V VCC reset HIGH LOW
3.3 V VCC after reset HIGH LOW
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Product data sheet Rev. 09 — 29 September 2009 13 of 64
ISP1582
Hi-Speed USB peripheral controller
Fig 3. Interrupt logic
OR
Interrupt register
DMA Interrupt Reason
register
DMA Interrupt Enable
register
Interrupt Enable register
DMA_XFER_OK
EXT_EOT
INT_EOT
IE_DMA_XFER_OK
IE_EXT_EOT
IE_INT_EOT
OR
IEBRESET
IESOF
IEDMA
IEP7RX
IEP7TX
BRESET
SOF
DMA
EP7RX
EP7TX
....................
..........
004aaa275
LATCH
GLINTENA
INTPOL
LE
Interrupt Configuration
register
Mode register
INT PULSE OR LEVEL
GENERATOR
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 14 of 64
ISP1582
Hi-Speed USB peripheral controller
7.12.2 Interrupt control
Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The be havior
of this bit is given in Figure 4.
The following illustrations are only applicable for level trigger.
Event A: When an interr upt event occurs (for example, SOF interrupt) with bit GLINTENA
set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in
the corresponding Interrupt register bit.
Event B: When bi t GLIN TENA is set to logi c 1, pin INT is asser ted beca use bit SOF in the
Interrupt re gist er is alread y s et .
Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The
bold line shows the desired behavior of pin INT.
Deassertion of pin INT can be achieved ei ther by clearing all the bits in the Interrupt
register or the DMA Interrupt Reason register, depending on the event.
Remark: When clearing an interrupt event, perform write to all the bytes of the register.
For more information on interrupt control, see Section 8.2.2, Section 8.2.5 and
Section 8.5.1.
7.13 VBUS sensing
The VBUS pin is one of the ways to wake up the clock when the ISP1582 is suspended
with bit CLKAON set to logic 0 (clock off option).
To detect whether the host is connected or not, that is VBUS sensing, a 1 M Ω resistor and
a 1 μF electrolytic or tantalum capacitor must be added to damp the overshoot on plug-in.
Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).
Fig 4. Behavior of bit GLINTENA
INT pin
004aaa394
GLINTENA = 0
SOF asserted
GLINTENA = 1
SOF asserted
GLINTENA = 0
(during this time,
an interrupt event
occurs, for example,
SOF asserted)
ABC
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 15 of 64
ISP1582
Hi-Speed USB peripheral controller
7.14 Power-on reset
The ISP1582 requires a minimum pulse width of 500 μs.
Fig 5. Resistor and electro lytic or tantalum capacitor needed for VBUS sensing
Fig 6. Oscillosco pe reading: no resistor and capacitor in the network
Fig 7. Oscilloscope reading: with resistor and capacitor in the network
001aaf440
001aaf441
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 16 of 64
ISP1582
Hi-Speed USB peripheral controller
The RESET_N pin can either be connected to VCC (using the internal POR circuit) or
externally controlled (by the microcontroller, ASIC, and so on). When VCC is directly
connected to the RESET_N pin, the internal pulse width tPORP will typically be 200 ns.
The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5
on the VCC(POR) curve (Figure 8).
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
t2-t3 — The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for
more than 11 μs.
t4-t5 — The dip is too short (< 11 μs) and the internal POR pulse will not react and will
remain LOW.
Figure 9 shows the availability of the clock with respect to the external POR.
7.15 Power supply
The ISP1582 can be powered by 3.3 V ± 0.3 V. For connection details, see Figure 10.
If the ISP1582 is powered by V CC = 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator
provides a 1.8 V supply voltage for the internal logic.
(1) PORP = Power-On Reset Pulse.
Fig 8. POR timing
Power on VCC at A.
Stable external clock is to be available at B.
The ISP1582 is operational at C.
Fig 9. Clock with respect to the external POR
004aab162
V
CC(POR)
t0 t1 t2 t3 t4 t5
V
trip
t
PORP
PORP
(1)
t
PORP
V
CC
external
clock
A
004aaa927
500 μs
RESET_N
2 ms
C
B
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 17 of 64
ISP1582
Hi-Speed USB peripheral controller
Table 6 shows power modes in which the ISP1582 can be operated.
[1] The power supply to the IC (VCC) is 3.3 V. Therefore, if the application is bus-powered, a 3.3 V regulator
must be used.
[2] VCC(I/O) = VCC. If the application is bus-powered, a voltage regulator must be used.
(1) At the VCC input (3.3 V) to the USB controller, if the ripple voltage is less than 20 mV, then 4.7 μF
standard electrolytic or tantalum cap acitors (tested ESR up to 10 Ω) should be OK at the VCC1V8
output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 μF LOW ESR cap acitors
(ESR from 0.2 Ω to 2 Ω) at the VCC1V8 output. This is to improve the high-speed signal quality at
the USB side.
Fig 10. ISP1582 with 3.3 V supply
Table 6. Power modes
VCC VCC(I/O) Power mode
VBUS[1] VBUS[2] bus-powered
System-powered system-powered self-powered
004aaa203
53, 54
VCC(I/O)
ISP1582
3.3 V ± 0.3 V
VCC(I/O)
VCC
48
34
VCC(I/O)
VCC1V8
21
50
4.7 μF(1) 0.1 μF
0.01 μF0.1 μF
0.01 μF0.1 μF
0.01 µF 0.1 μF
0.01 μF0.1 μF
VCC1V8
28
0.1 μF
VCC
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 18 of 64
ISP1582
Hi-Speed USB peripheral controller
7.15.1 Self-powered mode
In self-powered mode, VCC and VCC(I/O) are supplied by the system. See Figure 11.
[1] When the USB cable is removed, SoftConnect is disabled.
VCC(I/O) and VCC are system powered.
Fig 11. Self-powered mode
Table 7. Operation truth table for SoftConnect
ISP1582 operation Power supply Bit SOFTCT in
Mode register
VCC VCC(I/O) RPU
(3.3 V) VBUS
Normal bus operation 3.3 V 3.3 V 3.3 V 5 V enabled
No pull-up on DP 3.3V 3.3V 3.3V 0V
[1] disabled
Table 8. Operation truth table for clock off during suspend
ISP1582 operation Power supply Clock off
during
suspend
VCC VCC(I/O) RPU
(3.3 V) VBUS
Clock will wake up:
After resume and
After a bus reset
3.3 V 3.3 V 3.3 V 5 V enabled
Clock will wake up:
After detecting the presence of VBUS
3.3V 3.3V 3.3V 0V 5 V enabled
Table 9. Operation truth table for back voltage compliance
ISP1582 operation Power supply Bit SOFTCT
in Mode
register
VCC VCC(I/O) RPU
(3.3 V) VBUS
Back voltage is not measured in this
mode 3.3 V 3.3 V 3.3 V 5 V enabled
Back voltage is not an issue because pull
up on DP will not be present when VBUS
is not present
3.3 V 3.3 V 3.3 V 0 V disabled
004aaa460
ISP1582
USB
1 MΩ
VCC
VCC(I/O)
VBUS
RPU VBUS
1.5 kΩ
1 μF
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 19 of 64
ISP1582
Hi-Speed USB peripheral controller
7.15.2 Bus-powered mode
In bus-powered mode (see Figure 12), VCC and VCC(I/O) are supplied by the output of the
5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. On plugging the
USB cable, the ISP1582 goes through the power-on reset cycle. In this mode, OTG is
disabled.
Table 10. Operation truth table for OTG
ISP1582 operation Power supply OTG register
VCC VCC(I/O) RPU
(3.3 V) VBUS
SRP is not applicable 3.3 V 3.3 V 3.3 V 5 V not applicable
SRP is possible 3.3 V 3.3 V 3.3 V 0 V operational
VCC(I/O) is powered by VBUS.
Fig 12. Bus-powered mo de
Table 11. Operation truth table for SoftConnect
ISP1582 operation Power supply Bit SOFTCT in
Mode register
VCC VCC(I/O) RPU
(3.3 V) VBUS
Normal bus operation 3.3 V 3.3 V 3.3 V 5 V enabled
Power loss 0V 0V 0V 0V not applicable
Table 12. Operation truth table for clock off during suspend
ISP1582 operation Power supply Clock off during
suspend
VCC VCC(I/O) RPU
(3.3 V) VBUS
Clock will wake up:
After resume and
After a bus reset
3.3 V 3.3 V 3.3 V 5 V enabled
Power loss 0V 0V 0V 0V not applicable
004aaa462
ISP1582
5 V-to-3.3 V
USB
VOLTAGE
REGULATOR
1 MΩ
VCC
VCC(I/O)
VBUS
VBUS
RPU
1 μF
1.5 kΩ
3.3 V
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 20 of 64
ISP1582
Hi-Speed USB peripheral controller
Table 13. Operation truth table for back voltage compliance
ISP1582 operation Power supply Bit SOFTCT in
Mode register
VCC VCC(I/O) RPU
(3.3 V) VBUS
Back voltage is not measured in this
mode 3.3 V 3.3 V 3.3 V 5 V enabled
Power loss 0V 0V 0V 0V not applicable
Table 14. Operation truth table for OTG
ISP1582 operation Power supply OTG register
VCC VCC(I/O) RPU
(3.3 V) VBUS
SRP is not applicable 3.3 V 3.3 V 3.3 V 5 V not applicable
Power loss 0V 0V 0V 0V not applicable
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 21 of 64
ISP1582
Hi-Speed USB peripheral controller
8. Register description
Table 15. Register overview
Name Destination Address Description Size
(bytes) Reference
Initialization registers
Address device 00h USB device address and enable 1 Section 8.2.1
on page 22
Mode device 0Ch power-down options, global interrupt
enable, SoftConnect 2Section 8.2.2
on page 23
Interrupt Configuration device 10h interrupt sources, trigger mode, output
polarity 1Section 8.2.3
on page 24
OTG device 12h OTG implementation 1 Section 8.2.4
on page 25
Interrupt Enable device 14h interrupt source ena bling 4 Section 8.2.5
on page 27
Data flow registers
Endpoint Index endpoints 2Ch endpoint selection, data flow direction 1 Section 8.3.1
on page 29
Control Function endpoint 28h endpoint buffer management 1 Section 8.3.2
on page 30
Data Port endpoint 20h data access to endpoint FIFO 2 Section 8.3.3
on page 31
Buffer Length endpoint 1Ch packet size counter 2 Section 8.3.4
on page 32
Buffer Status endpoint 1Eh buffer status for each endpoint 1 Section 8.3.5
on page 33
Endpoint MaxPacketSize endpoint 04h maximum packet size 2 Section 8.3.6
on page 34
Endpoint Type endpoint 08h selects endpoint type: isochronous, bulk
or interrupt 2Section 8.3.7
on page 35
DMA regi sters
DMA Command DMA controller 30h controls all DMA transfers 1 Section 8.4.1
on page 37
DMA Transfer Counter DMA controller 34h sets byte count for DMA transfer 4 Section 8.4.2
on page 38
DMA Configuration DMA controller 38h sets GDMA configuration (counter
enable, data strobing, bus width) 2Section 8.4.3
on page 39
DMA Hardware DMA controller 3Ch endian type, signal polarity for DACK,
DREQ, DIOW, DIOR, EOT 1Section 8.4.4
on page 40
DMA Interrupt Reason DMA controller 50h shows reason (source) for DMA interrupt 2 Section 8.4.5
on page 41
DMA Interrupt Enable DMA controller 54h enables DMA interrupt sources 2 Section 8.4.6
on page 42
DMA Endpoint DMA controller 58h selects endpoint FIFO, data flow direction 1 Section 8.4.7
on page 43
DMA Burst Counter DMA controller 64h DMA burst counter 2 Section 8.4.8
on page 43
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 22 of 64
ISP1582
Hi-Speed USB peripheral controller
8.1 Register access
The ISP1582 uses a 16-bit b us access. For single-byte registers, the upper byte (MSByte)
must be ignored.
Endpoint sp ecific registers are indexed using the Endpoint Index register. The target
endpoint mu st be selected before accessing the following registers:
Buffer length
Buffer status
Control function
Data port
Endpoint MaxPacketSize
Endpoint type
Remark: Write zero to all reserved bits, unless otherwise specified.
8.2 Initialization registers
8.2.1 Address register (address: 00h)
This register sets the USB assigned address and enables the USB device . Table 16
shows the Address register bit allocation.
Bits DEVADDR[6:0] will be cleared whenever a bus reset, a power-on reset or a sof t reset
occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs.
In response to the standard USB request SET_ADDRESS, firmware must write the
(enabled) device address to th e Address register, followed by se nding an empty p acket to
the host. The new device address is activated when the device receives an
acknowledgment from the host for the em pty packet token.
General registers
Interrupt device 18h shows interrupt sources 4 Section 8.5.1
on page 44
Chip ID device 70h product ID code and hardware version 3 Section 8.5.2
on page 46
Frame Number device 74h last successfully received
Start-Of-Frame: lower byte (byte 0) is
accessed first
2Section 8.5.3
on page 46
Scratch device 78h allows save or restore of firmware status
during suspend 2Section 8.5.4
on page 47
Unlock Device device 7Ch re-enables register write access after
suspend 2Section 8.5.5
on page 47
Test Mode PHY 84h direct se tting of the DP and DM states,
internal transceiver test (PHY) 1Section 8.5.6
on page 48
Table 15. Register overview …continued
Name Destination Address Description Size
(bytes) Reference
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 23 of 64
ISP1582
Hi-Speed USB peripheral controller
8.2.2 Mode register (address: 0Ch)
This register consists of 2 b ytes (bit allocation: see Table 18).
The Mode register contro ls resume, suspend and wake-up behavior, interrupt activity, soft
reset, clock signals and SoftConnect operation.
[1] Value depends on the status of the VBUS pin.
Table 16. Address register: bit allocatio n
Bit 76543210
Symbol DEVEN DEVADDR[6:0]
Reset 00000000
Bus reset unchanged 0 0 00000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 17. Address register: bit description
Bit Symbol Description
7 DEVEN Device Enable : Logic 1 enables the device. The device will not respond to
the host, unless this bit is set.
6 to 0 DEVADDR
[6:0] Device Address: This field specifies the USB device address.
Table 18. Mode register: bit allocation
Bit 15 14 13 12 11 10 9 8
Symbol reserved DMA
CLKON VBUSSTAT
Reset ------0-
[1]
Bus reset ------0-
[1]
Access RRRRRRR/WR
Bit 76543210
Symbol CLKAON SNDRSU GOSUSP SFRESET GLINTENA WKUPCS PWRON SOFTCT
Reset 00000000
Bus reset unchanged 0 0 0 unchanged 0 unchanged unchanged
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 19. Mode register: bit description
Bit Symbol Description
15 to 10 - reserved
9DMACLKONDMA Clock On:
0 — Power save mode; the DMA circuit wi ll stop completely to save
power.
1 — Supply clock to the DMA circuit.
8 VBUSSTAT VBUS Pin Status: This bit reflects the VBUS pin status.
ISP1582_9 © ST-ERICSSON 2009. All rights reserved.
Product data sheet Rev. 09 — 29 September 2009 24 of 64
ISP1582
Hi-Speed USB peripheral controller
The status of the chip is shown in Table 20.
8.2.3 Interrupt Configuration register (address: 10h)
This 1-byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in Table 21. When the USB SIE receives or generates an ACK, NAK
or NYET, it will generate interrupts, depending on three Debug mode fields.
7 CLKAON Clock Always On: Logic 1 indicates that internal clocks are always
running when in the suspend state. Logic 0 switches off the internal
oscillator and PLL when the device goes into suspend mode. The
device will consume less power if this bit is set to logic 0. The clock is
stopped about 2 ms after bit GOSUSP is set and then cleared.
6 SNDRSU Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms
upstream resume signal.
Remark: The upstream resume signal is generated 5 ms after this bit is
set to logic 0.
5GOSUSPGo Suspend: Writing logic 1, followed by logic 0 will activate suspend
mode.
4 SFRESET Sof t Reset: Writing logic 1, followed by logic 0 will enable a
software-initiated reset to the ISP1582. A soft reset is similar to a
hardware-initiated reset (using pin RESET_N).
3GLINTENAGlobal Interrupt Enable: Logic 1 enables all interrupts. Individual
interrupts can be masked by clearing the corresponding bits in the
Interrupt Enable register.
When this bit is not set, an unmasked interrup t will not genera te an
interrupt trigger on the interrupt pin. If global interrupt, however, is
enabled while there is any pending unmasked interrupt, an interrupt
signal will be immediately generated on the interrupt pin. (If the interrupt
is set to pulse mode, the interrupt events that were generated before the
global interrupt is enabled will not app ear on the interrupt pin).
2 WKUPCS Wake Up On Chip Sele ct: Logic 1 enables wake-up from suspend
mode through a valid register read on the ISP1582. (A read will invoke
the chip clock to restart. If you write to the register before the clock gets
stable, it may cause malfunctioning).
1PWRONPower On: The SUSPEND pin output control.
0 — The SUSPEND pin is HIGH when the ISP1582 is in the su spend
state. Otherwise, the SUSPEND pin is LOW.
1 — When the device is woken up from the suspend state, there will be
a 1 ms active HIGH pulse on the SUSPEND pin. The SUSPEND pin will
remain LOW in all other states.
0 SOFTCT SoftConnect: Logic 1 enables the connection of the 1.5 kΩ pull-up
resistor on pin RPU to the DP pin.
Table 19. Mode register: bit description …continued
Bit Symbol Description
Table 20. Status of the chip
VBUS SoftConnect = on Sof tConnect = off
On pull-up resistor on pin DP pull-up resistor on pin DP is removed; suspend interrupt is
generated after 3 m s of no bus activity
Off pull-up resistor on pin DP is present; suspend
interrupt is generated after 3 ms of no bus activity pull-up resistor on pin DP is removed; suspend interrupt is
generated after 3 m s of no bus activity