4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Features 3.0V Core Async/Page PSRAM Memory MT45V256KW16PEGA Features Figure 1: * Asynchronous and page mode interface * Random access time: 55ns and 70ns * VCC, VCCQ voltages - 2.7-3.6V VCC - 2.7-3.6V VCCQ * Page mode read access - 16-word page size - Interpage read access: 55ns and 70ns - Intrapage read access: 15ns and 20ns * Low power consumption - Asynchronous READ: <30mA - Intrapage READ: <18mA - Standby: <140A - Deep power-down (DPD): <45A (TYP at 25C) * Low-power features - Partial-array refresh (PAR) - DPD mode Options Designator * Configuration - 256K x 16 * Package - 48-ball VFBGA ("green") * Access time - 55ns - 70ns * Operating temperature range - Wireless (-30C to +85C) - Industrial (-40C to +85C) PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__1.fm - Rev. B 4/08 EN 48-Ball VFBGA Ball Assignments 1 2 3 4 5 6 A LB# OE# A0 A1 A2 ZZ# B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VssQ DQ11 A17 A7 DQ3 Vcc E VccQ DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE# DQ7 H DNU A8 A9 A10 A11 NC MT45V256KW16PE Top view (Ball down) GA -55 -70 Part Number Example: MT45V256KW16PEGA-55WT WT IT 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Designator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Configuration Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Access Using ZZ# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PDF: 09005aef832450a3/Source: 09005aef82f264aa 4mb_ap_3v_psram_p22zTOC.fm - Rev. B 4/08 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: 48-Ball VFBGA Ball Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram 256K x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Page Mode READ Operation (ADV = LOW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Software Access PAR Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Configuration Register Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Load Configuration Register Operation Using ZZ#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Typical Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Power-Up Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Deep Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Single READ Operation (WE# = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Page Mode READ Operation (WE# = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 WRITE Cycle (WE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 WRITE Cycle (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 WRITE Cycle (LB#/UB# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PDF: 09005aef832450a3/Source: 09005aef82f264aa 4mb_ap_3v_psram_p22zLOF.fm - Rev. B 4/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Deep Power-Down Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Capacitance Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Load Configuration Register Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 PDF: 09005aef832450a3/Source: 09005aef82f264aa 4mb_ap_3v_psram_p22zLOT.fm - Rev. B 4/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 General Description General Description Micron(R) PSRAM products are high-speed, CMOS memory devices developed for lowpower, portable applications. The MT45V256KW16PE is a 4Mb DRAM core device organized as 256K x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration register (CR) defines how the PSRAM device performs on-chip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. Special attention has been focused on current consumption during self refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR. Functional Block Diagram Figure 2: Functional Block Diagram 256K x 16 A[17:0] Address decode logic Configuration register (CR) 256K x 16 DRAM memory array Input/ output MUX and buffers DQ[7:0] DQ[15:8] CE# WE# OE# UB# Control logic LB# ZZ# Notes: 1. Functional block diagrams illustrate simplified device operation. See the ball description table, bus operations table, and timing diagrams for detailed information. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Ball Descriptions Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol Type Description D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4, A3 B5 A[17:0] Input Address inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. CE# Input A1 A2 LB# OE# Input Input B2 G5 A6 UB# WE# ZZ# Input Input Input G1, F1, F2, E2, D2, C2, C1, B1, G6, F6, F5, E5, D5, C6, C5, B6 D6 E1 E6 D1 E3, G2, H6 H1 DQ[15:0] Input/ Output Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Lower byte enable: DQ[7:0]. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Upper byte enable: DQ[15:8]. Write enable: Enables WRITE operations when LOW. Sleep enable: When ZZ# is LOW, the CR can be loaded, or the device can enter one of two low-power modes (DPD or PAR). Data inputs/outputs. VCC VCCQ VSS VSSQ NC DNU Supply Supply Supply Supply - - PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN Device power supply (2.7-3.6V): Power supply for device core operation. I/O power supply (2.7-3.6V): Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. No connect: Not internally connected. Do not use: DNUs must be left unconnected or tied to ground. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Bus Operations Bus Operations Table 2: Bus Operations Mode Standby Read Write No operation PAR DPD Load configuration register Notes: Power CE# WE# OE# LB#/UB# ZZ# DQ[15:0]1 Notes Standby Active Active Idle Partial-array refresh Deep power-down Active H L L L H H L X H L X X X L X L X X X X X X L L X X X X H H H H L L L High-Z Data-out Data-in X High-Z High-Z High-Z 2, 5 1, 4 1, 3, 4 4, 5 6 6 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in select mode, only DQ[7:0] are affected. When UB# alone is in the select mode, only DQ[15:8] are affected. 2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are internally isolated from any external influence. 3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os. 4. The device will consume active power in this mode whenever addresses are changed. 5. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve minimum standby current. 6. DPD is enabled when configuration register bit CR[4] is "0"; otherwise, PAR is enabled. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Part Numbering Information Part Numbering Information Micron PSRAM devices are available in several configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 V 256K W 16 PE GA -55 Micron Technology WT ES Production Status Blank = Production Product Family ES = Engineering sample 45 = PSRAM memory MS = Mechanical sample Operating Core Voltage Operating Temperature V = 2.7V-3.6V WT = -30C to +85C IT = -40C to +85C Address Locations Standby Power Options K = Kilobits Blank = Standard Operating Voltage Access/Cycle Time W = 2.7V-3.6V 55 = 55ns Bus Configuration 70 = 70ns 16 = x16 READ/WRITE Operation Mode PE = Asynchronous/Page Package Codes GA = VFBGA "Green" (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball Valid Part Number Combinations After building the part number using the part numbering chart, visit the Micron Web site at www.micron.com/psram to verify that the part number is offered and valid. If the device required is not on this list, contact the factory. Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, "Product Mark/Label," at www.micron.com/csn. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Functional Description Functional Description In general, MT45V256KW16PE devices are high-density alternatives to SRAM and PSRAM products that are popular in low-power, portable applications. MT45V256KW16PE devices contain an 4,194,304-bit DRAM core organized as 262,144 addresses by 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings. Page mode access is also supported as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization Micron PSRAM products include an on-chip voltage sensor that is used to launch the power-up initialization process. Initialization will load the CR with its default setting. VCC and VCCQ must be applied simultaneously, and when they reach a stable level above 1.7V, the device will require 150s to complete its self-initialization process (see Figure 4). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 4: Power-Up Initialization Timing Vcc (MIN) Vcc, VccQ = 2.7V tPU Device ready for normal operation Bus Operating Modes The MT45V256KW16PE PSRAM product incorporates the industry-standard, asynchronous interface. This bus interface supports asynchronous READ and WRITE operations as well as page mode READ operation for enhanced bandwidth. The supported interface is defined by the value loaded into the CR. Asynchronous Mode Micron PSRAM products power up in the asynchronous operating mode. This mode uses the industry-standard SRAM control interface (CE#, OE#, WE#, and LB#/UB#). READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH (see Figure 5 on page 10). Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations occur when CE#, WE#, and LB#/ UB# are driven LOW (see Figure 6 on page 10). During WRITE operations, the level of OE# is a "Don't Care"; WE# overrides OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be limited to t CEM. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Bus Operating Modes Figure 5: READ Operation CE# OE# WE# Address Data Valid address Valid data LB#/UB# tRC = READ cycle time Don't Care Figure 6: WRITE Operation CE# OE# <tCEM WE# Address Valid address Data Valid data LB#/UB# tWC = WRITE cycle time Don't Care PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Bus Operating Modes Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the loworder address. Addresses A[3:0] are used to determine the members of the 16-address PSRAM page. Any change in addresses A[4] or higher will initiate a new tAA access (see Figure 7). Page mode takes advantage of the fact that adjacent addresses can be read faster than random addresses. WRITE operations do not include comparable page mode functionality. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. Figure 7: Page Mode READ Operation (ADV = LOW) < tCEM CE# OE# WE# Address Address[0] tAA Data Address Address Address [1] [3] [2] tAPA D[0] tAPA D[1] tAPA D[2] D[3] LB#/UB# Don't Care LB#/UB# Operation The lower byte (LB#) and upper byte (UB#) enable signals accommodate byte-wide data transfers. During READ operations, enabled bytes are driven onto the DQ. The DQ signals associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, disabled bytes are not transferred to the memory array, and the internal value remains unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device prevents the data bus from receiving or transmitting data. Although the device may appear to be deselected, it remains in active mode as long as CE# remains LOW. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Low-Power Operation Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH. The device enters a reduced-power state upon completion of READ and WRITE operations when the address and control inputs remain static for an extended period of time. This mode continues until a change occurs to the address or control inputs. Partial-Array Refresh Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are "full array" and "none of the array." Data stored in addresses not receiving refresh will become corrupted. READ and WRITE operations are ignored during PAR operation. The device only enters PAR mode if the sleep bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated by taking the ZZ# ball to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause an exit from PAR, and the entire array will be immediately available for READ and WRITE operations. Alternatively, PAR can be initiated using the CR software-access sequence (see "Software Access to the Configuration Register" on page 15). Using this method, PAR is enabled immediately upon setting CR[4] to "1." However, using software access to write to the CR alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, even though ZZ# continues to enable WRITEs to the CR. This functional change persists until the next time the device is powered up (see Figure 8 on page 13). PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Low-Power Operation Figure 8: Software Access PAR Functionality Power-up To enable PAR, bring ZZ# LOW for 10s No Software LOAD executed? Yes Change to ZZ# functionality; PAR permanently enabled, independent of ZZ# level Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the PSRAM device. Any stored data will become corrupted upon entering DPD. When refresh activity has been re-enabled, the PSRAM device will require 150s to perform an initialization procedure before normal operations can resume. READ and WRITE operations are ignored during DPD operation. The device can only enter DPD if the sleep bit in the CR has been set LOW (CR[4] = 0). DPD is initiated by bringing ZZ# to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150s initialization process. During this time, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using the CR software-access sequence. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Configuration Register Operation Configuration Register Operation The configuration register (CR) defines how the PSRAM device performs a transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is embedded in the CR. This register can be updated any time the device is operating in a standby state. The control bits used in the CR are shown in Figure 9. At power-up, the CR is set to 0010h. Figure 9: Configuration Register Bit Mapping A7 A[17:8] A5 6 5 7 17-8 Reserved Page All must be set to "0" CR[7] A6 Ignored A4 4 Sleep Setting is ignored (default 00b) A3 A2 3 2 Page mode disabled (default) 1 Page mode enabled Must be set to "0" Notes: CR[4] Sleep Mode 0 DPD enabled 1 PAR enabled (default) A0 1 0 Address Bus PAR1 Reserved Page Mode Enable/Disable 0 A1 CR[2] CR[1] CR[0] PAR Coverage 0 0 0 Full array (default) 1 0 0 None of array 1. Use of other settings will result in full-array refresh coverage. Access Using ZZ# The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGHto-LOW transition (see Figure 10). The values placed on addresses A[17:0] are latched into the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are "Don't Care." Access using ZZ# is WRITE only. Figure 10: Load Configuration Register Operation Using ZZ# Address Valid address CE# WE# t < 500ns ZZ# PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Configuration Register Operation Software Access to the Configuration Register The contents of the CR can be read or modified using a software access sequence. The nature of this access mechanism can potentially eliminate the need for the ZZ# ball. If the software-access mechanism is used, ZZ# can simply be tied to VCCQ; the port line typically used for ZZ# control purposes will no longer be required. However, ZZ# should not be tied to VCCQ if the system will use DPD; DPD cannot be enabled or disabled using the software-access sequence. The CR is loaded using a four-step sequence consisting of two READ operations followed by two WRITE operations (see Figure 11). The READ sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 12 on page 16). The address used during all READ and WRITE operations is the highest address of the PSRAM device being accessed (3FFFFh for 4Mb devices); the content of this address is not changed by using the software-access sequence. The data bus is used to transfer data into or out of bits[15:0] of the CR. Writing to the CR using the software-access sequence modifies the function of the ZZ# ball. After the software sequence loads the CR, the level of the ZZ# ball no longer enables PAR operation. PAR operation is updated whenever the software-access sequence loads a new value into the CR. This ZZ# functionality will remain active until the next time the device is powered up. The operation of the ZZ# ball is not affected if the software-access sequence is only used to read the contents of the CR. Use of the software-access sequence does not affect the performance of standard (ZZ#-controlled) CR loading. Figure 11: Load Configuration Register Address READ READ WRITE WRITE Address (MAX) Address (MAX) Address (MAX) Address (MAX) CE# OE# WE# 0ns (MIN), see Note 1 LB#/UB# Data XXXXh CR value in XXXXh CR: 0000h Don't Care Notes: 1. It is possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Configuration Register Operation Figure 12: Read Configuration Register Address READ READ WRITE READ Address (MAX) Address (MAX) Address (MAX) Address (MAX) CE# OE# WE# 0ns (MIN), see Note 1 LB#/UB# Data XXXXh CR value out XXXXh CR: 0000h Don't Care Notes: 1. It is possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h. Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh The PAR bits restrict REFRESH operation to a portion of the total memory array. The refresh options are "full array" and "none of the array." Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled The sleep mode bit defines the low-power mode to be entered when ZZ# is driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can also be enabled directly by writing to the CR using the software-access sequence. Note that this disables ZZ# initiation of PAR. DPD cannot properly be enabled or disabled using the software-access sequence; DPD should only be enabled or disabled using ZZ# to access the CR. DPD operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the PSRAM device. When DPD is enabled, any stored data will become corrupted. When refresh activity has been re-enabled, the PSRAM device will require 150s to perform an initialization procedure before normal operation can resume. DPD should not be enabled using CR software access. Page Mode READ Operation (CR[7]) Default = Disabled The page mode operation bit determines whether page mode READ operations are enabled. In the power-up default state, page mode is disabled. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Electrical Characteristics Electrical Characteristics Stresses greater than those listed in Table 3 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 3: Absolute Maximum Ratings Parameter Rating -0.5V to 4.0V or VCCQ + 0.3V (whichever is less) -0.2V to +4.0V -0.2V to +4.0V -55C to +150C Voltage to any ball except VCC; VCCQ relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage temperature Operating temperature (case) Wireless Industrial -30C to +85C -40C to +85C Soldering temperature and time 10 seconds (solder ball only) Table 4: 260C Electrical Characteristics and Operating Conditions Wireless temperature (-30C TC +85 C); Industrial temperature (-40C < TC < +85C) Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current IOH = -0.2mA IOL = 0.2mA VIN = 0 to VCCQ OE# = VIH or Chip disabled Operating Current Asynchronous random READ/WRITE Asynchronous page READ Standby current Notes: VIN = VCCQ or 0V Chip enabled; IOUT = 0 VIN = VCCQ or 0V CE# = VCCQ Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO Min Max Unit 2.7 2.7 VCCQ - 0.4 -0.2 0.8 VCCQ - - - 3.6 3.6 VCCQ + 0.2 +0.4 - 0.2 VCCQ 1 1 V V V V V V A A Notes 1 2 ICC1 -55, -70 - 30 mA 3 ICC1P ISB -55, -70 - - 18 140 mA A 3 4 1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. 2. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. 3. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 4. ISB (MAX) values measured with PAR set to FULL ARRAY. To achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for up to 500ms after power-up or when entering standby mode. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Electrical Characteristics Maximum and Typical Standby Currents Maximum and typical standby currents for the MT45V256KW16PE device are shown in Figure 13. Figure 13: Typical Refresh Current vs. Temperature 90 80 70 ISB (A) 60 50 40 30 20 PAR full PAR 0 10 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 Temperature (C) Table 5: Deep Power-Down Specifications and Conditions Description Deep power-down Table 6: Conditions Symbol Typ Units VIN = VCCQ or 0V; +25C ZZ# = 0V CR[4] = 0 IZZ 45 A Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: Conditions Symbol Min Max Unit Notes TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.0 6.5 6.5 pF pF 1 1 1. These parameters are verified in device characterization and are not 100% tested. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Electrical Characteristics Figure 14: AC Input/Output Reference Waveform VCCQ Input 2 1 VCCQ/2 3 VCCQ/2 Test points Output VSSQ Notes: Figure 15: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. Output Load Circuit Test point 50 DUT VccQ/2 30pF Table 7: READ Cycle Timing Requirements -55 Parameter Address access time Page access time LB#/UB# access time LB#/UB# disable to High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time Chip disable to High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to High-Z output Output enable to Low-Z output Page cycle time Read cycle time Notes: -70 Symbol Min Max Min Max Unit tAA - - - - 10 - - - 10 - 5 - 3 20 55 55 15 55 8 - 8 55 8 - 20 - 8 - - - - - - - 10 - - - 10 - 5 - 3 20 70 70 20 70 8 - 8 70 8 - 20 - 8 - - - ns ns ns ns ns s ns ns ns ns ns ns ns ns ns tAPA tBA tBHZ t BLZ tCEM tCO tHZ t LZ t OE tOH tOHZ tOLZ t PC t RC Notes 1 2 3 1 2 1 2 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 19. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 19. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 3. Page mode enabled only. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Electrical Characteristics Table 8: WRITE Cycle Timing Requirements -55 Parameter Symbol Address setup time Address valid to end of write Byte select to end of write CE# HIGH time during write Chip enable to end of write Data hold from write time Data write setup time Chip enable to Low-Z output End write to Low-Z output WRITE cycle time Write to High-Z output Write pulse width Write pulse width HIGH Write recovery time Notes: Table 9: t AS AW t BW t CPH tCW t DH t DW tLZ tOW t WC tWHZ tWP tWPH tWR t -70 Min Max Min Max Unit 0 45 45 5 45 0 23 10 5 55 - 35 10 0 - - - - - - - - - - 8 - - - 0 70 70 5 70 0 23 10 5 70 - 46 10 0 - - - - - - - - - - 8 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 3 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 19. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 19. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 3. WE# LOW time must be limited to tCEM (8s). Load Configuration Register Timing Requirements -55 Description Address setup time Address valid to end of write Chip deselect to ZZ# LOW Chip enable to end of write Write cycle time Write pulse width Write recovery time ZZ# LOW to WE# LOW Table 10: Notes -70 Symbol Min Max Min Max Unit tAS 0 45 5 45 55 35 0 10 - - - - - - - 500 0 70 5 70 70 46 0 10 - - - - - - - 500 ns ns ns ns ns ns ns ns tAW tCDZZ tCW tWC t WP tWR tZZWE Deep Power-Down Timing Requirements -55 Description Chip deselect to ZZ# LOW Deep power-down recovery Minimum ZZ# pulse width PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN Symbol t CDZZ tR tZZ (MIN) -70 Min Max Min Max Unit 5 150 10 - - - 5 150 10 - - - ns s s 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Timing Diagrams Timing Diagrams Table 11: Initialization Timing Parameters Parameter Symbol t Initialization period (required before normal operations) Figure 16: PU Min Max Unit - 150 s Power-Up Initialization Period Vcc (MIN) Vcc, VccQ = 2.7V Figure 17: tPU Device ready for normal operation Load Configuration Register tWC Address OPCODE tAW tWR tCW CE# LB#/UB# tAS tWP WE# OE# tCDZZ tZZWE ZZ# Don't Care Figure 18: Deep Power-Down Entry and Exit tCDZZ tZZ (MIN) ZZ# tR CE# Device ready for normal operation Don't Care PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Timing Diagrams Figure 19: Single READ Operation (WE# = VIH) tRC Valid address Address tAA tHZ CE# tCO tBA tBHZ LB#/UB# tLZ tBLZ tOHZ tOE OE# tOLZ Data out High-Z Valid data High-Z Don't Care Figure 20: Undefined Page Mode READ Operation (WE# = VIH) tRC Address A[17:4] Valid address Address A[3:0] tAA tPC tCEM tHZ CE# tCO tBHZ tBA LB#/UB# tBLZ tLZ tOHZ tOE OE# tAPA tOH tOLZ Data out Valid data High-Z Valid data Valid data Don't Care PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 22 Valid data High-Z Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Timing Diagrams Figure 21: WRITE Cycle (WE# Control) tWC Address Valid address tWR tAW tCW CE# tBW LB#/UB# tWPH tWP tAS WE# OE# tDW Data in tDH Valid data tWHZ tOW High-Z Data out Don't Care Figure 22: WRITE Cycle (CE# Control) tWC Valid address Address tAW tWR tCPH tCW CE# tAS tBW LB#/UB# tWP WE# OE# tDW Data in tLZ tDH Valid data tWHZ High-Z Data out Don't Care PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Timing Diagrams Figure 23: WRITE Cycle (LB#/UB# Control) tWC Valid address Address tAW tWR tCW CE# tAS tBW LB#/UB# WE# OE# tDW Data in tDH Valid data tLZ tWHZ Data out High-Z Don't Care PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Package Dimensions Package Dimensions Figure 24: 48-Ball VFBGA 0.70 0.05 Seating plane A 0.10 A 48X O0.37 Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu Substrate material: plastic laminate Mold compound: epoxy novolac 3.75 Dimensions apply to solder balls post-reflow. Pre-reflow ball diameter is 0.35 on a 0.30 SMD ball pad. 0.75 TYP Ball A1 ID Ball A1 Ball A1 ID 4.00 0.05 Ball A6 CL 5.25 8.00 0.10 2.625 0.75 TYP CL 1.875 1.00 MAX 3.00 0.05 6.00 0.10 Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45V256KW16PE uses "green" packaging. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Revision History Revision History Rev. B, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08 * Changed to production status. Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08 * Initial release. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved.