DESCRIPTION
The 38C5 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38C5 group has an LCD drive control circuit, an A/D converter,
and a serial interface as additional functions.
The various microcomputers in the 38C5 group include variations of
internal memory type, memory size, and packaging.
This data sheet has described only the One Time PROM version of
38C5 group. Refer to “38C5 Group Datasheet” about products other
than the One Time PROM version.
FEATURES
●Basic machine-language instructions ....................................... 71
●The minimum instruction execution time .......................... 0.67 µs
(at 6 MHz oscillation frequency)
●Memory size
ROM ............................................................................ 60 K bytes
RAM ............................................................................ 2048 bytes
●Programmable input/output ports ......... 59 (common to SEG: 32)
●Interrupts...................................................17 sources, 16 vectors
(Key input interrupt included)
●Timers ............................................................8-bit ✕ 4, 16-bit ✕ 2
●Serial interface
Serial I/O1 ......................8-bit ✕ 1 (UART or Clock-synchronized)
Serial I/O2 .....................................8-bit ✕ 1 (Clock-synchronized)
●PWM .................. 10-bit ✕ 2, 16-bit ✕ 1 (common to IGBT output)
●A/D converter ................................................. 10-bit ✕ 8 channels
(A/D converter can be operated in low-speed mode.)
●Watchdog timer ............................................................... 8-bit ✕ 1
● LED direct drive port .................................................................. 6
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
●LCD drive control circuit
Bias ................................................................................... 1/2, 1/3
Duty ......................................................... Static, 1/2, 1/3, 1/4, 1/8
Common output ....................................................................... 4/8
Segment output ................................................................... 32/36
●Main clock generating circuit ...................................................... 1
(connect to external ceramic resonator or on-chip oscillator)
●Sub-clock generating circuit........................................................ 1
(connect to external quartz-crystal oscillator)
●Power source voltage
In high-speed mode (f(XIN) = 6 MHz) .........................3.0 to 3.6 V
In high-speed mode (f(XIN) = 4 MHz) .........................2.0 to 3.6 V
In middle-speedmode (f(XIN) = 6 MHz).......................1.8 to 3.6 V
In low-speed mode .....................................................1.8 to 3.6 V
●Power dissipation (Mask ROM version)
• In high-speed mode................................................. Typ. 15 mW
(VCC = 2.5 V, f(XIN) = 4 MHz, Ta = 25°C)
• In low-speed mode ...................................................Typ. 18 µW
(VCC = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
●Operating temperature range ................................... – 20 to 85°C
APPLICATION
Household products, Consumer electronics, etc.
Rev.2.00 Nov 23, 2005 page 1 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0098-0200
Rev.2.00
Nov 23, 2005
Rev.2.00 Nov 23, 2005 page 2 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
PIN CONFIGURATION
(TOP VIEW)
Package type : PLQP0080GA-A (80P6U-A)
Fig. 1 M38C59GFFP pin configuration
P20/SEG0/(KW4)
P21/SEG1/(KW5)
P22/SEG2/(KW6)
P23/SEG3/(KW7)
P24/SEG4
P25/SEG5
P26/SEG6
P27/SEG7
P00/SEG8
P03/SEG11
P04/SEG12
P05/SEG13
P06/SEG14
P07/SEG15
P11/SEG17
P12/SEG18
P13/SEG19
P14/SEG20
P15/SEG21
P16/SEG22
P17/SEG23
P44/SIN2/(KW0)
P45/SOUT2/(KW1)
P46/SCLK2/(KW2)
P47/SRDY2/(KW3)
COM1
COM3
COM0
P37/SEG31
P36/SEG30
P35/SEG29
P34/SEG28
P33/SEG27
P32/SEG26
P31/SEG25
P30/SEG24
COM2
P10/SEG16
P01/SEG9
P02/SEG10
123456789 19 22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
414243
44
4546474849505152535455565758596061626364
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
23 2410 11 12 13 14 15 16 17 18 20 21
P55/AN5
P54/AN4
P53/AN3
P52/AN2
VREF
AVss
P63/TXOUT2/(LED1)
P66/INT10/CNTR0/(LED4)
M38C59GFFP
P5
7/AN7/ADKEY0
P56/AN6
P65/TXOUT1 /(LED3)
P64/INT2 /(LED2)
P62/INT00 /(LED0)
COM4/SEG35
COM5/SEG34
COM6/SEG33
COM7/SEG32
P43/SRDY1
P42/SCLK1
P41/T
X
D
P40/R
X
D
P51/AN1/RTP1
P50/AN0/RTP0
P61/XCOUT
P60/XCIN
P71/C
2
/INT11
V
L3
V
L2
V
L1
P72/T2OUT/CKOUT
XIN
P74/PWM1/T4OUT
VSS
XOUT
VCC
CNVSS
P67/CNTR1/(LED5)
RESET
P73/PWM0/T3OUT
P70/C
1
/INT01
Rev.2.00 Nov 23, 2005 page 3 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
PIN CONFIGURATION
(TOP VIEW)
Package type : PLQP0080KB-A (80P6Q-A)
Fig. 2 M38C59GFHP pin configuration
1
2
3
4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
M38C59GFHP
P5
1
/AN
1
/RTP
1
P5
0
/AN
0
/RTP
0
P6
3
/T
XOUT2
/(LED
1
)
P6
6
/INT
10
/CNTR
0
/(LED
4
)
P6
5
/T
XOUT1
/(LED3)
P6
4
/INT
2
/(LED
2
)
P6
2
/INT
00
/(LED
0
)
P6
1
/X
COUT
P6
0
/X
CIN
P7
1
/C
2
/INT
11
V
L3
V
L2
P7
2
/T
2OUT
/CKOUT
X
IN
P7
4
/PWM
1
/T
4OUT
V
SS
X
OUT
V
CC
CNV
SS
P6
7
/CNTR
1
/(LED
5
)
RESET
P7
3
/PWM
0
/T
3OUT
P7
0
/C
1
/INT
01
V
L1
COM
1
COM
3
COM
0
P3
7
/SEG
31
P3
6
/SEG
30
P3
5
/SEG
29
P3
4
/SEG
28
COM
2
COM
5
/SEG
34
COM
6
/SEG
33
COM
7
/SEG
32
P3
3
/SEG
27
P3
2
/SEG
26
P3
1
/SEG
25
P3
0
/SEG
24
P1
5
/SEG
21
P1
6
/SEG
22
P1
7
/SEG
23
P1
4
/SEG
20
P1
3
/SEG
19
P1
2
/SEG
18
P1
1
/SEG
17
P1
0
/SEG
16
P0
7
/SEG
15
P0
6
/SEG
14
P0
5
/SEG
13
P0
4
/SEG
12
P0
3
/SEG
11
P0
2
/SEG
10
P0
1
/SEG
9
P0
0
/SEG
8
P2
7
/SEG
7
P2
6
/SEG
6
P2
5
/SEG
5
P2
4
/SEG
4
P2
3
/SEG
3
/(KW
7
)
P2
2
/SEG
2
/(KW
6
)
P2
1
/SEG
1
/(KW
5
)
P2
0
/SEG
0
/(KW
4
)
P4
4
/S
IN2
/(KW0)
P4
5
/S
OUT2
/(KW
1
)
P4
6
/S
CLK2
/(KW
2
)
P4
7
/S
RDY2
/(KW
3
)
P5
5
/AN
5
P5
4
/AN
4
P5
3
/AN
3
P5
2
/AN
2
V
REF
AVss
P5
7
/AN
7
/ADKEY
0
P5
6
/AN
10
P4
3
/S
RDY1
P4
2
/S
CLK1
P4
1
/T
X
D
P4
0
/R
X
D
COM
4
/SEG
35
Rev.2.00 Nov 23, 2005 page 4 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
FUNCTIONAL BLOCK DIAGRAM
Fig. 3 Functional block diagram
T
i
m
e
r
T
i
m
e
r
X
(
1
6
b
i
t
s
)
P
W
M
(
1
6
b
i
t
s
)
I
G
B
T
o
u
t
p
u
t
T
i
m
e
r
Y
(
1
6
b
i
t
s
)
T
i
m
e
r
1
(
8
b
i
t
s
)
T
i
m
e
r
2
(
8
b
i
t
s
)
T
i
m
e
r
3
(
8
b
i
t
s
)
P
W
M
0
(
1
0
b
i
t
s
)
T
i
m
e
r
4
(
8
b
i
t
s
)
P
W
M
1
(
1
0
b
i
t
s
)
P
o
r
t
P
0
(
8
)
8
P
o
r
t
P
1
(
8
)
8
P
o
r
t
P
2
(
8
)
8
I
n
t
e
r
n
a
l
p
e
r
i
p
h
e
r
a
l
f
u
n
c
t
i
o
n
A
/
D
c
o
n
v
e
r
s
i
o
n
1
0
-
b
i
t
✕
8
-
c
h
a
n
n
e
l
S
e
r
i
a
l
I
/
O
S
e
r
i
a
l
I
/
O
1
(
U
A
R
T
o
r
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
)
S
e
r
i
a
l
I
/
O
2
(
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
)
S
y
s
t
e
m
c
l
o
c
k
φ g
e
n
e
r
a
t
i
o
n
X
I
N
–
X
O
U
T
(
M
a
i
n
c
l
o
c
k
)
X
C
I
N
–
X
C
O
U
T
(
S
u
b
-
c
l
o
c
k
)
M
e
m
o
r
y
R
O
M
R
A
M
f
o
r
L
C
D
d
i
s
p
l
a
y
(
3
6
b
y
t
e
s
)
R
A
M
C
P
U
c
o
r
e
W
a
t
c
h
d
o
g
t
i
m
e
r
8
8
P
o
r
t
P
4
(
8
)
P
o
r
t
P
5
(
8
)
P
o
r
t
P
6
(
8
)
P
o
r
t
P
3
(
8
)
8
8
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
P
o
r
t
P
7
(
5
)
3
2
Rev.2.00 Nov 23, 2005 page 5 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
• Apply power source voltage to VCC, and 0 V to VSS.
•Reset input pin for active “L.”
•Input and output pins for the main clock generating circuit.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to
set the oscillation frequency. When an external clock is used, connect the clock source to XIN,
and leave XOUT pin open.
•Feedback resistor is built in between XIN pin and XOUT pin.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
•Input 0 – VL3 voltage to LCD.
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
• LCD common/segment output pins.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each 4-bit pin to be
programmed as either input or output.
• Pull-up control is enabled in 4-bit unit.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each 4-bit pin to be
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each 4-bit pin to be
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
VCC, VSS
RESET
XIN
VL1, VL2, VL3
COM0 –
COM3
COM4/SEG35 –
COM7/SEG32
P00/SEG8 –
P07/SEG15
P10/SEG16 –
P17/SEG23
P20/SEG0/(KW4)–
P23/SEG3/(KW7)
P24/SEG4 –
P27/SEG7
P30/SEG24 –
P37/SEG31
P40/RxD
P41/TxD
P42/SCLK1
P43/SRDY1
P44/SIN2/(KW0),
P4
5
/S
OUT2
/(KW
1
),
P46/SCLK2/(KW2),
P47/SRDY2/(KW3),
Power source
Reset input
Clock input
LCD power
source
Common output
Common output
Segment output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Function except a port function
PIN DESCRIPTION
Table 1 Pin description (1)
FunctionPin Name
• Serial I/O1 function pins
XOUT Clock output
•Key input interrupt
input pins
• Serial I/O2
function pins •Key input interrupt
input pins
Rev.2.00 Nov 23, 2005 page 6 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Function except a port function
PIN DESCRIPTION
Table 2 Pin description (2)
FunctionPin Name
P50/AN0/RTP0,
P51/AN1/RTP1
P52/AN2 –
P56/AN6
P57/AN7/ADKEY0
P60/XCIN,
P61/XCOUT
P62/INT00/(LED0),
P63/TXOUT2/
(LED1),
P64/INT2/(LED2)
P65/TXOUT1/
(LED3)
P66/INT10/
CNTR0/(LED4),
P67/CNTR1/
(LED5)
P70/C1/INT01,
P71/C2/INT11
P72/T2OUT/
CKOUT
P73/PWM0/T3OUT,
P74/PWM1/T4OUT
CNVSS
VREF
AVSS
I/O port P5
I/O port P6
Input port P7
I/O port P7
CNVSS
Analog reference
voltage
Analog power source
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• P62 to P67 (6 bits) are enabled to output large current
for LED drive.
• 2-bit input port.
• CMOS input level.
•3-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•Connect to VSS.
•Reference voltage input pin for A/D converter.
•GND input pin for A/D converter. Connect to VSS.
• A/D converter input
pins
•Sub clock generating I/O pins
(oscillator connected)
•External interrupt pin
•Timer X output pin
•External interrupt pin
•Timer X output pin
• T imer X, Timer Y
output pins
•External interrupt
pins
• Clock output pin
•PWM output pins
•Real time port
function pins
• ADKEY input pin
•External interrupt
pins
• External capacitor
connect pins for a
voltage multiplier
of LCD.
• Timer 2 output pin
• Timer 3 output pin
• Timer 4 output pin
Rev.2.00 Nov 23, 2005 page 7 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
PART NUMBERING
Fig. 4 Part numbering
M38C5 9 G F FP
Product
ROM/PROM memory size
1
2
3
4
5
6
7
8
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
G : One Time PROM verison
RAM size
0
1
2
3
4
5
6
7
8
9
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
Package type
FP
HP: PLQP0080GA-A package
: PLQP0080KB-A package
9
A
B
C
D
E
F
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
Rev.2.00 Nov 23, 2005 page 8 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
GROUP EXPANSION
Renesas plans to expand the 38C5 group (One Time PROM ver-
sion) as follows.
Memory Size
One Time PROM size ..................................................... 60 K bytes
RAM size........................................................................ 2048 bytes
Packages
PLQP0080GA-A.......................... 0.5 mm-pitch plastic molded QFP
PLQP0080KB-A .......................... 0.8 mm-pitch plastic molded QFP
Memory Expansion Plan
Fig. 5 Memory expansion plan
Currently supported products are listed below.
Table 3 Support products As of November. 2005
Package
PLQP0080GA-A
PLQP0080KB-A
Part number ROM size (bytes)
ROM size for User in ( ) RAM size
(bytes)
One Time PROM version
Remarks
M38C59GFFP
M38C59GFHP
32k
28k
24k
20k
16k
12k
8k
4k
256 384 512 640 768 896 1,024
192
40k
48k
1,536 2,048
56k
60k
M38C59GF
ROM size (
bytes)
RAM size
(
b
y
tes
)
Mass production
2048
61440 (61310)
Rev.2.00 Nov 23, 2005 page 9 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 38C5 group uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
The central processing unit (CPU) has six registers. Figure 6 shows
the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as arith-
metic data transfer, etc., are executed mainly through the accumula-
tor.
[Index Register X (X)]
The index register X is an 8-bit register . In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the con-
tents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack
page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and pop-
ping them from the stack are shown in Figure 7.
Table 4 shows the push and pop instructions of accumulator or pro-
cessor status register.
Store registers other than those described in Figure 7 with program
when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PCH and PCL. It is used to indicate the address of the next in-
struction to be executed.
Fig. 6 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PC
L
Program counterPC
H
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Rev.2.00 Nov 23, 2005 page 10 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Fig. 7 Register push and pop at interrupt generation and subroutine call
Note: Condition for acceptance of an interrupt request here Interrupt disable flag is “0” and
E
x
e
c
u
t
e
J
S
R
O
n
-
g
o
i
n
g
R
o
u
t
i
n
e
M
(
S
)(
P
CH)
(
S
)
(
S
)
–
1
M
(
S
)(
P
CL)
E
x
e
c
u
t
e
R
T
S
(
P
CL)M
(
S
)
(
S
)
(
S
)
–
1
(
S
)
(
S
)
+
1
(
S
)
(
S
)
+
1
(
P
CH)M
(
S
)
S
u
b
r
o
u
t
i
n
e
P
O
P
re
t
u
r
n
a
d
d
r
e
s
s
f
r
o
m
s
t
a
c
k
P
u
s
h
r
e
t
u
r
n
a
d
d
r
e
s
s
o
n
s
t
a
c
k
M
(
S
)(
P
S
)
Execute RTI
(
P
S
)M
(
S
)
(
S
)
(
S
)
–
1
(S) (S) + 1
I
n
t
e
r
r
u
p
t
S
e
r
v
i
c
e
R
o
u
t
i
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P
O
P
c
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n
t
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o
f
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r
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f
r
o
m
s
t
a
c
k
M
(
S
)(
P
CH)
(S) (S) – 1
M (S) (PCL)
(
S
)
(
S
)
–
1
(PCL)M (S)
(
S
)
(
S
)
+
1
(S) (S) + 1
(PCH)M (S)
POP return
address
from stack
I
F
l
a
g
i
s
s
e
t
f
r
o
m
“
0
”
t
o
“
1
”
F
e
t
c
h
t
h
e
j
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m
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t
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P
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r
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r
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s
o
n
s
t
a
c
k
P
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s
h
c
o
n
t
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t
s
o
f
p
r
o
c
e
s
s
o
r
s
t
a
t
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s
r
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g
i
s
t
e
r
o
n
s
t
a
c
k
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
N
o
t
e
)
Interrupt enable bit corresponding to each interrupt source is “1”
Pop instruction from stack
PLA
PLP
Rev.2.00 Nov 23, 2005 page 11 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic opera-
tion and 3 flags which decide MCU operation. Branch operations
can be performed by testing the Carry (C) flag , Zero (Z) flag, Over-
flow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N
flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set to “1” if the result of an immediate arithmetic
operation or a data transfer is “0”, and set to “0” if the result is
anything other than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. When the BRK instruction is gener-
ated, the B flag is set to “1” automatically. When the other inter-
rupts are generated, the B flag is set to “0”, and the processor
status register is pushed onto the stack.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory. When the T flag is “1”, direct arith-
metic operations and direct data transfers are enabled between
memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of
signed data. It is set if the result exceeds +127 to -128. When the
BIT instruction is executed, bit 6 of the memory location operated
on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set to “1” if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is executed, bit
7 of the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
Rev.2.00 Nov 23, 2005 page 12 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the control bit for the internal system clock etc.
The CPU mode register is allocated at address 003B16.
After system is released from reset, the on-chip oscillator mode is
selected, and the XIN–XOUT oscillation and the XCIN–XCOUT oscilla-
tion are stopped.
Fig. 8 Structure of CPU mode register
N
o
t
a
v
a
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l
a
b
l
e
P
r
o
c
e
s
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1
b
0
0
0
:
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0
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:
1
0
:
1
1
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t
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b
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0
:
X
I
N
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p
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t
s
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l
(
X
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N
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X
O
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–
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C
O
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T
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s
c
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l
a
t
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g
f
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c
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–
X
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M
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m
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(
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(
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C
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–
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C
O
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T
s
e
l
e
c
t
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d
(
l
o
w
-
s
p
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d
m
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)
C
P
U
m
o
d
e
r
e
g
i
s
t
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r
(
C
P
U
M
(
C
M
)
:
a
d
d
r
e
s
s
0
0
3
B
1
6
)
b
7
b
0
N
Y
A
f
t
e
r
r
e
l
e
a
s
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r
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t
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t
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e
o
s
c
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l
l
a
t
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n
(
b
i
t
s
4
a
n
d
5
o
f
C
P
U
M
)
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w
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t
c
h
t
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m
a
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r
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t
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b
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t
(
b
i
t
6
o
f
C
P
U
M
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M
a
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n
r
o
u
t
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n
e
S
t
a
r
t
w
i
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h
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o
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c
h
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p
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s
c
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l
a
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r
.
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n
i
t
i
a
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v
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f
C
P
U
M
i
s
6
8
1
6
.
A
s
f
o
r
t
h
e
d
e
t
a
i
l
s
o
f
c
o
n
d
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o
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t
r
a
n
s
i
t
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a
m
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g
e
a
c
h
m
o
d
e
,
r
e
f
e
r
t
o
t
h
e
s
t
a
t
e
t
r
a
n
s
i
t
i
o
n
o
f
s
y
s
t
e
m
c
l
o
c
k
.
Oscillator starts osci llation.
Do not ch ange b it 3 , bi t 6 and bit 7
of CPUM until oscillation stabilizes.
W
a
i
t
b
y
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
o
p
e
r
a
t
i
o
n
u
n
t
i
l
e
s
t
a
b
l
i
s
h
m
e
n
t
o
f
o
s
c
i
l
l
a
t
o
r
c
l
o
c
k
L
o
w
-
,
m
i
d
d
l
e
-
,
o
r
h
i
g
h
-
s
p
e
e
d
m
o
d
e
?
S
e
l
e
c
t
i
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
(
b
i
t
3
o
r
b
i
t
7
o
f
C
P
U
M
)
System c an operate in on-chip os c illator
mode unt il o s c illation stabilize.
S
e
l
e
c
t
i
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
.
D
o
n
o
t
c
h
a
n
g
e
b
i
t
3
a
n
d
b
i
t
7
,
o
r
b
i
t
6
a
n
d
b
i
t
7
o
f
C
P
U
M
a
t
t
h
e
s
a
m
e
t
i
m
e
.
Select main clock division ratio.
Switch to high-speed mode here, if necessary.
Fig. 9 Switch procedure of CPU mode register
When the low-, middle- or high-speed mode is used after the XIN–
XOUT oscillation and the XCIN–XCOUT oscillation are enabled, wait in
the on-chip oscillator mode etc. until oscillation stabilizes, and then,
switch the operation mode.
When the middle- and high-speed mode are not used (XIN–XOUT
oscillation and external clock input are not performed), connect XIN
to VCC through a resistor.
Rev.2.00 Nov 23, 2005 page 13 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 10 Memory map diagram
010016
000016
004016
084016
FF0016
FFDC16
FFFE16
FFFF16
192
256
384
512
640
768
896
1024
1536
2048
XXXX16
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
YYYY16
ZZZZ16
RAM
ROM
RAM area
RAM size
(bytes) Address
XXXX16
ROM area
ROM size
(bytes) Address
YYYY16 Address
ZZZZ16
Reserved area
SFR area
Not used
Interrupt vector area
Reserved ROM area
(128 bytes)
Zero
page
Special
page
LCD display RAM area
Reserved ROM area
SFR area
086316
0FF016
100016
Rev.2.00 Nov 23, 2005 page 14 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 11 Memory map of special function register (SFR)
0
FF
9
16
0020
16
0021
16
0
0
2
2
1
6
0
0
2
3
1
6
0
0
2
4
1
6
0
0
2
5
1
6
0
0
2
6
1
6
0
0
2
7
1
6
0
0
2
8
1
6
0
0
2
9
1
6
002
A
16
002
B
16
002
C
16
002
D
16
002
E
16
002
F
16
0
0
3
0
1
6
0
0
3
1
1
6
0
0
3
2
1
6
0
0
3
3
1
6
0
0
3
4
1
6
0
0
3
5
1
6
0
0
3
6
1
6
0
0
3
7
1
6
0
0
3
8
1
6
0
0
3
9
1
6
003
A
16
003
B
16
003
C
16
003
D
16
003
E
16
0
0
3
F
1
6
0000
16
0001
16
0
0
0
2
1
6
0
0
0
3
1
6
0
0
0
4
1
6
0
0
0
5
1
6
0
0
0
6
1
6
0
0
0
7
1
6
0
0
0
8
1
6
0
0
0
9
1
6
0
0
0
A
1
6
000
B
16
000
C
16
000
D
16
000
E
16
000
F
16
0
0
1
0
1
6
0
0
1
1
1
6
0
0
1
2
1
6
0
0
1
3
1
6
0
0
1
4
1
6
0
0
1
5
1
6
0
0
1
6
1
6
0
0
1
7
1
6
0
0
1
8
1
6
0
0
1
9
1
6
001
A
16
001
B
16
001
C
16
001
D
16
0
0
1
E
1
6
0
0
1
F
1
6
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
4
(
P
4
)
P
ort
P
4
di
rect
i
on reg
i
ster
(P
4
D)
P
o
r
t
P
5
(
P
5
)
P
ort
P
5
di
rect
i
on reg
i
ster
(P
5
D)
P
o
r
t
P
6
(
P
6
)
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
6
D
)
AD
contro
l
re g
i
ster
(ADCON)
AD
convers
i
on reg
i
ster
(l
ow-or
d
er
)
(ADL)
A
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
(
A
D
H
)
I
nterrupt contro
l
reg
i
ster 2
(ICON
2
)
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
I
N
T
E
D
G
E
)
CPU
mo
d
e reg
i
ster
(CPUM)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
(
I
R
E
Q
1
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
(
I
R
E
Q
2
)
I
nterrupt contro
l
reg
i
ster 1
(ICON
1
)
T
i
m
e
r
1
(
T
1
)
T
i
m
e
r
3
(
T
3
)
P
W
M
0
1
r
e
g
i
s
t
e
r
(
P
W
M
0
1
)
T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
M
)
T
i
m
e
r
2
(
T
2
)
T
i
m
e
r
4
(
T
4
)
C
ompare reg
i
ster 1
(l
ow-or
d
er
)
(COMP
1
L)
C
ompare reg
i
ster 1
(hi
g
h
-or
d
er
)
(COMP
1
H)
Ti
mer
X
(l
ow-or
d
er
)
(TXL)
Ti
mer
X
(hi
g
h
-or
d
er
)
(TXH)
Ti
mer
X
(
extens
i
on
)
(TXEX)
0
FF
0
16
0
FF
1
16
0
F
F
2
1
6
0
FF
6
16
0
F
F
7
1
6
0
F
F
3
1
6
0
FF
4
16
0
FF
5
16
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
3
D
)
T
ransm
i
t/rece
i
ve
b
u
ff
er reg
i
ster 1
(TB
1/
RB
1
)
S
er
i
a
l
I
/
O
1 status reg
i
ster
(SIO
1
STS)
S
er
i
a
l
I
/
O
2 reg
i
ster
(SIO
2
)
UART
contro
l
reg
i
ster
(UARTCON)
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
1
C
O
N
)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
2
C
O
N
)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
(
B
R
G
)
Cl
oc
k
output contro
l
reg
i
ster
(CKOUT)
T
i
m
e
r
3
4
m
o
d
e
r
e
g
i
s
t
e
r
(
T
3
4
M
)
Ti
mer
X
mo
d
e reg
i
ster
(TXM)
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
W
D
T
C
O
N
)
0
FF
8
16
0
FFA
16
0
FFB
16
0
FFC
16
0
FFD
16
0
FFE
16
0
FFF
16
P
ort
P
7
(P
7
)
P
ort
P
7
di
rect
i
on reg
i
ster
(P
7
D)
R
eserve
d
area
(
access
di
sa
bl
e
d)
Ti
me r 1234 mo
d
e reg
i
ster
(T
1234
M)
T
i
m
e
r
1
2
3
4
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
R
E
1
2
3
4
)
T
i
m
e
r
X
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
T
X
C
O
N
1
)
T
i
m
e
r
X
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
T
X
C
O
N
2
)
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
2
(
l
o
w
-
o
r
d
e
r
)
(
C
O
M
P
2
L
)
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
2
(
h
i
g
h
-
o
r
d
e
r
)
(
C
O
M
P
2
H
)
C
ompare reg
i
ster 3
(l
ow-or
d
er
)
(COMP
3
L)
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
3
(
h
i
g
h
-
o
r
d
e
r
)
(
C
O
M
P
3
H
)
Ti
mer
Y
(l
ow-or
d
er
)
(TYL)
Ti
mer
Y
(hi
g
h
-or
d
er
)
(TYH)
Ti
mer
Y
mo
d
e reg
i
ster
(TYM)
Ti
mer
Y
contro
l
reg
i
ster
(TYCON)
PULL
reg
i
ster 1
(PULL
1
)
K
ey
i
nput contro
l
re g
i
ster
(KIC)
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
1
(
L
M
1
)
S
egment output
di
sa
bl
e reg
i
ster 0
(SEG
0
)
S
egment output
di
sa
bl
e reg
i
ster 1
(SEG
1
)
S
egment output
di
sa
bl
e reg
i
ster 2
(SEG
2
)
PULL
reg
i
ster 2
(PULL
2
)
PULL
reg
i
ster 3
(PULL
3
)
LCD
mo
d
e reg
i
ster 2
(LM
2
)
R
R
F
r
e
g
i
s
t
e
r
(
R
R
F
R
)
N
ote.
D
o not access to t
h
e
SFR
area
i
nc
l
u
di
ng not
hi
ng.
Rev.2.00 Nov 23, 2005 page 15 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
I/O PORTS
Direction Registers (Ports P0–P6, P72–P74)
The I/O ports P0–P6, P72–P74 have direction registers which deter-
mine the input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, each pin can be set to be
input port or output port.
When “0” is written to the bit of the direction register , the correspond-
ing pin becomes an input pin. As for ports P0–P3, when “1” is written
to the bit of the direction register and the segment output disable
register, the corresponding pin becomes an output pin. As for ports
P4–P6, P72–P74, when “1” is written to the bit of the direction regis-
ter, the corresponding pin becomes an output pin.
If data is read from a pin set to output, the value of the port latch is
read, not the value of the pin itself. However, when RTP1, RTP0,
TXOUT1, TXOUT2, T4OUT, T3OUT and T2OUT/CKOUT output are se-
lected, the output value is read, not the value of the port latch. Pins
set to input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Ports P70, P71
These are input ports which are shared with the voltage multiplier.
When these are read out at using the voltage multiplier, the contents
are “1”.
Pull-up Control
Each individual bit of ports P0–P3 can be pulled up with a program
by setting direction registers and segment output disable registers 0
to 2 (addresses 0FF416 to 0FF616).
The pin is pulled up by setting “0” to the direction register and “1” to
the segment output disable register.
By setting the PULL registers (addresses 0FF016 to 0FE216), ports
P4–P7 can control pull-up with a program.
However, the contents of PULL register do not affect ports pro-
grammed as the output ports.
Fig. 13 Structure of PULL register and segment output disable register
Fig. 12 Structure of ports P0 to P3
Segment output
disable register
Direction register
“
0
”
“
1
”
“
0
”“
1
”
I
n
p
u
t
p
o
r
t
N
o
p
u
l
l
-
u
p
S
e
g
m
e
n
t
o
u
t
p
u
tP
o
r
t
o
u
t
p
u
t
I
n
p
u
t
p
o
r
t
P
u
l
l
-
u
p
I
n
i
t
i
a
l
s
t
a
t
e
P6
0
pull-up
P6
1
pull-up
P6
2
pull-up
P6
3
pull-up
P6
4
pull-up
P6
5
pull-up
P6
6
pull-up
P6
7
pull-up
PULL register 2
(PULL2 : address 0FF1
16
)
b7 b0
P0
0
pull-up
P0
1
pull-up
P0
2
pull-up
P0
3
pull-up
P0
4
pull-up
P0
5
pull-up
P0
6
pull-up
P0
7
pull-up
Segment output disable register 0
(SEG0 : address 0FF4
16
)
b7 b0
Note: The PULL register and segment output disable register affect only ports
programmed as the input ports.
0: No pull-up
1: Pull-up
P2
0
pull-up
P2
1
pull-up
P2
2
pull-up
P2
3
pull-up
P2
4
pull-up
P2
5
pull-up
P2
6
pull-up
P2
7
pull-up
b7 b0 Segment output disable register 1
(SEG1 : address 0FF5
16
)
P1
0
–P1
3
pull-up
P1
4
–P1
7
pull-up
P3
0
–P3
3
pull-up
P3
4
–P3
7
pull-up
Not used (return “0 ” when read)
(Do not write to “1 ”)
b7 b0 Segment output disable register 2
(SEG2 : address 0FF6
16
)
0: No pull-up
1: Pull-up
P5
0
pull-up
P5
1
pull-up
P5
2
pull-up
P5
3
pull-up
P5
4
pull-up
P5
5
pull-up
P5
6
pull-up
P5
7
pull-up
PULL register 1
(PULL1 : address 0FF0
16
)
b7 b0
0: No pull-up
1: Pull-up
P4
0
–P4
3
pull-up
P4
4
–P4
7
pull-up
P7
2
–P7
4
pull-up
Not used (return “0 ” when read)
(Do not write to “1 ”)
PULL register 3
(PULL3 : address 0FF2
16
)
b7 b0
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Rev.2.00 Nov 23, 2005 page 16 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Common
Common/
Segment
Input/Output
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input
Input/Output,
individual bits
Output
I/O format
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS compatible input level
CMOS 3-state output
LCD common output
LCD common/segment
output
Non-port function
LCD segment
output
Serial I/O1 function I/O
Serial I/O2
function I/O
A/D conversion
input
Sub-clock oscillation circuit
External interrupt input
Timer X output 2
External interrupt input
Timer X output 1
Timer X function input
External interrupt input
Timer Y function input
External interrupt input
LCD voltage multiplier input
Timer 2 output
Timer 3 output
Timer 4 output
LCD common output
Related SFRs
Segment output disable
register 0
Segment output disable
register 2
Segment output disable
register 1
Key input control register
Segment output disable
register 1
Segment output disable
register 2
PULL register 3
Serial I/O1 control register
Serial I/O1 status register
UART control register
PULL register 3
Serial I/O2 control register
Serial I/O2 register
Key input control register
PULL register 1
A/D control register
Timer Y mode register
PULL register 1
A/D control register
PULL register 2
CPU mode register
PULL register 2
Interrupt edge selection
register
PULL register 2
Timer X mode register
Timer X control registers 1, 2
PULL register 2
Interrupt edge selection
register
PULL register 2
Timer X mode register
Timer X control register 1
PULL register 2
Interrupt edge selection
register
Timer X mode register
Timer X control registers 1, 2
PULL register 2
Timer Y mode register
Interrupt edge selection
register
LCD mode registers 1, 2
PULL register 3
Timer 1234 mode register
Timer 1234 frequency
division register
LCD mode registers 1, 2
Ref. No.
(1)
(2)
(1)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(18)
(17)
(18)
(19)
(17)
(20)
(21)
(22)
(23)
Table 6 List of I/O port function
P00/SEG8 –
P07/SEG15
P10/SEG16 –
P17/SEG23
P20/SEG0/(KW4)–
P23/SEG3/(KW7)
P24/SEG4 –
P27/SEG7
P30/SEG24 –
P37/SEG31
P40/RxD
P41/TxD
P42/SCLK1
P43/SRDY1
P44/SIN2/(KW0),
P4
5
/S
OUT2
/(KW
1
),
P46/SCLK2/(KW2),
P47/SRDY2/(KW3)
P50/AN0/RTP0,
P51/AN1/RTP1
P52/AN2 –
P56/AN6
P57/AN7/ADKEY0
P60/XCIN,
P61/XCOUT
P62/INT00/(LED0)
P63/TXOUT2/
(LED1)
P64/INT2/(LED2)
P65/TXOUT1/
(LED3)
P66/INT10/
CNTR0/(LED4),
P67/CNTR1/
(LED5)
P70/C1/INT01,
P71/C2/INT11
P72/T2OUT/CKOUT
P73/PWM0/T3OUT,
P74/PWM1/T4OUT
COM0–COM3
COM4/SEG35–
COM7/SEG32
Pin
Key input
(key-on wakeup)
interrupt input
Key input
(key-on wakeup)
interrupt input
Real time
port function
output
ADKEY input
Clock output
PWM output
LCD segment
output
Rev.2.00 Nov 23, 2005 page 17 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 14 Port block diagram (1)
(2)Ports P20–P23
(6)Port P43
(5)Port P42
(3)Port P40(4)Port P41
(1)Ports P0,P1,P24–P27,P3
Serial I/O1 ready output
Data bus Port latch
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Direction
register
Pull-up control
Serial I/O1 synchronous
clock selection bit
Data bus
Serial I/O1 clock output
Serial I/O1 clock input
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Port latch
Direction
register
Serial I/O1 enable bit Pull-up control
Serial I/O1 enable bit
Transmit enable bit
Serial I/O output
P41/TxD P-channel output disable bit
Pull-up control
Serial I/O1 enable bit
Receive enable bit
Serial I/O input
VL3/VL2
Segment data
VL1/VSS
Data bus Port latch
Segment output disable bit
Direction
register
Key input control
Key-on wakeup
interrupt input
VL3/VL2
VL1/VSS
Segment data
Data bus Port latch
Segment output disable bit
Direction
register
Data bus Port latch
Direction
register
Pull-up control
Data bus Port latch
Direction
register
Rev.2.00 Nov 23, 2005 page 18 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 15 Port block diagram (2)
(7)Port P4
4
Serial I/O2 input
Key-on wakeup interrupt input Key input control
(8)Port P4
5
Serial I/O2 transmit end signal
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
P4
5
/S
OUT2
P-channel output disable bit
(9)Port P4
6
Serial I/O2 synchronous clock selection bit
Serial I/O2 clock output
Serial I/O2 port selection bit
Serial I/O2 clock input
(10)Port P4
7
Serial I/O2 ready output
SRDY2 output selection bit
(11)Ports P5
0
,P5
1
Real time port control bit
Data for real time port
(12)Ports P5
2
–P5
6
Analog input pin selection bit
A/D conversion input
ADKEY enable bit
Data bus Port latch
Direction
register
Pull-up control
Serial I/O2 output
Data bus Port latch
Direction
register
Pull-up control
Key input control
Data bus Port latch
Direction
register
Pull-up control
Data bus Port latch
Direction
register
Pull-up control
Key input control Key input control
Key-on wakeup interrupt input
Data bus Port latch
Direction
register
Pull-up control
Data bus Port latch
Direction
register
Pull-up control
Analog input pin selection bit
A/D conversion input
ADKEY enable bit
Key-on wakeup interrupt input
Key-on wakeup interrupt input
Rev.2.00 Nov 23, 2005 page 19 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 16 Port block diagram (3)
(
1
4
)
P
o
r
t
P
6
0
Port Xc switch bit
S
u
b
-
c
l
o
c
k
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
i
n
p
u
t
(15) Port P6
1Pull-up control
Port P6
0
S
u
b
-
c
l
o
c
k
os
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
Xc oscillation enable
(16) Port P6
2
INT
0
interrupt input
I
N
T
0
i
n
p
u
t
p
o
r
t
s
w
i
t
c
h
b
i
t
(18) Ports P6
3,
P6
5
Pulse output mode
Timer X outpu t 1
Timer X outpu t 2
(
1
3
)
P
o
r
t
P
5
7
A
/
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
A
D
K
E
Y
s
e
l
e
c
t
i
o
n
b
i
t
A
D
K
E
Y
e
n
a
b
l
e
b
i
t
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
(
1
7
)
P
o
r
t
s
P
6
4
,
P
6
7
C
N
T
R
1
i
n
t
e
r
r
u
p
t
i
n
p
u
t
I
N
T
2
i
n
t
e
r
r
u
p
t
i
n
p
u
t
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Data bus Port latch
Direction
register
Data bus Port latch
Direction
register
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
a
t
a
b
u
sPort latch
Direction
register
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
Data bus P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Port Xc switch bit
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Rev.2.00 Nov 23, 2005 page 20 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 17 Port block diagram (4)
Port/Timer output selected
(21) PortsP72,P73,P74(22) COM0 to COM3
V
L3
V
L2
V
L1
V
SS
(23) COM4/SEG35 to COM7/SEG32
V
L3
V
L2
V
L1
V
SS
V
L2
/V
L3
V
L1
/V
SS
Segment data
(20) Ports P70, P71
Data bus
INT
0
interrupt
INT
1
interrup
C
1
,C
2
INT
0
input port switch bit
INT
1
input port switch bit
Voltage multiplier
control bit
(19) Port P66
Data bus
Direction
register
Port latch
Pull-up control
INT
1
interrupt input
INT
1
input port switch bit
CNTR
0
interrupt input
Data bus
Direction
register
Port latch
Pull-up control
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
Duty ratio selection bits
Timer output/PWM output
Timer output/system clock φ output/X
CIN
output
Rev.2.00 Nov 23, 2005 page 21 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Termination of unused pins
• Termination of common pins
I/O ports: Select an input port or an output port and follow each
processing method.
Output ports: Open.
Input ports: If the input level become unstable, through current flow
to an input circuit, and the power supply current may
increase.
Especially, when expecting low consumption current
Table 7 Termination of unused pins
Pin
P00/SEG8–P07/SEG15
P10/SEG16–P17/SEG23
P20/SEG0–P27/SEG7
P30/SEG24–P37/SEG31
P40/RxD
P41/TxD
P42/SCLK1
P43/SRDY1
P44/SIN2
P45/SOUT2
P46/SCLK2
P47/SRDY2
P50/AN0/RTP0
P51/AN1/RTP1
P52/AN2–P56/AN6
P57/AN7/ADKEY
P60/XCIN
P61/XCOUT
P62/INT00
P63/TXOUT2
P64/INT2
P65/TXOUT1
P66/INT10/CNTR0
P67/CNTR1
P70/C1/INT01
P71/C2/INT11
P72/T2OUT/CKOUT
P73/PWM0/T3OUT
P74/PWM1/T4OUT
VL3
VL2
VL1
COM0–COM3
COM
4
/SEG
35
–COM
7
/SEG
32
VREF
Termination 2
When selecting SEG output, open.
When selecting RxD function, perform
termination of input port.
When selecting TxD function, perform
termination of input port.
When selecting external clock input,
perform termination of output port.
When selecting SRDY1 function,
perform termination of output port.
When selecting SIN2 function, perform
termination of input port.
When selecting SOUT2 function,
perform termination of output port.
When selecting external clock input,
perform termination of output port.
When selecting SRDY2 function,
perform termination of output port.
When selecting AN function, these
pins can be opened. (A/D conversion
result cannot be guaranteed.)
Do not select XCIN-XCOUT oscillation
function by program.
When selecting INT function, perform
termination of input port.
When selecting TXOUT function,
perform termination of output port.
When selecting INT function, perform
termination of input port.
When selecting TXOUT function,
perform termination of output port.
When selecting CNTR input function
or INT function, perform termination of
input port.
When selecting CNTR input function,
perform termination of input port.
When selecting INT function, perform
termination of input port.
When selecting T
2OUT
function or CKOUT
function, perform termination of output port.
When selecting PWM, T
3OUT
, or T
4OUT
function, perform termination of output port.
–
–
–
–
–
–
Termination 3
When selecting internal clock output,
perform termination of output port.
When selecting internal clock output,
perform termination of output port.
When selecting RTP function,
perform termination of output port.
–
When selecting ADKEY function,
pull-up this pin through a resistor.
(at STP or WIT instruction execution etc.), pull-up or
pull-down input ports to prevent through current (built-
in resistor can be used).
We recommend processing unused pins through a re-
sistor which can secure IOH(avg) or IOL(avg).
Because, when an I/O port or a pin which have an out-
put function is selected as an input port, it may operate
as an output port by incorrect operation etc.
Termination 1 (recommend)
I/O port
Do not select the C pin (voltage
multiplir).
–
–
–
–
–
–
–
–
–
–
–
–
Input port
I/O port
Connect to Vcc
VL3 ≥ VL2 ≥ VL1
Connect to Vss
Open
Open
Connect to Vcc
–
–
–
–
–
–
–
–
–
–
Rev.2.00 Nov 23, 2005 page 22 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
INTERRUPTS
Interrupts occur by seventeen sources: six external, ten internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by program. Interrupt re-
quest bits can be cleared by program, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupt requests occur at the same
time, the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
2.The interrupt disable flag is set to “1” and the corresponding
interrupt request bit is set to “0”.
3.The interrupt jump destination address is read from the vector
table into the program counter.
■ Notes on Interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X control register (address 2E16)
Timer Y mode register (address 3816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring the interrupt occurrence synchronous with these
setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge selection bit (polarity switch bit) or the inter-
rupt source selection bit.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Source
Reset (Note 2)
INT0 (INT00 or
INT01) (Note 3)
INT1 (INT10 or
INT11) (Note 3)
INT2
Key input
(key-on wakeup)
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2
CNTR0
Timer Y
CNTR1
A/D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V ector Addresses (Note 1)
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling
edge of INT0 input
At detection of either rising or falling
edge of INT1 input
At detection of either rising or falling
edge of INT2 input
At falling of ports P20–P23, P44–P47
input logical level AND
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data trans-
mit/receive
At detection of either rising or falling
edge of CNTR0 input
At timer Y underflow
At detection of either rising or falling
edge of CNTR1 input
At completion of A/D conversion
At BRK instruction execution
Non-maskable
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when INT2 interrupt is selected
External interrupt (active edge selectable)
Valid when key input interrupt is selected
External interrupt (falling valid)
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Non-maskable software interrupt
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: INT0 (INT00 or INT01), INT1 (INT10 or INT11) input pins are selected by the interrupt edge selection register (INTEDGE).
Table 8 Interrupt vector addresses and priority
Remarks
Rev.2.00 Nov 23, 2005 page 23 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
b7 b0 Interrupt edge selection register
INT
0
interrupt edge selection bit
INT
1
interrupt edge selection bit
INT
2
interrupt edge selection bit
Timer Y/CNTR
1
interrupt switch bit
0 : Timer Y interrupt
1 : CNTR
1
interrupt
INT
0
input port switch bit
0 : Input from Port P6
2
(INT
00
)
1 : Input from Port P7
0
(INT
01
)
INT
1
input port switch bit
0 : Input from Port P6
6
(INT
10
)
1 : Input from Port P7
1
(INT
11
)
Not used (return “0” when read)
(INTEDGE : address 003A
16
)
Interrupt request register 1
INT
0
interrupt request bit
INT
1
interrupt request bit
INT
2
interrupt request bit
Key input interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt control register 1
INT
0
interrupt enable bit
INT
1
interrupt enable bit
INT
2
interrupt enable bit
Key input interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
)
(ICON1 : address 003E
16
)
Interrupt request register 2
Timer 4 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive/transmit interrupt request bit
CNTR
0
interrupt request bit
Timer Y interrupt request bit
CNTR
1
interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D
16
)
Interrupt control register 2
Timer 4 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive/transmit interrupt enable bit
CNTR
0
interrupt enable bit
Timer Y interrupt enable bit
CNTR
1
interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write to “1”.)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
)
0 : Falling edge active
1 : Rising edge active
b7 b0
b7 b0
b7 b0
b7 b0
Fig. 18 Interrupt control
Fig. 19 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset Interrupt request
Rev.2.00 Nov 23, 2005 page 24 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by detecting the falling
edge from any pin of ports P20–P23, P44–P47 that have been set to
input mode. In other words, it is generated when AND of input level
goes from “1” to “0”. An example of using a key input interrupt is
shown in Figure 20, where an interrupt request is generated by press-
ing one of the keys consisted as an active-low key matrix which in-
puts to ports P44–P47.
Fig. 20 Connection example when using key input interrupt
Key input control
register bit 0 = “1”
Key input control
register bit 1 = “1”
Key input control
register bit 2 = “1”
Key input control
register bit 3 = “1”
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
i
t
4
=
“
1
”
Key input control
register bit 5 = “1”
Key input control
register bit 6 = “1”
Port P4
4
latch
Port P4
direction
register bit 4 = “0”
P
o
r
t
P
4
5
l
a
t
c
h
Port P4
direction
register bit 5 = “0”
Port P4
6
latch
Port P4
direction
register bit 6 = “0”
P
o
r
t
P
4
7
l
a
t
c
h
Port P2
0
latch
P
o
r
t
P
2
1
l
a
t
c
h
Port P2
2
latch
P
o
r
t
P
2
3
l
a
t
c
h
Port P2 direction
register bit 3 = “1”
P4
4
input
P
4
5
i
n
p
u
t
P
4
6
i
n
p
u
t
P4
7
input
P
2
0
o
u
t
p
u
t
P
2
1
o
u
t
p
u
t
P2
2
output
P
2
3
o
u
t
p
u
t
PULL register 3
Bit 1 = “1”
P
o
r
t
P
2
I
n
p
u
t
r
e
a
d
i
n
g
c
i
r
c
u
i
t
P
o
r
t
P
X
x
“
L
”
l
e
v
e
l
o
u
t
p
u
t
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Port P4
Input reading circuit
Key input control
register bit 7 = “1”
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
1
B
i
t
3
=
“
1
”
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
1
B
i
t
2
=
“
1
”
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
1
B
i
t
1
=
“
1
”
Segment output
disable register 1
Bit 0 = “1”
✽ P-cha nnel tr ansistor for pull-up
✽ ✽ CMOS output buffer
✽
✽
✽
✽
✽
✽
✽
✽✽✽
✽✽
✽✽
✽✽
✽✽
✽✽
✽✽
✽✽
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
b
i
t
7
=
“
0
”
Port P2 direction
register bit 2 = “1”
Port P2 direction
register bit 1 = “1”
Port P2 direction
register bit 0 = “1”
Rev.2.00 Nov 23, 2005 page 25 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
A key input interrupt is controlled by the key input control register and
port direction registers. When the key input interrupt is enabled, set
“1” to the key input control register. A key input of any pin of ports
P20–P23, P44–P47 that have been set to input mode is accepted.
Fig. 21 Structure of key input control register
Key input control register
P44 key input control bit
P45 key input control bit
P46 key input control bit
P47 key input control bit
P20 key input control bit
P21 key input control bit
P22 key input control bit
P23 key input control bit
(KIC : address 0FF716)
b7 b0
0 : Key input interrupt disabled
1 : Key input interrupt enabled
Rev.2.00 Nov 23, 2005 page 26 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
X
C
I
N
1
/
2
Q
Q
ST
P7
4
/PWM
1
/
T
4OUT
1
/
2
Q
Q
ST
P
7
3
/
P
W
M
0
/
T
3
O
U
T
8
1
/
2
Q
Q
ST
P
7
2
/
T
2
O
U
T
/
C
K
O
U
T
φ
S
O
U
R
C
E
f
(
X
I
N
)
(
N
o
t
e
)
Timer 1 latch (8)
T
i
m
e
r
1
(
8
)
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Timer 2 interrupt request
D
a
t
a
b
u
s
T
i
m
e
r
1
c
o
u
n
t
s
t
o
p
b
i
t
C
l
o
c
k
f
o
r
T
i
m
e
r
1
Clock for
Timer 2
Frequency division
selection bits
(2 bits for each Timer)
C
l
o
c
k
f
o
r
T
i
m
e
r
4
C
l
o
c
k
f
o
r
T
i
m
e
r
3
C
l
o
c
k
f
o
r
T
i
m
e
r
2
C
l
o
c
k
f
o
r
T
i
m
e
r
1
The following values can be selected
the clock for Timer;
1/1,1/2,1/16,1/256
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
T
2
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
T
i
m
e
r
2
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
P
7
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rP7
2
latch
T
i
m
e
r
2
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
P7
2
clock output
co ntr o l bi t
T
i
m
e
r
Y
o
u
t
p
u
t
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Ti mer 1 c ount
source selection
bits
Ti mer 2 c ount
source selection
bits
Timer 2 count stop bit
T
i
m
e
r
1
T
i
m
e
r
2
T
i
m
e
r
3
T
i
m
e
r
4
Timer 2 latch (8)
Timer 2 (8)
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Timer 3 write control bit
Timer 3 latch (8)
T
i
m
e
r
3
(
8
)
1
0
b
i
t
P
W
M
1
c
i
r
c
u
i
t
P
7
4
l
a
t
c
h
10 bit
PWM0
circuit
Timer 3 operating
mode selection bit
P
7
3
l
a
t
c
h
Time r 3 output selection bit
P
7
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Clock for
Timer 3
Clock for
Timer 4
PWM01 register (2)
PWM01 register (2)
Timer 3 count source
selection bi t
Timer 3 count stop bit
Timer 4 interrupt request
Ti mer 4 w rite
control bit
Timer 4 latch (8)
T
i
m
e
r
4
(
8
)
T
i
m
e
r
4
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
Timer 4 count stop bit
T
3OUT
output
edge switch bit
Time r 3 output selection bit
T
i
m
e
r
4
o
p
e
r
a
t
i
n
g
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
T
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e
r
4
o
u
t
p
u
t
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e
l
e
c
t
i
o
n
b
i
t
P
7
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rT
4
O
U
T
o
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t
p
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e
d
g
e
s
w
i
t
c
h
b
i
t
T
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r
4
o
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p
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l
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c
t
i
o
n
b
i
t
“01”
“
1
0
”
“
0
0
”
“
1
”
“0”
“11”
“
1
”
“
0
”
“1”
“
0
”
“1”
“
0
”
“
1
”
“0”
“
1
”
“0”
“1”
“
0
”
“00”
“
0
1
”
“10”
“00”
“01”
“
1
0
”
φ
SOURCE: represents the oscillation frequency of
X
IN
input in the middle- and high-speed mode,
on-chip oscillator divided by 4 in the on-chip
oscillator mode,
and sub-clock in the low-speed mode.
System clock φ
Fig. 22 Structure of timer related register
TIMERS
8-Bit Timer
The 38C5 group has four built-in 8-bit timers : Timer 1, Timer 2,
Timer 3, and Timer 4.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016”, the contents of the timer latch is
reloaded into the timer with the next count pulse. In this mode, the
interrupt request bit corresponding to that timer is set to “1”.
The count can be stopped by setting the stop bit of each timer to “1”.
Rev.2.00 Nov 23, 2005 page 27 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Output waveform of Timer 3 PWM0 or Timer 4 PWM1
256 ✕
t
s256 ✕
t
s256 ✕
t
s256 ✕
t
s
n ✕ tsn ✕ tsn ✕ tsn ✕ ts
n ✕ tsn ✕ tsn ✕ ts
n ✕ ts
n ✕ ts
n ✕ ts
PWM01 register = “00
2
”
n: Setting value of Timer 3 or Timer 4
ts: One period of Timer 3 count source or Timer 4 count source
PWM01 register (address 0024
16
) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3)
(n+1) ✕ ts
(n+1) ✕ ts
(n+1) ✕ ts (n+1) ✕ ts (n+1) ✕ ts
(n+1) ✕ ts
PWM01 register = “01
2
”
PWM01 register = “10
2
”
PWM01 register = “11
2
”
Short interval Short interval Short interval Short interval
4 ✕ 256 ✕
t
s
Long interval
Interrupt request Interrupt request
● Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for
the count source. The count source of the frequency divider is switched
to XIN, XCIN, or the on-chip oscillator (ROSC) divided by 4 in the on-
chip oscillator mode by the CPU mode register. The frequency di-
vider is controlled by each timer division ratio selection bit. The divi-
sion ratio can be selected from as follows;
1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(ROSC)/4.
Stop a timer to switch the division of frequency.
● Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register.
When XCIN is selected as the count source, a pulse input from XCIN
can be counted. Also, by the timer 12 mode register , each time timer
2 underflows, the signal of which polarity is inverted can be output
from P72/T2OUT pin.
At reset, all bits of the timer 12 mode register are set to “0,” timer 1 is
set to “FF16”, and timer 2 is set to “0116”.
When executing the STP instruction, previously set the wait time at
return.
● Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register . Also, by the timer 34 mode register, each
time timer 3 or timer 4 underflows, the signal of which polarity is
inverted can be output from P73/T3OUT pin or P74/T4OUT pin.
● Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit accuracy
can be output from the P73/PWM0 pin and P74/PWM1 pin by set-
ting the timer 34 mode register and PWM01 register (refer to Figure
23).
One output pulse is the short interval. Four output pulses are the
long interval. The “n” is the value set in the timer 3 (address 002216)
or the timer 4 (address 002316). The “ts” is one period of timer 3 or
timer 4 count source. “H” width of the short interval is obtained by n
✕ ts.
However, in the long interval, “H” width of output pulse is extended
for ts which is set by the PWM01 register (address 002416).
■ Notes on T imer 3 PWM0 Mode, T imer 4 PWM1
Mode
●When PWM output is suspended after starting PWM output, de-
pending on the level of the output pulse at that time to resume an
output, the delay of the one section of the short interval may be
needed.
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256 ✕ ts
●In the PWM mode, the follows are performed every cycle of the
long interval (4 ✕ 256 ✕ ts).
•Generation of timer 3, timer 4 interrupt requests
•Update of timer 3, timer 4
■ Writing to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload latch
and the underflow timing are almost the same, the value is set into
the timer and the timer latch at the same time. In this time, counting
is stopped during writing to the reload latch.
Fig. 23 Waveform of PWM0 and PWM1
Rev.2.00 Nov 23, 2005 page 28 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 24 Structure of Timer 1 to timer 4 related registers
T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
M
:
a
d
d
r
e
s
s
0
0
2
5
1
6
)
T
i
m
e
r
1
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
o
p
e
r
a
t
i
o
n
1
:
C
o
u
n
t
s
t
o
p
T
i
m
e
r
2
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
o
p
e
r
a
t
i
o
n
1
:
C
o
u
n
t
s
t
o
p
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
b
3
b
2
00
:
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
f
o
r
T
i
m
e
r
1
01
:
f
(
X
C
I
N
)
10
:
U
n
d
e
r
f
l
o
w
o
f
T
i
m
e
r
Y
11
:
N
o
t
a
v
a
i
l
a
b
l
e
T
i
m
e
r
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
b
5
b
4
00
:
U
n
d
e
r
f
l
o
w
o
f
T
i
m
e
r
1
01
:
f
(
X
C
I
N
)
10
:
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
f
o
r
T
i
m
e
r
2
11
:
N
o
t
a
v
a
i
l
a
b
l
e
T
i
m
e
r
2
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
(
P
7
2
)
0
:
I
/
O
p
o
r
t
1
:
T
i
m
e
r
2
o
u
t
p
u
t
T
2
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
S
t
a
r
t
a
t
“
L
”
o
u
t
p
u
t
1
:
S
t
a
r
t
a
t
“
H
”
o
u
t
p
u
t
Timer 34 mode register
(T34M: address 0026
16
)
Timer 3 count stop bit
0 : Count operation
1 : Coun t stop
Timer 4 count stop bit
0 : Count operation
1 : Coun t stop
Timer 3 count source selection bit
0 : Frequency divider for Timer 3
1 : Unde rflow of Timer 2
Timer 4 count source selection bits
b4 b3
00 : Frequency divider for Timer 4
01 : Und e rflow of Timer 3
10 : Und e rflow of Timer 2
11 : f(X
IN
)
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
Not used (returns “0” when read)
T
i
m
e
r
1
2
3
4
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
3
4
M
:
a
d
d
r
e
s
s
0
0
2
7
1
6
)
T
3
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
S
t
a
r
t
a
t
“
L
”
o
u
t
p
u
t
1
:
S
t
a
r
t
a
t
“
H
”
o
u
t
p
u
t
T
4
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
S
t
a
r
t
a
t
“
L
”
o
u
t
p
u
t
1
:
S
t
a
r
t
a
t
“
H
”
o
u
t
p
u
t
T
i
m
e
r
3
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
(
P
7
3
)
0
:
I
/
O
p
o
r
t
1
:
T
i
m
e
r
3
o
u
t
p
u
t
T
i
m
e
r
4
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
(
P
7
4
)
0
:
I
/
O
p
o
r
t
1
:
T
i
m
e
r
4
o
u
t
p
u
t
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
t
o
b
o
t
h
t
i
m
e
r
l
a
t
c
h
a
n
d
t
i
m
e
r
1
:
W
r
i
t
e
d
a
t
a
t
o
t
i
m
e
r
l
a
t
c
h
o
n
l
y
T
i
m
e
r
3
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
t
o
b
o
t
h
t
i
m
e
r
l
a
t
c
h
a
n
d
t
i
m
e
r
1
:
W
r
i
t
e
d
a
t
a
t
o
t
i
m
e
r
l
a
t
c
h
o
n
l
y
T
i
m
e
r
4
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
t
o
b
o
t
h
t
i
m
e
r
l
a
t
c
h
a
n
d
t
i
m
e
r
1
:
W
r
i
t
e
d
a
t
a
t
o
t
i
m
e
r
l
a
t
c
h
o
n
l
y
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
b
7b
0
b
7b0
b
7b
0
PWM01 register
(PWM01: address 0024
16
)
P
W
M
0
s
e
t
b
i
t
s
b
1
b
0
00
:
N
o
e
x
t
e
n
d
e
d
01
:
E
x
t
e
n
d
e
d
o
n
c
e
i
n
f
o
u
r
p
e
r
i
o
d
s
10
:
E
x
t
e
n
d
e
d
t
w
i
c
e
i
n
f
o
u
r
p
e
r
i
o
d
s
11
:
E
x
t
e
n
d
e
d
t
h
r
e
e
t
i
m
e
s
i
n
f
o
u
r
p
e
r
i
o
d
s
P
W
M
1
s
e
t
b
i
t
s
b
3
b
2
00
:
N
o
e
x
t
e
n
d
e
d
01
:
E
x
t
e
n
d
e
d
o
n
c
e
i
n
f
o
u
r
p
e
r
i
o
d
s
10
:
E
x
t
e
n
d
e
d
t
w
i
c
e
i
n
f
o
u
r
p
e
r
i
o
d
s
11
:
E
x
t
e
n
d
e
d
t
h
r
e
e
t
i
m
e
s
i
n
f
o
u
r
p
e
r
i
o
d
s
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
Timer 1234 frequency division selection regi ster
(PRE1234: address 0028
16
)
Timer 1 frequency division selection bits
b1 b0
0 0 : 1/ 16 ✕ φ SOURCE
0 1 : 1/ 1 ✕ φ SOURCE
1 0 : 1/ 2 ✕ φ SOURCE
1 1 : 1/ 256 ✕ φ SOURCE
Timer 2 frequency division selection bits
b3 b2
0 0 : 1/16 ✕ φ SOUR CE
0 1 : 1/ 1 ✕ φ SOURCE
1 0 : 1/ 2 ✕ φ SOURCE
1 1 : 1/ 256 ✕ φ SOURCE
Timer 3 frequency division selection bits
b5 b4
0 0 : 1/16 ✕ φ SOUR CE
0 1 : 1/ 1 ✕ φ SOURCE
1 0 : 1/ 2 ✕ φ SOURCE
1 1 : 1/ 256 ✕ φ SOURCE
Timer 4 frequency division selection bits
b7 b6
0 0 : 1/16 ✕ φ SOUR CE
0 1 : 1/ 1 ✕ φ SOURCE
1 0 : 1/ 2 ✕ φ SOURCE
1 1 : 1/ 256 ✕ φ SOURCE
b
7b0
b
7b0
φ SOURCE: represents the oscillat ion frequ ency of
X
IN
input in the middle- and high-speed mode,
on-chip oscillator divided by 4 in the on-chip
oscillator mode,
and sub-clock in the low-speed mode.
N
o
t
e
:
Rev.2.00 Nov 23, 2005 page 29 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
16-bit Timer
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer , read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
Fig. 25 Structure of timer related register
1/2
1
/
4
I
N
T
2
D
Q
L
a
t
c
h
C
N
T
R
0
I
N
T
0
0
/
I
N
T
0
1
0
µs
4
/
f
(
X
I
N
)
8
/
f
(
X
I
N
)
1
6
/
f
(
X
I
N
)
Xc
IN
X
I
N
2
Timer X output
control bit 1
Timer X output
control bit 2
“010”
S
Q
QT
S
P
6
5
/
T
X
O
U
T
1
/
(
L
E
D
3
)
S
Q
QT
R
S
Q
Q
T
R
P6
3
/T
XOUT2
/(LED
1
)
Timer X output 2 edge
switch bit
φSOURCE
φ
S
O
U
R
C
E
:
Delay circuit 1/2
X
2
T
r
i
g
g
e
r
f
o
r
I
G
B
T
c
o
n
t
r
o
l
b
i
t
Trigger for IGBT control bit
I
N
T
1
0
/
I
N
T
1
1
D
a
t
a
b
u
s
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
Noise filter sampling
clock selection bit
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
E
q
u
a
l
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Timer X count
stop bit
Compare register 1
(low-order)(8) C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
1
(
h
i
g
h
-
o
r
d
e
r
)
(
8
)
Pulse output mode
CNTR
0
active
edge switch bits
Timer X operating
mode bits
CNTR
0
interrupt request
Extend latch
(2)
Extend counter
(2)
Timer X write
control bit
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
D
a
t
a
f
o
r
c
o
n
t
r
o
l
o
f
e
v
e
n
t
c
o
u
n
t
e
r
w
i
n
d
o
w
Delay time
selection bits
Noise filter
(4 times same
levels judgment)
INT
0
interrupt request
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
C
l
o
c
k
f
o
r
T
i
m
e
r
X
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
rT
i
m
e
r
X
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
s
B
o
t
h
e
d
g
e
s
d
e
t
e
c
t
i
o
n
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
Timer X operating
mode bits
D
e
l
a
y
c
i
r
c
u
i
t
T
i
m
e
r
X
(
l
o
w
-
o
r
d
e
r
)
l
a
t
c
h
(
8
)
Timer X (low-order)(8)
Timer X (high-order) latch (8)
T
i
m
e
r
X
(
h
i
g
h
-
o
r
d
e
r
)
(
8
)
E
d
g
e
s
e
l
e
c
t
i
o
n
*
Edge
selection *
Edge
detection
E
d
g
e
s
e
l
e
c
t
i
o
n
*
Compare register 2
(low-order)(8) Compare register 2
(high-order)(8)
Compare register 3
(low-order)(8) Compare register 3
(high-order)(8)
T
i
m
e
r
X
o
u
t
p
u
t
2
s
e
l
e
c
t
i
o
n
b
i
t
P
63
l
a
t
c
h
P
63
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
IGBT output mode
PWM mode
T
i
m
e
r
X
o
u
t
p
u
t
1
e
d
g
e
s
w
i
t
c
h
b
i
t
Timer X output 1 selection bit
P
65
l
a
t
c
h
P
65
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
“000”
“001”
“010”
“011”
“101”
“0”
“1”
“100”
“00”
“01”
“10”
“11”
“00”
“01”
“
1
0
”
“
1
1
”
“1”
“0”
“1”
“0”
“0”
“1”
“
0
1
0
”
“0”
“1”
“1”
“
0
”
“
0
0
0
”
“
0
0
1
”
“
0
1
1
”
“
1
0
0
”
“
1
0
1
”
represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and
Sub clock in the low-speed mode.
Rev.2.00 Nov 23, 2005 page 30 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
● Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the count
source. The count source of the frequency divider is switched to XIN,
XCIN, or the on-chip oscillator in the on-chip oscillator mode by the
CPU mode register . The division ratio of each timer can be controlled
by each timer division ratio selection bit. The division ratio can be
selected from as follows;
1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(ROSC)/4.
● Timer X
The timer X count source can be selected by setting the timer X
mode register. When XCIN is selected as the count source, a pulse
input from XCIN can be counted.
The timer X operates as down-count. When the timer contents reach
“000016”, an underflow occurs at the next count pulse and the timer
latch contents are reloaded. After that, the timer continues count-
down. When the timer underflows, the interrupt request bit corre-
sponding to the timer X is set to “1”.
Six operating modes can be selected for timer X by the timer X mode
register and timer X control register.
(1) Timer Mode
The count source can be selected by setting the timer X mode regis-
ter . In this mode, timer X operates as the 18-bit counter by setting the
timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TXOUT1 pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set the port sharing the TXOUT1 pin to output
mode.
(3) IGBT Output Mode
After dummy output from the TXOUT1 pin, count starts with the INT0
pin input as a trigger . In the case that the timer X1 output edge switch
bit is “0”, when the trigger is detected or the timer X underflows, “H” is
output from the TXOUT1 pin. And then, when the count value corre-
sponds with the compare register 1 value, the TXOUT1 output be-
comes “L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT0 signal can use 4
types of delay time by a delay circuit.
When using this mode, set the port sharing the INT0 pin to input
mode and set the port sharing the pin used as TXOUT1 or TXOUT2
function to output mode.
When the timer X output control bit 1 or 2 of the timer X control reg-
ister is set to “1”, the timer X count stop bit is fixed to “1” forcibly by
the interrupt signal of INT1 or INT2. And then, the TXOUT1 output and
TXOUT2 output can be set to “L” forcibly at the same time that the
timer X stops counting.
Do not write “1” to the timer X register (extension) when using the
IGBT output mode.
(4) PWM Mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer X set value. In
the case that the timer X1 output edge switch bit is “0”, the “H” inter-
val is specified by the compare register 1 set value. In the case that
the timer X2 output edge switch bit is “0”, the “H” interval is specified
by the compare registers 2 and 3 set values.
When using this mode, set the port sharing the pin used as TXOUT1
or TXOUT2 function to output mode.
Do not write “1” to the timer X register (extension) when using the
PWM mode.
(5) Event Counter Mode
The timer counts signals input through the CNTR0 pin. In this mode,
timer X operates as the 18-bit counter by setting the timer X register
(extension). When using this mode, set the port sharing the CNTR0
pin to input mode.
In this mode, the window control can be performed by the timer 1
underflow. When the bit 5 (data for control of event counter window)
of the timer X mode register is set to “1”, counting is stopped at the
next timer 1 underflow. When the bit is set to “0”, counting is re-
started at the next timer 1 underflow.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider for
timer. In this mode, timer X operates as the 18-bit counter by setting
the timer X register (extension). When the bit 6 of the CNTR0 active
edge switch bits is “0”, counting is executed during the “H” interval of
CNTR0 pin input. When the bit is “1”, counting is executed during the
“L” interval of CNTR0 pin input. When using this mode, set the port
sharing the CNTR0 pin to input mode.
Rev.2.00 Nov 23, 2005 page 31 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 26 Waveform of PWM/IGBT
■ Notes on Timer X
(1) Write Order to Timer X
•In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following registers in
the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after reset is
released, setting the timer X register (extension) is not required. In
this case, write the timer X register (low-order) first and the timer X
register (high-order). However, once writing to the timer X register
(extension) is executed, note that the value is retained to the reload
latch.
• In the IGBT output and PWM modes, do not write “1” to the timer X
register (extension). Also, when “1” is already written to the timer X
register, be sure to write “0” to the register before using.
Write to the following registers in the order as shown below;
the compare registers 1, 2, 3 (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare regis-
ters 1, 2, 3 (high- and low-order). However , write both the compare
registers 1, 2, 3 and the timer X register at the same time.
(2) Read Order to Timer X
•In all modes, read the following registers in the order as shown below;
the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required, read
the timer X register (high-order) first and the timer X register (low-
order).
Read order to the compare registers 1, 2, 3 is not specified.
•Write to or read from the timer X register by the 16-bit unit. If read-
ing to the timer X register during write operation or writing to it dur-
ing read operation is performed, normal operation will not be per-
formed.
(3) Write to Timer X
•Which write control can be selected by the timer X write control bit
(b3) of the timer X mode register (address 2D16), writing data to
both the latch and the timer at the same time or writing data only to
the latch. When writing a value to the timer X address to write to the
latch only, the value is set into the reload latch and the timer is
updated at the next underflow. After reset release, when writing a
value to the timer X address, the value is set into the timer and the
timer latch at the same time, because they are written at the same
time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this time,
counting is stopped during writing to the high-order reload latch.
•Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
t
s
Timer X count source
Timer X PWM mode
IGBT output mode
m ✕ ts
(n+1) ✕ ts
T
XOUT1
output
(TXCON1 bit 5 = “1”)
T
XOUT2
output
(TXCON2 bit 1 = “0”)q ✕ ts
p ✕ ts
n : Timer X setting value
m: Compare register 1 setting value
p : Compare register 2 setting value
q : Compare register 3 setting value
ts: One period of timer X count source
External trigger (INT0 source)
is generated. INT1 or INT2 source is generated.
Level is “H” only IGBT
output mode.
The following PWM waveform is output;
Duty of T
XOUT1
output :{(n+1)-m}/(n+1),
Duty of T
XOUT2
output :(p-q)/(n+1),
Period :(n+1)✕ ts
Level is forcibly “L” only IGBT output mode.
Rev.2.00 Nov 23, 2005 page 32 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
(4) Set of Timer X Mode Register
Set the write control bit of the timer X mode register to “1” (write to
the latch only) when setting the IGBT output and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer X register (high-
order).
(5) Output Control Function of Timer X
• When using the output control function (INT1 and INT2) in the IGBT
output mode, set the levels of INT1 and INT2 to “H” in the falling
edge active or to “L” in the rising edge active before switching to the
IGBT output mode.
(6) Switch of CNTR0 Active Edge
• When the CNTR0 active edge switch bits are set, at the same time,
the interrupt active edge is also affected.
• When the pulse width is measured, set the bit 7 of the CNTR0 ac-
tive edge switch bits to “0”.
Fig. 27 Structure of Timer X related registers
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
(
T
X
M
:
a
d
d
r
e
s
s
0
0
2
D
1
6
)
Timer X operating mode bits
b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse outpu t mo de
0 1 0 : IGBT output mode
0 1 1 : PWM mode
1 0 0 : Event counter mode
1 0 1 : Pulse width me asure men t mode
1 1 0 : Not available
1 1 1 : Not available
b7 b
0
Timer X control register 1
(TXCON1: address 002E
16
)
Noise filter sampling clock selection bit
0 : f(X
IN
)/2
1 : f(X
IN
)/4
b7 b0
T
i
m
e
r
X
o
u
t
p
u
t
2
s
e
l
e
c
t
i
o
n
b
i
t
(
P
6
3
)
0
:
I
/
O
p
o
r
t
1
:
T
i
m
e
r
X
o
u
t
p
u
t
2
b
7b
0
φ
S
O
U
R
C
E
:represents the supply source of internal clock φ.
X
IN
input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip
oscillator mode, and
Sub clock in the low-speed mode.
Timer X control register 2
(TXCON2: address 002F
16
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
T
r
i
g
g
e
r
f
o
r
I
G
B
T
i
n
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
✕
1
E
x
t
e
r
n
a
l
t
r
i
g
g
e
r
d
e
l
a
y
t
i
m
e
✕
1
1
:
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
✕
2
E
x
t
e
r
n
a
l
t
r
i
g
g
e
r
d
e
l
a
y
t
i
m
e
✕
1
/
2
T
i
m
e
r
X
d
i
v
i
n
g
f
r
e
q
u
e
n
c
y
s
e
l
e
c
t
i
o
n
b
i
t
s
b
3
b
2
00
:
1
/
1
6
✕ φ
S
O
U
R
C
E
01
:
1
/
1
✕ φ
S
O
U
R
C
E
(
N
o
t
e
)
10
:
1
/
2
✕ φ
S
O
U
R
C
E
11
:
1
/
2
5
6
✕
φ
S
O
U
R
C
E
T
i
m
e
r
X
o
u
t
p
u
t
2
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
S
t
a
r
t
a
t
“
L
”
o
u
t
p
u
t
1
:
S
t
a
r
t
a
t
“
H
”
o
u
t
p
u
t
T
i
m
e
r
X
o
u
t
p
u
t
1
s
e
l
e
c
t
i
o
n
b
i
t
(
P
6
5
)
0
:
I
/
O
p
o
r
t
1
:
T
i
m
e
r
X
o
u
t
p
u
t
1
Timer X count stop bit
0 : Count operation
1 : Count s top
D
a
t
a
f
o
r
c
o
n
t
r
o
l
o
f
e
v
e
n
t
c
o
u
n
t
e
r
w
i
n
d
o
w
0
:
E
v
e
n
t
c
o
u
n
t
e
n
a
b
l
e
d
1
:
E
v
e
n
t
c
o
u
n
t
d
i
s
a
b
l
e
d
Timer X count source selection bit
0 : Frequency divider output
1 : f(X
CIN
)
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
t
o
b
o
t
h
t
i
m
e
r
l
a
t
c
h
a
n
d
t
i
m
e
r
1
:
W
r
i
t
e
d
a
t
a
t
o
t
i
m
e
r
l
a
t
c
h
o
n
l
y
CNTR
0
active edge switch bits
b7 b6
0 0 : Count at rising edge in event counter mode
Falling edge active for CNTR
0
interrupt
Measure “H” pulse width in pulse width measurement mode
0 1 : Count at falling edge in event counter mode
Rising edge active for CNTR
0
interrupt
Measure “L” pulse width in pulse width measurement mode
10 :
11 :
Timer X output 1 edge switch bit
0 : Start at “L” output
1 : Start at “H” output
T
i
m
e
r
X
o
u
t
p
u
t
2
c
o
n
t
r
o
l
b
i
t
(
P
6
4
)
0
:
N
o
t
u
s
e
d
1
:
I
N
T
2
i
n
t
e
r
r
u
p
t
u
s
e
d
T
i
m
e
r
X
o
u
t
p
u
t
1
c
o
n
t
r
o
l
b
i
t
(
P
6
6
o
r
P
7
1
)
0
:
N
o
t
u
s
e
d
1
:
I
N
T
1
i
n
t
e
r
r
u
p
t
u
s
e
d
External trigger delay time selection bits
b2 b1
0 0 : Not delayed
0 1 : (4/f(X
IN
)) µs
1 0 : (8/f(X
IN
)) µs
1 1 : (16/f(X
IN
)) µs
Count at both edges in event counter mode
Both edges active for CNTR
0
interrupt
Rev.2.00 Nov 23, 2005 page 33 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Timer Y
Timer Y is a 16-bit timer. The timer Y count source can be selected
by setting the timer Y mode register. When f(XCIN) is selected as the
count source, counting can be performed regardless of XCIN oscilla-
tion. However, when XCIN is stopped, the external pulse input from
XCIN pin is counted.
Four operating modes can be selected for timer Y by the timer Y
mode register. Also, the real time port can be controlled.
(1) Timer Mode
The timer Y count source can be selected by setting the timer Y mode
register.
(2) Period Measurement Mode
The interrupt request is generated at rising or falling edge of CNTR1
pin input signal. Simultaneously, the value in timer Y latch is reloaded
in timer Y and timer Y continues counting. Except for that, this mode
operates just as in the timer mode.
The timer value just before the reloading at rising or falling of CNTR1
pin input is retained until the timer Y is read once after the reload.
The rising or falling timing of CNTR1 pin input is found by CNTR1
interrupt. When using this mode, set the port sharing the CNTR1 pin
to input mode.
Fig. 28 Block diagram of Timer Y
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for that, this mode operates just as in the timer mode.
When using this mode, set the port sharing the CNTR1 pin to input
mode.
(4) Pulse Width HL Continuously Measurement
Mode
The interrupt request is generated at both rising and falling edges of
CNTR1 pin input signal. Except for that, this mode operates just as in
the period measurement mode. When using this mode, set the port
sharing the CNTR1 pin to input mode.
Data bus
P51/RTP1/AN1
P50/RTP0/AN0
CNTR1Timer Y
interrupt request
CNTR1
interrupt request
XcIN
φSOURCE Timer Y operating mode bits
AA
AA
AA
AA
Frequency divider 2
Real time port 1
control bit
Real time port 2
control bit Q D
Latch
Q D
Latch
P51 direction
register P51 latch
P51 data for real time port
P50 direction
register P50 latch
P50 data for real time port
“1”
Timer Y (low-order) latch (8)
“0”
CNTR1 active
edge switch bit
“10”
Falling edge detection Period measurement
mode
Pulse width HL continuous
measurement mode
Timer Y operating
mode bits
Rising edge detection
Count source selection bit
“1”
Timer Y dividing frequency selection bit
Real time port 2 control bit
Timer Y mode register
write signal
Timer Y (low-order)(8)
“00”, “01”, “11”
“1”
“0”
“1”
“0”
“1”
“0”
“00”, “01”, “10”
“11”
“0”
Timer Y write control bit
Timer Y count stop bit
Timer Y (high-order) latch (8)
Timer Y (high-order)(8)
Real time port 1 control bit
Timer Y mode register
write signal
“1”
“0”
Rev.2.00 Nov 23, 2005 page 34 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Timer Y mode register
(TYM: address 0038
16
)
Real time port 1 control bit (P50)
0 : Real time port function invalid
1 : Real time port functin valid
b
7b0 T
i
m
e
r
Y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
Y
C
O
N
:
a
d
d
r
e
s
s
0
0
3
9
1
6
)
Timer Y wr ite control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
b
7b
0
φ
S
O
U
R
C
E
:represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip
oscillator mode, and
Sub clock in the low-speed mode.
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
Timer Y frequency division selection bits
b3 b2
0 0 : 1/16 ✕ φSOURCE
0 1 : 1/1 ✕ φSOURCE
1 0 : 1/2 ✕ φSOURCE
1 1 : 1/256 ✕
φ
SOURCE
Timer Y count source selection bit
0 : Frequency divider output
1 : f(X
CIN
)
Timer Y count stop bit
0 : Count operation
1 : Coun t s top
CNTR
1
active edge swi tch bit
0 : Count at rising edge in event counter mode
Measure falling period in period measur eme nt mode
Falling edge active for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure rising period in period measurement mode
Rising edge active for CNTR
1
interrupt
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pul se width HL continuous measurement mode
P
5
1
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
5
0
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
R
e
a
l
t
i
m
e
p
o
r
t
2
c
o
n
t
r
o
l
b
i
t
(
P
51)
0
:
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
o
n
i
n
v
a
l
i
d
1
:
R
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a
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t
i
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p
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c
t
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v
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d
■ Notes on Timer Y
● CNTR1 Interrupt Active Edge Selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of CNTR1
active edge switch bit.
● Timer Y Read/Write Control
• When reading from/writing to timer Y, read from/write to both the
high-order and low-order bytes of timer Y. When the value is read,
read the high-order bytes first and the low-order bytes next. When
the value is written, write the low-order bytes first and the high-
order bytes next.
Write to or read from the timer X register by the 16-bit unit. If read-
ing from the timer Y register during write operation or writing to it
during read operation is performed, normal operation will not be
performed.
• Which write control can be selected by the timer Y write control bit
(b0) of the timer Y control register (address 0039 16), writing data to
both the latch and the timer at the same time or writing data only to
the latch. When writing a value to the timer Y address to write to the
latch only, the value is set into the reload latch and the timer is
updated at the next underflow. After reset release, when writing a
value to the timer Y address, the value is set into the timer and the
timer latch at the same time, because they are set to write at the
same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the high-order reload
latch.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
Fig. 29 Structure of Timer X related registers
● Real Time Port Control
When the real time port function is valid, data for the real time port is
output from ports P50 and P51 each time the timer Y underflows.
(However, if the real time port control bit is changed from “0” to “1”
after the data for real time port is set, data is output independent of
the timer Y operation.) When the data for the real time port is changed
while the real time port function is valid, the changed data is output at
the next underflow of timer Y. Before using this function, set the cor-
responding port direction registers to output mode.
Rev.2.00 Nov 23, 2005 page 35 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
1/4
1
/
4
F
/
F
S
e
r
i
a
l
I
/
O
1
s
t
a
t
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g
i
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r
S
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r
i
a
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I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
φ
SOURCE
Receive buffer register
Address 0018
16
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
Receive buffer full flag (RBF)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
C
l
o
c
k
c
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t
r
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c
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u
i
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S
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k
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I
/
O
1
s
y
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r
o
n
o
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c
k
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l
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c
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b
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F
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y
d
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o
n
r
a
t
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o
1
/
(
n
+
1
)
B
a
u
d
r
a
t
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g
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n
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r
a
t
o
r
A
d
d
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s
s
0
0
1
C
1
6
B
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G
c
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n
t
s
o
u
r
c
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s
e
l
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c
t
i
o
n
b
i
t
Clock control circuit
F
a
l
l
i
n
g
-
e
d
g
e
d
e
t
e
c
t
o
r
T
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
Data bus
Address 0018
16
S
h
i
f
t
c
l
o
c
k
Transmit shift completion f lag (TSC)
Transmit buf fer empty flag (TBE)
Transmit inter rupt request (TI)
Transmit inter rupt source selection bit
A
d
d
r
e
s
s
0
0
1
9
1
6
Data bus
A
d
d
r
e
s
s
0
0
1
A
1
6
T
r
a
n
s
m
i
t
s
h
i
f
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g
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r
P
4
0
/
R
X
D
P
4
2
/
S
C
L
K
1
P
4
3
/
S
R
D
Y
1
P
4
1
/
T
X
D
φ SOURCE:represents the supply source of internal clock φ.
X
IN
input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and
Sub clock in the low-speed mode.
SERIAL INTERFACE
● Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for baud
rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting the
serial I/O mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig. 30 Block diagram of clock synchronous serial I/O1
Fig. 31 Operation of clock synchronous serial I/O1 function
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
R
B
F
=
1
T
S
C
=
1
T
B
E
=
0TBE = 1
TSC = 0
T
r
a
n
s
f
e
r
s
h
i
f
t
c
l
o
c
k
(
1
/
2
t
o
1
/
2
0
4
8
o
f
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t
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r
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,
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k
)
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u
t
p
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x
D
Serial input RxD
W
r
i
t
e
p
u
l
s
e
t
o
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c
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v
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/
t
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s1: As the transmit interrupt (TI) source, which can be selected, eit her when the t ransmit buffer has emptied (TBE = 1) or
after the transmit shift operation has ended (TSC = 1), by setting the transmit interr upt source select ion bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC= 0, the transmit clo ck is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
R
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Rev.2.00 Nov 23, 2005 page 36 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by set-
ting the serial I/O mode selection bit of the serial I/O1 control register
to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift regis-
ter cannot be written to or read from directly, transmit data is written
to the transmit buffer register, and receive data is read from the re-
ceive buffer register.
The transmit buffer register can also hold the next data to be trans-
mitted, and the receive buffer register can hold a character while the
next character is being received.
Fig. 32 Block diagram of UART serial I/O1
Fig. 33 Operation of UART serial I/O1 function
1/4
OE
PE F
E
1/16
1
/
1
6
D
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p
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Baud rate generator
Frequency division ratio 1/(n+1)
S
T
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A
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r
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D
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Transmit shift register
T
r
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m
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S
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SP detector U
A
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A
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1
B
1
6
Character length selection bit
B
R
G
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Transmit interrupt source selection bit
S
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1
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n
b
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7
b
i
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s
8
b
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s
Serial I/O1 control register
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r
i
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I
/
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1
s
t
a
t
u
s
r
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g
i
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t
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r
Address 0018
16
Address 001C
16
A
d
d
r
e
s
s
0
0
1
8
1
6
Address 0019
16
A
d
d
r
e
s
s
0
0
1
A
1
6
P
4
0
/
R
X
D
P
4
2
/
S
C
L
K
1
P
4
1
/
T
X
D
φ
S
O
U
R
C
E
φ
S
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U
R
C
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n
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c
l
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k
φ.
X
I
N
i
n
p
u
t
:
i
n
t
h
e
m
i
d
d
l
e
-
o
r
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s
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.
T
S
C
=
0
T
B
E
=
1
RBF=0
T
B
E
=
0T
B
E
=
0
RBF=1 R
B
F
=
1
S
T
D0D1S
P
D0D1
S
T
S
P
TBE=1 TSC=1
S
T
D0D1S
P
D0D1
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P
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m
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,
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r
.
3
:
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r
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p
t
(
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w
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f
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4
:
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f
t
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r
d
a
t
a
i
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w
r
i
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m
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n
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l
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=
“
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,
0
.
5
t
o
1
.
5
c
y
c
l
e
s
o
f
t
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d
a
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f
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=
“
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.
N
o
t
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s
✽
✽
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e
r
i
a
l
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t
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t
TXD
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a
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a
d
s
i
g
n
a
l
Rev.2.00 Nov 23, 2005 page 37 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
[Transmit Buffer Register/Receive Buffer Reg-
ister (TB/RB)]
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and the
receive buffer is read-only. If a character bit length is 7 bits, the MSB
of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIO1STS)]
The read-only serial I/O1 status register consists of seven flags (bits
0 to 6) which indicate the operating status of the serial I/O function
and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is set to “0” when the receive buf fer
register is read.
If there is an error, it is detected at the same time that data is trans-
ferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A write to the serial I/O1 status
register sets all the error flags OE, PE, FE, and SE (bit 3 to bit 6,
respectively) to “0”. Writing “0” to the serial I/O1 enable bit SIOE (bit
7 of the serial I/O1 control register) also sets all the status flags to
“0”, including the error flags.
All bits of the serial I/O1 status register are set to “0” at reset, but if
the transmit enable bit (bit 4) of the serial I/O1 control register has
been set to “1”, the transmit shift completion flag (bit 2) and the trans-
mit buffer empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIO1CON)]
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)]
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer and one bit (bit 4) which is always
valid and sets the output structure of the P41/TXD pin.
[Baud Rate Generator (BRG)]
The baud rate generator determines the baud rate for serial transfer .
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Notes on serial I/O1
When setting transmit enable bit of serial I/O1 to “1”, the serial I/O1
transmit interrupt request bit is automatically set to “1”. When not
requiring the interrupt occurrence synchronous with the transmision
enabled, take the following sequence.
➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
Rev.2.00 Nov 23, 2005 page 38 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 34 Structure of serial I/O1 related registers
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 status register
Serial I/O1 control register
b0 b0
BRG count source selection bit (CSS)
0: φSOURCE
1: φSOURCE/4
b7 UART control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
b0
(SIO1STS : address 001916) (SIO1CON : address 001A16)
(UARTCON : address 001B16)
φ SOURCE: represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode,
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and
Sub clock in the low-speed mode.
(Note)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P40 to P43 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P40 to P43 operate as serial I/O pins)
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
SRDY1 output enable bit (SRDY)
0: P43 pin operates as ordinary I/O pin
1: P43 pin operates as SRDY1 output pin
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
Not used (return “1” when read)
P41/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
Parity selection bit (
PARS)
0: Even parity
1: Odd parity
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Not used (returns “1” when read)
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Framing error flag (FE)
0: No error
1: Framing error
Parity error flag (PE)
0: No error
1: Parity error
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Rev.2.00 Nov 23, 2005 page 39 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
●Serial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For serial I/O2, the transmitter and the receiver must use the same
clock. When the internal clock is used, transfer is started by a write
signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
Fig. 35 Structure of serial I/O2 control registers
Fig. 36 Block diagram of serial I/O2
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Serial I/O2 control register
(SIO2CON: address 001D16)
Serial I/O2 port selection bit
0 : I/O port
1 : SOUT2, SCLK2 signal pin
φ S
O
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Frequency
divider
1/8
1/16
1/32
1/64
1/128
1/256
Data bus
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
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Rev.2.00 Nov 23, 2005 page 40 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 37 Serial I/O2 timing
D7D0D1D2D3D4D5D6
Transfer clock
(Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 input SIN2
Serial I/O2 output SOUT2
Serial I/O2 interrupt request bit set
1: When the internal clock is selected as the transfer, the dividing frequency of internal clock for transfer clock
can be selected by bits 0 to 2 of serial I/O2 control register.
2: When the internal clock is selected as the transfer, the SOUT2 pin is in a high impedance state
after the data transfer is completed.
When the external clock is selected as the transfer, the contents of serial I/O shift register keeps shifting during the
transmit/receive clock is input.
Also, the SOUT2 pin is not in a high impedance state after the data transfer is completed.
Rev.2.00 Nov 23, 2005 page 41 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
A/D CONVERTER
The 38C5 group has a 10-bit A/D converter. The A/D converter per-
forms successive approximation conversion.The 38C5 group has the
ADKEY function which perform A/D conversion of the “L” level ana-
log input from the ADKEY pin automatically.
[AD Conversion Register (ADL, ADH)]
One of these registers is a high-order register , and the other is a low-
order register . The high-order 8 bits of a conversion result is stored in
the AD conversion register (high-order) (address 001716), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
AD conversion register (low-order) (address 001616).
During A/D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference volt-
age input pin (VREF) can be controlled by the VREF input switch bit (bit
0 of address 001616). When “1” is written to this bit, the resistor ladder
is always connected to VREF. When “0” is written to this bit, the resistor
ladder is disconnected from VREF except during the A/D conversion.
[AD Control Register (ADCON)]
This register controls A/D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 3 is an AD conversion completion bit and “0” during A/
D conversion. This bit is set to “1” upon completion of A/D conversion.
A/D conversion is started by setting “0” in this bit.
Bit 5 is the ADKEY enable bit. The ADKEY function is enabled by
setting “1” to this bit. When this function is valid, the analog input
selection bit is ignored. Also, when bit 5 is “1”, do not set “0” to bit 3
by program.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
Fig. 38 Block diagram of A/D converter
A
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AD conversion register (H) AD conversion register (L)
(Address 001716)(
A
d
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0
1
61
6)
Resistor ladder
[Channel Selector]
The channel selector selects one of the input ports P57/AN7–P50/
AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compare an analog input voltage
with the comparison voltage and store the result in the AD conver-
sion register. When an A/D conversion is completed, the control cir-
cuit sets the AD conversion completion bit and the AD conversion
interrupt request bit to “1.”
The comparator is constructed linked to a capacitor. The conversion
accuracy may be low because the change is lost if the conversion
speed is not enough.
Accordingly, set f(XIN) to at least 500 kHz during A/D conversion in
the middle- or high- speed mode.
Also, do not execute the STP and WIT instructions during the A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by the
built-in self-oscillation circuit, the minimum value of f(XIN) frequency.
Rev.2.00 Nov 23, 2005 page 42 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 39 Structure of AD control register
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Analog input pin selection bits
b2 b1 b0
00 0: P5
0/AN0
00 1: P51/AN1
01 0: P52/AN2
01 1: P53/AN3
10 0: P54/AN4
10 1: P55/AN5
11 0: P56/AN6
11 1: P57/AN7
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Rev.2.00 Nov 23, 2005 page 43 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
ADKEY function
The ADKEY function is used to judge the analog input voltage input
from the ADKEY pin. When the A/D converter starts operating after
VIL (0.7 ✕ Vcc-0.5) or less is input, the event of analog voltage input
can be judged with the A/D conversion interrupt.
This function can be used with the STP and WIT state.
As for the ADKEY function in 38C5 group, the A/D conversion of
analog input voltage immediately after starting ADKEY function is
not performed.
Therefore, the A/D conversion result immediately after an ADKEY
function is undefined. Accordingly, when the A/D conversion result of
the analog input voltage input from the ADKEY pin is required, start
the A/D conversion by program after the analog input pin correspond-
ing to ADKEY is selected.
• ADKEY Selection
When the ADKEY pin is used, set the ADKEY selection bit to “1”. The
ADKEY selection bit is “0”, just after the A/D conversion is started.
• ADKEY Enable
The ADKEY function is enabled by writing “1” to the ADKEY enable
bit. Surely, in order to enable ADKEY function, set “1” to the ADKEY
enable bit, after setting the ADKEY selection bit to “1”.
When the ADKEY enable bit of the AD control register is “1”, the
analog input pin selection bits become invalid. Please do not write
“0” in the AD conversion completion bit by the program during ADKEY
enabled state.
[ADKEY Control Circuit]
In order to obtain a more exact conversion result, by the A/D conver-
sion with ADKEY, execute the following;
• set the input to the ADKEY pin into a steep falling waveform,
• stabilize the input voltage within 8 clock cycles (1 µs at f(XIN) = 8
MHz) after the input voltage is under VIL, and
• maintain the input voltage until the completion of the A/D conver-
sion.
The threshold voltage with an actual ADKEY pin is the voltage be-
tween VIH-VIL.
In order not to make ADKEY operation perform superfluously in a
noise etc., in the state of the waiting for an input, set the voltage of an
ADKEY pin to VIH (0.9VCC) or more.
When the following operations are performed, the A/D conversion
operation cannot be guaranteed.
• When the CPU mode register is operated during A/D conversion
operation,
• When the AD conversion control register is operated during A/D
conversion operation,
• When the STP or WIT instruction is executed during A/D conver-
sion operation.
Rev.2.00 Nov 23, 2005 page 44 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
LCD DRIVE CONTROL CIRCUIT
The 38C5 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
•LCD display RAM
•Segment output disable register
•LCD mode register
•Selector
•Timing controller
•Common driver
•Segment driver
•Bias control circuit
A maximum of 36 segment output pins and 8 common output pins
can be used.
Up to 256 pixels can be controlled for an LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
segment output disable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Fig. 40 Structure of LCD related registers
Table 9 Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pixels
36 dots
or 8 segment LCD 4 digits
72 dots
or 8 segment LCD 9 digits
108 dots
or 8 segment LCD 12 digits
144 dots
or 8 segment LCD 18 digits
256 dots
or 8 segment LCD 32 digits
1
2
3
4
8
Segment output disable bit 0
0 : Segment output SEG
8
1 : Output port P0
0
Segment output disable bit 1
0 : Segment output SEG
9
1 : Output port P0
1
Segment output disable bit 2
0 : Segment output SEG
10
1 : Output port P0
2
Segment output disable bit 3
0 : Segment output SEG
11
1 : Output port P0
3
Segment output disable bit 4
0 : Segment output SEG
12
1 : Output port P0
4
Segment output disable bit 5
0 : Segment output SEG
13
1 : Output port P0
5
Segment output disable bit 6
0 : Segment output SEG
14
1 : Output port P0
6
Segment output disable bit 7
0 : Segment output SEG
15
1 : Output port P0
7
Segment output disable register 0
(SEG0 : address 0FF4
16
)
b7 b0 LCD mode register 1
(LM1 : address 0013
16
)
Duty ratio selection bits
b2 b1 b0
0 0 0 : 1 (Static)
0 0 1 : 2 (use COM
0
,COM
1
)
0 1 0 : 3 (use COM
0
–COM
2
)
0 1 1 : 4 (use COM
0
–COM
3
)
1 0 0 to 1 1 0: Not available
1 1 1 : 8 (COM
0
–COM
7
)
Bias control bit
0 : 1/3 bias (Note 1)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD circuit divider division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note 2)
0 : f(X
CIN
)/32
1 : φSOURCE/8192
Note : LCDCK is a clock for an LCD timing controller.
b7 b0
Segment output disable bit 8
0 : Segment output SEG
0
1 : Output port P2
0
Segment output disable bit 9
0 : Segment output SEG
1
1 : Output port P2
1
Segment output disable bit 10
0 : Segment output SEG
2
1 : Output port P2
2
Segment output disable bit 11
0 : Segment output SEG
3
1 : Output port P2
3
Segment output disable bit 12
0 : Segment output SEG
4
1 : Output port P2
4
Segment output disable bit 13
0 : Segment output SEG
5
1 : Output port P2
5
Segment output disable bit 14
0 : Segment output SEG
6
1 : Output port P2
6
Segment output disable bit 15
0 : Segment output SEG
7
1 : Output port P2
7
Segment output disable register 1
(SEG1 : address 0FF5
16
)
b7 b0
Segment output disable bit 16
0 : Segment output SEG
16
–SEG
19
1 : Output port P1
0
–P1
3
Segment output disable bit 17
0 : Segment output SEG
20
–SEG
23
1 : Output port P1
4
–P1
7
Segment output disable bit 18
0 : Segment output SEG
24
–SEG
27
1 : Output port P3
0
–P3
3
Segment output disable bit 19
0 : Segment output SEG
28
–SEG
31
1 : Output port P3
4
–P3
7
Do not write “1” to these bits.
Segment output disable register 2
(SEG2 : address 0FF6
16
)
b7 b0 Notes 1: When “1” is selected as duty ratio by the duty ratio selection bits, set “1” to the bias
control bit.
2: LCDCK is the clock for the LCD timing controller. φ
SOURCE
represents the supply
source of internal clock φ. X
IN
input: in the middle- or high-speed mode, Internal on-
chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-
speed mode.
3: Only pins set to output ports by the direction register can be controlled to switch to
output ports or segment outputs by the segment output disable register.
4: When disabling the voltage multiplier circuit, the C
1
and C
2
pins function as input
ports P7
0
/INT
01
, P7
1
/INT
11
.
b7 b0 LCD mode register 2
(LM2 : address 0014
16
)
Voltage multiplier circuit control bit
0 : Voltage multiplier circuit disabled
(Input ports P7
0
/INT
01
, P7
1
/INT
11
)
1 : Voltage multiplier circuit enabled
V
L3
connection bit
0 : Connect V
L3
to V
CC
.
1 : Leave V
L3
and V
CC
open.
Not available
Rev.2.00 Nov 23, 2005 page 45 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 41 Block diagram of LCD controller/driver
f(X
CIN
)/32
φ
SOURCE
/8192
COM
0
COM
1
COM
2
COM
3
V
SS
V
L3
P2
3
/SEG
3
P2
2
/SEG
2
P2
1
/SEG
1
P2
0
/SEG
0
“0”
“1”
LCDCK
22
V
L2
V
L1
COM4/
SEG35 COM5/
SEG34 COM6/
SEG33 COM7/
SEG32
COM4/
SEG35
COM5/
SEG34
COM7/
SEG32 C
1
C
2
VL3
connection
bit
VCC
(Note 1)
Level
shift Level
shift Level
shift Level
shift
Level
shift Level
shift Level
shift Level
shift Level
shift Level
shift
Data bus
Timing controller
Common
driver
Bias control
LCDCK count
source selection bit
LCD circuit
divider division
ratio selection bits
Bias control bit
LCD enable bit
Duty ratio selection bits
SelectorSelector
Selector Selector
LCD display RAM
Address
086216
Segment
driver Segment
driver Segment
driver Segment
driver
Common
driver Common
driver Common
driver
Selector Selector
Segment
driver Segment
driver
Voltage multiplier
control bit
Level
shift Level
shift Level
shift Level
shift
Common
driver Common
driver Common
driver Common
driver
Address
086316
Address
084016 Address
084116 Address
084216 Address
084316
LCD
divider
Notes 1: LCDCK is the clock for the LCD timing controller. φ SOURCE represents the supply source of internal clock φ.
X
IN
input: in the middle- or high-speed mode, internal on-chip oscillator divided by 4 in the on-chip oscillator
mode, and Sub clock in the low-speed mode.
2: When the voltage multiplier circuit is not used (bit 0 of LCD mode register 2 = “0”), the C
1
and C
2
pins function
as input ports P7
0
/INT
01
, P7
1
/INT
11
.
(Note 2)
Rev.2.00 Nov 23, 2005 page 46 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Duty
ratio
1
2
3
4
8
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Fig. 42 Example of circuit at each bias
Table 10 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Note : VLCD is the maximum value of supplied voltage for the LCD panel.
Table 11 Duty ratio control and common pins used
Note: Unused common pin outputs the unselected waveform.
Common pins used
COM0
COM0, COM1
COM0–COM2
COM0–COM3
COM0–COM7
Bit 1
0
0
1
1
1
Bit 0
0
1
0
1
1
Duty ratio selection bits
Segment Signal Output Pin
The segment signal output pins (SEG0–SEG31) are shared with ports
P0–P3. When these pins are used as the segment signal output pins,
set the direction registers of the corresponding pins to “1”, and set
the segment output disable register to “0”.
Also, these pins are set to the input port after reset, the VCC voltage
is output by the pull-up resistor.
Bit 2
0
0
0
0
1
V
L3
V
L2
P7
1
/INT
11
P7
0
/INT
01
V
L1
✻
R1
R2
R3
1/3 bias: R1 = R2 = R3
1/3 bias
Voltage multiplier is used.
V
L3
V
L2
C
2
C
1
V
L1
1/3 bias
Voltage multiplier is used.
V
L3
V
L2
P7
1
/INT
11
P7
0
/INT
01
V
L1
R4
R5
R4 = R5
1/2 bias 1/1 bias (static)
V
L3
V
L2
V
L1
Contrast adjust Contrast adjust
✻: When the volta
g
e multi
p
lier is not used, the C
1
and C
2
p
ins function as in
p
ut
p
orts P7
0
/INT
01
, P7
1
/INT
11
.
✻
✻
✻
Common Pin and Duty Ratio Control
The common pins (COM0–COM7) to be used are determined by duty
ratio. Select duty ratio by the duty ratio selection bits (bits 0, 1 and 2
of the LCD mode register 1). When reset is released, VCC voltage is
output from the common pin.
Voltage Multiplier
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin V
L1
.
Set each bit of the segment output disable registers and the LCD
mode registers in the following order for operating the voltage multi-
plier.
1. Set the segment output disable bits (bits 0 to 19) of the segment
output disable registers (SEG0, 1, 2) to “0” or “1”.
2. Set the duty ratio selection bits (bits 0 to 2), the bias control bit
(bit 3), the LCD circuit divider division ratio selection bits (bits 5
and 6), and the LCDCK count source selection bit (bit 7) of the
LCD mode register 1 to “0” or “1”.
3. Set the VL3 connection bit (bit 1 of the LCD mode register 2
(LM2)) to “1”. Apply the limit voltage or less to the VL1 pin.
4. Set the voltage multiplier control bit (bit 0) of the LCD mode reg-
ister 2 to “1”. However, be sure to select 1/3 bias for bias control.
When voltage is input to the V
L1
pin during operating the voltage
multiplier , voltage that is twice as large as V
L1
occurs at the V
L2
pin,
and voltage that is three times as large as V
L1
occurs at the V
L3
pin.
The voltage multiplier is controlled by the voltage multiplier control
bit (bit 0 of the LCD mode register 2).
In addition, when the voltage multiplier is used, set the voltage multi-
plier control bit to “1” (voltage multiplier enabled) after the voltage 1.3
V or more and 2.1 V or less.
When the voltage multiplier is not used, set the VL3 connection bit to
“1” (open), and apply the suitable voltage for the power supply input
pins for LCD (VL1-VL3).
When VL3 connection bit is set to be opened, VL3 pin is in a high
impedance state.
Bias Control and Applied V oltage to LCD Power
Input Pins
Apply the voltage value shown in Table 9 according to the bias value
to the LCD power input pins.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Rev.2.00 Nov 23, 2005 page 47 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 43 LCD display RAM map
LCD Display RAM
The 36-byte area of address 084016 to 086316 is the designated RAM
for the LCD display. When “1” is written to these addresses, the cor-
responding segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated inter-
nally and the frame frequency can be determined with the following
equation;
SEG
1
SEG
3
SEG
5
SEG
7
SEG
9
SEG
11
SEG
13
SEG
15
SEG
17
SEG
19
SEG
21
SEG
23
SEG
25
SEG
27
SEG
29
SEG
31
SEG
0
SEG
2
SEG
4
SEG
6
SEG
8
SEG
10
SEG
12
SEG
14
SEG
16
SEG
18
SEG
20
SEG
22
SEG
24
SEG
26
SEG
28
SEG
30
76543210
Bits
Address
COM3 COM2 COM1 COM0
SEG
33
SEG
35
SEG
32
SEG
34
SEG
1
SEG
3
SEG
5
SEG
7
SEG
9
SEG
11
SEG
13
SEG
15
SEG
17
SEG
19
SEG
21
SEG
23
SEG
25
SEG
27
SEG
29
SEG
31
SEG
0
SEG
2
SEG
4
SEG
6
SEG
8
SEG
10
SEG
12
SEG
14
SEG
16
SEG
18
SEG
20
SEG
22
SEG
24
SEG
26
SEG
28
SEG
30
COM7 COM6 COM5 COM4
0840
16
0841
16
0842
16
0843
16
0844
16
0845
16
0846
16
0847
16
0848
16
0849
16
084A
16
084B
16
084C
16
084D
16
084E
16
084F
16
Bits
Address
0850
16
0851
16
COM3 COM2 COM1 COM0
0852
16
0853
16
0854
16
0855
16
0856
16
0857
16
0858
16
0859
16
085A
16
085B
16
085C
16
085D
16
085E
16
085F
16
0860
16
0861
16
0862
16
0863
16
0840
16
0841
16
0842
16
0843
16
0844
16
0845
16
0846
16
0847
16
0848
16
0849
16
084A
16
084B
16
084C
16
084D
16
084E
16
084F
16
0850
16
0851
16
0852
16
0853
16
0854
16
0855
16
0856
16
0857
16
0858
16
0859
16
085A
16
085B
16
085C
16
085D
16
085E
16
085F
16
0860
16
0861
16
0862
16
0863
16
Not used
(This area can be used as normal RAM.)
at 4COM ✕ 36SEG at 8COM ✕ 32SEG
76543210
Not used
(This area can be
used as normal RAM.)
Rev.2.00 Nov 23, 2005 page 48 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 44 LCD drive waveform (1/2 bias)
1/4 duty Voltage level
VL3
VL2=VL1
VSS
VL3
VSS
COM0
COM1
COM2
COM3
SEG0
1/3 duty
1/2 duty
COM0
COM1
COM2
SEG0
COM0
COM1
SEG0
COM3COM2COM1COM0COM3COM2COM1COM0
OFFON ON OFF ON OFF
OFFON OFFON OFFON OFFON
COM0COM2COM1COM0COM2COM1COM0COM2
COM1COM0COM1COM0COM1COM0COM1COM0
1/8 duty
VL3
VL2=VL1
VSS
VL3
VSS
VL3
VL2=VL1
VSS
VL3
VSS
Voltage level
VL3
VL2=VL1
VSS
VL3
VSS
Internal signal
LCDCK timing
COM0
COM1
COM2
COM3
SEG0
COM4
COM5
COM6
COM7
OFF ON
COM7COM6COM5COM4COM3COM2COM1COM0COM7COM6COM5COM4COM3COM2COM1COM0
COM3COM2COM1COM0COM3COM2COM1COM0
OFFON ON OFF ON OFF
OFFON OFFON OFFON OFFON
COM1COM0COM2COM1COM0COM2COM1COM0
COM1COM0COM1COM0COM1COM0COM1COM0
OFF ON OFF ON OFF ON
OFF ON OFF ON OFF ON OFF ON
Rev.2.00 Nov 23, 2005 page 49 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 45 LCD drive waveform (1/3 bias)
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
1/3 duty
1
/
2
d
u
t
y
COM
0
COM
1
COM
2
S
E
G
0
COM
0
C
O
M
1
SEG
0
O
F
FO
N O
NO
F
F O
NOFF
COM
0
COM
2
C
O
M
1
COM
0
COM
2
COM
1
COM
0
COM
2
1
/
8
d
u
t
y
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
V
L
3
V
SS
V
L3
V
L2
V
S
S
V
L1
V
L
3
V
L
2
V
S
S
V
L
1
V
L3
V
S
S
V
L3
V
L2
V
S
S
V
L1
V
L3
V
SS
V
L
3
V
S
S
Voltage level
V
L
3
V
L
2
V
S
S
V
L
1
C
O
M
4
C
O
M
5
C
O
M
6
C
O
M
7
O
F
FO
NOFFO
N O
F
FO
NOFFO
N
COM
1
COM
0
C
O
M
1
COM
0
COM
1
COM
0
COM
1
COM
0
OFF O
NOFF O
N
C
O
M
7
COM
6
COM
5
COM
4
C
O
M
3
COM
2
COM
1
COM
0
O
F
FO
N O
F
FO
N
COM
7
COM
6
C
O
M
5
C
O
M
4
COM
3
C
O
M
2
C
O
M
1
C
O
M
0
1
/
4
d
u
t
y
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
O
F
FO
N O
F
FON
COM
3
COM
2
C
O
M
1
COM
0
COM
3
COM
2
C
O
M
1
COM
0
OFF O
NOFF O
N
COM
3
COM
2
C
O
M
1
C
O
M
0
COM
3
C
O
M
2
COM
1
C
O
M
0
SEG
0
O
F
FON ON OFF O
NO
F
F
COM
0
C
O
M
2
C
O
M
1
COM
0
COM
2
COM
1
COM
0
COM
2
O
F
FON O
F
FON O
F
FO
N O
F
FON
COM
1
COM
0
COM
1
C
O
M
0
COM
1
COM
0
COM
1
COM
0
S
E
G
0
Rev.2.00 Nov 23, 2005 page 50 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software run-away). The watchdog timer consists of an 8-bit
counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register , each watch-
dog timer is set to “FF16.” Instructions such as STA, LDM and CLB to
generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values are
set.
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the watch-
dog timer control register. An internal reset occurs at an underflow of
the watchdog timer. Then, reset is released after the reset release
time is elapsed, the program starts from the reset vector address.
Normally, writing to the watchdog timer control register before an
underflow of the watchdog timer is programmed. If writing to the watch-
dog timer control register is not executed, the watchdog timer does
not operate.
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction dis-
able bit (bit 6), and the count source selection bit (bit 7) are read out.
Bit 6 of Watchdog Timer Control Register
•When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting(Note). When executing the WIT instruction, the watchdog
timer does not stop.
•When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to “0” by
program. Bit 6 is “0” at reset.
The time until the underflow of the watchdog timer register after writ-
ing to the watchdog timer control register is executed is as follows
(when the bit 7 of the watchdog timer control register is “0”) ;
• at high-speed and middle-speed mode (f(XIN)) = 8 MHz): 32.768
ms
• at low-speed mode (f(XCIN) = 32 KHz): 8.19s
■ Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait mode.
Accordingly, do not underflow the watchdog timer in this time.
Fig. 46 Block diagram of Watchdog timer
Fig. 47 Structure of Watchdog timer control register
1
/
1
0
2
4
RESET
1/4
φ SOURCE
Undefined instruction
Reset
W
a
i
t
u
n
t
i
l
r
e
s
e
t
r
e
l
e
a
s
e
Data bus
Watchdog timer
count source
selection bit
Reset
circuit
S
T
P
i
n
s
t
r
u
c
t
i
o
n
d
i
s
a
b
l
e
b
i
t
Watchdog timer
H (6)
I
n
t
e
r
n
a
l
r
e
s
e
t
STP instruction
Watchdog timer
L (2)
“
F
F
1
6
”
i
s
s
e
t
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n
w
a
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c
h
d
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r
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o
.
“0”
“1”
b
0
S
T
P
i
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s
t
r
u
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i
o
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d
i
s
a
b
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b
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t
0
:
E
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e
r
i
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s
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o
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b
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o
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S
T
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1
:
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c
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0
:
φ
S
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R
C
E
/
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0
2
4
1
:
φ
S
O
U
R
C
E
/
4
Watc hdog timer H (for re ad-out of high-o r der 6 bit)
“FF
16
” is set to w atchdog timer by wr iting to these bits.
Watchdog timer control register
(WDTCON : address 0029
16
)
b7
N
o
t
e
:
φ
S
O
U
R
C
E
r
e
p
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k
φ.
X
I
N
i
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p
u
t
:
i
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e
m
i
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d
l
e
-
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r
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i
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-
s
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.
Rev.2.00 Nov 23, 2005 page 51 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
CLOCK OUTPUT FUNCTION
A system clock φ can be output from I/O port P72.The triple function
of I/O port, timer 2 output function and system clock φ output func-
tion are controlled by the clock output control register (address
0FF316) and the timer 2 output selection bit of the timer 12 mode
register (address 002516).
In order to output a system clock φ from I/O port P72, set the timer 2
output selection bit to “1“ and P72 clock output control bits of the
clock output control register to “01”. In order to output the same sig-
nal as oscillation frequency of sub clock XCIN, set the P72 clock out-
put control bits to “10”. When the clock output function is selected, a
clock is output while the direction register of port P72 is set to the
output mode.
P72 is switched to the port output or the output (timer 2 output or the
clock output) except port at the cycle after the P72 clock output con-
trol bits are switched.
Fig. 49 Block diagram of Clock output function
Fig. 48 Structure of clock output control register
b7 b0 Clock output control register
(CKOUT : address 0FF3
16
)
P72 clock output control bits
b1b0
0 0: Timer 2 output
0 1:
φ
frequency signal output
1 0: XCIN frequency signal output
1 1: Not available
Not used (returns “0” when read)
(Do not write “1” to these bits.)
1/2 Q
Q
S
T“0”
“1”
P7
2
/T
2OUT
/CKOUT
P7
2
clock output
control bits
b7 b0
System clock φ
XCIN
“00”
“01”
“10”
Timer 2 latch (8)
Timer 2 (8)
T
2OUT
output
edge switch bit
P7
2
clock output control bits
P7
2
latch
Timer 2 output selection bit
P7
2
direction register
Timer 12 mode register (address 0025
16
)
T12M
Timer 2 output selection bit
0: I/O port
1: Timer 2 output
Rev.2.00 Nov 23, 2005 page 52 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
b7 b0
DB4 data storage
DB5 data storage
DB6 data storage
DB7 data storage
DB0 data storage
DB1 data storage
DB2 data storage
DB3 data storage
RRF register
(RRFR : address 001216)
Fig. 50 Structure of RRF register
Other function registers
The RRF register (address 001216) is the 8-bit register and does not
have the control function.
As for the value written in this register, high-order 4 bits and low-
order 4 bits interchange.
It is initialized after reset.
Rev.2.00 Nov 23, 2005 page 53 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between VCC (min.) and 3.6 V,
and the quartz-crystal oscillator should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address FFFC16
(low-order byte). Make sure that the reset input voltage meets VIL
spec. when a power source voltage passes VCC (min.).
Fig. 52 Reset sequence
Fig. 51 Reset circuit example
VIL spec.
0V
0V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
RESET
SYNC
ROSC
FFFC FFFD ADH, ADL
ADLADH
????
........
Internal
reset
Address
Data
System clockφ
ROSC : about 32800 cycles
Notes
Reset address from
vector table
1: The frequency relation of f(XIN) and f(φ) is f(ROSC) = 32 • f(φ).
2: The question marks (?) indicate an undefined state.
Rev.2.00 Nov 23, 2005 page 54 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 53 Internal status at reset
003A
16
X: Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Address Register contents Address Register contents
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
0000
16
0001
16
0002
16
0004
16
0005
16
0006
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
0012
16
0015
16
0019
16
001D
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
Port P0
Port P0 direction register
Port P1
Port P2
Port P2 direction register
Port P3
Port P4
Port P4 direction register
Port P5
Port P5 direction register
Port P6
Port P6 direction register
RRF register (RRFR)
AD control register
Serial I/O1 status register
Timer 2
Timer 3
Timer 4
PWM01 register
Timer 12 mode register
Timer 34 mode register
(1)
(2)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(34)
(35)
(36)
(37)
(38)
Interrupt edge selection register
00
16
003B
16
003C
16
003F
16
(39)
(40)
(43)
(44)
(45)
(46)
(47)
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
00
16
Serial I/O2 control register
Timer 1
(33)
FFFC
16
contents
(PS)
(PC
H
)
(PC
L
)
Program counter
Processor status register
FFFD
16
contents
1
✕
08
16
FF
16
01
16
FF
16
FF
16
00
16
00
16
00
16
✕✕✕✕✕✕
00
16
0003
16
Port P1 direction register
(4)
003E
16
(41)
(42)
00
16
00
16
003D
16
00
16
00
16
00
16
0FF0
16
0FF1
16
0FF2
16
0FF3
16
(48)
(49)
(50)
(51)
00
16
FF
16
0FF4
16
0FF5
16
0FF6
16
(52)
(53)
(54)
FF
16
0F
16
00
16
0FF7
16
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
Port P3 direction register 0007
16
0026
16
10000000
Timer X (low-order)
Timer X (high-order)
Timer X (extension)
Timer Y (low-order)
Timer Y (high-order)
Timer X mode register
PULL register 3
Key input control register
Segment output disable register 0
Segment output disable register 1
Segment output disable register 2
Timer Y mode register
01101000
00
16
00
16
000E
16
000F
16
(15)
(16)
Port P7
Port P7 direction register 00
16
001B
16
UART control register 11100000
001A
16
Serial I/O1 control register
00
16
0013
16
LCD mode register 1
00
16
0014
16
LCD mode register 2
Timer 1234 mode register 0027
16
00
16
Watchdog timer control register
0028
16
00
16
0029
16
00
16
00
16
001111 11
Timer 1234 frequency division
selection register
Clock output control register
PULL register 2
PULL register 1
Timer X control register 1
Timer Y control register
Timer X control register 2
(63)
(64)
(65)
(66)
Compare register 1 (low-order)
Compare register 1 (high-order)
Compare register 2 (low-order)
Compare register 2 (high-order)
Compare register 3 (low-order)
Compare register 3 (high-order) 0035
16
FF
16
0036
16
0037
16
00
16
0039
16
00
16
00
16
0038
16
0030
16
00
16
0031
16
0032
16
00
16
0034
16
00
16
0033
16
002A
16
00
16
002B
16
002C
16
002F
16
FF
16
002E
16
002D
16
00
16
FF
16
00
16
00
16
00
16
FF
16
00
16
00
16
Rev.2.00 Nov 23, 2005 page 55 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 54 Ceramic resonator circuit example
Fig. 55 External clock input circuit
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock φ stops at an “H”
level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values to
generate the wait time required for oscillation stabilization to timer 1
latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8
bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count source,
and the output of timer 1 is forcibly connected to timer 2. In this time,
bits 0 to 5 of the timer 12 mode register are cleared to “0”.
The values of the timer 12 frequency divider selection register are
not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to be disabled
(“0”) before executing the STP instruction.
When an external interrupt is received, the clock oscillated before
stop mode and the on-chip oscillator start oscillating.
However, bit 3 of CPUM is set to “1” forcibly and system returns to
the on-chip oscillator mode.
Oscillator restarts when reset occurs or an interrupt request is re-
ceived, but the system clock φ is not supplied to the CPU until timer 2
underflows.
This allows time for the clock circuit oscillation to stabilize.
(2) Wait Mode
If the WIT instruction is executed, only the system clock φ stops at an
“H” state. The states of main clock, on-chip oscillator and sub clock
are the same as the state before executing the WIT instruction, and
oscillation does not stop. Since supply of system clock φ is started
immediately after the interrupt is received, the instruction can be ex-
ecuted immediately.
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
O
U
T
C
C
I
N
C
C
O
U
T
R
fR
d
R
d
(
N
o
t
e
)
Notes : Insert a damping resisto r if required.
The resistance will vary depending on the oscillator and the
oscillation drive capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer's data sheet speci fies
that a feedback resistor be added external to the chip
though a feedback resistor exists on-chip, insert a feedback
resistor between X
IN
and X
OUT
following the instruction.
XCIN XCOUT XIN XOUT
External oscillation circuit
Open
VCC
VSS
CCIN
Rf Rd
CCOUT
CLOCK GENERATING CIRCUIT
The oscillation circuit of 38C5 group can be formed by connecting an
oscillator, capacitor and resistor between XIN and XOUT (XCIN and
XCOUT). To supply a clock signal externally, input it to the XIN pin and
make the XOUT pin open. The clocks that are externally generated
cannot be directly input to XCIN. Use the circuit constants in accor-
dance with the oscillator manufacturer's recommended values. No
external resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. (An external feed-back resistor may be needed
depending on conditions.) However, an about 10 MΩ external feed-
back resistor is needed between XCIN and XCOUT.
Immediately after reset is released, only the on-chip oscillator starts
oscillating, XIN -XOUT oscillation stops oscillating, and XCIN and XCOUT
pins function as I/O ports.
Frequency Control
(1) On-chip oscillation Mode
The system clock φ is the on-chip oscillator oscillation divided by 32.
(2) Middle-speed Mode
The system clock φ is the frequency of XIN divided by 8.
(3)High-speed Mode
The system clock φ is half the frequency of XIN.
(4) Low-speed Mode
The system clock φ is half the frequency of sub clock.
After reset release and when system returns from the stop mode, the
on-chip oscillator mode is selected.
Refer to the clock state transition diagram for the setting of transition
to each mode.
The XIN–XOUT oscillation is controlled by the bit 5 of CPUM, and the
sub-clock oscillation is controlled by the bit 4 of CPUM. When the
mode is switched to the on-chip oscillator mode, set the bit 3 of CPUM
to “1”.
In the on-chip oscillator mode, the oscillation by the oscillator can be
stopped. In the low-speed mode, the power consumption can be re-
duced by stopping the XIN–XOUT oscillation.
When the mode is switched from the on-chip oscillator mode to the
low-speed mode, the on-chip oscillator is stopped.
Set enough time for oscillation to stabilize by programming to re-start
the stopped oscillation and switch the operation mode. Also, set
enough time for oscillation to stabilize by programming to switch the
timer count source .
■ Notes on Clock Generating Circuit
If you switch the mode between on-chip oscillator mode, middle/high-
speed mode and low-speed mode, stabilize both XIN and XCIN oscil-
lations. Especially be careful immediately after power-on and at re-
turning from stop mode. Refer to the clock state transition diagram
for the setting of transition to each mode. Set the frequency in the
condition that f(XIN) > 3•f(XCIN).
When the middle- and high-speed mode are not used (XIN-XOUT os-
cillation and external clock input are not performed), connect XIN to
VCC through a resistor.
Rev.2.00 Nov 23, 2005 page 56 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 56 Clock generating circuit block diagram
N
o
t
e
s
1
:
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W
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System clock φ
S
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q
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Reset
Main clock division
ratio selectio n bit
CPUM BIT6
Interrupt disable flag I
S
T
P
i
n
s
t
r
u
c
t
i
o
n
Port Xc
switch bit
CPUM BIT4
Internal system
clock selection bit
CPUM BIT7
F
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l
a
t
i
o
n
s
t
o
p
b
i
t
C
P
U
M
B
I
T
5
Main clock selection bit
CPUM BIT3
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
C
P
U
M
B
I
T
7
(
N
o
t
e
1
)
M
a
i
n
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
C
P
U
M
B
I
T
3
“
1
0
”
“00”
“
1
”“0”
“1”
“0”
“
1
”
“
0
”
“
1
”
“
0
”
“1”
“0”
“1”
“
0
”
(
N
o
t
e
2
)
Rev.2.00 Nov 23, 2005 page 57 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 57 State transitions of system clock
R
e
s
e
t
r
e
l
e
a
s
e
X
I
N
s
t
o
p
X
C
I
N
s
t
o
p
φ
=
f
(
R
O
S
C
)
/
3
2
C
M
7
=
0
C
M
6
=
1
(
N
o
t
e
5
)
C
M
5
=
1
C
M
4
=
0
C
M
3
=
1
X
I
N
s
t
o
p
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
f
(
R
O
S
C
)
/
3
2
C
M
7
=
0
C
M
6
=
1
(
N
o
t
e
5
)
C
M
5
=
1
C
M
4
=
1
C
M
3
=
1
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
s
t
o
p
φ
=
f
(
R
O
S
C
)
/
3
2
C
M
7
=
0
C
M
6
=
1
(
N
o
t
e
5
)
C
M
5
=
0
C
M
4
=
0
C
M
3
=
1
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
f
(
R
O
S
C
)
/
3
2
C
M
7
=
0
C
M
6
=
1
(
N
o
t
e
5
)
C
M
5
=
0
C
M
4
=
1
C
M
3
=
1
C
M
4
C
M
4
C
M
4
C
M
5
C
M
5
C
M
5
X
I
N
s
t
o
p
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
1
6
k
H
z
C
M
7
=
1
C
M
6
=
1
C
M
5
=
1
C
M
4
=
1
C
M
3
=
*
(
N
o
t
e
9
)
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
1
6
k
H
z
C
M
7
=
1
C
M
6
=
0
(
N
o
t
e
5
)
C
M
5
=
0
C
M
4
=
1
C
M
3
=
*
(
N
o
t
e
9
)
CM
6
C
M
6
CM
5
CM
5
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
s
t
o
p
φ
=
1
M
H
z
C
M
7
=
0
C
M
6
=
1
C
M
5
=
0
C
M
4
=
0
C
M
3
=
0
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
1
M
H
z
C
M
7
=
0
C
M
6
=
1
C
M
5
=
0
C
M
4
=
1
C
M
3
=
0
CM
4
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
s
t
o
p
φ
=
4
M
H
z
C
M
7
=
0
C
M
6
=
0
(
N
o
t
e
5
)
C
M
5
=
0
C
M
4
=
0
C
M
3
=
0
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
4
M
H
z
C
M
7
=
0
C
M
6
=
0
(
N
o
t
e
5
)
C
M
5
=
0
C
M
4
=
1
C
M
3
=
0
C
M
4
C
M
7
CM
7
C
M
7
X
I
N
o
s
c
i
l
l
a
t
i
o
n
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
φ
=
1
6
k
H
z
C
M
7
=
1
C
M
6
=
1
C
M
5
=
0
C
M
4
=
1
C
M
3
=
*
(
N
o
t
e
9
)
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
eLow-s peed mode
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
H
i
g
h
-
s
p
e
e
d
m
o
d
e
CM
3
b7 b3
CM
3
C
M
6
C
M
6
C
M
7
Main clock selection bit
0: Ceramic oscillation
1: On-chip oscillator
Port Xc switch bit
0: I/O port function (oscillation stop)
1: XCIN–XCOUT oscillation function
XIN–XOUT oscillation stop bit
0: Oscillation
1: Stop
Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (low-speed mode)
Internal system clock selection bit
0: Main clock selected
(middle-speed/high-speed/on-chip oscillator mode)
1: XCIN-XCOUT selected (low-speed mode)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B
1
6
)
1
:
S
w
i
t
c
h
t
h
e
m
o
d
e
b
y
t
h
e
a
r
r
o
w
s
s
h
o
w
n
b
e
t
w
e
e
n
t
h
e
m
o
d
e
b
l
o
c
k
s
.
T
h
e
a
l
l
m
o
d
e
s
c
a
n
b
e
s
w
i
t
c
h
e
d
t
o
t
h
e
s
t
o
p
m
o
d
e
o
r
t
h
e
w
a
i
t
m
o
d
e
.
2
:
T
i
m
e
r
a
n
d
L
C
D
o
p
e
r
a
t
e
i
n
t
h
e
w
a
i
t
m
o
d
e
.
S
y
s
t
e
m
i
s
r
e
t
u
r
n
e
d
t
o
t
h
e
s
o
u
r
c
e
m
o
d
e
w
h
e
n
t
h
e
w
a
i
t
m
o
d
e
i
s
e
n
d
e
d
.
3
:
C
M4,
C
M5
a
n
d
C
M6
a
r
e
r
e
t
a
i
n
e
d
i
n
t
h
e
s
t
o
p
m
o
d
e
.
S
y
s
t
e
m
i
s
r
e
t
u
r
n
e
d
t
o
t
h
e
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
(
C
M3=
1
,
C
M7=
0
)
.
4
:
W
h
e
n
t
h
e
s
t
o
p
m
o
d
e
i
s
e
n
d
e
d
,
s
e
t
t
h
e
o
s
c
i
l
l
a
t
i
o
n
s
t
a
b
i
l
i
z
i
n
g
w
a
i
t
t
i
m
e
i
n
t
h
e
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
.
5
:
W
h
e
n
t
h
e
s
t
o
p
m
o
d
e
i
s
e
n
d
e
d
,
s
e
t
t
h
e
i
n
i
t
i
a
l
v
a
l
u
e
t
o
C
M6
(
C
M6=
1
)
.
6
:
E
x
e
c
u
t
e
t
h
e
t
r
a
n
s
i
t
i
o
n
a
f
t
e
r
t
h
e
o
s
c
i
l
l
a
t
i
o
n
u
s
e
d
i
n
t
h
e
d
e
s
t
i
n
a
t
i
o
n
m
o
d
e
i
s
s
t
a
b
i
l
i
z
e
d
.
7
:
W
h
e
n
s
y
s
t
e
m
g
o
e
s
t
o
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
t
h
e
o
s
c
i
l
l
a
t
i
o
n
s
t
a
b
i
l
i
z
i
n
g
w
a
i
t
t
i
m
e
i
s
n
o
t
n
e
e
d
e
d
.
8
:
D
o
n
o
t
g
o
t
o
t
h
e
h
i
g
h
-
s
p
e
e
d
m
o
d
e
f
r
o
m
t
h
e
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
.
9
:
W
r
i
t
e
t
h
e
p
r
o
p
e
r
v
a
l
u
e
s
f
o
r
d
e
s
t
i
n
a
t
i
o
n
m
o
d
e
b
e
f
o
r
e
h
a
n
d
.
1
0
:
T
h
e
e
x
a
m
p
l
e
a
s
s
u
m
e
s
t
h
a
t
8
M
H
z
i
s
b
e
i
n
g
a
p
p
l
i
e
d
t
o
t
h
e
XI
N
p
i
n
a
n
d
3
2
k
H
z
t
o
t
h
e
XC
I
N
p
i
n
.
f
(
R
O
S
C
)
i
n
d
i
c
a
t
e
s
t
h
e
o
s
c
i
l
l
a
t
i
o
n
f
r
e
q
u
e
n
c
y
o
f
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
.
N
o
t
e
s
Rev.2.00 Nov 23, 2005 page 58 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
PROM Mode
M38C59GFFP/HP (referred to as “the MCU”) has a PROM Mode as
well as the normal operation mode. PROM Mode enables an exter-
nal device (referred to as “Programmer”) to read and program the
built-in EPROM via a minimum number of serial I/O pins by sending
commands to control the MCU.
To enable PROM Mode, use the pin connection shown in Figure 58
to 59 and apply power (VCC). Then execute the new One T ime PROM
entry operation, called “Mad Dog Entry”.
There are three operation modes in PROM Mode : Read, Program
and Program-Verify. Three commands are defined to enable each
mode respectively.
The format of the serial I/O is : clock synchronous and LSB-data-
first.
Fig. 58 Pin diagram in PROM mode (PLQP0080GA-A package type)
P20/SEG0/(KW4)
P21/SEG1/(KW5)
P22/SEG2/(KW6)
P23/SEG3/(KW7)
P24/SEG4
P25/SEG5
P26/SEG6
P27/SEG7
P00/SEG8
P03/SEG11
P04/SEG12
P05/SEG13
P06/SEG14
P07/SEG15
P11/SEG17
P12/SEG18
P13/SEG19
P14/SEG20
P15/SEG21
P16/SEG22
P17/SEG23
P44/SIN2/(KW0)
P45/SOUT2/(KW1)
P46/SCLK2/(KW2)
P47/SRDY2/(KW3)
COM1
COM3
COM0
P37/SEG31
P36/SEG30
P35/SEG29
P34/SEG28
P33/SEG27
P32/SEG26
P31/SEG25
P30/SEG24
COM2
P10/SEG16
P01/SEG9
P02/SEG10
M3822xMX-XXXFP
123456789 19 22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
414243
44
4546474849505152535455565758596061626364
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
23 2410 11 12 13 14 15 16 17 18 20 21
P55/AN5
P54/AN4
P53/AN3
P52/AN2
VREF
AVss
P63/TXOUT2/(LED1)
P66/INT10/CNTR0/(LED4)
M38C59GFFP
P57/AN7/ADKEY0
P56/AN6
P65/TXOUT1 /(LED3)
P64/INT2 /(LED2)
P62/INT00 /(LED0)
COM4/SEG35
COM5/SEG34
COM6/SEG33
COM7/SEG32
P43/SRDY1
P42/SCLK1
P41/TXD
P40/RXD
P51/AN1/RTP1
P50/AN0/RTP0
P61/XCOUT
P60/XCIN
P71/C2/INT11
VL3
VL2
VL1
P72/T2OUT/CKOUT
XIN
P74/PWM1/T4OUT
VSS
XOUT
VCC
CNVSS
P67/CNTR1/(LED5)
RESET
P73/PWM0/T3OUT
P70/C1/INT01
RESETB
VPP
ESCLK
VCC
XIN
ESPGMB
ESDA
XOUT
VSS
Rev.2.00 Nov 23, 2005 page 59 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 59 Pin Diagram in PROM mode (PLQP0080KB-A package type)
1
2
3
4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
M38C59GFHP
P5
1
/AN
1
/RTP
1
P5
0
/AN
0
/RTP
0
P6
3
/T
XOUT2
/(LED
1
)
P6
6
/INT
10
/CNTR
0
/(LED
4
)
P6
5
/T
XOUT1
/(LED3)
P6
4
/INT
2
/(LED
2
)
P6
2
/INT
00
/(LED
0
)
P6
1
/X
COUT
P6
0
/X
CIN
P7
1
/C
2
/INT
11
V
L3
V
L2
P7
2
/T
2OUT
/CKOUT
X
IN
P7
4
/PWM
1
/T
4OUT
V
SS
X
OUT
V
CC
CNV
SS
P6
7
/CNTR
1
/(LED
5
)
RESET
P7
3
/PWM
0
/T
3OUT
P7
0
/C
1
/INT
01
V
L1
COM
1
COM
3
COM
0
P3
7
/SEG
31
P3
6
/SEG
30
P3
5
/SEG
29
P3
4
/SEG
28
COM
2
COM
5
/SEG
34
COM
6
/SEG
33
COM
7
/SEG
32
P3
3
/SEG
27
P3
2
/SEG
26
P3
1
/SEG
25
P3
0
/SEG
24
P1
5
/SEG
21
P1
6
/SEG
22
P1
7
/SEG
23
P1
4
/SEG
20
P1
3
/SEG
19
P1
2
/SEG
18
P1
1
/SEG
17
P1
0
/SEG
16
P0
7
/SEG
15
P0
6
/SEG
14
P0
5
/SEG
13
P0
4
/SEG
12
P0
3
/SEG
11
P0
2
/SEG
10
P0
1
/SEG
9
P0
0
/SEG
8
P2
7
/SEG
7
P2
6
/SEG
6
P2
5
/SEG
5
P2
4
/SEG
4
P2
3
/SEG
3
/(KW
7
)
P2
2
/SEG
2
/(KW
6
)
P2
1
/SEG
1
/(KW
5
)
P2
0
/SEG
0
/(KW
4
)
P4
4
/S
IN2
/(KW0)
P4
5
/S
OUT2
/(KW
1
)
P4
6
/S
CLK2
/(KW
2
)
P4
7
/S
RDY2
/(KW
3
)
P5
5
/AN
5
P5
4
/AN
4
P5
3
/AN
3
P5
2
/AN
2
V
REF
AVss
P5
7
/AN
7
/ADKEY
0
P5
6
/AN
10
P4
3
/S
RDY1
P4
2
/S
CLK1
P4
1
/T
X
D
P4
0
/R
X
D
COM
4
/SEG
35
RESETB
VPP
ESCLK
VCC
XIN
ESPGMB
ESDA
XOUT
VSS
Rev.2.00 Nov 23, 2005 page 60 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 60 Programming and testing of One Time PROM
Precaution for Handling One-Time-Programmable
Devices
Our company ships one-time-programmable version MCUs (One-
T ime PROM MCU) without being screened by the PROM writing test.
To ensure the reliability of the MCU, We recommend that the user
performs the program and test procedure shown in Figure 60 before
using the MCU.
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
The screening temperature is far highe
r
than the storage temperature. Neve
r
expose to 150 °C exceeding 100 hours.
Caution:
Rev.2.00 Nov 23, 2005 page 61 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
ROM Code Access Protection
We would like to support a simple ROM code protection function that
prevents a party other than the ROM-code owner to read and repro-
gram the builit-in PROM code of the MCU.
The MCU has 7 bytes of dedicated ROM spaces in address 0xFFD4
to 0xFFDA, as an ID-code (referred to as “the ID-code”) enabling a
Programmer to verify with the input ID-code and validate further op-
erations.
Expected Programmer ID-Code Verification
Function
First, Programmer must check the ID-code of the MCU.
If the ID-code is still in blank, Programmer enebles all operations,
Read, Program, and Program-Verify.
When Programmer programs the MCU, Programmer also programs
the given ID-code as well as the actual firmware.
If the ID-code is not blank, Programmer verifies it with the input ID-
code.
When the ID-codes don't mutch, Programmer will reject all further
operations.
If they match, Programmer perform operations according to the given
command.
Fig. 61 ROM-Code Protection ID Location
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Address
FFD4
16
FFD5
16
FFD6
16
FFD7
16
FFD8
16
FFD9
16
FFDA
16
Rev.2.00 Nov 23, 2005 page 62 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing an SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
• If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
• The timers share the one frequency divider to generate the count
source. Accordingly, when each timer starts operating, initializing
the frequency divider is not executed. Therefore, when the frequency
divider is selected for the count source, the delay of the maximum
one cycle of the count source is generated until the timer starts
counting or the waveform is output from timer starts operating. Also,
the count source cannot be checked externally.
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read. The fol-
lowing cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an exter-
nal clock and it is to output the SRDY signal, set the transmit enable
bit, the receive enable bit, and the SRDY output enable bit to “1.”
Serial I/O continues to output the final bit from the TXD pin after trans-
mission is completed.
A/D Converter
The comparator is constructed linked to a capacitor. The conversion
accuracy may be low because the change is lost if the conversion
speed is not enough.
Accordingly, set f(XIN) to at least 500 kHz during A/D conversion in
the middle- or high- speed mode.
Also, do not execute the STP and WIT instructions during the A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by the
built-in self-oscillation circuit, the minimum value of f(XIN) frequency.
Instruction Execution Time
The instruction execution time is obtained by multiplying the number
of cycles shown in the list of machine instructions by the period of the
internal clock φ.
Rev.2.00 Nov 23, 2005 page 63 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
NOTES ON USE
VL3 pin
When LCD drive control circuit is not used, connect VL3 to VCC.
Countermeasures against noise
The following countermeasures are effective against noise in theory,
however, it is necessary not only to take masures as follows but to
evaluate before actual use.
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring (within
20 mm).
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
Fig. 63 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1
µ
F bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at
equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line
and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS
pin and the VCC pin.
Fig. 62 Wiring for the RESET pin
➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat-
terns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
Fig. 64 Bypass capacitor across the VSS line and the VCC line
RESET
Reset
circuit
Noise
V
SS
V
SS
Reset
circuit
V
SS
RESET
V
SS
N.G.
O.K.
Noise
X
IN
X
OUT
V
SS
X
IN
X
OUT
V
SS
N.G. O.K.
V
SS
V
CC
AA
AA
AA
AA
AA
AA
V
SS
V
CC
AA
AA
AA
AA
AA
AA
AA
AA
AA
N.G. O.K.
Rev.2.00 Nov 23, 2005 page 64 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
(3) Oscillator concerns
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select the
osillator and oscillation circuit constants. Be careful especially when
range of voltage and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as pos-
sible from signal lines where a current larger than the tolerance of
current value flows.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise occurs
because of mutual inductance.
➁ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also,
do not cross such signal lines over the clock lines or the signal
lines which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock wave-
forms may be deformed, which causes a microcomputer failure or
a program runaway.
➀ Keeping oscillator away from large current signal lines
➁ Installing oscillator away from signal lines where potential levels
change frequently
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in one
group, actual values such as an electrical characteristics, A/D con-
version accuracy, and the amount of -proof of noise incorrect opera-
tion may differ from the ideal values.
When these products are used switching, perform system evalua-
tion for each product of every after confirming product specification.
(6) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin at the shortest
possible in series and also to the VSS pin.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcomputer
operates correctly.
● Reason
The VPP pin of the One Time PROM version is the power source
input pin for the built-in PROM. When programming in the built-in
PROM, the impedance of the VPP pin is low to allow the electric
current for writing flow into the built-in PROM. Because of this,
noise can enter easily. If noise enters the VPP pin, abnormal in-
struction codes or data are read from the built-in PROM, which
may cause a program runaway.
Fig. 66 Wiring for the VPP pin of One Time PROM
Electric Characteristic Differences Between
Mask ROM and One T ime PROM V ersion MCUs
There are differences in electric characteristics, operation margin, noise
immunity, and noise radiation between the mask ROM and One Time
PROM version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the One Time PROM ver-
sion and then switching to use of the mask ROM version, please perform
sufficient evaluations for the commercial samples of the Mask ROM version.
Oscillation Circuit Constant
(1) Determine an oscillation circuit constant after consulting the oscil-
lator manufacturer about the matching characteristic evaluation.
(2) Since oscillation circuit constants may be differences between
the One Time PROM version and the mask ROM version, evalu-
ate them, respectively.
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when the
power source voltage drops or the power supply is turned off, reset a
microcomputer when the power source voltage is less than the rec-
ommended operating conditions and design a system not to cause
errors to the system by this unstable operation.
Fig. 65 Wiring for a large current signal line/Writing of signal
lines where potential levels change frequently
X
IN
X
OUT
V
SS
Microcomputer
Mutual inductance
Large
current
GND
X
IN
X
OUT
V
SS
CNTR
Do not cross
N.
G.
M
P
4
0
/
(
V
P
P
)
V
SS
T
h
e
s
h
o
r
t
e
s
t
T
h
e
s
h
o
r
t
e
s
t
Approx. 5kΩ
(
N
o
t
e
)
(N
ote
)
N
o
t
e
.
S
h
o
w
s
t
h
e
m
i
c
r
o
c
o
m
p
u
t
e
r
'
s
p
i
n
.
(4) Analog input
The analog input pin is connected to the capacitor of a voltage com-
parator. Accordingly, sufficient accuracy may not be obtained by the
charge/discharge current at the time of A/D conversion when the ana-
log signal source of high-impedance is connected to an analog input
pin. In order to obtain the A/D covnversion result stabilized more,
please lower the impedance of an analog signal source, or add the
smoothing capacitor to an analog input pin.
Rev.2.00 Nov 23, 2005 page 65 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 12 Absolute maximum ratings
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P70–P74
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
Output voltage P00–P07, P10–P17, P20–P27, P30–P37
Output voltage P40–P47, P50–P57, P60–P67, P72–P74
Output voltage VL3
Output voltage VL2, SEG32–SEG35
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
VO
VO
Pd
Topr
Tstg
Conditions
All voltages are based on Vss.
When an input voltage is measured,
output transistors are cut off.
At output port
At segment output
Ta = 25°C
Ratings
–0.3 to 4.0
–0.3 to VCC+0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to 6.5
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC+0.3
–0.3 to 6.5
–0.3 to VL3
–0.3 to VCC + 0.3
300
–20 to 85
–40 to 125
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
Rev.2.00 Nov 23, 2005 page 66 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Recommended Operating Conditions
Table 13 Recommended operating conditions
(Vcc = 1.8 to 3.6 V, Ta = –20 to 85°C, unless otherwise noted)
Power source voltage High-speed mode f(XIN) = 6 MHz
(Note 1) f(XIN) = 4 MHz
Middle-speed mode f(XIN) = 12.5 MHz
f(XIN) = 8 MHz
f(XIN) = 6 MHz
Low-speed mode
Oscillation start voltage (Note 2)
Power source voltage
VL1 input voltage Voltage multiplier is used
A/D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P00–P07, P10–P17, P24–P27, P30–P37,
P41, P43, P50–P57, P60(CM4=0), P61, P65,
P72–P74
“H” input voltage P20–P23, P40, P42, P44–P47, P62–P64,
P66–P67, P70, P71
“H” input voltage RESET
“H” input voltage XIN
“L” input voltage P00–P07, P10–P17, P24–P27, P30–P37,
P41, P43, P50–P57, P60(CM4=0), P61, P65,
P72–P74
“L” input voltage P20–P23, P40, P42, P44–P47, P62–P64,
P66–P67, P70, P71
“L” input voltage RESET
“L” input voltage XIN
VCC
VSS
VLI
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Parameter Min.
3.0
2.0
3.0
2.0
1.8
1.8
0.15 ✕ f + 1.3
1.3
2.0
AVSS
0.7VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
Typ.
3.3
3.3
3.3
3.3
3.3
3.3
0
1.8
0
Max.
3.6
3.6
3.6
3.6
3.6
3.6
2.1
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.2VCC
0.2VCC
Symbol Unit
Notes 1: When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.
2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc.
When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions.
f: Oscillation frequency (MHz) of oscillator. When the 8 MHz oscillation is used, assign “8” to “f”.
Rev.2.00 Nov 23, 2005 page 67 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P72–P74
“H” total peak output current (Note 1)
P40–P47, P50–P57, P60–P67
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P72–P74
“L” total peak output current (Note 1)
P40–P47, P50–P57, P60, P61
“L” total peak output current (Note 1)
P62–P67
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P72–P74
“H” total average output current (Note 1)
P40–P47, P50–P57, P60–P67
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P72–P74
“L” total average output current (Note 1)
P40–P47, P50–P57, P60, P61
“L” total average output current (Note 1)
P62–P67
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37
“H” peak output current (Note 2)
P40–P47, P50–P57, P60–P67, P72–P74
“L” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37
“L” peak output current (Note 2)
P40–P47, P50–P57, P60, P61, P72–P74
“L” peak output current (Note 2)
P62–P67
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37
“H” average output current (Note 3)
P40–P47, P50–P57, P60–P67, P72–P74
“L” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37
“L” average output current (Note 3)
P40–P47, P50–P57, P60, P61, P72–P74
“L” average output current (Note 3)
P62–P67
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
Limits
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter Min. Typ. Max.
Symbol Unit
–40
–40
40
40
110
–20
–20
20
20
90
–2
–5
5.0
10
30
–1.0
–2.5
2.5
5.0
15
Table 14 Recommended operating conditions (Mask ROM version)
(Vcc = 1.8 to 3.6 V, Ta = –20 to 85°C, unless otherwise noted)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
Rev.2.00 Nov 23, 2005 page 68 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Table 15 Recommended operating conditions
(Vcc = 1.8 to 3.6 V, Ta = –20 to 85°C, unless otherwise noted)
Timer X and Timer Y
Input frequency (duty cycle 50%)
Main clock input frequency
(duty cycle 50%) (Note 1)
Sub-clock oscillation frequency
(duty cycle 50%) (Notes 2, 4)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Limits
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Parameter Min. Typ.
32.768
Max.
VCC
5✕VCC–8
12.5
12.5
8.0
6.0
80
Symbol Unit
(2.0 V ≤ VCC < 3.6 V)
(VCC < 2.0 V)
High-speed mode
(2.0 V < VCC ≤ 3.6 V)
Middle-speed mode (Notes 3, 4)
(3.0 V ≤ VCC ≤ 3.6 V)
Middle-speed mode (Notes 3, 4)
(2.0 V ≤ VCC ≤ 3.6 V)
Middle-speed mode (Notes 3, 4)
Notes 1: When the A/D converter is used, refer to the recommended operationg conditions of the A/D converter.
2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3: When the timer X dividing frequency selection bit and timer Y dividing frequency selection bit are “01(1/1 ✕ φSOURCE)” or “10(1/2 ✕ φSOURCE)”, the limits
at the high-speed mode are suitable for the recommended operating condition of main clock input frequency f(XIN).
4: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply
voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions.
Rev.2.00 Nov 23, 2005 page 69 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
IOH = –0.6 mA
VCC = 2.5 V
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
IOL = 3.0 mA
VCC = 2.5 V
VCC = 2.0 - 3.6 V on RESET
VI = VCC
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-up “OFF”
VCC = 3.0 V, VI = VSS
Pull-up “ON”
VI = VSS
Pull-up “OFF”
VCC = 3.0 V, VI = VSS
Pull-up “ON”
VI = VSS
VI = VSS
VCC = 3.3 V, Ta = 25 °C
“H” output voltage
P00–P07, P10–P17, P20–P27, P30–P37
“H” output voltage
P40–P47, P50–P57, P60–P67, P72–P74 (Note)
“L” output voltage
P00–P07, P10–P17, P20–P27, P30–P37
“L” output voltage
P40–P47, P50–P57, P60, P61, P72–P74 (Note)
“L” output voltage
P62–P67
Hysteresis
INT00, INT01, INT10, INT11, INT2, CNTR0, CNTR1,
KW0–KW7
Hysteresis SIN2, SCLK1, SCLK2, RxD
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P30–P37
“H” input current
P40–P47, P50–P57, P60–P67, P70–P74
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27, P30–P37
“L” input current
P40–P47, P50–P57, P60–P67, P72–P74
“L” input current RESET
“L” input current XIN
On-chip oscillator frequency
Limits
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
kHz
Parameter Min.
VCC–1.0
VCC–0.5
VCC–1.0
–25
–6.5
1300
Typ.
0.3
0.3
0.3
4.0
–50
–25
–4.0
2700
Max.
0.5
1.0
0.5
1.0
0.8
5.0
5.0
5.0
–5.0
–100
–5.0
–45
–5.0
4000
Symbol UnitTest conditions
VOH
VOH
VOL
VOL
VOL
VT+–VT-
VT+–VT-
VT+–VT-
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
ROSC
Electrical Characteristics
Table 16 Electrical characteristics
(Vcc = 3.0 to 3.6 V, Ta = –20 to 85°C, unless otherwise noted)
Note: When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is “1”, the drivability of P61 is different from the above.
Rev.2.00 Nov 23, 2005 page 70 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
RAM hold voltage
Power source
current
Limits
Parameter Min.
1.8 Typ.
0.6
0.3
0.4
0.5
0.3
0.3
7.0
3.5
35
25
0.1
0.4
0.1
0.1
Max.
3.6
1.2
0.6
0.8
1.0
0.6
0.6
14
7.0
90
75
1.0
10
Symbol Unit
When clock is stopped
High-speed mode Vcc = 2.5 V f(XIN) = 4 MHz
f(XIN) = 4 MHz (in WIT state)
f(XIN) = 2 MHz
Middle-speed mode Vcc = 2.5 V f(XIN) = 8 MHz
f(XIN) = 8 MHz (in WIT state)
f(XIN) = 4 MHz
Low-speed mode Vcc = 2.5 V f(XIN) = stop
in WIT state
On-chip oscillator mode VCC = 2.5 V
f(XIN) and, f(XCIN) = stopped VCC = 2.5 V (in WIT state)
All oscillations stopped Ta = 25 °C
(in STP state) Ta = 85 °C
Current increased f(XIN) = 6 MHz, VCC = 3.3 V
at A/D converter operating in middle- or high-speed mode
f(XIN) = stop, VCC = 3.3 V
in on-chip oscillator operating
f(XIN) = stop, VCC = 3.3 V
in low-speed mode
Test conditions
VRAM
ICC
V
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
mA
mA
mA
Table 17 Electrical characteristics
(Vcc = 1.8 to 3.6 V, Ta = –20 to 85°C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, AD converter stopped, unless otherwise noted)
Rev.2.00 Nov 23, 2005 page 71 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
A/D Converter Characteristics
Table 18 A/D converter recommended operating condition
(Vcc = 2.0 to 3.6 V, Ta = –20 to 85°C, output transistors in cut-off state, unless otherwise noted)
Power source voltage
“H” input voltage ADKEY0
“L” input voltage ADKEY0
AD converter control clock
(Note)
(Low-speed • on-chip oscillator
mode excluded)
Unit
V
V
V
MHz
MHz
MHz
Limits
Parameter Min.
2.0
0.9Vcc
0
Typ. Max.
3.6
Vcc
0.7 ✕ V
CC
–0.5
20 ✕ Vcc–38
45 ✕ Vcc–35
8
12.5
Symbol
VCC ≤ 2.2 V
2.2 V < VCC ≤ 3.0 V
3.0 V < VCC ≤ 3.6 V
Test conditions
Note: Confirm the recommended opearting condition for main clock input frequency.
Table 19 A/D converter characteristics
(Vcc = 2.0 to 3.6 V, Ta = –20 to 85°C, output transistors in cut-off state, low-speed • on-chip oscillator mode included, unless otherwise noted)
VCC
VIH
VIL
f(XIN)
Resolution
Absolute accuracy
(quantification error excluded)
Unit
Bits
LSB
µs
kΩ
µA
µA
Limits
Parameter Min.
12
30
Typ.
35
100
Max.
10
4
4
2
2
tc(φAD)✕121
(Note)
100
130
5.0
Symbol
2.5 < VCC ≤ 3.6, f(XIN) ≤ 6 MHz
AD conversion clock = φSOURCE/2
10bitAD mode
2.2 < VCC ≤ 2.5, f(XIN) ≤ 12.5 MHz
or Low-speed mode • on-chip oscillator mode
AD conversion clock = φSOURCE/2
10bitAD mode
3.0 < VCC ≤ 3.6, f(XIN) ≤ 12.5 MHz
AD conversion clock = φSOURCE/8
8bitAD mode
2.2 < VCC ≤ 3.0, f(XIN) ≤ 8 MHz
AD conversion clock = φSOURCE/8
8bitAD mode
2.0 < VCC ≤ 2.2, f(XIN) ≤ 6 MHz
AD conversion clock = φSOURCE/8
or Low-speed mode • on-chip oscillator mode
AD conversion clock = φSOURCE/2
8bitAD mode
AD conversion clock = φSOURCE/2
10bitAD mode
VREF = 3.3 V
Test conditions
—
ABS Resolution
Absolute accuracy
(quantification error excluded)
Conversion time
Ladder resistor
Reference input current
Analog input current
—
ABS
Tconv
RLADDER
IVREF
IIA
Note: When “φSOURCE/8” is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 4.
The operation clock is XIN in the middle- or high-speed mode, or the on-chip oscillator in the other modes.
When the A/D conversion is executed in the middle- or high-speed mode, set f(XIN) ≤ 500 kHz.
tc(φAD): One cycle of control clock for A/D converter. XIN input is used in the middel- or high-speed mode, and on-chip oscillator is used in the low- or on-chip
oscillator mode for the control clock.
Rev.2.00 Nov 23, 2005 page 72 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT00, INT01, INT10, INT11, INT2 input “H” pulse width
INT00, INT01, INT10, INT11, INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(RxD-SCLK2)
th(SCLK2-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
125
166
50
70
50
70
1000/Vcc
1000/(5✕Vcc-8)
tc(CNTR)/2-20
tc(CNTR)/2-20
230
230
2000
950
950
400
200
2000
950
950
400
200
Typ. Max.
Symbol Unit
Timing Requirements And Switching Characteristics
Table 20 Timing requirements
(Vcc = 1.8 to 3.6 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
(2.0 V < VCC ≤ 3.6 V)
(VCC ≤ 2.0 V)
(2.0 V < VCC ≤ 3.6 V)
(VCC ≤ 2.0 V)
(2.0 V < VCC ≤ 3.6 V)
(VCC ≤ 2.0 V)
(2.0 V < VCC ≤ 3.6 V)
(VCC ≤ 2.0 V)
Rev.2.00 Nov 23, 2005 page 73 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
twH(SCLK1)
twL(SCLK1)
td(SCLK1-TxD)
tV(SCLK1-TxD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
tf(SCLK2)
td(SCLK2-SOUT2)
tV(SCLK2-SOUT2)
Limits
Parameter Min.
tc(SCLK1)/2–80
tc(SCLK1)/2–80
–30
tc(SCLK1)/2–80
tc(SCLK1)/2–80
–30
Typ. Max.
350
80
80
80
350
Symbol Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is “0.”
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note)
Serial I/O1 output valid time (Note)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 clock output falling time
Serial I/O2 output delay time
Serial I/O2 output valid time
Table 21 Switching characteristics
(Vcc = 1.8 to 3.6 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Fig. 67 Circuit for measuring output switching characteristics
100pF
1kΩ
Measurement output pin
CMOS output
Measurement output pin
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B
16) is “ 1.”
(N-channel open-drain output mode)
100pF
Rev.2.00 Nov 23, 2005 page 74 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
Fig. 68 Timing chart
INT00,INT01
INT10,INT11
INT2
CNTR
0
, CNTR
1
0.2VCC
tWL(INT)
0.8VCC
tWH(INT)
0.2VCC
0.2VCC
0.8VCC
0.8VCC
0.2VCC
tWL(X
IN
)
0.8VCC
tWH(X
IN)
tC(X
IN
)
XIN
0.2VCC 0.8VCC
tW(RESET)
RESET
tftr
0.2VCC
tWL(CNTR)
0.8VCC
tWH(CNTR)
tC(CNTR)
td(S
CLK1
-T
X
D),td(S
CLK2-
S
OUT2
)tv(S
CLK1
-T
X
D),
tv(S
CLK2-
S
OUT2
)
tC(S
CLK1
), tC(S
CLK2
)
tWL(S
CLK1
), tWL(S
CLK2
)tWH(S
CLK1
), tWH(S
CLK2
)
th(S
CLK1-
R
X
D),
t
h
(S
CLK2-
S
IN
2)
tsu(R
X
D
-
S
CLK1
),
tsu(S
IN2-
S
CLK2
)
TXD
SOUT2
RXD
SIN2
SCLK1
SCLK2
Rev.2.00 Nov 23, 2005 page 75 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
PACKAGE OUTLINE
Terminal cross section
b
1
c
1
bp
c
F
80
65
64 41
40
25
24
1
*1
*2
*3
x
Index mark
y
b
p
e
H
E
E
H
D
D
Z
D
Z
E
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
Detail F
L
A
2
A
1
L
1
A
c
Previous CodeJEITA Package Code RENESAS Code
PLQP0080GA-A 80P6U-A
MASS[Typ.]
1.0gP-LQFP80-14x20-0.80
1.0
0.125
0.35
0.8
1.0
0.20
0.200.1450.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
20.120.019.9
D
14.114.013.9
E
1.4
A
2
22.222.021.8
16.216.015.8
1.7
A
0.20.1250.05
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Detail F
c
A
L
1
L
A
1
A
2
Index mark
y
*2
*1
*3
F
80
61
60 41
40
21
20
1
x
Z
E
Z
D
E
H
E
D
H
D
eb
p
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Previous CodeJEITA Package Code RENESAS Code
PLQP0080KB-A 80P6Q-A
MASS[Typ.]
0.5gP-LQFP80-12x12-0.50
1.0
0.125
0.18
1.25
1.25
0.08
0.200.1450.09
0.250.200.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
12.112.011.9
D
12.112.011.9
E
1.4
A
2
14.214.013.8
14.214.013.8
1.7
A
0.20.1
0
0.70.50.3
L
x
10°0°
c
0.5
e
0.08
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
c
bp
c
1
b
1
REVISION HISTORY
Rev. Date Description
Page Summary
38C5 Group Data Sheet
1.00
Mar. 31, 2004
1.10 Jun.14.2004
First edition issued
Words standardized: On-chip oscillator, A/D converter
–
All pages
2.00
Nov. 23, 2005
2, 3, 7, 8 Package name revised.
14 Fig.11: Memory map of special function register (SFR) Note added.
44 Table 9: Maximum number of display pixels at each duty ratio revised.
46 Voltage Multiplier revised.
Table 10: Bias control and applied voltage to VL
1
-VL
3
revised.
Fig.42: Example of circuit at each bias revised.
50 Standard Operation of Watchdog Timer revied.
Bit 6 of Watchdog Timer Control Register revised.
Fig.47: Structure of Watchdog timer control register revised.
55
Fig.54: Ceramic resonator circuit example revised.
58, 59 Package name revised.
64 Fig.66: Wiring for the V
PP
pin of One Time PROM revised.
Power Source Voltage added.
65 Table 12: absolute maximum ratings revised.
75 PACKAGE OUTLINE revised.
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