This is information on a product in full production.
January 2017 DocID025832 Rev 5 1/117
STM32F042x4 STM32F042x6
ARM®-based 32-bit MCU, up to 32 KB Flash, crystal-less USB
FS 2.0, CAN, 9 timers, ADC and comm. interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
•Core: ARM® 32-bit Cortex®-M0 CPU,
frequency up to 48 MHz
•Memories
– 16 to 32 Kbytes of Flash memory
– 6 Kbytes of SRAM with HW parity
•CRC calculation unit
•Reset and power management
– Digital and I/Os supply: VDD = 2 V to 3.6 V
– Analog supply: VDDA = from VDD to 3.6 V
– Selected I/Os: VDDIO2 = 1.65 V to 3.6 V
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
–V
BAT supply for RTC and backup registers
•Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
– Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
•Up to 38 fast I/Os
– All mappable on external interrupt vectors
– Up to 24 I/Os with 5 V tolerant capability
and 8 with independent supply VDDIO2
•5-channel DMA controller
•One 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6 V
– Separate analog supply: 2.4 V to 3.6 V
•Up to 14 capacitive sensing channels for
touchkey, linear and rotary touch sensors
•Calendar RTC with alarm and periodic wakeup
from Stop/Standby
•Nine timers
– One 16-bit advanced-control timer for six
channel PWM output
– One 32-bit and four 16-bit timers, with up to
four IC/OC, OCN, usable for IR control
decoding
– Independent and system watchdog timers
– SysTick timer
•Communication interfaces
–One I
2C interface supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus and wakeup
– Two USARTs supporting master
synchronous SPI and modem control, one
with ISO7816 interface, LIN, IrDA, auto
baud rate detection and wakeup feature
– Two SPIs (18 Mbit/s) with 4 to 16
programmable bit frames, one with I2S
interface multiplexed
– CAN interface
– USB 2.0 full-speed interface, able to run
from internal 48 MHz oscillator and with
BCD and LPM support
•HDMI CEC, wakeup on header reception
•Serial wire debug (SWD)
•96-bit unique ID
•All packages ECOPACK®2
Table 1. Device summary
Reference Part number
STM32F042x4 STM32F042F4, STM32F042G4,
STM32F042K4, STM32F042T4, STM32F042C4
STM32F042x6 STM32F042F6, STM32F042G6,
STM32F042K6, STM32F042T6, STM32F042C6
LQFP48 7x7 mm
UFQFPN48 7x7 mm WLCSP36
UFQFPN32 5x5 mm
UFQFPN28 4x4 mm
TSSOP20
LQFP32 7x7 mm
2.6x2.7 mm 6.5x4.4 mm
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Contents STM32F042x4 STM32F042x6
2/117 DocID025832 Rev 5
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12.2 General-purpose timers (TIM2, 3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . 22
3.12.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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STM32F042x4 STM32F042x6 Contents
4
3.15 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25
3.16 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26
3.17 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 47
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 48
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Contents STM32F042x4 STM32F042x6
4/117 DocID025832 Rev 5
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.18 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.3 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.5 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.6 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.7 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 111
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
DocID025832 Rev 5 5/117
STM32F042x4 STM32F042x6 List of tables
6
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F042x4/x6 device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Capacitive sensing GPIOs available on STM32F042x4/x6 devices . . . . . . . . . . . . . . . . . . 20
Table 6. No. of capacitive sensing channels available on STM32F042x devices. . . . . . . . . . . . . . . 21
Table 7. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. STM32F042x4/x6 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. STM32F042x4/x6 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. STM32F042x4/x6 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. STM32F042x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 37
Table 15. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 38
Table 16. Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 38
Table 17. STM32F042x4/x6 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 24. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 50
Table 27. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 52
Table 28. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 53
Table 29. Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 54
Table 30. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 34. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 36. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 38. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 39. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 40. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 41. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 42. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 43. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 44. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 45. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 46. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 47. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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Table 48. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 49. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 50. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 51. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 52. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 53. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 55. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 56. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 57. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 58. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 59. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 60. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 61. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 62. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 64. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 65. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 66. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 67. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 68. WLCSP36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 69. WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 70. LQFP32 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 71. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 72. UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 73. TSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 74. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 75. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 76. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
DocID025832 Rev 5 7/117
STM32F042x4 STM32F042x6 List of figures
8
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. WLCSP36 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6. LQFP32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. UFQFPN32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. TSSOP20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. STM32F042x6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 65
Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 31. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 32. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 33. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 34. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 35. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 37. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 38. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 39. WLCSP36 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 40. Recommended pad footprint for WLCSP36 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 41. WLCSP36 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 42. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 43. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 44. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 45. UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 46. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 47. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 48. UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
List of figures STM32F042x4 STM32F042x6
8/117 DocID025832 Rev 5
Figure 49. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 50. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 51. TSSOP20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 52. Recommended footprint for TSSOP20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 53. TSSOP20 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DocID025832 Rev 5 9/117
STM32F042x4 STM32F042x6 Introduction
27
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F042x4/x6 microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
Description STM32F042x4 STM32F042x6
10/117 DocID025832 Rev 5
2 Description
The STM32F042x4/x6 microcontrollers incorporate the high-performance
ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed
embedded memories (up to 32 Kbytes of Flash memory and 6 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. All devices offer standard
communication interfaces (one I2C, two SPIs/one I2S, one HDMI CEC and two USARTs),
one USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, four 16-bit timers, one
32-bit timer and an advanced-control PWM timer.
The STM32F042x4/x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F042x4/x6 microcontrollers include devices in seven different packages ranging
from 20 pins to 48 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F042x4/x6 microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
DocID025832 Rev 5 11/117
STM32F042x4 STM32F0 42x6 Description
27
Table 2. STM32F042x4/x6 device features and peripheral counts
Peripheral STM32F042Fx STM32F042G STM32F042K STM32F042T STM32F042C
Flash memory (Kbyte) 16 32 16 32 16 32 16 32 16 32
SRAM (Kbyte) 6
Timers
Advanced
control 1 (16-bit)
General
purpose
4 (16-bit)
1 (32-bit)
Comm.
interfaces
SPI [I2S](1) 1 [1] 2 [1]
I2C1
USART 2
CAN 1
USB 1
CEC 1
12-bit ADC
(number of channels)
1
(9 ext. + 3 int.)
1
(10 ext. + 3 int.)
GPIOs 16 24 26
28 30 38
Capacitive sensing
channels 711
13
14 14 14
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
Packages TSSOP20 UQFPN28 LQFP32
UQFPN32 WLCSP36 LQFP48
UFQFPN48
1. The SPI interfaces can be used either in SPI mode or in I2S audio mode.
Description STM32F042x4 STM32F042x6
12/117 DocID025832 Rev 5
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DocID025832 Rev 5 13/117
STM32F042x4 STM32F0 42x6 Functional overview
27
3 Functional overview
Figure 1 shows the general block diagram of the STM32F042x4/x6 devices.
3.1 ARM®-Cortex®-M0 core
The ARM® Cortex®-M0 is a generation of ARM 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an ARM core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F042x4/x6 devices embed ARM core and are compatible with all ARM tools and
software.
3.2 Memories
The device has the following features:
•6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
•The non-volatile memory is divided into two arrays:
– 16 to 32 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and
boot in RAM selection disabled
3.3 Boot modes
At startup, the boot pin and boot selector option bits are used to select one of the three boot
options:
•boot from User Flash memory
•boot from System Memory
•boot from embedded SRAM
The boot pin is shared with the standard GPIO and can be disabled through the boot
selector option bits. The boot loader is located in System Memory. It is used to reprogram
the Flash memory by using USART on pins PA14/PA15, or PA9/PA10 or I2C on pins
PB6/PB7 or through the USB DFU interface.
Functional overview STM32F042x4 STM32F042x6
14/117 DocID025832 Rev 5
3.4 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes
•VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
•VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). It is
provided externally through VDDA pin. The VDDA voltage level must be always greater
or equal to the VDD voltage level and must be established first.
•VDDIO2 = 1.65 to 3.6 V: external power supply for marked I/Os. VDDIO2 is provided
externally through the VDDIO2 pin. The VDDIO2 voltage level is completely independent
from VDD or VDDA, but it must not be provided without a valid supply on VDD. The
VDDIO2 supply is monitored and compared with the internal reference voltage
(VREFINT). When the VDDIO2 is below this threshold, all the I/Os supplied from this rail
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
3.5.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
•The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
DocID025832 Rev 5 15/117
STM32F042x4 STM32F0 42x6 Functional overview
27
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3 Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
•Main (MR) is used in normal operating mode (Run).
•Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4 Low-power modes
The STM32F042x4/x6 microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1 USART1, USB
or the CEC.
The CEC, USART1 and I2C1 peripherals can be configured to enable the HSI RC
oscillator so as to get clock for processing incoming data. If this is used when the
voltage regulator is put in low power mode, the regulator is first switched to normal
mode before the clock is provided to the given peripheral.
•Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note: The RTC, the IWDG, and the corre sponding clock so urces are not stoppe d by entering S top
or Standby mode.
Functional overview STM32F042x4 STM32F042x6
16/117 DocID025832 Rev 5
3.6 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
DocID025832 Rev 5 17/117
STM32F042x4 STM32F0 42x6 Functional overview
27
Figure 2. Clock tree
3.7 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
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18/117 DocID025832 Rev 5
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14) and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4
priority levels.
•Closely coupled NVIC gives low latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Closely coupled NVIC core interface
•Allows early processing of interrupts
•Processing of late arriving higher priority interrupts
•Support for tail-chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 38
GPIOs can be connected to the 16 external interrupt lines.
3.10 Analog-to-digital converter (ADC)
The 12-bit analog-to-digital converter has up to 10 external and 3 internal (temperature
DocID025832 Rev 5 19/117
STM32F042x4 STM32F0 42x6 Functional overview
27
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.
Table 3. Temperature se n so r calib rat io n val ue s
Calibration value name Description Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
0x1FFF F7C2 - 0x1FFF F7C3
Table 4. Internal voltage reference calibration values
Calibration value name Description Memory address
VREFINT_CAL
Raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
0x1FFF F7BA - 0x1FFF F7BB
Functional overview STM32F042x4 STM32F042x6
20/117 DocID025832 Rev 5
3.10.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.11 Touch sensing controller (TSC)
The STM32F042x4/x6 devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 14 capacitive sensing channels
distributed over 5 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists in
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F042x4/x6 devices
Group Capacitive sensing
signal name Pin
name Group Capacitive sensing
signal name Pin
name
1
TSC_G1_IO1 PA0
4
TSC_G4_IO1 PA9
TSC_G1_IO2 PA1 TSC_G4_IO2 PA10
TSC_G1_IO3 PA2 TSC_G4_IO3 PA11
TSC_G1_IO4 PA3 TSC_G4_IO4 PA12
2
TSC_G2_IO1 PA4
5
TSC_G5_IO1 PB3
TSC_G2_IO2 PA5 TSC_G5_IO2 PB4
TSC_G2_IO3 PA6 TSC_G5_IO3 PB6
TSC_G2_IO4 PA7 TSC_G5_IO4 PB7
3
TSC_G3_IO2 PB0
TSC_G3_IO3 PB1
TSC_G3_IO4 PB2
DocID025832 Rev 5 21/117
STM32F042x4 STM32F0 42x6 Functional overview
27
3.12 Timers and watchdogs
The STM32F042x4/x6 devices include up to five general-purpose timers and an advanced
control timer.
Table 7 compares the features of the different timers.
3.12.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
Table 6. No. of capacitive sensing channels available on STM32F042x devices
Analog I/O group
Number of capacitive sensing channels
STM32F042Cx
LQPF48
UQFPN48
STM32F042Tx
WLCSP36
STM32F042Kx
LQFP32
UQFPN32
STM32F042Gx
UQFPN28 STM32F042Fx
TSSOP20
G1 33333
G2 33333
G3 2 2 1
210
G4 33311
G5 33330
Number of capacitive
sensing channels 14 14 13
14 11 7
Table 7. Timer feature comparison
Timer
type Timer Counter
resolution Counter
type Prescaler
factor
DMA
request
generation
Capture/compare
channels Complementary
outputs
Advanced
control TIM1 16-bit Up, down,
up/down
integer from
1 to 65536 Yes 4 3
General
purpose
TIM2 32-bit Up, down,
up/down
integer from
1 to 65536 Yes 4 -
TIM3 16-bit Up, down,
up/down
integer from
1 to 65536 Yes 4 -
TIM14 16-bit Up integer from
1 to 65536 No 1 -
TIM16
TIM17 16-bit Up integer from
1 to 65536 Yes 1 1
Functional overview STM32F042x4 STM32F042x6
22/117 DocID025832 Rev 5
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
•input capture
•output compare
•PWM generation (edge or center-aligned modes)
•one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.12.2 General-purpose timers (TIM2, 3, 14, 16, 17)
There are five synchronizable general-purpose timers embedded in the STM32F042x4/x6
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F042x4/x6 devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
They each have a single channel for input capture/output compare, PWM or one-pulse
mode output.
DocID025832 Rev 5 23/117
STM32F042x4 STM32F0 42x6 Functional overview
27
TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.12.3 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.12.4 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.12.5 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•a 24-bit down counter
•autoreload capability
•maskable system interrupt generation when the counter reaches 0
•programmable clock source (HCLK or HCLK/8)
3.13 Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or at wake up from Standby mode.
Functional overview STM32F042x4 STM32F042x6
24/117 DocID025832 Rev 5
The RTC is an independent BCD timer/counter. Its main features are the following:
•calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•automatic correction for 28, 29 (leap year), 30, and 31 day of the month
•programmable alarm with wake up from Stop and Standby mode capability
•on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
•digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
•two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
•timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
•reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
•a 32.768 kHz external crystal
•a resonator or oscillator
•the internal low-power RC oscillator (typical frequency of 40 kHz)
•the high-speed external clock divided by 32
3.14 Inter-integrated circuit interface (I2C)
The I2C interface (I2C1) can operate in multimaster or slave modes. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). It also includes programmable analog and digital
noise filters.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
Table 8. Comparison of I2C analog and digital filters
Aspect Analog filter Digital filter
Pulse width of
suppressed spikes ≥ 50 ns Programmable length from 1 to 15
I2Cx peripheral clocks
Benefits Available in Stop mode
–Extra filtering capability vs.
standard requirements
–Stable length
Drawbacks Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
DocID025832 Rev 5 25/117
STM32F042x4 STM32F0 42x6 Functional overview
27
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripheral can be served by the DMA controller.
3.15 Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds two universal synchronous/asynchronous receivers/transmitters
(USART1, USART2) which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 supports also SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a
clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 9. STM32F042x4/x6 I2C implementation
I2C features(1)
1. X = supported.
I2C1
7-bit addressing mode X
10-bit addressing mode X
Standard mode (up to 100 kbit/s) X
Fast mode (up to 400 kbit/s) X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X
Independent clock X
SMBus X
Wakeup from STOP X
Table 10. STM32F042x4/x6 USART implementation
USART modes/features(1) USART1 USART2
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wakeup from Stop mode X -
Receiver timeout interrupt X -
Functional overview STM32F042x4 STM32F042x6
26/117 DocID025832 Rev 5
3.16 Serial peripheral interface (SPI) / Inter-integrated sound
interface (I2S)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit
programmable linear prescaler. When operating in master mode, it can output a clock for an
external audio component at 256 times the sampling frequency.
3.17 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.18 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
Modbus communication X -
Auto baud rate detection X -
Driver Enable X X
1. X = supported.
Table 10. STM32F042x4/x6 USART implementat ion (continued)
USART modes/features(1) USART1 USART2
Table 11. STM32F042x4/x6 SPI/I2S implementation
SPI features(1)
1. X = supported.
SPI1 SPI2
Hardware CRC calculation X X
Rx/Tx FIFO X X
NSS pulse mode X X
I2S mode X -
TI mode X X
DocID025832 Rev 5 27/117
STM32F042x4 STM32F0 42x6 Functional overview
27
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.19 Universal serial bus (USB)
The STM32F042x4/x6 embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.20 Clock recovery system (CRS)
The STM32F042x4/x6 embeds a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from USB SOF signalization, from LSE oscillator, from an
external signal on CRS_SYNC pin or generated by user software. For faster lock-in during
startup it is also possible to combine automatic trimming with manual trimming action.
3.21 Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
Pinouts and pin descriptions STM32F042x4 STM32F042x6
28/117 DocID025832 Rev 5
4 Pinouts and pin descriptions
Figure 3. LQFP48 package pinout
Figure 4. UFQFPN48 package pinout
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STM32F042x4 STM32F042x6 Pinouts and pin descriptions
38
Figure 5. WLCSP36 package pinout
1. The above figure shows the package in top view, changing from bottom view in the previous document
versions.
Figure 6. LQFP32 package pinout
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Pinouts and pin descriptions STM32F042x4 STM32F042x6
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Figure 7. UFQFPN32 package pinout
Figure 8. UFQFPN28 package
1. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using the SYSCFG_CFGR1 register.
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STM32F042x4 STM32F042x6 Pinouts and pin descriptions
38
Figure 9. TSSOP20 package
1. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using the SYSCFG_CFGR1 register.
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Table 12. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin type
S Supply pin
I/O Input / output pin
I/O structure
FT 5 V-tolerant I/O
FTf 5 V-tolerant I/O, FM+ capable
TTa 3.3 V-tolerant I/O directly connected to ADC
TC Standard 3.3 V I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Pinouts and pin descriptions STM32F042x4 STM32F042x6
32/117 DocID025832 Rev 5
Table 13. STM32F042x pin definitions
Pin numbers
Pin name
(function upon
reset)
Pin
type
I/O structure
Notes
Pin functions
LQFP48/UFQFPN48
WLCSP36
LQFP32
UFQFPN32
UFQFPN28
TSSPOP20
Alternate function Additional
functions
1 - - - - - VBAT S - - Backup power supply
2A6 - - - - PC13 I/OTC
(1)
(2) -
WKUP2,
RTC_TAMP1,
RTC_TS,
RTC_OUT
3B6 - - - -
PC14-
OSC32_IN
(PC14)
I/O TC
(1)
(2) - OSC32_IN
4C6 - - - -
PC15-
OSC32_OUT
(PC15)
I/O TC
(1)
(2) - OSC32_OUT
5B52 2 2 2 PF0-OSC_IN
(PF0) I/O FTf - CRS_ SYNC
I2C1_SDA OSC_IN
6C53 3 3 3 PF1-OSC_OUT
(PF1) I/O FTf - I2C1_SCL OSC_OUT
7 D5 4 4 4 4 NRST I/O RST - Device reset input / internal reset output
(active low)
8 D6 32 0 16 15 VSSA S (3) Analog ground
9E55 5 5 5 VDDA S- Analog power supply
10 F6 6 6 6 6 PA0 I/O TTa -
USART2_CTS,
TIM2_CH1_ETR,
TSC_G1_IO1
RTC_
TAMP2,
WKUP1,
ADC_IN0,
11 D4 7 7 7 7 PA1 I/O TTa -
USART2_RTS,
TIM2_CH2,
TSC_G1_IO2,
EVENTOUT
ADC_IN1
12 E4 8 8 8 8 PA2 I/O TTa -
USART2_TX,
TIM2_CH3,
TSC_G1_IO3
ADC_IN2,
WKUP4
13 F5 9 9 9 9 PA3 I/O TTa -
USART2_RX,
TIM2_CH4,
TSC_G1_IO4
ADC_IN3
DocID025832 Rev 5 33/117
STM32F042x4 STM32F042x6 Pinouts and pin descriptions
38
14 C3 10 10 10 10 PA4 I/O TTa -
SPI1_NSS, I2S1_WS,
TIM14_CH1,
TSC_G2_IO1,
USART2_CK
USB_NOE
ADC_IN4
15 D3 11 11 11 11 PA5 I/O TTa -
SPI1_SCK, I2S1_CK,
CEC,
TIM2_CH1_ETR,
TSC_G2_IO2
ADC_IN5
16 E3 12 12 12 12 PA6 I/O TTa -
SPI1_MISO, I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
TSC_G2_IO3,
EVENTOUT
ADC_IN6
17 F4 13 13 13 13 PA7 I/O TTa -
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
TSC_G2_IO4,
EVENTOUT
ADC_IN7
18 F3 14 14 14 - PB0 I/O TTa -
TIM3_CH3,
TIM1_CH2N,
TSC_G3_IO2,
EVENTOUT
ADC_IN8
19 F2 15 15 15 14 PB1 I/O TTa -
TIM3_CH4, TIM14_CH1,
TIM1_CH3N,
TSC_G3_IO3
ADC_IN9
20 D2 - 16 - - PB2 I/O FT - TSC_G3_IO4 -
21 - - - - - PB10 I/O FTf -
SPI2_SCK, CEC,
TSC_SYNC, TIM2_CH3,
I2C1_SCL
-
22 - - - - - PB11 I/O FTf -
TIM2_CH4,
EVENTOUT,
I2C1_SDA
-
23 F1 16 0 16 15 VSS S - - Ground
24 - - - 17 16 VDD S - - Digital power supply
25 - - - - - PB12 I/O FT - TIM1_BKIN, SPI2_NSS,
EVENTOUT -
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
I/O structure
Notes
Pin functions
LQFP48/UFQFPN48
WLCSP36
LQFP32
UFQFPN32
UFQFPN28
TSSPOP20
Alternate function Additional
functions
Pinouts and pin descriptions STM32F042x4 STM32F042x6
34/117 DocID025832 Rev 5
26 - - - - - PB13 I/O FTf -
SPI2_SCK,
TIM1_CH1N,
I2C1_SCL
-
27 - - - - - PB14 I/O FTf -
SPI2_MISO,
TIM1_CH2N,
I2C1_SDA
-
28 - - - - - PB15 I/O FT - SPI2_MOSI,
TIM1_CH3N
WKUP7,
RTC_REFIN
29 E2 18 18 - - PA8 I/O FT (4)
USART1_CK,
TIM1_CH1,
EVENTOUT, MCO,
CRS_SYNC
-
30 D1 19 19 19 17 PA9 I/O FTf (4)
USART1_TX,
TIM1_CH2,
TSC_G4_IO1,
I2C1_SCL
-
31 C1 20 20 20 18 PA10 I/O FTf (4)
USART1_RX,
TIM1_CH3,
TIM17_BKIN,
TSC_G4_IO2,
I2C1_SDA
-
32 C2 21 21 19(5) 17(5) PA11 I/O FTf (4)
CAN_RX,
USART1_CTS,
TIM1_CH4,
TSC_G4_IO3,
EVENTOUT,
I2C1_SCL
USB_DM
33 A1 22 22 20(5) 18(5) PA12 I/O FTf (4)
CAN_TX,USART1_RTS,
TIM1_ETR,
TSC_G4_IO4,
EVENTOUT,
I2C1_SDA
USB_DP
34 B1 23 23 21 19 PA13 I/O FT
(4)
(6)
IR_OUT, SWDIO
USB_NOE -
35 - - - - - VSS S - - Ground
36 E1 17 17 18 16 VDDIO2 S - - Digital power supply
37 B2 24 24 22 20 PA14 I/O FT
(4)
(6) USART2_TX, SWCLK -
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
I/O structure
Notes
Pin functions
LQFP48/UFQFPN48
WLCSP36
LQFP32
UFQFPN32
UFQFPN28
TSSPOP20
Alternate function Additional
functions
DocID025832 Rev 5 35/117
STM32F042x4 STM32F042x6 Pinouts and pin descriptions
38
38 A2 25 25 23 - PA15 I/O FT (4)
SPI1_NSS, I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
EVENTOUT,
USB_NOE
-
39 B3 26 26 24 - PB3 I/O FT -
SPI1_SCK, I2S1_CK,
TIM2_CH2,
TSC_G5_IO1,
EVENTOUT
-
40 A3 27 27 25 - PB4 I/O FT -
SPI1_MISO, I2S1_MCK,
TIM17_BKIN,
TIM3_CH1,
TSC_G5_IO2,
EVENTOUT
-
41 E6 28 28 26 - PB5 I/O FT -
SPI1_MOSI, I2S1_SD,
I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
WKUP6
42 C4 29 29 27 - PB6 I/O FTf -
I2C1_SCL,
USART1_TX,
TIM16_CH1N,
TSC_G5_I03
-
43 A4 30 30 28 - PB7 I/O FTf -
I2C1_SDA,
USART1_RX,
TIM17_CH1N,
TSC_G5_IO4
-
44 - - 31 - - PF11-BOOT0 I/O FT - - Boot memory
selection
- B4 31 - 1 1 PB8-BOOT0 I/O FTf -
I2C1_SCL, CEC,
TIM16_CH1,
TSC_SYNC,
CAN_RX
Boot memory
selection
45 - - 32 - - PB8 I/O FTf -
I2C1_SCL, CEC,
TIM16_CH1,
TSC_SYNC,
CAN_RX
-
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
I/O structure
Notes
Pin functions
LQFP48/UFQFPN48
WLCSP36
LQFP32
UFQFPN32
UFQFPN28
TSSPOP20
Alternate function Additional
functions
Pinouts and pin descriptions STM32F042x4 STM32F042x6
36/117 DocID025832 Rev 5
46 - - - - - PB9 I/O FTf -
SPI2_NSS,
I2C1_SDA, IR_OUT,
TIM17_CH1,
EVENTOUT,
CAN_TX
-
47 - 32 0 - - VSS S - - Ground
48 A5 1 1 - - VDD S - - Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the reference manual.
3. Distinct VSSA pin is only available on 48-pin packages. On all other packages, the pin number corresponds to the VSS
pin to which VSSA pad of the silicon die is connected.
4. PA8, PA9, PA10, PA11, PA12, PA13, PA14 and PA15 I/Os are supplied by VDDIO2.
5. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using SYSCFG_CFGR1 register.
6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO
pin and the internal pull-down on the SWCLK pin are activated.
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
I/O structure
Notes
Pin functions
LQFP48/UFQFPN48
WLCSP36
LQFP32
UFQFPN32
UFQFPN28
TSSPOP20
Alternate function Additional
functions
STM32F042x4 STM32F042x6 Pinouts and pin descriptions
DocID025832 Rev 5 37/117
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA0 - USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 - - - -
PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2 - - - -
PA2 - USART2_TX TIM2_CH3 TSC_G1_IO3 - - - -
PA3 - USART2_RX TIM2_CH4 TSC_G1_IO4 - - - -
PA4 SPI1_NSS, I2S1_WS USART2_CK USB_NOE TSC_G2_IO1 TIM14_CH1 - - -
PA5 SPI1_SCK, I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 - - - -
PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 - TIM16_CH1 EVENTOUT -
PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT -
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT CRS_SYNC - - -
PA9 - USART1_TX TIM1_CH2 TSC_G4_IO1 I2C1_SCL MCO - -
PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2 I2C1_SDA - - -
PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 CAN_RX I2C1_SCL - -
PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 CAN_TX I2C1_SDA - -
PA13 SWDIO IR_OUT USB_NOE - - - - -
PA14 SWCLK USART2_TX - - - - - -
PA15 SPI1_NSS, I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT - USB_NOE - -
Pinouts and pin descriptions STM32F042x4 STM32F042x6
38/117 DocID025832 Rev 5
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Pin name AF0 AF1 AF2 AF3 AF4 AF5
PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2 - -
PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3 - -
PB2 - - - TSC_G3_IO4 - -
PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1 - -
PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 - TIM17_BKIN
PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA - -
PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3 - -
PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4 - -
PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC CAN_RX -
PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT CAN_TX SPI2_NSS
PB10 CEC I2C1_SCL TIM2_CH3 TSC_SYNC - SPI2_SCK
PB11 EVENTOUT I2C1_SDA TIM2_CH4 - - -
PB12 SPI2_NSS EVENTOUT TIM1_BKIN - - -
PB13 SPI2_SCK - TIM1_CH1N - - I2C1_SCL
PB14 SPI2_MISO - TIM1_CH2N - - I2C1_SDA
PB15 SPI2_MOSI - TIM1_CH3N - - -
Table 16. Alternate functions selected through GPIOF_AFR registers for port F
Pin name AF0 AF1
PF0 CRS_SYNC I2C1_SDA
PF1 - I2C1_SCL
DocID025832 Rev 5 39/117
STM32F042x4 STM32F042x6 Memory mapping
41
5 Memory mapping
To the difference of STM32F042x6 memory map in Figure 10, the two bottom code memory
spaces of STM32F042x4 end at 0x0000 3FFF and 0x0800 3FFF, respectively.
Figure 10. STM32F042x6 memo ry map
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40/117 DocID025832 Rev 5
Table 17. STM32F042x4/x6 peripheral register boundary addresses
Bus Boundary address Size Peripheral
0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved
AHB2
0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 0C00 - 0x4800 13FF 2 KB Reserved
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
AHB1
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 3 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2400 - 0x4002 2FFF 3 KB Reserved
0x4002 2000 - 0x4002 23FF 1 KB Flash memory interface
0x4002 1400 - 0x4002 1FFF 3 KB Reserved
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 0FFF 3 KB Reserved
0x4002 0000 - 0x4002 03FF 1 KB DMA
0x4001 8000 - 0x4001 FFFF 32 KB Reserved
APB
0x4001 5C00 - 0x4001 7FFF 9 KB Reserved
0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 3C00 - 0x4001 43FF 2 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB Reserved
0x4001 2400 - 0x4001 27FF 1 KB ADC
0x4001 0800 - 0x4001 23FF 7 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG
0x4000 8000 - 0x4000 FFFF 32 KB Reserved
DocID025832 Rev 5 41/117
STM32F042x4 STM32F042x6 Memory mapping
41
APB
0x4000 7C00 - 0x4000 7FFF 1 KB Reserved
0x4000 7800 - 0x4000 7BFF 1 KB CEC
0x4000 7400 - 0x4000 77FF 1 KB Reserved
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB CRS
0x4000 6800 - 0x4000 6BFF0 1 KB Reserved
0x4000 6400 - 0x4000 67FF 1 KB BxCAN
0x4000 6000 - 0x4000 63FF 1 KB USB/CAN RAM
0x4000 5C00 - 0x4000 5FFF 1 KB USB
0x4000 5800 - 0x4000 5BFF 1 KB Reserved
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 4800 - 0x4000 53FF 3 KB Reserved
0x4000 4400 - 0x4000 47FF 1 KB USART2
0x4000 3C00 - 0x4000 43FF 2 KB Reserved
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 2400 - 0x4000 27FF 1 KB Reserved
0x4000 2000 - 0x4000 23FF 1 KB TIM14
0x4000 0800 - 0x4000 1FFF 6 KB Reserved
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB TIM2
Table 17. STM32F042x4/x6 perip heral register boundary addresses (continued)
Bus Boundary address Size Peripheral
Electrical characteristics STM32F042x4 STM32F042x6
42/117 DocID025832 Rev 5
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions Figure 12. Pin input voltage
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9,1
DocID025832 Rev 5 43/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
6.1.6 Power supply scheme
Figure 13. Power supply scheme
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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DocID025832 Rev 5 45/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 18. Voltage characteristics(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
Symbol Ratings Min Max Unit
VDD–VSS External main supply voltage - 0.3 4.0 V
VDDIO2–VSS External I/O supply voltage - 0.3 4.0 V
VDDA–VSS External analog supply voltage - 0.3 4.0 V
VDD–VDDA Allowed voltage difference for VDD > VDDA -0.4V
VBAT–VSS External backup supply voltage - 0.3 4.0 V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum
allowed injected current values.
Input voltage on FT and FTf pins VSS - 0.3 VDDIOx + 4.0 (3)
3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is
enabled, the maximum limit is 4 V.
V
Input voltage on TTa pins VSS - 0.3 4.0 V
Input voltage on any other pin VSS - 0.3 4.0 V
|∆VDDx| Variations between different VDD power pins - 50 mV
|VSSx - VSS|Variations between all the different ground
pins -50mV
VESD(HBM)
Electrostatic discharge voltage
(human body model)
see Section 6.3.12: Electrical
sensitivity characteristics -
Electrical characteristics STM32F042x4 STM32F042x6
46/117 DocID025832 Rev 5
Table 19. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1) 120
mA
ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) -120
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100
IIO(PIN)
Output current sunk by any I/O and control pin 25
Output current source by any I/O and control pin -25
ΣIIO(PIN)
Total output current sunk by sum of all I/Os and control pins(2) 80
Total output current sourced by sum of all I/Os and control pins(2) -80
Total output current sourced by sum of all I/Os supplied by VDDIO2 -40
IINJ(PIN)(3)
Injected current on FT and FTf pins -5/+0(4)
Injected current on TC and RST pin ± 5
Injected current on TTa pins(5) ± 5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 56: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 20. Thermal characteristics
Symbol Ratings Valu e Uni t
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
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6.3 Operating conditions
6.3.1 General operating conditions
6.3.2 Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 21. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 48
MHz
fPCLK Internal APB clock frequency - 0 48
VDD Standard operating voltage - 2.0 3.6 V
VDDIO2 I/O supply voltage Must not be supplied if VDD
is not present 1.65 3.6 V
VDDA
Analog operating voltage
(ADC not used) Must have a potential equal
to or higher than VDD
VDD 3.6
V
Analog operating voltage
(ADC used) 2.4 3.6
VBAT Backup operating voltage - 1.65 3.6 V
VIN I/O input voltage
TC and RST I/O -0.3 VDDIOx+0.3
VTTa I/O -0.3 VDDA+0.3(1)
FT and FTf I/O -0.3 5.5(1)
PD
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(2)
LQFP48 - 364
mW
UFQFPN48 - 606
WLCSP36 - 313
LQFP32 - 351
UFQFPN32 - 526
UFQFPN28 - 170
TSSOP20 - 263
TA
Ambient temperature for the
suffix 6 version
Maximum power dissipation –40 85
°C
Low power dissipation(3) –40 105
Ambient temperature for the
suffix 7 version
Maximum power dissipation –40 105
°C
Low power dissipation(3) –40 125
TJ Junction temperature range
Suffix 6 version –40 105
°C
Suffix 7 version –40 125
1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.8: Thermal characteristics.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristicsSection 7.8: Thermal characteristics).
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6.3.3 Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 22. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate
-
0∞
µs/V
VDD fall time rate 20 ∞
tVDDA
VDDA rise time rate
-
0∞
VDDA fall time rate 20 ∞
Table 23. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPOR/PDR(1)
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
Power on/power down
reset threshold
Falling edge(2)
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
1.80 1.88 1.96(3)
3. Data based on characterization results, not tested in production.
V
Rising edge 1.84(3) 1.92 2.00 V
VPDRhyst PDR hysteresis - - 40 - mV
tRSTTEMPO(4)
4. Guaranteed by design, not tested in production.
Reset temporization - 1.50 2.50 4.50 ms
Table 24. Programmable voltage detector chara cteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD0 PVD threshold 0
Rising edge 2.1 2.18 2.26 V
Falling edge 2 2.08 2.16 V
VPVD1 PVD threshold 1
Rising edge 2.19 2.28 2.37 V
Falling edge 2.09 2.18 2.27 V
VPVD2 PVD threshold 2
Rising edge 2.28 2.38 2.48 V
Falling edge 2.18 2.28 2.38 V
VPVD3 PVD threshold 3
Rising edge 2.38 2.48 2.58 V
Falling edge 2.28 2.38 2.48 V
VPVD4 PVD threshold 4
Rising edge 2.47 2.58 2.69 V
Falling edge 2.37 2.48 2.59 V
VPVD5 PVD threshold 5
Rising edge 2.57 2.68 2.79 V
Falling edge 2.47 2.58 2.69 V
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6.3.4 Embedded reference voltage
The parameters given in Table 25 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
6.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14 : Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
VPVD6 PVD threshold 6
Rising edge 2.66 2.78 2.9 V
Falling edge 2.56 2.68 2.8 V
VPVD7 PVD threshold 7
Rising edge 2.76 2.88 3 V
Falling edge 2.66 2.78 2.9 V
VPVDhyst(1) PVD hysteresis - - 100 - mV
IDD(PVD) PVD current consumption - - 0.15 0.26(1) µA
1. Guaranteed by design, not tested in production.
Table 24. Programmable voltage detector characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 25. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.2 1.23 1.25 V
tSTART
ADC_IN17 buffer startup
time ---10
(1) µs
tS_vrefint
ADC sampling time when
reading the internal
reference voltage
-4(1)
1. Guaranteed by design, not tested in production.
-- µs
∆VREFINT
Internal reference voltage
spread over the
temperature range
VDDA = 3 V - - 10(1) mV
TCoeff Temperature coefficient - - 100(1) -100(1) ppm/°C
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in analog input mode
•All peripherals are disabled except when explicitly mentioned
•The Flash memory access time is adjusted to the fHCLK frequency:
– 0 wait state and Prefetch OFF from 0 to 24 MHz
– 1 wait state and Prefetch ON above 24 MHz
•When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 26 to Table 28 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 26. Typical and maximum current consumption from V DD supply at VDD = 3.6 V
Symbol
Parameter
Conditions fHCLK
All peripherals enabled(1) All peripherals disabled
Unit
Typ Max @ TA(2)
Typ Max @ TA(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
IDD
Supply current in Run mode,
code executing from Flash memory
HSI48 48 MHz 20.3 23.2 23.4 24.6 12.7 14.4 14.4 14.7
mA
HSE bypass,
PLL on
48 MHz 20.2 22.9 23.0 23.9 12.6 14.1 14.3 14.4
32 MHz 14.0 16.0 16.1 16.7 8.7 9.5 9.7 10.3
24 MHz 11.0 13.5 13.7 13.8 6.9 7.6 7.8 8.2
HSE bypass,
PLL off
8 MHz 3.9 5.2 5.3 5.6 2.6 3.1 3.2 3.3
1 MHz 0.9 1.3 1.5 1.8 0.7 1.0 1.1 1.3
HSI clock,
PLL on
48 MHz 20.5 23.1 23.3 23.6 12.8 14.6 14.6 15.0
32 MHz 14.3 15.6 15.9 17.0 8.6 9.5 9.7 10.0
24 MHz 11.2 13.6 13.8 14.8 6.9 7.4 7.5 7.7
HSI clock,
PLL off 8 MHz 4.1 5.2 5.3 5.6 2.6 3.1 3.1 3.3
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STM32F042x4 STM32F042x6 Electrical characteristics
89
IDD
Supply current in Run mode,
code executing from RAM
HSI48 48 MHz 19.3 21.9 22.1 23.7 11.9 13.4 13.6 13.7
mA
HSE bypass,
PLL on
48 MHz 19.2 21.8(3) 22.0 22.1(3) 11.7 13.3(3) 13.5 13.7(3)
32 MHz 13.4 15.8 15.9 16.0 7.9 8.8 8.9 9.7
24 MHz 10.3 12.6 13.0 13.4 6.2 8.0 8.2 8.3
HSE bypass,
PLL off
8 MHz 3.6 4.1 4.3 4.4 2.0 2.1 2.1 2.5
1 MHz 0.8 0.9 0.9 1.1 0.4 0.5 0.6 0.8
HSI clock,
PLL on
48 MHz 19.5 22.0 22.1 22.5 11.8 13.6 13.8 13.9
32 MHz 13.5 16.3 16.4 16.6 8.0 8.8 9.1 9.9
24 MHz 10.5 12.8 13.0 13.8 6.5 8.0 8.1 8.4
HSI clock,
PLL off 8 MHz 3.7 4.7 5.0 5.3 2.1 2.3 2.4 3.0
Supply current in Sleep mode
HSI48 48 MHz 12.4 15.1 16.3 16.7 3.0 3.2 3.3 3.4
HSE bypass,
PLL on
48 MHz 12.3 15.0(3) 16.0 16.2(3) 2.9 3.2(3) 3.3 3.4(3)
32 MHz 8.5 10.6 11.2 11.7 1.9 2.1 2.2 2.5
24 MHz 6.5 8.1 8.5 8.7 1.6 1.8 1.8 1.9
HSE bypass,
PLL off
8 MHz 2.3 3.0 3.1 3.2 0.7 0.8 0.8 0.9
1 MHz 0.4 0.4 0.4 0.6 0.1 0.3 0.3 0.4
HSI clock,
PLL on
48 MHz 12.4 15.3 15.7 15.9 3.0 3.0 3.2 3.4
32 MHz 8.6 10.7 11.3 11.6 2.1 2.2 2.2 2.5
24 MHz 6.6 8.4 8.7 8.9 1.6 1.6 1.7 1.9
HSI clock,
PLL off 8 MHz 2.4 3.2 3.4 3.6 0.6 0.8 0.9 1.0
1. USB is kept disabled as this IP functions only with a 48 MHz clock.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
Table 26. Typical and maximum current consumption from VDD supply at VDD = 3.6 V (continued)
Symbol
Parameter
Conditions fHCLK
All peripherals enabled(1) All peripherals disabled
Unit
Typ Max @ TA(2)
Typ Max @ TA(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
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Table 27. Typical and maximum current consumption from the VDDA supply
Symbol Para-
meter Conditions
(1) fHCLK
VDDA = 2.4 V VDDA = 3.6 V
Unit
Typ Max @ TA(2)
Typ Max @ TA(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
IDDA
Supply
current in
Run or
Sleep
mode,
code
executing
from
Flash
memory
or RAM
HSI48 48 MHz 309 325 332 342 317 334 338 344
µA
HSE
bypass,
PLL on
48 MHz 148 167(3) 176 179(3) 161 181(3) 193 197(3)
32 MHz 102 119 124 126 111 128 135 137
24 MHz 80 95 99 100 88 102 106 108
HSE
bypass,
PLL off
8 MHz 2.7 3.7 4.2 4.5 3.5 4.7 5.2 5.5
1 MHz 2.7 3.7 4.2 4.2 3.6 4.7 5.2 5.5
HSI clock,
PLL on
48 MHz 220 242 251 254 242 264 275 279
32 MHz 173 193 200 202 191 211 219 221
24 MHz 151 169 175 177 167 184 191 193
HSI clock,
PLL off 8 MHz 72 82 85 85 82 92 95 95
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from
the frequency.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
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89
Table 28. Typical and maximum consumption in Stop and Standby modes
Symbol
Parameter
Conditions
Typ @VDD (VDD = VDDA)Max
(1)
Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA =
25°C TA =
85°C TA =
105°C
IDD
Supply
current in
Stop mode
Regulator in run
mode, all
oscillators OFF
14.3 14.5 14.6 14.7 14.8 14.9 21.0 47.0 64.0
µA
Regulator in low-
power mode, all
oscillators OFF
2.93.13.23.33.43.56.532.044.0
Supply
current in
Standby
mode
LSI ON and IWDG
ON 0.80.91.11.21.31.5 - - -
LSI OFF and IWDG
OFF 0.60.70.80.91.01.12.02.53.0
IDDA
Supply
current in
Stop mode
VDDA monitoring ON
Regulator in
run mode, all
oscillators
OFF
2.02.12.22.42.52.73.53.54.5
Regulator in
low-power
mode, all
oscillators
OFF
2.02.12.22.42.52.73.53.54.5
Supply
current in
Standby
mode
LSI ON and
IWDG ON 2.42.62.83.03.13.4 - - -
LSI OFF and
IWDG OFF 1.92.02.12.32.42.53.43.54.5
Supply
current in
Stop mode
VDDA monitoring OFF
Regulator in
run mode, all
oscillators
OFF
1.31.31.31.41.41.5 - - -
Regulator in
low-power
mode, all
oscillators
OFF
1.31.31.31.41.41.5 - - -
Supply
current in
Standby
mode
LSI ON and
IWDG ON 1.71.81.82.02.12.2 - - -
LSI OFF and
IWDG OFF 1.11.21.21.31.31.4 - - -
1. Data based on characterization results, not tested in production unless otherwise specified.
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Typical current consumption
The MCU is placed under the following conditions:
•VDD = VDDA = 3.3 V
•All I/O pins are in analog input configuration
•The Flash memory access time is adjusted to fHCLK frequency:
– 0 wait state and Prefetch OFF from 0 to 24 MHz
– 1 wait state and Prefetch ON above 24 MHz
•When the peripherals are enabled, fPCLK = fHCLK
•PLL is used for frequencies greater than 8 MHz
•AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
Table 29. Typical and maximum current consumption from the VBAT supply
Symbol Parameter Conditions
Typ @ VBAT Max(1)
Unit
1.65 V
1.8 V
2.4 V
2.7 V
3.3 V
3.6 V
TA =
25 °C TA =
85 °C TA =
105 °C
IDD_VBAT
RTC
domain
supply
current
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
LSEDRV[1:0] = '00'
0.5 0.5 0.6 0.7 0.9 1.1 1.2 1.5 2.0
µA
LSE & RTC ON; “Xtal
mode” higher driving
capability;
LSEDRV[1:0] = '11'
0.8 0.9 1.1 1.2 1.4 1.5 1.6 2.0 2.6
1. Data based on characterization results, not tested in production.
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I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
Table 30. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Symbol Parameter fHCLK
Typical co nsumption in
Run mode Typical consumption in
Sleep mode Unit
Peripherals
enabled Peripherals
disabled Peripherals
enabled Peripherals
disabled
IDD
Current
consumption
from VDD
supply
48 MHz 20.7 12.8 12.3 3.4
mA
36 MHz 15.9 9.9 9.5 2.7
32 MHz 14.3 9.0 8.5 2.5
24 MHz 11.0 7.1 6.6 2.1
16 MHz 7.7 5.0 4.7 1.6
8 MHz 4.3 3.0 2.7 1.2
4 MHz 2.6 2.0 1.7 0.9
2 MHz 1.8 1.5 1.2 0.8
1 MHz 1.4 1.2 1.0 0.8
500 kHz 1.2 1.1 0.8 0.7
IDDA
Current
consumption
from VDDA
supply
48 MHz 163.3
μA
36 MHz 124.3
32 MHz 111.9
24 MHz 87.1
16 MHz 62.5
8 MHz 2.5
4 MHz 2.5
2 MHz 2.5
1 MHz 2.5
500 kHz 2.5
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trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 32: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDDIOx fSW C××=
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Table 31. Switching output I/O current consumption
Symbol Parameter Conditions(1)
1. CS = 7 pF (estimated value).
I/O toggling
frequency (fSW)Typ Unit
ISW
I/O current
consumption
VDDIOx = 3.3 V
C =CINT
4 MHz 0.07
mA
8 MHz 0.15
16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
VDDIOx = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
4 MHz 0.18
8 MHz 0.37
16 MHz 0.76
24 MHz 1.39
48 MHz 2.188
VDDIOx = 3.3 V
CEXT = 10 pF
C = CINT + CEXT+ CS
4 MHz 0.32
8 MHz 0.64
16 MHz 1.25
24 MHz 2.23
48 MHz 4.442
VDDIOx = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
4 MHz 0.49
8 MHz 0.94
16 MHz 2.38
24 MHz 3.99
VDDIOx = 3.3 V
CEXT = 33 pF
C = CINT + CEXT+ CS
4 MHz 0.64
8 MHz 1.25
16 MHz 3.24
24 MHz 5.02
VDDIOx = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
4 MHz 0.81
8 MHz 1.7
16 MHz 3.67
VDDIOx = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
4 MHz 0.66
8 MHz 1.43
16 MHz 2.45
24 MHz 4.97
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On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 32. The MCU is placed
under the following conditions:
•All I/O pins are in analog mode
•All peripherals are disabled unless otherwise mentioned
•The given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
•Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
Table 32. Peripheral current consumption
Periphera l Typical consump t io n at 25 °C Unit
AHB
BusMatrix(1) 2.2
µA/MHz
CRC 1.9
DMA 5.1
Flash memory interface 15.0
GPIOA 8.2
GPIOB 7.7
GPIOC 2.1
GPIOF 1.8
SRAM 1.1
TSC 4.9
All AHB peripherals 49.8
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APB
APB-Bridge(2) 2.9
µA/MHz
ADC(3) 3.9
CAN 12.9
CEC 1.5
CRS 1.0
DBG (MCU Debug Support) 0.2
I2C1 3.6
PWR 1.4
SPI1 8.5
SPI2 6.1
SYSCFG 1.8
TIM1 15.1
TIM2 16.8
TIM3 11.7
TIM14 5.5
TIM16 7.0
TIM17 6.9
USART1 17.8
USART2 5.6
USB 4.9
WWDG 1.4
All APB peripherals 136.7
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.
3. The power consumption of the analog part (IDDA) of peripherals such as ADC is not included. Refer to the
tables of characteristics in the subsequent sections.
Ta ble 32. Peripheral current consumption (continued)
Periphera l Typical consump t io n at 25 °C Unit
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6.3.6 Wakeup time from low-power mode
The wakeup times given in Table 33 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 21: General operating conditions..
6.3.7 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15: High-speed ex ter n al clock
source AC timing diagram.
Table 33. Low-power mode wakeup timings
Symbol Parameter Conditions Typ @VDD = VDDA Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
tWUSTOP
Wakeup from Stop
mode
Regulator in run
mode 3.23.12.92.92.85
µs
Regulator in low
power mode 7.05.85.24.94.69
tWUSTANDBY
Wakeup from
Standby mode - 60.4 55.6 53.5 52 51 -
tWUSLEEP
Wakeup from Sleep
mode - 4 SYSCLK cycles -
Table 34. High-speed external user clock characteristics
Symbol Parameter(1) Min Typ Max Unit
fHSE_ext User external clock source frequency - 8 32 MHz
VHSEH OSC_IN input pin high level voltage 0.7 VDDIOx -V
DDIOx V
VHSEL OSC_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(HSEH)
tw(HSEL)
OSC_IN high or low time 15 - -
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time - - 20
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Figure 15. High-speed external clock source AC timing diagram
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 16.
Figure 16. Low-speed external clock source AC timing diagram
1. Guaranteed by design, not tested in production.
Table 35. Low-speed external user clock characteristics
Symbol Parameter(1)
1. Guaranteed by design, not tested in production.
Min Typ Max Unit
fLSE_ext User external clock source frequency - 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage 0.7 VDDIOx -V
DDIOx V
VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time - - 50
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 36. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST mic ro co ntro ller s” av aila ble fro m the ST webs ite www.st.com.
Table 36. HSE oscillator characteristics
Symbol Parameter Conditions(1)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
Min(2) Typ Max(2)
2. Guaranteed by design, not tested in production.
Unit
fOSC_IN Oscillator frequency - 4 8 32 MHz
RFFeedback resistor - - 200 - kΩ
IDD HSE current consumption
During startup(3)
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
--8.5
mA
VDD = 3.3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-0.4-
VDD = 3.3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
-0.5-
VDD = 3.3 V,
Rm = 30 Ω,
CL = 5 pF@32 MHz
-0.8-
VDD = 3.3 V,
Rm = 30 Ω,
CL = 10 pF@32 MHz
-1-
VDD = 3.3 V,
Rm = 30 Ω,
CL = 20 pF@32 MHz
-1.5-
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
DocID025832 Rev 5 63/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
Figure 17. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 37. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
IDD LSE current consumption
low drive capability - 0.5 0.9
µA
medium-low drive capability - - 1
medium-high drive capability - - 1.3
high drive capability - - 1.6
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low drive capability 5 - -
µA/V
medium-low drive capability 8 - -
medium-high drive capability 15 - -
high drive capability 25 - -
tSU(LSE)(3) Startup time VDDIOx is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Electrical characteristics STM32F042x4 STM32F042x6
64/117 DocID025832 Rev 5
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST mic ro co ntro ller s” av aila ble fro m the ST webs ite www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
Note: An external resistor is no t required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8 Internal clock source characteristics
The parameters given in Table 38 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
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STM32F042x4 STM32F042x6 Electrical characteristics
89
High-speed internal (HSI) RC oscillator
Figure 19. HSI oscill at or ac cu ra cy ch aract eriz at io n results for soldered parts
Table 38. HSI oscillator characteristics(1)
1. VDDA = 3.3 V, TA = -40 to 105°C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - - 8 - MHz
TRIM HSI user trimming step - - - 1(2)
2. Guaranteed by design, not tested in production.
%
DuCy(HSI) Duty cycle - 45(2) -55
(2) %
ACCHSI
Accuracy of the HSI
oscillator
TA = -40 to 105°C -2.8(3)
3. Data based on characterization results, not tested in production.
-3.8
(3)
%
TA = -10 to 85°C -1.9(3) -2.3
(3)
TA = 0 to 85°C -1.9(3) -2
(3)
TA = 0 to 70°C -1.3(3) -2
(3)
TA = 0 to 55°C -1(3) -2
(3)
TA = 25°C(4)
4. Factory calibrated, parts not soldered.
-1 - 1
tsu(HSI) HSI oscillator startup time - 1(2) -2
(2) µs
IDDA(HSI)
HSI oscillator power
consumption - - 80 100(2) µA
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High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Figure 20. HSI14 oscillator accuracy characterization results
Table 39. HSI14 oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI14 Frequency - - 14 - MHz
TRIM HSI14 user-trimming step - - - 1(2)
2. Guaranteed by design, not tested in production.
%
DuCy(HSI14) Duty cycle - 45(2) -55
(2) %
ACCHSI14
Accuracy of the HSI14
oscillator (factory calibrated)
TA = –40 to 105 °C –4.2(3)
3. Data based on characterization results, not tested in production.
-5.1
(3) %
TA = –10 to 85 °C –3.2(3) -3.1
(3) %
TA = 0 to 70 °C –2.5(3) -2.3
(3) %
TA = 25 °C –1 - 1 %
tsu(HSI14) HSI14 oscillator startup time - 1(2) -2
(2) µs
IDDA(HSI14)
HSI14 oscillator power
consumption --100150
(2) µA
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DocID025832 Rev 5 67/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
High-speed internal 48 MHz (HSI48) RC oscillator
Figure 21. HSI48 oscillator accuracy characterization results
Table 40. HSI48 oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI48 Frequency - - 48 - MHz
TRIM HSI48 user-trimming step - 0.09(2) 0.14 0.2(2) %
DuCy(HSI48) Duty cycle - 45(2)
2. Guaranteed by design, not tested in production.
-55
(2) %
ACCHSI48
Accuracy of the HSI48
oscillator (factory calibrated)
TA = –40 to 105 °C -4.9(3)
3. Data based on characterization results, not tested in production.
-4.7
(3) %
TA = –10 to 85 °C -4.1(3) -3.7
(3) %
TA = 0 to 70 °C -3.8(3) -3.4
(3) %
TA = 25 °C -2.8 - 2.9 %
tsu(HSI48) HSI48 oscillator startup time - - - 6(2) µs
IDDA(HSI48)
HSI48 oscillator power
consumption - - 312 350(2) µA
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Low-speed internal (LSI) RC oscillator
6.3.9 PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
6.3.10 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 41. LSI oscillator characteristics(1)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 50 kHz
tsu(LSI)(2)
2. Guaranteed by design, not tested in production.
LSI oscillator startup time - - 85 µs
IDDA(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA
Table 42. PLL characteristics
Symbol Parameter Value Unit
Min Typ Max
fPLL_IN
PLL input clock(1)
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT
.
1(2) 8.0 24(2) MHz
PLL input clock duty cycle 40(2) -60
(2) %
fPLL_OUT PLL multiplier output clock 16(2) -48MHz
tLOCK PLL lock time - - 200(2)
2. Guaranteed by design, not tested in production.
µs
JitterPLL Cycle-to-cycle jitter - - 300(2) ps
Table 43. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Guaranteed by design, not tested in production.
Unit
tprog 16-bit programming time TA = - 40 to +105 °C 40 53.5 60 µs
tERASE Page (1 KB) erase time TA = - 40 to +105 °C 20 - 40 ms
tME Mass erase time TA = - 40 to +105 °C 20 - 40 ms
IDD Supply current
Write mode - - 10 mA
Erase mode - - 12 mA
DocID025832 Rev 5 69/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
6.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Table 44. Flash memory endurance and data retention
Symbol Parameter Conditions Min(1)
1. Data based on characterization results, not tested in production.
Unit
NEND Endurance TA = –40 to +105 °C 10 kcycle
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Yea r1 kcycle(2) at TA = 105 °C 10
10 kcycle(2) at TA = 55 °C 20
Table 45. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, LQFP48, TA = +25 °C,
fHCLK = 48 MHz,
conforming to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP48, TA = +25°C,
fHCLK = 48 MHz,
conforming to IEC 61000-4-4
4B
Electrical characteristics STM32F042x4 STM32F042x6
70/117 DocID025832 Rev 5
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
6.3.12 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 46. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]Unit
8/48 MHz
SEMI Peak level
VDD = 3.6 V, TA = 25 °C,
LQFP48 package
compliant with
IEC 61967-2
0.1 to 30 MHz -9
dBµV30 to 130 MHz 9
130 MHz to 1 GHz 17
EMI Level 3 -
DocID025832 Rev 5 71/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•A supply overvoltage is applied to each power supply pin.
•A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 49.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 47. ESD absolute maximum ratings
Symbol Ratings Conditions Packages Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming
to JESD22-A114 All 2 2000 V
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = +25 °C, conforming
to ANSI/ESD STM5.3.1 All C4 500 V
1. Data based on characterization results, not tested in production.
Table 48. Electrical sensitivitie s
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
Electrical characteristics STM32F042x4 STM32F042x6
72/117 DocID025832 Rev 5
6.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 49. I/O current injection susceptibility
Symbol Description
Functional
susceptibility Unit
Negative
injection Positive
injection
IINJ
Injected current on PA12 pin -0 +5
mA
Injected current on PA9, PB3, PB13, PF11 pins with induced
leakage current on adjacent pins less than 50 µA -5 NA
Injected current on PB0, PB1 and all other FT and FTf pins -5 NA
Injected current on all other TC, TTa and RST pins -5 +5
Table 50. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL
Low level input
voltage
TC and TTa I/O - - 0.3 VDDIOx+0.07(1)
VFT and FTf I/O - - 0.475 VDDIOx–0.2(1)
All I/Os - - 0.3 VDDIOx
VIH
High level input
voltage
TC and TTa I/O 0.445 VDDIOx+0.398(1) --
VFT and FTf I/O 0.5 VDDIOx+0.2(1) --
All I/Os 0.7 VDDIOx --
Vhys Schmitt trigger
hysteresis
TC and TTa I/O - 200(1) -
mV
FT and FTf I/O - 100(1) -
Ilkg Input leakage
current(2)
TC, FT and FTf I/O
TTa in digital mode
VSS ≤ VIN ≤ VDDIOx
--± 0.1
µA
TTa in digital mode
VDDIOx ≤ VIN ≤ VDDA
--1
TTa in analog mode
VSS ≤ VIN ≤ VDDA
--± 0.2
FT and FTf I/O
VDDIOx ≤ VIN ≤ 5 V --10
RPU
Weak pull-up
equivalent resistor
(3)
VIN = VSS 25 40 55 kΩ
DocID025832 Rev 5 73/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
RPD
Weak pull-down
equivalent
resistor(3)
VIN = - VDDIOx 25 40 55 kΩ
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 49:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
Table 50. I/O static characteristics (continu ed)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32F042x4 STM32F042x6
74/117 DocID025832 Rev 5
Figure 22. TC an d TTa I/O input characteristics
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics
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STM32F042x4 STM32F042x6 Electrical characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18: Voltage characteristics).
•The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 18: Volt age characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
Table 51. Output voltage ch aracteristics(1)
Symbol Parameter Conditions Min Max Unit
VOL Output low level voltage for an I/O pin CMOS port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-0.4
V
VOH Output high level voltage for an I/O pin VDDIOx–0.4 -
VOL Output low level voltage for an I/O pin TTL port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-0.4
V
VOH Output high level voltage for an I/O pin 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA
VDDIOx ≥ 2.7 V
-1.3
V
VOH(3) Output high level voltage for an I/O pin VDDIOx–1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 6 mA
VDDIOx ≥ 2 V
-0.4
V
VOH(3) Output high level voltage for an I/O pin VDDIOx–0.4 -
VOL(4) Output low level voltage for an I/O pin
|IIO| = 4 mA
-0.4V
VOH(4) Output high level voltage for an I/O pin VDDIOx–0.4 - V
VOLFm+(3) Output low level voltage for an FTf I/O pin in
Fm+ mode
|IIO| = 20 mA
VDDIOx ≥ 2.7 V -0.4V
|IIO| = 10 mA - 0.4 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
V oltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
4. Data based on characterization results. Not tested in production.
Electrical characteristics STM32F042x4 STM32F042x6
76/117 DocID025832 Rev 5
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 52, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 21: General operating conditions.
Table 52. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] value(1) Symbol Parameter Conditions Min Max Unit
x0
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx ≥ 2 V
-2MHz
tf(IO)out Output fall time - 125
ns
tr(IO)out Output rise time - 125
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx < 2 V
-1MHz
tf(IO)out Output fall time - 125
ns
tr(IO)out Output rise time - 125
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx ≥ 2 V
-10MHz
tf(IO)out Output fall time - 25
ns
tr(IO)out Output rise time - 25
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx < 2 V
-4MHz
tf(IO)out Output fall time - 62.5
ns
tr(IO)out Output rise time - 62.5
11
fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDDIOx ≥ 2.7 V - 50
MHz
CL = 50 pF, VDDIOx ≥ 2.7 V - 30
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 20
CL = 50 pF, VDDIOx < 2 V - 10
tf(IO)out Output fall time
CL = 30 pF, VDDIOx ≥ 2.7 V - 5
ns
CL = 50 pF, VDDIOx ≥ 2.7 V - 8
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 12
CL = 50 pF, VDDIOx < 2 V - 25
tr(IO)out Output rise time
CL = 30 pF, VDDIOx ≥ 2.7 V - 5
CL = 50 pF, VDDIOx ≥ 2.7 V - 8
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V - 12
CL = 50 pF, VDDIOx < 2 V - 25
DocID025832 Rev 5 77/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
Figure 24. I/O AC characteristics de f i n iti on
6.3.15 NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
Fm+
configuration
(4)
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx ≥ 2 V
-2MHz
tf(IO)out Output fall time - 12
ns
tr(IO)out Output rise time - 34
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx < 2 V
-0.5MHz
tf(IO)out Output fall time - 16
ns
tr(IO)out Output rise time - 44
-t
EXTIpw
Pulse width of external
signals detected by the
EXTI controller
-10-ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 24.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091
for a detailed description of Fm+ I/O configuration.
Table 52. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] value(1) Symbol Parameter Conditions Min Max Unit
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Table 53. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1)
V
VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) --
Electrical characteristics STM32F042x4 STM32F042x6
78/117 DocID025832 Rev 5
Figure 25. Recommended NRST pin protection
1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53: NRST p in characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis --200-mV
RPU
Weak pull-up equivalent
resistor(2) VIN = VSS 25 40 55 kΩ
VF(NRST) NRST input filtered pulse - - - 100(1) ns
VNF(NRST) NRST input not filtered pulse
2.7 < VDD < 3.6 300(3) --
ns
2.0 < VDD < 3.6 500(3) --
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.
Table 53. NRST pin characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Ta ble 54. ADC characteristics
Symbol Para meter Conditions Min Typ Max Unit
VDDA
Analog supply voltage for
ADC ON - 2.4 - 3.6 V
IDDA (ADC)
Current consumption of
the ADC(1) VDDA = 3.3 V - 0.9 - mA
fADC ADC clock frequency - 0.6 - 14 MHz
fS(2) Sampling rate 12-bit resolution 0.043 - 1 MHz
DocID025832 Rev 5 79/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
fTRIG(2) External trigger frequency
fADC = 14 MHz,
12-bit resolution --823kHz
12-bit resolution - - 17 1/fADC
VAIN Conversion voltage range - 0 - VDDA V
RAIN(2) External input impedance See Equation 1 and
Table 55 for details --50kΩ
RADC(2) Sampling switch
resistance ---1kΩ
CADC(2) Internal sample and hold
capacitor ---8pF
tCAL(2)(3) Calibration time
fADC = 14 MHz 5.9 µs
-831/f
ADC
WLATENCY(2)(4) ADC_DR register ready
latency
ADC clock = HSI14
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
cycles + 3
fPCLK cycles
-
ADC clock = PCLK/2 - 4.5 - fPCLK
cycle
ADC clock = PCLK/4 - 8.5 - fPCLK
cycle
tlatr(2) Trigger conversion latency
fADC = fPCLK/2 = 14 MHz 0.196 µs
fADC = fPCLK/2 5.5 1/fPCLK
fADC = fPCLK/4 = 12 MHz 0.219 µs
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs
JitterADC ADC jitter on trigger
conversion fADC = fHSI14 -1-1/f
HSI14
tS(2) Sampling time
fADC = 14 MHz 0.107 - 17.1 µs
- 1.5 - 239.5 1/fADC
tSTAB(2) Stabilization time - 14 1/fADC
tCONV(2) Total conversion time
(including sampling time)
fADC = 14 MHz,
12-bit resolution 1-18µs
12-bit resolution 14 to 252 (tS for sampling +12.5 for
successive approximation) 1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
Table 54. ADC characteristics (cont inued)
Symbol Para meter Conditions Min Typ Max Unit
Electrical characteristics STM32F042x4 STM32F042x6
80/117 DocID025832 Rev 5
Equation 1: RAIN max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
RAIN
TS
fADC CADC 2N2+
()ln××
----------------------------------------------------------------RADC
–<
Table 55. RAIN max for fADC = 14 MHz
Ts (cycles) tS (µs) RAIN max (kΩ)(1)
1.5 0.11 0.4
7.5 0.54 5.9
13.5 0.96 11.4
28.52.0425.2
41.52.9637.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
1. Guaranteed by design, not tested in production.
Table 56. ADC accuracy(1)(2)(3)
Symbol Parameter Test conditions Typ Max(4) Unit
ET Total unadjusted error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
VDDA = 3 V to 3.6 V
TA = 25 °C
±1.3 ±2
LSB
EO Offset error ±1 ±1.5
EG Gain error ±0.5 ±1.5
ED Differential linearity error ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
ET Total unadjusted error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
VDDA = 2.7 V to 3.6 V
TA = - 40 to 105 °C
±3.3 ±4
LSB
EO Offset error ±1.9 ±2.8
EG Gain error ±2.8 ±3
ED Differential linearity error ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
ET Total unadjusted error
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
VDDA = 2.4 V to 3.6 V
TA = 25 °C
±3.3 ±4
LSB
EO Offset error ±1.9 ±2.8
EG Gain error ±2.8 ±3
ED Differential linearity error ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
1. ADC DC accuracy values are measured after internal calibration.
DocID025832 Rev 5 81/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
Figure 26. ADC accuracy characteristics
Figure 27. Typical connection diagram using the ADC
1. Refer to Table 54: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
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82/117 DocID025832 Rev 5
6.3.17 Temperature sensor characteristics
6.3.18 VBAT monitoring characteristics
6.3.19 Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 57. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1) VSENSE linearity with temperature - ± 1 ± 2 °C
Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C
V30 Voltage at 30 °C (± 5 °C)(2) 1.34 1.43 1.52 V
tSTART(1) ADC_IN16 buffer startup time - - 10 µs
tS_temp(1) ADC sampling time when reading the
temperature 4- -µs
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:
Temperature sensor calibration values.
Table 58. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -2 x 50- kΩ
QRatio on VBAT measurement - 2 - -
Er(1) Error on Q –1 - +1 %
tS_vbat(1) ADC sampling time when reading the VBAT 4--µs
1. Guaranteed by design, not tested in production.
Ta bl e 59 . TI Mx ch ara ct eri st ic s
Symbol Parameter Conditions Min Typ Max Unit
tres(TIM) Timer resolution time
--1-
tTIMxCLK
fTIMxCLK = 48 MHz - 20.8 - ns
fEXT
Timer external clock
frequency on CH1 to
CH4
--
fTIMxCLK/2 -MHz
fTIMxCLK = 48 MHz - 24 - MHz
tMAX_COUNT
16-bit timer maximum
period
--
216 -tTIMxCLK
fTIMxCLK = 48 MHz - 1365 - µs
32-bit counter
maximum period
--
232 -tTIMxCLK
fTIMxCLK = 48 MHz - 89.48 - s
DocID025832 Rev 5 83/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
6.3.20 Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•Standard-mode (Sm): with a bit rate up to 100 kbit/s
•Fast-mode (Fm): with a bit rate up to 400 kbit/s
•Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 60. IWDG min/max timeout period at 40 kHz (LSI)(1)
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits Min timeout RL[11:0]=
0x000 Max timeout RL[11:0]=
0xFFF Unit
/4 0 0.1 409.6
ms
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
Table 61. WWDG min/max timeout value at 48 MHz (PCLK)
Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0853 5.4613
ms
2 1 0.1706 10.9226
4 2 0.3413 21.8453
8 3 0.6826 43.6906
Electrical characteristics STM32F042x4 STM32F042x6
84/117 DocID025832 Rev 5
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 21: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 62. I2C analog filter characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Min Max Unit
tAF
Maximum width of spikes that are
suppressed by the analog filter 50(2)
2. Spikes with widths below tAF(min) are filtered.
260(3)
3. Spikes with widths above tAF(max) are not filtered
ns
Table 63. SPI characteristics(1)
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode - 18
MHz
Slave mode - 18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time Capacitive load: C = 15 pF - 6 ns
tsu(NSS) NSS setup time Slave mode 4Tpclk -
ns
th(NSS) NSS hold time Slave mode 2Tpclk + 10 -
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode, fPCLK = 36 MHz,
presc = 4 Tpclk/2 -2 Tpclk/2 + 1
tsu(MI)
tsu(SI)
Data input setup time
Master mode 4 -
Slave mode 5 -
th(MI) Data input hold time
Master mode 4 -
th(SI) Slave mode 5 -
ta(SO)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
tdis(SO)(3) Data output disable time Slave mode 0 18
tv(SO) Data output valid time Slave mode (after enable edge) - 22.5
tv(MO) Data output valid time Master mode (after enable edge) - 6
th(SO) Data output hold time
Slave mode (after enable edge) 11.5 -
th(MO) Master mode (after enable edge) 2 -
DuCy(SCK) SPI slave input clock
duty cycle Slave mode 25 75 %
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
DocID025832 Rev 5 85/117
STM32F042x4 STM32F042x6 Electrical characteristics
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Figure 28. SPI timing diagram - slave mode and CPHA = 0
Figure 29. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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86/117 DocID025832 Rev 5
Figure 30. SPI timing diagram - master mode
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Ta b le 64 . I2S characteristics(1)
Symbol Parameter Conditions Min Max Unit
fCK
1/tc(CK)
I2S clock frequency
Master mode (data: 16 bits, Audio
frequency = 48 kHz) 1.597 1.601
MHz
Slave mode 0 6.5
tr(CK) I2S clock rise time
Capacitive load CL = 15 pF
-10
ns
tf(CK) I2S clock fall time - 12
tw(CKH) I2S clock high time Master fPCLK= 16 MHz, audio
frequency = 48 kHz
306 -
tw(CKL) I2S clock low time 312 -
tv(WS) WS valid time Master mode 2 -
th(WS) WS hold time Master mode 2 -
tsu(WS) WS setup time Slave mode 7 -
th(WS) WS hold time Slave mode 0 -
DuCy(SCK) I2S slave input clock duty
cycle Slave mode 25 75 %
DocID025832 Rev 5 87/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
Figure 31. I2S slave timing diagram (Philips protocol)
1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
tsu(SD_MR) Data input setup time
Master receiver 6 -
ns
tsu(SD_SR) Slave receiver 2 -
th(SD_MR)(2)
Data input hold time
Master receiver 4 -
th(SD_SR)(2) Slave receiver 0.5 -
tv(SD_MT)(2)
Data output valid time
Master transmitter - 4
tv(SD_ST)(2) Slave transmitter - 20
th(SD_MT) Data output hold time
Master transmitter 0 -
th(SD_ST) Slave transmitter 13 -
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
Table 64. I2S characteristics(1) (continued)
Symbol Parameter Conditions Min Max Unit
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Electrical characteristics STM32F042x4 STM32F042x6
88/117 DocID025832 Rev 5
Figure 32. I2S master timing diagram (Philips protocol)
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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DocID025832 Rev 5 89/117
STM32F042x4 STM32F042x6 Electrical characteristics
89
USB characteristics
The STM32F042x4/x6 USB interface is fully compliant with the USB specification version
2.0 and is USB-IF certified (for Full-speed device operation).
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
Table 65. USB electrical characteristics
Symbol Parameter Conditions Min. Typ Max. Unit
VDDIO2
USB transceiver operating
voltage -3.0
(1)
1. The STM32F042x4/x6 USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V voltage range.
-3.6V
tSTARTUP(2)
2. Guaranteed by design, not tested in production.
USB transceiver startup time - - - 1.0 µs
RPUI
Embedded USB_DP pull-up
value during idle - 1.1 1.26 1.5
kΩ
RPUR
Embedded USB_DP pull-up
value during reception - 2.0 2.26 2.6
ZDRV(2) Output driver impedance(3)
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
Driving high
and low 28 40 44 Ω
Package information STM32F042x4 STM32F042x6
90/117 DocID025832 Rev 5
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 33. LQFP48 package outline
1. Drawing is not to scale.
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DocID025832 Rev 5 91/117
STM32F042x4 STM32F0 42x6 Package information
113
Figure 34. Recommended footprint for LQFP48 package
1. Dimensions are expressed in millimeters.
Ta ble 66. LQFP48 package mechan ic a l da ta
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
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Package information STM32F042x4 STM32F042x6
92/117 DocID025832 Rev 5
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 35. LQFP48 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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7.2 UFQFPN48 package information
UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 36. UFQFPN48 package outline
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
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Figure 37. Recommended footprint for UFQFPN48 package
1. Dimensions are expressed in millimeters.
Table 67. UFQFPN48 package mechanical data
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
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STM32F042x4 STM32F0 42x6 Package information
113
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 38. UFQFPN48 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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7.3 WLCSP36 package information
WLCSP36 is a 36-ball, 2 .605 x 2.703 mm, 0 .4 mm pitch wa fer-le vel chip-scale p ac kage.
Figure 39. WLCSP36 package outline
1. Drawing is not to scale.
Table 68. WLCSP36 package mechanical data
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
A3(2) - 0.025 - - 0.0010 -
b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 2.570 2.605 2.640 0.1012 0.1026 0.1039
E 2.668 2.703 2.738 0.1050 0.1064 0.1078
e - 0.400 - - 0.0157 -
e1 - 2.000 - - 0.0787 -
e2 - 2.000 - - 0.0787 -
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STM32F042x4 STM32F0 42x6 Package information
113
Figure 40. Recommended pad footprint for WLCSP36 package
F - 0.3025 - - 0.0119 -
G - 0.3515 - - 0.0138 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Table 69. WLCSP36 recommended PCB design rules
Dimension Recommended values
Pitch 0.4 mm
Dpad 260 µm max. (circular)
220 µm recommended
Dsm 300 µm min. (for 260 µm diameter pad)
PCB pad design Non-solder mask defined via underbump allowed
Table 68. WLCSP36 package mechanical data (continued)
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
069
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Package information STM32F042x4 STM32F042x6
98/117 DocID025832 Rev 5
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 41. WLCSP36 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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STM32F042x4 STM32F0 42x6 Package information
113
7.4 LQFP32 package information
LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 42. LQFP32 package outline
1. Drawing is not to scale.
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100/117 DocID025832 Rev 5
Figure 43. Recommended footprint for LQFP32 package
1. Dimensions are expressed in millimeters.
Ta ble 70. LQFP32 package mechan ic a l da ta
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.100 - - 0.0039
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DocID025832 Rev 5 101/117
STM32F042x4 STM32F0 42x6 Package information
113
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 44. LQFP32 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
7.5 UFQFPN32 package information
UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.
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102/117 DocID025832 Rev 5
Figure 45. UFQFPN32 package outline
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device
ground and must be connected. It is referred to as pin 0 in Table: Pin definitions.
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STM32F042x4 STM32F0 42x6 Package information
113
Figure 46. Recommended footprint for UFQFPN32 package
1. Dimensions are expressed in millimeters.
Table 71. UFQFPN32 package mechanical data
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
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Package information STM32F042x4 STM32F042x6
104/117 DocID025832 Rev 5
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 47. UFQFPN32 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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STM32F042x4 STM32F0 42x6 Package information
113
7.6 UFQFPN28 package information
UFQFPN28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 48. UFQFPN28 package outline
1. Drawing is not to scale.
Table 72. UFQFPN28 package mechanical data(1)
Symbol millimeters inches
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 - 0.000 0.050 - 0.0000 0.0020
D 3.900 4.000 4.100 0.1535 0.1575 0.1614
D1 2.900 3.000 3.100 0.1142 0.1181 0.1220
E 3.900 4.000 4.100 0.1535 0.1575 0.1614
E1 2.900 3.000 3.100 0.1142 0.1181 0.1220
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
L1 0.250 0.350 0.450 0.0098 0.0138 0.0177
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
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Figure 49. Recommended footprint for UFQFPN28 package
1. Dimensions are expressed in millimeters.
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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DocID025832 Rev 5 107/117
STM32F042x4 STM32F0 42x6 Package information
113
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 50. UFQFPN28 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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108/117 DocID025832 Rev 5
7.7 TSSOP20 package information
TSSOP20 is a 20-lead thin shrink small-outline , 6.5 x 4.4 mm, 0.65 mm pitch, package.
Figure 51.TSSO P2 0 package outline
1. Drawing is not to scale.
Table 73. TSSOP20 package mechanical data
Symbol millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
D(2) 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
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STM32F042x4 STM32F0 42x6 Package information
113
Figure 52. Recommended footprint for TSSOP20 package
1. Dimensions are expressed in millimeters.
L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Table 73. TSSOP20 package mechanical data (continued)
Symbol millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
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Package information STM32F042x4 STM32F042x6
110/117 DocID025832 Rev 5
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 53. TSSOP20 package marking example
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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STM32F042x4 STM32F0 42x6 Package information
113
7.8 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 21: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•TA max is the maximum ambient temperature in °C,
•ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
7.8.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.8.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Table 74. Packa g e th e rma l cha r ac te ris tic s
Symbol Parameter Value Unit
ΘJA
Thermal resistance junction-ambient
LQFP48 - 7 mm x 7 mm 55
°C/W
Thermal resistance junction-ambient
UFQFPN48 - 7 mm x 7 mm 33
Thermal resistance junction-ambient
WLCSP36 2.6 mm x 2.7 mm 64
Thermal resistance junction-ambient
LQFP32 - 7 mm x 7 mm 57
Thermal resistance junction-ambient
UFQFPN32 - 5 mm x 5 mm 38
Thermal resistance junction-ambient
UFQFPN28 - 4 mm x 4 mm 118
Thermal resistance junction-ambient
TSSOP20 - 6.5 mm x 6.4 mm 76
Package information STM32F042x4 STM32F042x6
112/117 DocID025832 Rev 5
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F042x4/x6 at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
DocID025832 Rev 5 113/117
STM32F042x4 STM32F042x6 Ordering information
113
8 Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 75. Ordering information scheme
Example: STM32 F 042 C 6 T 6 xxx
Device fam ily
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
042 = STM32F042xx
Pin count
F = 20 pins
G = 28 pins
K = 32 pins
T = 36 pins
C = 48 pins
User code memory size
4 = 16 Kbyte
6 = 32 Kbyte
Package
P = TSSOP
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
Revision histor y STM32F042x4 STM32F042x6
114/117 DocID025832 Rev 5
9 Revision history
Table 76. Document revision history
Date Revision Changes
25-Feb-2014 1 Initial release.
03-Apr-2014 2
Added the sample engineering sections for all the packages in the
chapter Package information:
Updated tables:
– STM32F042x4/x6 USART implementation: added one table
footnote.
– STM32F042x pin definitions,
– Current characteristics,
– Typical and maximum current consumption from VDD supply at VDD
= 3.6 V,
– Typical and maximum current consumption from the VDDA supply,
– Typical and maximum consumption in Stop and Standby modes,
– Typical and maximum current consumption from the VBAT supply,
– Typical current consumption, code executing from Flash, running
from HSE 8 MHz crystal,
– Flash memory characteristics,
– I/O static characteristics,
– I/O current injection susceptibility,
– EMS characteristics,
– EMI characteristics,
Updated figures:
– UFQFPN32 32-pin package pinout,
– UQFPN28 28-pin package,
– Power supply scheme,
– TC and TTa I/O input characteristics,
– Five volt tolerant (FT and FTf) I/O input characteristics.
– LQFP48 marking example (package top view),
– UFQFPN48 marking example (package top view),
– WLCSP36 marking example (package top view),
– LQFP32 marking example (package top view),
– UFQFPN28 marking example (package top view),
– UFQFPN32 marking example (package top view),
– TSSOP20 marking example (package top view)
26-Oct-2015 3
Cover page: number of I/Os and timers updated.
Updates in Section 2: Descrip tion:
– updated Figure 1 : Block dia gram
Updates in Section 3: Functional overview:
– updated Figure 2: Clock tree
– addition of the number of complementary outputs for the advanced
control timer and for TIM16, TIM17 general purpose timers in
Table 7: Timer feat u re co mparison
– removal of USART2 from Figure 3.5.4: Low-power modes
DocID025832 Rev 5 115/117
STM32F042x4 STM32F042x6 Revision history
116
26-Oct-2015 3
–Table 9: STM32F042x4/x6 I2C implementation - adding 20 mA
Updates in Section 4: Pinouts and pin descriptions
–Table 12: Legend/abbreviations used in the pinout table - removing
“I” pin type
Updates in Section 5: Memory mapping:
–Figure 10: STM32F042x6 memory map, x4 difference described in
text
Updates in Section 6: Electrical chara cteristics:
– the condition “Regulator in run mode, all oscillators OFF” in Table 28:
Typical and maximum consumption in Stop and St andby modes,
– footnote for VIN max value in Table 18: Voltage characteristics,
– footnote for max VIN in Table 21: Genera l operating conditi ons,
–t
START parameter definition in Table 25: Embedded internal
reference voltage
– addition of tSTART parameter in Table 25: Embedded internal
reference voltage, removal of -40°C to 85°C condition and the
associated footnote
–Table 26: Typical and maximum current consumptio n from VDD
supply at VDD = 3.6 V: removing “code executing from Flash or
RAM”
– removal of the min value for tSTART parameter in Table 57: TS
characteristics
– the typical value for R parameter in Table 58: VBAT monitoring
characteristics
– removal of ResTM parameter line from Table 59: TIMx characteristics
and putting all values in new Typ column, substitution of tCOUNTER
with tMAX_COUNT, values defined as powers of two
–V
ESD(CDM) class in Table 47: ESD absolute maximum ratings
– reorganization of Table 64: I2S characteristics and filling max value
of tv(SD_ST)
– adding definition of levels in Figure 32: I2S master timing diagram
(Philips protocol)
Updates in Section 7: Package information:
– heading and display of columns in Table 68: WLCSP36 package
mechanical da ta.,
– Figure 38: UFQFPN48 package marking example
– Figure 41: WLC SP3 6 package marki n g example
– Figure 50: UFQFPN28 package marking example
– Figure 41: WLC SP3 6 package marki n g example
–Figure 51: TSSOP20 package outline - correcting GAGE to GAUGE
– removing “die 445” from Table 74: Package thermal characteristics
Updates in Section 8: Part numbering:
– adding tray packing to options
Table 76. Document revision history (continued)
Date Revision Changes
Revision histor y STM32F042x4 STM32F042x6
116/117 DocID025832 Rev 5
16-Dec-2015 4
Section 3: Functional overview:
–Figure 2: Clock tree modified
Section 4: Pinouts and pin descriptions:
– Package pinout figures updated (look and feel)
–Figure 5: WLCSP36 package pinout- now presented in top view
–Table 13: STM32F042x pin definitions - note 3 added; CIMP1_OUT
and USART4_CTS removed
–Table 15: Alternate fu nctions selected through GPIOB_AFR
registers for port B - change of I2C2_SDA and I2C2_SCL to
I2C1_SDA and I2C1_SCL
Section 5: Memory mapping:
–Table 17: STM32F042x4/x6 peripheral register boundary addresses
- change of “SYSCFG + COMP” to “SYSCFG”
Section 6: Electrical charac teristics:
–Table 50: I/O static characteristi c s- removed note
–Section 6.3.16: 12-bit ADC characteristics - changed introductory
sentence
Section 7: Package information:
–Figure 49: Recommended foo tprint for UFQFPN28 package
distance between corner pads added
10-Jan-2017 5
Section 6: Electrical charac teristics:
–Table 37: LSE oscillator characteri stics (fLSE = 32.768 kHz) -
information on configuring different drive capabilities removed. See
the corresponding reference manual.
–Table 25: Embedde d internal reference voltage - VREFINT values
–Figure 28: SPI timing diagram - slave mode and CPHA = 0 and
Figure 29: SPI timing diagram - slave mode and CPHA = 1
enhanced and corrected
Section 8: Ordering information:
– The name of the section changed from the previous “Part
numbering”
Table 76. Document revision history (continued)
Date Revision Changes
DocID025832 Rev 5 117/117
STM32F042x4 STM32F042x6
117
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