TPS795xx www.ti.com SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 500-mA LOW-DROPOUT LINEAR REGULATORS Check for Samples: TPS795xx FEATURES 1 * * * * * * * DESCRIPTION 500-mA Low-Dropout Regulator With Enable Available in Fixed and Adjustable (1.2-V to 5.5-V) Versions High PSRR (50 dB at 10 kHz) Ultralow Noise (33 mVRMS, TPS79530) Fast Start-Up Time (50 ms) Stable With a 1-mF Ceramic Capacitor Excellent Load/Line Transient Response Low Dropout Voltage (110 mV at Full Load, TPS79530) 6-Pin SOT223 and 3 x 3 SON Packages The TPS795xx family of low-dropout (LDO), low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-6 and 3 x 3 SON packages. Each device in the family is stable with a small 1-mF ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (for example, 110 mV at 500 mA). Each device achieves fast start-up times (approximately 50 ms with a 0.001-mF bypass capacitor) while consuming very low quiescent current (265 mA, typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 mA. The TPS79530 exhibits approximately 33 mVRMS of output voltage noise at 3-V output with a 0.1-mF bypass capacitor. Applications with analog components that are noise-sensitive, such as portable RF electronics, benefit from the high-PSRR and low-noise features, as well as from the fast response time. APPLICATIONS * * * * * RF: VCOs, Receivers, ADCs Audio Bluetooth(R), Wireless LAN Cellular and Cordless Telephones Handheld Organizers, PDAs DRB PACKAGE 3mm x 3mm SON (TOP VIEW) IN 2 DCQ PACKAGE OUT 3 OUT 4 SOT223-6 (TOP VIEW) EN IN GND OUT NR/FB 1 2 3 4 5 8 EN 7 NC 6 GND 5 NR/FB 6 GND TPS79530 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 80 0.5 VIN = 4 V COUT = 10 mF CNR = 0.01 mF 70 Ripple Rejection - dB IN 1 TPS79530 RIPPLE REJECTION vs FREQUENCY Output Spectral Noise Density - mV/OHz * * 23 IOUT = 1 mA 60 50 40 IOUT = 500 mA 30 20 10 0 1 10 100 1 k 10 k 100 k 1 M Frequency (Hz) 10 M VIN = 5.5 V COUT = 2.2 mF CNR = 0.1 mF 0.4 0.3 IOUT = 1 mA 0.2 IOUT = 0.5 A 0.1 0 100 1k 10 k Frequency (Hz) 100 k 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2010, Texas Instruments Incorporated TPS795xx SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS795xx yyy z (1) (2) VOUT (2) XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS over operating temperature (unless otherwise noted) (1) VALUE VIN range -0.3 V to 6 V VEN range -0.3 V to VIN + 0.3 V VOUT range 6V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See the Thermal Information Table Junction temperature range, TJ -40C to +150C Storage temperature range, Tstg -65C to +150C (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx TPS795xx www.ti.com SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 THERMAL INFORMATION TPS795xx (3) THERMAL METRIC (1) (2) qJA Junction-to-ambient thermal resistance (4) qJCtop Junction-to-case (top) thermal resistance (5) (6) DRB (8 PINS) DCQ (6 PINS) 47.8 70.4 83 70 n/a n/a 2.1 6.8 qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter (7) yJB Junction-to-board characterization parameter (8) 17.8 30.1 (9) 12.1 6.3 qJCbot (1) (2) (3) (4) (5) (6) (7) (8) (9) Junction-to-case (bottom) thermal resistance UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. (b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. . ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in x 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx 3 TPS795xx SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating temperature range (TJ = -40C to +125C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT = 10 mF, CNR = 0.01 mF, unless otherwise noted. Typical values are at +25C. PARAMETER Input voltage, VIN TEST CONDITIONS MIN (1) Internal reference, VFB (TPS79501) 1.200 Continuous output current, IOUT Output voltage range Output voltage Accuracy TPS79501 0.98(VOUT) 0 mA IOUT 500 mA, VOUT + 1 V VIN 5.5 V (1) -2.0 Fixed VOUT VOUT + 1 V VIN 5.5 V Load regulation (VOUT%/IOUT) 0 mA IOUT 500 mA, Dropout voltage VIN = VOUT(nom) - 0.1 V 1.225 1.250 500 1.225 TPS79501 (2) 0 mA IOUT 500 mA, VOUT + 1 V VIN 5.5 V (1) MAX 5.5 0 Output voltage line regulation (VOUT%/VIN) (1) (3) TYP 2.7 5.5 - VDO VOUT 0.05 V V mA V 1.02(VOUT) V +2.0 % 0.12 %/V 3 mV TPS79530 IOUT = 500 mA 110 170 TPS79533 IOUT = 500 mA 105 160 mV Output current limit VOUT = 0 V 2.8 4.2 A Ground pin current 0 mA IOUT 500 mA 265 385 mA Shutdown current (4) VEN = 0 V, 2.7 V VIN 5.5 V 0.07 1 mA FB pin current VFB = 1.225 V 1 mA Power-supply ripple rejection TPS79530 2.4 UNIT f = 100 Hz, IOUT = 10 mA 59 f = 100 Hz, IOUT = 500 mA 58 f = 10 kHz, IOUT = 500 mA 50 f = 100 kHz, IOUT = 500 mA Output noise voltage (TPS79530) Time, start-up (TPS79530) BW = 100 Hz to 100 kHz, IOUT = 500 mA RL = 6 , COUT = 1 F 39 CNR = 0.001 mF 46 CNR = 0.0047 F 41 CNR = 0.01 mF 35 CNR = 0.1 mF 33 CNR = 0.001 mF 50 CNR = 0.0047 mF ms 110 High-level enable input voltage 2.7 V VIN 5.5 V Low-level enable input voltage 2.7 V VIN 5.5 V EN pin current VEN = 0 V 1 UVLO threshold VCC rising 2.25 1.7 UVLO hysteresis 4 mVRMS 75 CNR = 0.01 mF (1) (2) (3) (4) dB VIN V 1 mA 2.65 100 V 0.7 V mV Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater. Tolerance of external resistors not included in this specification. Dropout is not measured for the TPS79501 and TPS79525 since minimum VIN = 2.7 V. For adjustable version, this applies only after VIN is applied; then VEN transitions high to low. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx TPS795xx www.ti.com SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 FUNCTIONAL BLOCK DIAGRAM--ADJUSTABLE VERSION IN OUT 300 Current Sense UVLO Overshoot Detect GND ILIM SHUTDOWN R1 EN FB UVLO Thermal Shutdown R2 Quickstart Bandgap Reference 1.225 V VIN External to the Device VREF 250 k FUNCTIONAL BLOCK DIAGRAM--FIXED VERSION IN OUT 300 Current Sense UVLO Overshoot Detect GND ILIM SHUTDOWN R1 EN UVLO Thermal Shutdown R2 R2 = 40 k Quickstart VIN Bandgap Reference 1.225 V VREF NR 250 k Table 1. Terminal Functions SOT223 (DCQ) PIN NO. 3x3 SON (DRB) PIN NO. 2 1, 2 3, 6 6 Regulator ground EN 1 8 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. NR 5 5 Noise-reduction pin for fixed versions only. Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, which improves power-supply rejection and reduces output noise. (Not available on adjustable versions.) FB 5 5 Feedback input voltage for the adjustable device. (Not available on fixed voltage versions.) OUT 4 3, 4 NC - 7 NAME IN GND DESCRIPTION Unregulated input to the device Regulator output. Not connected Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx 5 TPS795xx SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS TPS79530 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS79530 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS79530 GROUND CURRENT vs JUNCTION TEMPERATURE 3.005 3.02 276 VIN = 4 V COUT = 10 F 3 3.01 274 272 IOUT = 1 mA 2.995 VIN = 4 V COUT = 10 F IOUT = 1 mA 3 IGND (A) VOUT (V) VOUT (V) 270 2.99 IOUT = 0.5 A 2.985 2.98 2.99 0 0.1 0.2 0.3 IOUT (mA) 0.4 2.97 0.5 260 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ (C) Figure 3. TPS79530 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS79530 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS79530 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 2.5 0.4 IOUT = 1 mA 0.2 IOUT = 0.5 A 1k 10 k Frequency (Hz) 100 k Figure 4. VIN = 5.5 V COUT = 10 F CNR = 0.1 F 0.5 0.4 Output Spectral Noise Density - V//Hz 0.6 0.1 20 35 50 65 80 95 110 125 Figure 2. Output Spectral Noise Density - V//Hz Output Spectral Noise Density - V//Hz -40 -25 -10 5 Figure 1. VIN = 5.5 V COUT = 2.2 F CNR = 0.1 F 0 100 6 262 TJ (C) 0.5 0.3 IOUT = 0.5 A 266 264 2.975 2.98 268 IOUT = 1 mA 0.3 0.2 IOUT = 0.5 A 0.1 0 100 1k 10 k Frequency (Hz) Figure 5. Submit Documentation Feedback 100 k 2 1.5 CNR = 0.001 F VIN = 5.5 V IOUT = 500 mA COUT= 10 F CNR = 0.0047 F CNR = 0.01 F 1 CNR = 0.1 F 0.5 0 100 1k 10 k 100 k Frequency (Hz) Figure 6. Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx TPS795xx www.ti.com SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) TPS79530 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 50 125 30 20 VIN = 4 V COUT = 10 F CNR = 0.1 F 70 Ripple Rejection - dB 40 100 75 50 IOUT = 1 mA 60 50 40 IOUT = 500 mA 30 20 10 25 10 BW = 100 Hz to 100 kHz 0 0.001 0.01 0.0047 CNR (F) 0 -40 -25 -10 5 0.1 0 20 35 50 65 80 95 110 125 1 TPS79530 RIPPLE REJECTION vs FREQUENCY TPS79530 RIPPLE REJECTION vs FREQUENCY TPS79530 RIPPLE REJECTION vs FREQUENCY 40 IOUT = 500 mA 30 IOUT = 1 mA 60 50 40 30 IOUT = 500 mA 50 40 30 IOUT = 500 mA 20 20 10 10 10 0 0 100 1 k 10 k 100 k 1 M Frequency (Hz) 1 10 M 100 1 k 10 k 100 k 1 M Frequency (Hz) 0 10 M 1 10 100 1 k 10 k 100 k 1 M 10 M Frequency (Hz) Figure 10. Figure 11. Figure 12. TPS79530 START-UP TIME TPS79518 LINE TRANSIENT RESPONSE TPS79530 LINE TRANSIENT RESPONSE 2.25 CNR = 0.01 F 2 Enable 1.75 20 30 10 20 VOUT (mV) CNR = 0.0047 F VOUT (mV) CNR = 0.001 F 2.50 10 IOUT = 1 mA 60 20 10 VIN = 4 V COUT = 2.2 F CNR = 0.1 F 70 Ripple Rejection - dB Ripple Rejection - dB IOUT = 1 mA 10 M 80 VIN = 4 V COUT = 2.2 F CNR = 0.01 F 70 50 3 1 k 10 k 100 k 1 M Frequency (Hz) Figure 9. 60 2.75 100 Figure 8. 80 1 10 TJ (C) Figure 7. VIN = 4 V COUT = 10 F CNR = 0.01 F 70 0 -10 1.50 10 0 -10 -20 1.25 1 COUT = 10 F, CNR = 0.01 F, IOUT = 0.5 A, dv/dt = 1 V/s 0.75 VIN = 4 V COUT = 10 F IOUT = 0.5 A 0.50 0.25 0 0 100 200 300 400 500 600 t (s) Figure 13. VIN (V) 4 -20 VIN (V) Ripple Rejection - dB 80 VIN = 2.9 V COUT = 10 F IOUT = 500 mA 150 80 VIN (V) TPS79530 RIPPLE REJECTION vs FREQUENCY 175 IOUT = 500 mA COUT= 10 F VDO (mV) RMS - Root Mean Squared Output Noise - VRMS TPS79530 ROOT MEAN SQUARED OUTPUT NOISE vs CNR 3 COUT = 10 F, CNR = 0.01 F, IOUT = 0.5 A, dv/dt = 1 V/s 5 4 3 2 0 50 100 150 t (s) Figure 14. 200 0 50 100 t (s) 150 Figure 15. Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx 200 7 TPS795xx SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS79530 LOAD TRANSIENT RESPONSE TPS79525 POWER UP/POWER DOWN 4.5 40 4 20 3.5 160 -40 -60 TJ = 25C 2 1.5 COUT = 10 F, CNR = 0.01 F, VL = 3.8 V, dv/dt = 0.5 A/s 100 80 60 VOUT 1 0.5 40 0 0 20 -0.5 -0.5 0.5 0 200 400 600 800 0 1000 400 800 t (s) 1200 1600 TJ = -40C 0 2000 0 100 200 300 IOUT (mA) Time (s) 400 500 Figure 16. Figure 17. Figure 18. TPS79501 DROPOUT VOLTAGE vs INPUT VOLTAGE TPS79530 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT TPS79530 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT 100 200 150 100 COUT = 1 F COUT = 10 F, CNR = 0.01 F, IOUT = 50 mA COUT = 2.2 F Region of Instability 10 TJ = 25C 50 1 Region of Stability 0.1 TJ = -40C 3 3.5 4 VIN (V) 4.5 0 5 100 Figure 19. 1 Region of Stability 0.1 0.01 0 200 300 IOUT (mA) 400 Region of Instability 10 ESR (W) 100 ESR (W) TJ = 125C 2.5 TJ = 125C 120 2.5 VOUT (V) -20 140 VIN 3 0 IOUT (A) 180 VOUT = 2.5 V, RL = 10 VDO (mV) DVOUT (mV) 60 VDO (mV) TPS79530 DROPOUT VOLTAGE vs OUTPUT CURRENT 500 0.01 1 10 100 1000 IOUT (mA) Figure 20. Figure 21. TPS79530 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT 100 COUT = 10 F ESR (W) 10 Region of Instability 1 Region of Stability 0.1 0.01 0 100 200 300 400 500 IOUT (A) Figure 22. 8 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx TPS795xx www.ti.com SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 APPLICATION INFORMATION The TPS795xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 mA typical), and an enable input to reduce supply currents to less than 1 mA when the regulator is turned off. A typical application circuit is shown in Figure 23. VIN IN VOUT OUT TPS795xx 1mF EN GND 1mF NR 0.01mF Figure 23. Typical Application Circuit order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1-mF in order to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the Functional Block Diagram. For example, the TPS79530 exhibits only 33 mVRMS of output voltage noise using a 0.1-mF ceramic bypass capacitor and a 10-mF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases because of the RC time constant at the bypass pin that is created by the internal 250-k resistor and external capacitor. EXTERNAL CAPACITOR REQUIREMENTS BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE Although not required, it is good analog design practice to place a 0.1mF to 2.2mF capacitor near the input of the regulator to counteract reactive input sources. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. To improve ac measurements such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device. Like most low-dropout regulators, the TPS795xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitor is 1 mF. Any 1 mF or larger ceramic capacitor is suitable. REGULATOR MOUNTING The internal voltage reference is a key source of noise in an LDO regulator. The TPS795xx has an NR pin which is connected to the voltage reference through a 250-k internal resistor. The 250-k internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation. Solder pad footprint recommendations for the devices are presented in application report SBFA015, Solder Pad Recommendations for Surface-Mount Devices, available from the TI web site (www.ti.com). Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx 9 TPS795xx SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 www.ti.com PROGRAMMING THE TPS79501 ADJUSTABLE LDO REGULATOR The approximate value of this capacitor can be calculated as Equation 3: (3 10 *7) (R 1 ) R 2) C1 + (R 1 R 2) (3) The output voltage of the TPS79501 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using Equation 1: V OUT + VREF 1 ) RR The suggested value of this capacitor for several resistor ratios is shown in the table within Figure 24. If this capacitor is not used (such as in a unity-gain configuration), then the minimum recommended output capacitor is 2.2 mF instead of 1 mF. 1 2 (1) where: * VREF = 1.2246 V typ (the internal reference voltage) REGULATOR PROTECTION The TPS795xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. Resistors R1 and R2 should be chosen for approximately 40-mA divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error. The TPS795xx features internal current limiting and thermal protection. During normal operation, the TPS795xx limits output current to approximately 2.8 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately +165C, thermal protection circuitry shuts it down. Once the device has cooled down to below approximately +140C, regulator operation resumes. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 40 mA, C1 = 15 pF for stability, and then calculate R1 using Equation 2: R1 + VV OUT REF *1 R2 (2) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. VIN IN 1mF EN OUT TPS79501 GND OUTPUT VOLTAGE PROGRAMMING GUIDE VOUT R1 FB C1 1mF OUTPUT VOLTAGE R1 R2 C1 1.8 V 14.0 kW 30.1 kW 33 pF 3.6 V 57.9 kW 30.1 kW 15 pF R2 Figure 24. TPS79501 Adjustable LDO Regulator Programming 10 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx TPS795xx www.ti.com SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 THERMAL INFORMATION Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: P D + VIN * VOUT I OUT (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On the SOT-223 (DCQ) package, the primary conduction path for heat is through the tab to the PCB. The tab should be connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5: ()125OC * T A) R qJA + PD (5) Knowing the maximum RqJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 25. 160 140 Figure 25 shows the variation of qJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effect of heat spreading in the ground plane and should not be used to estimate the thermal performance in real application environments. NOTE: When the device is mounted on an application PCB, it is strongly recommended to use JT and JB, as explained in the Estimating Junction Temperature section. ESTIMATING JUNCTION TEMPERATURE Using the thermal metrics JT and JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older qJC,Top parameter is also listed. YJT: TJ = TT + YJT * PD YJB: TJ = TB + YJB * PD (6) Where PD is the power dissipation shown by Equation 5, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (as Figure 27 shows). NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com. By looking at Figure 26, the new thermal metrics (JT and JB) have little dependency on board size. That is, using JT or JB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 35 100 DRB YJT 80 DCQ 30 60 DRB 25 40 20 0 0 2 4 6 2 Board Copper Area (in ) 8 10 YJT and YJB (C/W) qJA (C/W) 120 DRB YJB 20 15 DCQ YJT DCQ YTB 10 5 Note: qJA value at board size of 9 in2 (that is, 3 in x 3 in) is a JEDEC standard. 0 0 space 1 2 3 4 5 6 7 8 9 10 2 Figure 25. qJA vs Board Size Board Copper Area (in ) Figure 26. JT and JB vs Board Size Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx 11 TPS795xx SLVS350H - OCTOBER 2002 - REVISED AUGUST 2010 www.ti.com For a more detailed discussion of why TI does not recommend using qJC(top) to determine thermal characteristics, see the application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, see the application report SPRA953, IC Package Thermal Metrics, also available on the TI website. 1mm TT on Top of IC Surface X X TB TT TB on PCB 1mm (a) Example DRB (SON) Package Measurement (b) Example DCQ (SOT-223) Package Measurement Figure 27. Measuring Point for TT and TB SPACER REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (July, 2006) to Revision H Page * Replaced the Dissipation Ratings table with the Thermal Information Table ....................................................................... 3 * Updated the Thermal Information section ........................................................................................................................... 11 12 Submit Documentation Feedback Copyright (c) 2002-2010, Texas Instruments Incorporated Product Folder Link(s): TPS795xx PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) TPS79501DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS79501DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS79501DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79501DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79501DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79501DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79516DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79516DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79516DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79516DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79518DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79518DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79518DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79518DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79525DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79525DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79525DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 17-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS79525DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79530DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79530DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79530DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79530DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS79533DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS79533DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS79501 : * Automotive: TPS79501-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS79501DCQR SOT-223 DCQ 6 2500 330.0 12.4 TPS79501DRBR SON DRB 8 3000 330.0 TPS79501DRBT SON DRB 8 250 180.0 TPS79516DCQR SOT-223 DCQ 6 2500 TPS79518DCQR SOT-223 DCQ 6 TPS79525DCQR SOT-223 DCQ TPS79530DCQR SOT-223 DCQ TPS79533DCQR SOT-223 DCQ 6.8 7.3 1.88 8.0 12.0 Q3 12.4 3.3 3.3 1.1 8.0 12.0 Q2 12.4 3.3 3.3 1.1 8.0 12.0 Q2 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS79501DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79501DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS79501DRBT SON DRB 8 250 210.0 185.0 35.0 TPS79516DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79518DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79525DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79530DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS79533DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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