0
10
20
30
40
50
60
70
80
1 10 100 1k 10k 100k 1M 10M
RippleRejection − dB
TPS79530
RIPPLEREJECTION
vs
FREQUENCY
VIN =4V
COUT =10 mF
CNR =0.01 mFIOUT =1mA
IOUT =500mA
Frequency (Hz) Frequency(Hz)
0
0.1
0.2
0.3
0.4
0.5
100 1k 10k 100k
IOUT =1mA
VIN =5.5V
COUT =2.2 mF
CNR =0.1 mF
IOUT =0.5A
TPS79530
OUTPUT SPECTRALNOISEDENSITY
vs
FREQUENCY
OutputSpectralNoiseDensity − mV/ÖHz
1
2
3
4
5
DCQ PACKAGE
SOT223-6
(TOPVIEW)
NR/FB
OUT
GND
IN
EN
6
GND
EN
NC
GND
NR/FB
8
7
6
5
IN
IN
OUT
OUT
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS795xx
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SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 500-mA
LOW-DROPOUT LINEAR REGULATORS
Check for Samples: TPS795xx
1FEATURES DESCRIPTION
23• 500-mA Low-Dropout Regulator With Enable
• Available in Fixed and Adjustable (1.2-V to The TPS795xx family of low-dropout (LDO),
low-power linear voltage regulators features high
5.5-V) Versions power-supply rejection ratio (PSRR), ultralow noise,
• High PSRR (50 dB at 10 kHz) fast start-up, and excellent line and load transient
• Ultralow Noise (33 mVRMS, TPS79530) responses in small outline, SOT223-6 and 3 x 3 SON
• Fast Start-Up Time (50 ms) packages. Each device in the family is stable with a
small 1-mF ceramic capacitor on the output. The
• Stable With a 1-mF Ceramic Capacitor family uses an advanced, proprietary BiCMOS
• Excellent Load/Line Transient Response fabrication process to yield extremely low dropout
• Low Dropout Voltage (110 mV at Full Load, voltages (for example, 110 mV at 500 mA). Each
device achieves fast start-up times (approximately 50
TPS79530) ms with a 0.001-mF bypass capacitor) while
• 6-Pin SOT223 and 3 × 3 SON Packages consuming very low quiescent current (265 mA,
typical). Moreover, when the device is placed in
APPLICATIONS standby mode, the supply current is reduced to less
• RF: VCOs, Receivers, ADCs than 1 mA. The TPS79530 exhibits approximately 33
• Audio mVRMS of output voltage noise at 3-V output with a
0.1-mF bypass capacitor. Applications with analog
• Bluetooth®, Wireless LAN components that are noise-sensitive, such as
• Cellular and Cordless Telephones portable RF electronics, benefit from the high-PSRR
• Handheld Organizers, PDAs and low-noise features, as well as from the fast
response time.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Bluetooth is a registered trademark of Bluetooth SIG, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS795xx
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS795xx yyy zXX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS
over operating temperature (unless otherwise noted)(1)
VALUE
VIN range –0.3 V to 6 V
VEN range –0.3 V to VIN + 0.3 V
VOUT range 6 V
Peak output current Internally limited
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
Continuous total power dissipation See the Thermal Information Table
Junction temperature range, TJ–40°C to +150°C
Storage temperature range, Tstg –65°C to +150°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
THERMAL INFORMATION TPS795xx(3)
THERMAL METRIC(1)(2) UNITS
DRB (8 PINS) DCQ (6 PINS)
qJA Junction-to-ambient thermal resistance(4) 47.8 70.4
qJCtop Junction-to-case (top) thermal resistance(5) 83 70
qJB Junction-to-board thermal resistance(6) n/a n/a °C/W
yJT Junction-to-top characterization parameter(7) 2.1 6.8
yJB Junction-to-board characterization parameter(8) 17.8 30.1
qJCbot Junction-to-case (bottom) thermal resistance(9) 12.1 6.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified
in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
.ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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TPS795xx
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ= –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V(1), IOUT = 1 mA,
COUT = 10 mF, CNR = 0.01 mF, unless otherwise noted. Typical values are at +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage, VIN (1) 2.7 5.5 V
Internal reference, VFB (TPS79501) 1.200 1.225 1.250 V
Continuous output current, IOUT 0 500 mA
Output voltage range TPS79501 1.225 5.5 – VDO V
Output TPS79501(2) 0mA≤IOUT ≤500 mA, VOUT + 1 V ≤VIN ≤5.5 V(1) 0.98(VOUT) VOUT 1.02(VOUT) V
voltage Accuracy Fixed VOUT 0mA≤IOUT ≤500 mA, VOUT + 1 V ≤VIN ≤5.5 V(1) –2.0 +2.0 %
Output voltage line regulation (ΔVOUT%/ΔVIN)(1) VOUT + 1 V ≤VIN ≤5.5 V 0.05 0.12 %/V
Load regulation (ΔVOUT%/ΔIOUT) 0 mA≤IOUT ≤500 mA, 3 mV
TPS79530 IOUT = 500 mA 110 170
Dropout voltage(3) mV
VIN = VOUT(nom) - 0.1 V TPS79533 IOUT = 500 mA 105 160
Output current limit VOUT = 0 V 2.4 2.8 4.2 A
Ground pin current 0 mA≤IOUT ≤500 mA 265 385 mA
Shutdown current(4) VEN = 0 V, 2.7 V ≤VIN ≤5.5 V 0.07 1 mA
FB pin current VFB = 1.225 V 1 mA
f = 100 Hz, IOUT = 10 mA 59
f = 100 Hz, IOUT = 500 mA 58
Power-supply ripple rejection TPS79530 dB
f = 10 kHz, IOUT = 500 mA 50
f = 100 kHz, IOUT = 500 mA 39
CNR = 0.001 mF 46
CNR = 0.0047 µF 41
BW = 100 Hz to 100 kHz,
Output noise voltage (TPS79530) mVRMS
IOUT = 500 mA CNR = 0.01 mF 35
CNR = 0.1 mF 33
CNR = 0.001 mF 50
Time, start-up (TPS79530) RL= 6 Ω, COUT = 1 µF CNR = 0.0047 mF 75 ms
CNR = 0.01 mF 110
High-level enable input voltage 2.7 V ≤VIN ≤5.5 V 1.7 VIN V
Low-level enable input voltage 2.7 V ≤VIN ≤5.5 V 0.7 V
EN pin current VEN = 0 V 1 1 mA
UVLO threshold VCC rising 2.25 2.65 V
UVLO hysteresis 100 mV
(1) Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
(2) Tolerance of external resistors not included in this specification.
(3) Dropout is not measured for the TPS79501 and TPS79525 since minimum VIN = 2.7 V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
4Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS795xx
Current
Sense
Thermal
Shutdown
UVLO
UVLO
R1
FB
R2
External to
the Device
Overshoot
Detect
250 kΩ
Quickstart
Bandgap
Reference
1.225 V
IN
VIN
EN
GND
OUT
300Ω
VREF
ILIM SHUTDOWN
Current
Sense
Thermal
Shutdown
UVLO
UVLO
R1
R2
R2= 40 kΩ
Overshoot
Detect
250 kΩ
Quickstart
Bandgap
Reference
1.225 V
IN
VIN
EN
GND
NR
OUT
300Ω
VREF
ILIM SHUTDOWN
TPS795xx
www.ti.com
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
Table 1. Terminal Functions
SOT223 (DCQ) 3x3 SON (DRB)
NAME PIN NO. PIN NO. DESCRIPTION
IN 2 1, 2 Unregulated input to the device
GND 3, 6 6 Regulator ground
EN 1 8 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. EN can be connected to IN if not used.
NR 5 5 Noise-reduction pin for fixed versions only. Connecting an external capacitor to this pin bypasses
noise generated by the internal bandgap, which improves power-supply rejection and reduces
output noise. (Not available on adjustable versions.)
FB 5 5 Feedback input voltage for the adjustable device. (Not available on fixed voltage versions.)
OUT 4 3, 4 Regulator output.
NC – 7 Not connected
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Product Folder Link(s): TPS795xx
2.98
2.99
3
3.01
3.02
0 0.1 0.2 0.3 0.4 0.5
IOUT (mA)
VOUT (V)
−40−25−10 5 20 35 50 65 80 95 110 125
TJ (°C)
IOUT = 1 mA
VIN = 4 V
COUT = 10 µF
IOUT = 0.5 A
260
262
264
266
268
270
272
274
276
IGND (µA)
−40−25−10 5 20 35 50 65 80 95 110 125
TJ (°C)
IOUT = 0.5 A
IOUT = 1 mA
VIN = 4 V
COUT = 10 µF
2.97
2.975
2.98
2.985
2.99
2.995
3
3.005
VOUT (V)
0
0.1
0.2
0.3
0.4
0.5
100 1 k 10 k 100 k
Frequency (Hz)
IOUT = 1 mA
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
IOUT = 0.5 A
Output Spectral Noise Density − µV//Hz
100 1 k 10 k 100 k
Frequency (Hz)
VIN = 5.5 V
IOUT = 500 mA
COUT= 10 µF
CNR = 0.1 µF
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
0
0.5
1
1.5
2
2.5
Output Spectral Noise Density − µV//Hz
TPS795xx
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS
TPS79530 TPS79530 TPS79530
OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
vs vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
TPS79530 TPS79530 TPS79530
OUTPUT SPECTRAL OUTPUT SPECTRAL OUTPUT SPECTRAL
NOISE DENSITY NOISE DENSITY NOISE DENSITY
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
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−40−25−10 5 20 35 50 65 80 95 110 125
VIN = 2.9 V
COUT = 10 µF
IOUT = 500 mA
TJ (°C)
25
50
75
100
125
150
175
0
VDO (mV)
0
10
20
30
40
50
0.001 0.0047 0.01 0.1
CNR (µF)
IOUT = 500 mA
COUT= 10 µF
BW = 100 Hz to 100 kHz
RMS − Root Mean Squared Output Noise − µVRMS
0
10
20
30
40
50
60
70
80
1 10 100 1 k 10 k 100 k 1 M 10 M
Ripple Rejection − dB
IOUT = 1 mA
VIN = 4 V
COUT = 10 µF
CNR = 0.1 µF
IOUT = 500 mA
Frequency (Hz)
0
10
20
30
40
50
60
70
80
1 10 100 1 k 10 k 100 k 1 M 10 M
Ripple Rejection − dB
VIN = 4 V
COUT = 2.2 µF
CNR = 0.01 µFIOUT = 1 mA
IOUT = 500 mA
Frequency (Hz)
Ripple Rejection − dB
0
10
20
30
40
50
60
70
80
1 10 100 1 k 10 k 100 k 1 M 10 M
IOUT = 500 mA
IOUT = 1 mA
VIN = 4 V
COUT = 2.2 µF
CNR = 0.1 µF
Frequency (Hz)
0
10
20
30
40
50
60
70
80
1 10 100 1 k 10 k 100 k 1 M 10 M
Ripple Rejection − dB
VIN = 4 V
COUT = 10 µF
CNR = 0.01 µFIOUT = 1 mA
IOUT = 500 mA
Frequency (Hz)
3
4
5
0 50 100 150 200
−10
0
10
20
30
t (µs)
COUT = 10 µF, CNR = 0.01 µF,
IOUT = 0.5 A, dv/dt = 1 V/µs
−20
VOUT (mV)
VIN (V)
0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
2.75
3
0100 200 300 400 600
Enable
t (µs)
VIN = 4 V
COUT = 10 µF
IOUT = 0.5 A
CNR = 0.01 µF
CNR = 0.001 µF
CNR = 0.0047 µF
500
VIN (V)
2.25
2.50
2
3
4
0 50 100 150 200
−20
−10
0
10
20
t (µs)
COUT = 10 µF, CNR = 0.01 µF,
IOUT = 0.5 A, dv/dt = 1 V/µs
VIN (V) VOUT (mV)
TPS795xx
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SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
TPS79530 TPS79530 TPS79530
ROOT MEAN SQUARED DROPOUT VOLTAGE RIPPLE REJECTION
OUTPUT NOISE
vs vs vs
CNR JUNCTION TEMPERATURE FREQUENCY
Figure 7. Figure 8. Figure 9.
TPS79530 TPS79530 TPS79530
RIPPLE REJECTION RIPPLE REJECTION RIPPLE REJECTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
TPS79530 TPS79518 TPS79530
START-UP TIME LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 13. Figure 14. Figure 15.
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−0.5
0
0.5
0 200 400 600 800 1000
−40
−20
0
40
t (µs)
COUT = 10 µF, CNR = 0.01 µF,
VL = 3.8 V, dv/dt = 0.5 A/µs
20
−60
60
DVOUT (mV)IOUT (A)
Time (µs)
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN
VOUT
VOUT = 2.5 V,
RL = 10 Ω
VOUT (V)
4000 800 1200 1600 2000
0
20
40
60
80
100
120
140
160
180
0 100 200 300 400 500
TJ = 125°C
TJ = 25°C
TJ = −40°C
IOUT (mA)
VDO (mV)
0.01
0.1
1
10
100
0 100 200 300 400 500
IOUT (mA)
COUT = 1 µF
ESR (W)
Region of Stability
Region of
Instability
0
50
100
150
200
2.5 3 3.5 4 4.5 5
VIN (V)
TJ = 25°C
TJ = −40°C
TJ = 125°C
COUT = 10 µF,
CNR = 0.01 µF,
IOUT = 50 mA
VDO (mV)
0.01
0.1
1
10
100
1 10 100 1000
IOUT (mA)
COUT = 2.2 µF
ESR (W)
Region of Stability
Region of
Instability
0.01
0.1
1
10
100
0 100 200 300 400 500
IOUT (A)
COUT = 10 µF
ESR (W)
Region of Stability
Region of
Instability
TPS795xx
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued) TPS79530
DROPOUT VOLTAGE
TPS79530 TPS79525 vs
LOAD TRANSIENT RESPONSE POWER UP/POWER DOWN OUTPUT CURRENT
Figure 16. Figure 17. Figure 18.
TPS79530 TPS79530
TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY
TPS79501 EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE
DROPOUT VOLTAGE (ESR) (ESR)
vs vs vs
INPUT VOLTAGE OUTPUT CURRENT OUTPUT CURRENT
Figure 19. Figure 20. Figure 21.
TPS79530
TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
Figure 22.
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Product Folder Link(s): TPS795xx
TPS795xx
GNDEN NR
IN OUT
VIN VOUT
1 Fm
0.01 Fm
1 Fm
TPS795xx
www.ti.com
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
APPLICATION INFORMATION
order for the regulator to operate properly, the current
The TPS795xx family of low-dropout (LDO) regulators flow out of the NR pin must be at a minimum,
has been optimized for use in noise-sensitive because any leakage current creates an IR drop
equipment. The device features extremely low across the internal resistor, thus creating an output
dropout voltages, high PSRR, ultralow output noise, error. Therefore, the bypass capacitor must have
low quiescent current (265 mA typical), and an enable minimal leakage current. The bypass capacitor
input to reduce supply currents to less than 1 mAshould be no more than 0.1-mF in order to ensure that
when the regulator is turned off. it is fully charged during the quickstart time provided
by the internal switch shown in the Functional Block
A typical application circuit is shown in Figure 23.Diagram.
For example, the TPS79530 exhibits only 33 mVRMS
of output voltage noise using a 0.1-mF ceramic
bypass capacitor and a 10-mF ceramic output
capacitor. Note that the output starts up slower as the
bypass capacitance increases because of the RC
time constant at the bypass pin that is created by the
internal 250-kΩresistor and external capacitor.
Figure 23. Typical Application Circuit
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
EXTERNAL CAPACITOR REQUIREMENTS To improve ac measurements such as PSRR, output
Although not required, it is good analog design noise, and transient response, it is recommended that
practice to place a 0.1mF to 2.2mF capacitor near the the board be designed with separate ground planes
input of the regulator to counteract reactive input for VIN and VOUT, with each ground plane connected
sources. A higher-value input capacitor may be only at the ground pin of the device. In addition, the
necessary if large, fast-rise-time load transients are ground connection for the bypass capacitor should
anticipated and the device is located several inches connect directly to the ground pin of the device.
from the power source.
Like most low-dropout regulators, the TPS795xx REGULATOR MOUNTING
requires an output capacitor connected between OUT The tab of the SOT223-6 package is electrically
and GND to stabilize the internal control loop. The connected to ground. For best thermal performance,
minimum recommended capacitor is 1 mF. Any 1 mFthe tab of the surface-mount version should be
or larger ceramic capacitor is suitable. soldered directly to a circuit-board copper area.
The internal voltage reference is a key source of Increasing the copper area improves heat dissipation.
noise in an LDO regulator. The TPS795xx has an NR Solder pad footprint recommendations for the devices
pin which is connected to the voltage reference are presented in application report SBFA015,Solder
through a 250-kΩinternal resistor. The 250-kΩPad Recommendations for Surface-Mount Devices,
internal resistor, in conjunction with an external available from the TI web site (www.ti.com).
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
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C1+(3 10*7) (R1)R2)
(R1 R2)
VOUT +VREF ǒ1)R1
R2Ǔ
R1+ǒVOUT
VREF *1Ǔ R2
TPS79501
GND FB
IN OUT
EN
VIN VOUT
R1C1
R2
1 Fm
1 Fm
OUTPUTVOLTAGE
PROGRAMMINGGUIDE
1.8V
3.6V
14.0kW
57.9kW30.1kW
30.1kW33pF
15pF
OUTPUT
VOLTAGE R1R2C1
TPS795xx
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
www.ti.com
PROGRAMMING THE TPS79501 The approximate value of this capacitor can be
ADJUSTABLE LDO REGULATOR calculated as Equation 3:
The output voltage of the TPS79501 adjustable
regulator is programmed using an external resistor (3)
divider as shown in Figure 24. The output voltage is The suggested value of this capacitor for several
calculated using Equation 1:resistor ratios is shown in the table within Figure 24.
If this capacitor is not used (such as in a unity-gain
configuration), then the minimum recommended
(1) output capacitor is 2.2 mF instead of 1 mF.
where: REGULATOR PROTECTION
• VREF = 1.2246 V typ (the internal reference
voltage) The TPS795xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
Resistors R1and R2should be chosen for input voltage drops below the output voltage (for
approximately 40-mA divider current. Lower value example, during power down). Current is conducted
resistors can be used for improved noise from the output to the input and is not internally
performance, but the device wastes more power. limited. If extended reverse voltage operation is
Higher values should be avoided, as leakage current anticipated, external limiting might be appropriate.
at FB increases the output voltage error. The TPS795xx features internal current limiting and
The recommended design procedure is to choose thermal protection. During normal operation, the
R2= 30.1 kΩto set the divider current at 40 mA, TPS795xx limits output current to approximately 2.8
C1= 15 pF for stability, and then calculate R1using A. When current limiting engages, the output voltage
Equation 2:scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
gross device failure, care should be taken not to
(2) exceed the power dissipation ratings of the package.
In order to improve the stability of the adjustable If the temperature of the device exceeds
version, it is suggested that a small compensation approximately +165°C, thermal protection circuitry
capacitor be placed between OUT and FB. shuts it down. Once the device has cooled down to
below approximately +140°C, regulator operation
resumes.
Figure 24. TPS79501 Adjustable LDO Regulator Programming
10 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS795xx
PD+ǒVIN *VOUTǓ IOUT
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
RqJA +()125OC*TA)
PD
0
20
40
60
80
100
120
140
160
0 2 4 6 8 10
DRB
DCQ
qJA (°C/W)
BoardCopper Area(in )
2
0
5
10
15
20
25
30
35
0 1 2 3 4 5 6 7 8 9 10
DRB YJB
DRB YJT
DCQ YJT
DCQ YTB
Y Y
JT JB
and (°C/W)
Board Copper Area (in )
2
TPS795xx
www.ti.com
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
THERMAL INFORMATION
Figure 25 shows the variation of qJA as a function of
Power Dissipation ground plane copper area in the board. It is intended
only as a guideline to demonstrate the effect of heat
Knowing the device power dissipation and proper spreading in the ground plane and should not be
sizing of the thermal plane that is connected to the used to estimate the thermal performance in real
tab or pad is critical to avoiding thermal shutdown application environments.
and ensuring reliable operation. NOTE: When the device is mounted on an
Power dissipation of the device depends on input application PCB, it is strongly recommended to use
voltage and load conditions and can be calculated ΨJT and ΨJB, as explained in the Estimating Junction
using Equation 4:Temperature section.
(4) ESTIMATING JUNCTION TEMPERATURE
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest Using the thermal metrics ΨJT and ΨJB, as shown in
possible input voltage necessary to achieve the the Thermal Information table, the junction
required output voltage regulation. temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
On the SON (DRB) package, the primary conduction compatibility, an older qJC,Top parameter is also
path for heat is through the exposed pad to the listed.
printed circuit board (PCB). The pad can be
connected to ground or be left floating; however, it
should be attached to an appropriate amount of (6)
copper PCB area to ensure the device does not
overheat. On the SOT-223 (DCQ) package, the Where PDis the power dissipation shown by
primary conduction path for heat is through the tab to Equation 5, TTis the temperature at the center-top of
the PCB. The tab should be connected to ground. the IC package, and TBis the PCB temperature
The maximum junction-to-ambient thermal resistance measured 1 mm away from the IC package on the
depends on the maximum ambient temperature, PCB surface (as Figure 27 shows).
maximum device junction temperature, and power
dissipation of the device and can be calculated using NOTE: Both TTand TBcan be measured on actual
Equation 5: application boards using a thermo-gun (an infrared
thermometer).
For more information about measuring TTand TB, see
(5) the application note SBVA025,Using New Thermal
Knowing the maximum RqJA, the minimum amount of Metrics, available for download at www.ti.com.
PCB copper area needed for appropriate heatsinking By looking at Figure 26, the new thermal metrics (ΨJT
can be estimated using Figure 25.and ΨJB) have little dependency on board size. That
is, using ΨJT or ΨJB with Equation 6 is a good way to
estimate TJby simply measuring TTor TB, regardless
of the application board size.
Note: qJA value at board size of 9 in2(that is, 3 in
× 3 in) is a JEDEC standard.
Figure 25. qJA vs Board Size
Figure 26. ΨJT and ΨJB vs Board Size
space
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS795xx
1mm
1mm
T on PCB
B
T on Top of IC Surface
T
(a) Example DRB (SON) Package Measurement (b) Example DCQ (SOT-223) Package Measurement
TB
X
X
TT
TPS795xx
SLVS350H –OCTOBER 2002–REVISED AUGUST 2010
www.ti.com
For a more detailed discussion of why TI does not For further information, see the application report
recommend using qJC(top) to determine thermal SPRA953,IC Package Thermal Metrics, also
characteristics, see the application report SBVA025, available on the TI website.
Using New Thermal Metrics, available for download
at www.ti.com.
Figure 27. Measuring Point for TTand TB
SPACER
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (July, 2006) to Revision H Page
• Replaced the Dissipation Ratings table with the Thermal Information Table ....................................................................... 3
• Updated the Thermal Information section ........................................................................................................................... 11
12 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS795xx
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS79501DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79501DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79501DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79501DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79501DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79501DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79516DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79516DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79516DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79516DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79518DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79518DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79518DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79518DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79525DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79525DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79525DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS79525DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79530DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79530DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79530DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79530DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79533DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79533DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS79501 :
•Automotive: TPS79501-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS79501DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS79501DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS79501DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS79516DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS79518DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS79525DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS79530DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS79533DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS79501DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS79501DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS79501DRBT SON DRB 8 250 210.0 185.0 35.0
TPS79516DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS79518DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS79525DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS79530DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS79533DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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