July 2015
©2012 Fairchild Semiconductor Corporation
FDMS86300DC Rev. 1.13 www.fairchildsemi.com
1
FDMS86300DC N-Channel Dual CoolTM 56 PowerTrench® MOSFET
FDMS86300DC
N-Channel Dual CoolTM 56 PowerTrench® MOSFET
80 V, 110 A, 3.1 mΩ
Features
Dual CoolTM Top Side Cooling PQFN package
Max rDS(on) = 3.1 mΩ at VGS = 10 V, ID = 24 A
Max rDS(on) = 4.0 mΩ at VGS = 8 V, ID = 21 A
High performance technology for extremely low rDS(on)
100% UIL Tested
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process.
Advancements in both silicon and Dual CoolTM package
technologies have been combined to offer the lowest rDS(on)
while maintaining excellent switching performance by extremely
low Junction-to-Ambient thermal resistance.
Applications
Synchronous Rectifier for DC/DC Converters
Telecom Secondary Side Rectification
High End Server/Workstation Vcore Low Side
Bottom
Top
Pin 1
S
GSS
D
DDD
Dual CoolTM 56
S
Pin 1
D
D
D
D
S
S
S
G
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 80 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous TC = 25 °C 110 A -Continuous TA = 25 °C (Note 1a) 24
-Pulsed (Note 2) 260
EAS Single Pulse Avalanche Energy (Note 3) 240 mJ
PDPower Dissipation TC = 25 °C 125 W
Power Dissipation T A = 25 °C (Note 1a) 3.2
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case (Top Source) 2.3
°C/W
RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 38
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 81
RθJA Thermal Resistance, Junction to Ambient (Note 1i) 16
RθJA Thermal Resistance, Junction to Ambient (Note 1j) 23
RθJA Thermal Resistance, Junction to Ambient (Note 1k) 1 1
Device Marking Device Package Reel Size Tape Width Quantity
86300 FDMS86300DC Dual CoolTM 56 13’’ 12 mm 3000 units
FDMS86300DC N-Channel Dual CoolTM 56 PowerTrench® MOSFET
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©2012 Fairchild Semiconductor Cor poration
FDMS86300DC Rev. 1.13
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristic s
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 80 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 45 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA2.53.34.5V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -11 mV/°C
rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 24 A 2.6 3.1 mΩVGS = 8 V, ID = 21 A 3.1 4.0
VGS = 10 V, ID = 24 A, TJ = 125 °C 4.1 5.0
gFS Forward Transconductance VDD = 10 V, ID = 24 A 79 S
Ciss Input Capacitance VDS = 40 V, VGS = 0 V,
f = 1 MHz
5265 7005 pF
Coss Output Capacitance 929 1235 pF
Crss Reverse Transfer Capacitance 21 50 pF
RgGate Resistance 0.1 1.2 2.6 Ω
td(on) Turn-On Delay Time VDD = 40 V , ID = 24 A,
VGS = 10 V, RGEN = 6 Ω
29 47 ns
trRise Time 25 44 ns
td(off) Turn-Off Delay Time 35 57 ns
tfFall Time 918ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V VDD = 40 V
ID = 24 A
72 101 nC
Total Gate Charge VGS = 0 V to 8 V 59 84 nC
Qgs Total Gate Charge 26 nC
Qgd Gate to Drain “Miller” Charge 14 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2.7 A (Note 2) 0.72 1.2 V
VGS = 0 V, IS = 24 A (Note 2) 0.80 1.3
ISDiode continuous forward current TC = 25 °C 75 A
IS, pulse Diode pulse current 150
trr Reverse Recovery Time IF = 24 A, di/dt = 100 A/μs 56 88 ns
Qrr Reverse Recovery Charge 42 67 nC
FDMS86300DC N-Channel Dual CoolTM 56 PowerTrench® MOSFET
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©2012 Fairchild Semiconductor Cor poration
FDMS86300DC Rev. 1.13
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case (Top Source) 2.3
°C/W
RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 38
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 81
RθJA Thermal Resistance, Junction to Ambient (Note 1c) 27
RθJA Thermal Resistance, Junction to Ambient (Note 1d) 34
RθJA Thermal Resistance, Junction to Ambient (Note 1e) 16
RθJA Thermal Resistance, Junction to Ambient (Note 1f) 19
RθJA Thermal Resistance, Junction to Ambient (Note 1g) 26
RθJA Thermal Resistance, Junction to Ambient (Note 1h) 61
RθJA Thermal Resistance, Junction to Ambient (Note 1i) 16
RθJA Thermal Resistance, Junction to Ambient (Note 1j) 23
RθJA Thermal Resistance, Junction to Ambient (Note 1k) 1 1
RθJA Thermal Resistance, Junction to Ambient (Note 1l) 13
NOTES:
1. RθJA is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
c. Still air, 20.9x10.4x12.7 mm Aluminum Heat S i nk, 1 in2 pad of 2 oz copper
d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
g. 200FPM Airflow, No Heat Sink,1 in2 pad of 2 oz c opper
h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper
i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting TJ = 25 oC, L = 0.3 mH, IAS = 40 A, VDD = 72 V, VGS = 10 V.
a. 38 °C/W when mounted on
a 1 in2 pad of 2 oz copper b. 81 °C/W when mounted on
a minimum pad of 2 oz copper
G
DF
DS
SF
SS
G
DF
DS
SF
SS
FDMS86300DC N-Channel Dual CoolTM 56 PowerTrench® MOSFET
www.fairchildsemi.com
4
©2012 Fairchild Semiconductor Corporation
FDMS86300DC Rev. 1.13
Typical Characteristics TJ = 25 °C unless otherwise noted
Figure 1.
012345
0
52
104
156
208
260 VGS = 7 V
VGS = 6 V
VGS = 10 V
VGS = 6.5 V
VGS = 8 V
VGS = 5.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0 .5 % MAX
ID, DRAIN CURRENT (A)
VDS, DRAI N TO SOURCE VOLTAG E (V)
On-Region Characteristics Figure 2.
0 52 104 156 208 260
0
1
2
3
4
5
6
VGS = 7 V
VGS = 8 V
P ULS E DURATIO N = 8 0 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO S OU RCE O N- RES IS TANCE
ID, DRAIN CURRENT (A)
VGS = 5.5 V
VGS = 6 V
VGS = 6.5 V
VGS = 10 V
Normalized On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On- Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ID = 24 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTAN CE
TJ, JUNCTION TEMPERATURE (oC)
vs Junction Te mperature Figure 4.
5678910
0
3
6
9
12
15
TJ = 125 oC
ID = 24 A
TJ = 25 oC
VGS, G ATE TO SOURC E VO LTAGE (V)
rDS(on), DRAIN T O
SOURCE ON-RESISTANCE (mΩ)
PULSE DU R ATION = 80 μs
DUTY CYCLE = 0.5% MA X
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
345678
0
52
104
156
208
260
TJ = 2 5 oC
TJ = 150 oC
VDS = 5 V
P ULS E DURATION = 80 μs
DUTY CYCLE = 0 .5 % MAX
TJ = -5 5 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SO URCE V OLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
1E-3
0.01
0.1
1
10
100
300
TJ = -55 oC
TJ = 2 5 oC
TJ = 150 oC
VGS = 0 V
IS, R EVER SE DRAIN C U RREN T (A)
VSD, BODY DI ODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
FDMS86300DC N-Channel Dual CoolTM 56 PowerTrench® MOSFET
www.fairchildsemi.com
5
©2012 Fairchild Semiconductor Corporation
FDMS86300DC Rev. 1.13
Figure 7.
0 20406080
0
2
4
6
8
10
ID = 24 A
VDD = 40 V
VDD = 30 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 50 V
Gate Charge Characteristics Figure 8.
0.1 1 10 80
5
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs Drain
to Source Voltage
Figure 9.
Uncl a mped I nduc t ive
Switching Capability Figure 10.
25 50 75 100 125 150
0
20
40
60
80
100
120
140
160
Limited by Package VGS = 8 V
RθJC = 1. 0 oC/W
VGS = 10 V
ID, DRAIN CURRE NT ( A)
TC, CAS E TEMP E RATURE (oC)
Maximum Continuous Drain
Current vs Case Temperature
Figure 11.
0.01 0.1 1 10 100200
0.01
0.1
1
10
100
1000
CURV E BENT TO
ME AS URED DATA
1 ms
10 s
10 ms
DC
1 s
100 ms
100 u s
ID, DRA IN CURREN T ( A)
VDS, DRAIN to S OURCE V O LTAGE ( V )
S ING LE PULSE
TJ = M A X R A T ED
RθJA = 81 oC/W
TA = 25 oC
THIS AREA IS
LIMITED BY rDS(on)
Forward Bias Safe
Operating Area Figure 12. Single Pulse Maximum
Power Dissipation
10-4 10-3 10-2 10-1 100101100 1000
1
10
100
1000
10000 SINGLE PUL SE
RθJA = 81 oC/W
TA = 25 oC
P(PK), PEA K TR A NSI EN T POW ER (W)
t, PU L SE W I DT H (sec)
Typical Characteristics TJ = 25 °C unless otherwise noted
FDMS86300DC N-Channel Dual CoolTM 56 PowerTrench® MOSFET
www.fairchildsemi.com
6
©2012 Fairchild Semiconductor Corporation
FDMS86300DC Rev. 1.13
Figure 13. Junction-to-Ambient Transient Thermal Respon se Curve
10-4 10-3 10-2 10-1 100101100 1000
0.0001
0.001
0.01
0.1
1
2
SIN GL E PU L SE
DUTY CYCLE- DE S CEN DING O RDE R
r (t), NORMA LIZED EFFEC TIVE TRA NSIEN T
T H ERM A L R ESI ST ANCE
t, RE CTANG ULAR P ULSE DURATION (sec )
D = 0 .5
0 .2
0 .1
0.05
0.02
0.01
P
DM
t
1
t
2
NOTES:
Duty Cycle, D = t
1
/ t
2
Z
θ
JA
(t) = r(t) x R
θ
JA
Peak T
J
= P
DM
x Z
θ
JA
(t) + T
A
R
θ
JA
= 81 °C/W
Typical Characteristics TJ = 25 °C unless otherwise noted
C
L
L
C
5.00
4.80
5.85
5.50
C
1.27
3.86
3.61
CHAMFER
CORNER
AS PIN #1
IDENT MAY
APPEAR AS
OPTIONAL
1.27
3.81
1.27
3.91 1.27
123
4
8567
14
85
LAND PATTERN
RECOMMENDATION
12 3 4
876
0.10 C A B
0.50
0.40 (8X)
5
0.77
A
B
(0.34)
0.61
NOTES:
A) PACKAGE IS NOT FULLY COMPLIANT
TO JEDEC MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08DREV4
SEE
DETAIL A
SCALE: 2:1
0.05
0.00
0.30
0.20
0.08 C
OPTIONAL DRAFT ANGLE
MAY APPEAR ON FOUR
SIDES OF THE PACKAGE
OPTIONAL PIN 1
INDICATOR
SEATING
PLANE
0.10 C
1.05
0.95
7°
0.1 MAX
(0.90)
(2.60)
(3.30)
0.71
0.44
(0.82)
5.10
3.81
KEEP-
OUT
AREA
4.90
5.80
A
A
A
A
A(1.40)
3.58
3.38 (0.20)
A
0.41
0.31
A(8X)
(2.08)
0.65
0.45
(4X)
(4X)
(8X)
0.35
0.25 0.40
0.30
(0.50)
.1 C
.1 C
(2X)
(2X)
(1.05)
(1.02)
2.67
2.04
1.22
2.54
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