ICS950811yFLFT - Integrated Circuit Systems, Inc.

Integrated

Circuit

Systems, Inc.

ICS950811

0482E—08/09/07

Block Diagram

Recommended Application:

CK-408 clock for Brookdale-Mobile chipsets.

Programmable for group to group skew.

Output Features:

• 3 Differential CPU Clock Pairs (differential current

mode)

• 7 PCI (3.3V) @ 33.3MHz

• 3 PCI_F (3.3V) @ 33.3MHz

• 1 USB (3.3V) @ 48MHz

• 1 DOT (3.3V) @ 48MHz

• 1 REF (3.3V) @ 14.318MHz

• 5 3V66 (3.3V) @ 66.6MHz

• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz

Features:

• Supports spread spectrum modulation,

down spread 0 to -0.5%.

• Efficient power management scheme through PD#,

CPU_STOP# and PCI_STOP#.

Key Specifications:

•CPU Output Jitter <150ps

• 3V66 Output Jitter <250ps

• 66MHz Output Jitter (Buffered Mode Only) <100ps

• CPU Output Skew <100ps

Pin Configuration

56 pin SSOP/TSSOP

Frequency Generator with 200MHz Differential CPU Clocks

Functionality

* These inputs have 150K internal pull-up resistor to VDD.

2SF1SF0SF UPC

)zHM(

)0:1(66V3

)zHM(

)0:2(tuOzHM66

)2:4(66V3

)zHM(

F_ICP

ICP

)zHM(

nIzHM66

)5(66V3

)zHM(

00 0 66.6666.6666.663

3.3366.66

00 1 00.00166.6666.6633.3366.66

010 00.00266.6666.6633.3366.66

011 33.33166.6666.6633.3366.66

10 0 66.6666.66

edoMdereffuB

detrop

puStoN

508059SCIeeS

10 1 00.00166.66

110 00.00266.66

11 1 33.33166.66

diM00 etatsirTetatsirTetatsirTetatsirTetatsirT

diM01 2/KLCT4/KLCT4/K

LCT8/KLCT4/KLCT

diM10 -vreseR

de devreseRdevreseRdevreseRdevreseR

diM11 -vreseR

de devreseRdevreseRdevreseRdevreseR

ICS950811

0482E—08/09/07

Pin Configuration

REBMUNNIPEMANNIPEPYTNOITPIRCSED

,62,91,41,8,1

05,64,73,23 DDVRWPylppusrewopV3.3

21XlatsyrC2X

tupnI tupnilatsyrCzHM813.41

32XlatsyrC1X

tuptuO tupt

uolatsyrCzHM813.41

5,6,7

)0:2(F_KLCICPTUO rof#POTS_ICPybdetceffatonkcolcICPgninnureerF

.tnemeganamrewop

,72,02,51,9,4

74,14,63,13 DNGRWPylppusV3.3rofsnipdnuorG

,31,61,71,81

01,11,21 )0:6(KLCICPTUOstuptuokcolcICP

12,

22,32,42)2:5(66V3TUOOCVlanretnimorf,skcolcecnereferzHM66

52#DPNI.woLevitcA.edomnwod-rewopsekovnI

82#DGRWP_ttV

92ATADS

O/IIrofnipataD

tnarelotV5yrtiucricC

03KLCS

NIIfonipkcolC

tnarelotV5yrtiucricC

330_66V3TUOOCVlanretnimorf,skcolcecnereferzHM66

43#POTS_ICPNItpecxewoltupninehw,level0cigoltaskcolcKLCICPstlaH

gninnureerferahcihwF_KLCICP

53KLC_HCV/1_66V3TUO hguorhtelbatcelestuptuoV3.3

lanretnimorfzHM66ebot

)CSS-non(zHM84roOCV

83TOD_zHM84TUOTODrofkcolctuptuozHM84

93BSU_zHM84TUOBSUrofkcolctuptuo

zHM84

042SFNInoitcelesedoMroftupniV3.3laicepS

24FERITUO

KLCUPCehtroftnerrucecnereferehtsehsilbatsenipsihT

dnuo

rgotdeitrotsisernoisicerpdexifaseriuqernipsihT.sriap

.tnerrucetairporppaehthsilbatseotredroni

340LESTLUMN

IUPCrofreilpitlumtnerrucehtgnitcelesroftupniLTTVLV3.3

stuptuo

15,84,44)0:2(CKLCUPCTUO

esehT.stuptuoUPCriap

laitnereffidfoskcolc"yrotnemelpmoC"

rofderiuqererasrotsiserlanretxednastuptuotnerrucera

.saibegatlov

25,

94,54)0:2(TKLCUPCTUO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT"

.saibegatlovrofderiuqereras

rotsiserlanretxednastuptuo

35#POTS_UPCNIwoltupninehw,level0cigoltaskcolcKLCUPCstlaH

45,55)0:1(SFNIsniptcelesy

cneuqerF

65FERTUO.kcolcecnereferzHM813.41

Power Groups

(Analog)

VDDA = PLL1

VDD48 = 48MHz, PLL

VDDREF = VDD for Xtal, POR

(Digital)

VDDPCI

VDD3V66

VDDCPU

ICS950811

0482E—08/09/07

Host Swing Select Functions

Truth Table

Maximum Allowed Current

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)

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evitcAlluF Am063

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66V3

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)zHM(

)0:2(ffuB66

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/NI_zHM66

5_66V3

F_ICP

ICP

)zHM(

0FER

)zHM(

TOD/BSU

)zH

000 66.6666.6666.6666.6633.33813.4100.84

001 00.00166.6666.6666.6633.33813.4100.84

010 00.00266.6666.6666.6633.33813.4100.84

011 33.33166

.6666.6666.6633.33813.4100.84

100 66.6666.66

detroppuStoNedoMdereffuB

508059SCIeeS

10 1 00.00166.66

110 00.00266.66

111 33.33166.66

M00 etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT

diM01 2/KLCT4/KLCT4/KLCT4/KLCT8/KLCTKLCT2/KLCT

diM10 devreseRdevres

eRdevreseRdevreseRdevreseRdevreseRdevreseR

diM11 devreseRdevreseRdevreseRdevreseRdevreseRdevreseRdevreseR

0LESITLUM tegraTdraoB

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7.0

ICS950811

0482E—08/09/07

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches

for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the

controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop

after any complete byte has been transferred. The Command code and Byte count shown above must be

sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending first byte (Byte 0)

through byte 5

• ICS clock will acknowledge each byte one at a time .

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will acknowledge

• ICS clock will send the byte count

• Controller (host) acknowledges

• ICS clock sends first byte (Byte 0) through byte 6

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D2(H) AC

Dummy Command Code ACK

Dummy Byte Count AC

Byte 0 ACK

Byte 1 AC

Byte 2 ACK

Byte 3 AC

Byte 4 ACK

Byte 5 AC

Byte 6 ACK

Stop Bit

How to Wri te :

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D3(H) AC

Byte Count

ACK Byte 0

ACK Byte 1

ACK Byte 2

ACK Byte 3

ACK Byte 4

ACK Byte 5

ACK Byte 6

ACK

Stop Bit

How to Read:

ICS950811

0482E—08/09/07

Byte 0: Control Register

Byte 1: Control Register

tiB#niPemaNDWP

epyT

noitpircseD

0tiB450SFXR nodelpmasnip0SFfoeulavehtstcelfeR

purewop

1tiB551SFXR nodelpmasnip1SFfoeulavehtstcelfeR

pur

ewop

2tiB042SFXR nodelpmasnip2SFfoeulavehtstcelfeR

purewop

3tiB43#POTS_ICP

XR foeulavehtstcelfeR:edomerawdraH

DWPnodelpmasnip#POTS_ICP

1WR

:edomerawtfoS

deppotsKLCICP=0

deppotstonKLCIC

P=1

4tiB35#POTS_UPCXR lanretxeehtfoeulavtnerrucehtstcelfeR

nip#POTS_UPC

5tiB53HCV/1_66V30WRzHM84/zHM66tceleSHCV

zHM84=1,zHM66=0

6tiB- )0:2(T_UPC0

leveltuptuoslortnocedomnwodrewopnI

hgihpots=0

wolpots=1

7tiB- daerpS

delbanE 0WRnOda

erpS=1,ffOdaerpS=0

Notes:

1. R= Read only RW= Read and Write

2. PWD = Power on Default

3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.

Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert

PCI_STOP functionality via I2C Byte 0 Bit 3.

In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the

external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped

PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it

is not allowed to mix these modes.

In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip

is in PCI_STOP mode.

Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)].

4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,

CPUCLKC off, and external resistor termination will bring CPUCLKC low.

tiB#niPemaNDWP

epyT

noitpircseD

0tiB15,25 0TKLCUPC

0CKLCUPC 1WRdelbanE=1delbasiD=0

1tiB84,94 1TKLCUPC

1CKLCUPC 1WRdelbanE=1delbasiD=0

2tiB44,54 2TKLCUPC

2CKLCUPC 1WRdelbanE=1delbasiD=0

3tiB15,25 0TKLCUPC

0CKLCUPC 0WR

noitressahtiw0C/0TKLCUPCfolortnocwollA

eerF=1gninnureerftoN=0#POTS_UPCfo

gninnur

4tiB84,94 1TKLCUPC

1CKLCUPC 0WR

noitressahtiw1C/1TKLCUPCfolortnocwollA

eerF=1gninnureerftoN=0#POTS_UPCfo

ninnur

5tiB44,54 2TKLCUPC

2CKLCUPC 0WR

noitressahtiw2C/2TKLCUPCfolortnocwollA

eerF=1gninnureerftoN=0#POTS_UPC

gninnur

6tiB- - 0 - )devreseR(

7tiB340LESTLUMXR 0LESTLUMfoeulavtnerrucehtstcelfeR

ICS950811

0482E—08/09/07

Byte 2: Control Register

Notes:

1. R= Read only RW= Read and Write

2. PWD = Power on Default

tiB#niPemaNDWPepyTnoitpircseD

0tiB010KLCICP1WRdelbanE=1delbasiD=0

1tiB111KLCICP1WRdelbanE=1delbasiD=0

2tiB212KLCICP1WRdelban

E=1delbasiD=0

3tiB313KLCICP1WRdelbanE=1delbasiD=0

4tiB614KLCICP1WRdelbanE=1delbasiD=0

5tiB715KLCICP1WRdelbanE=1delbasiD

6tiB816KLCICP1WRdelbanE=1delbasiD=0

7tiB- - 0 - )devreseR(

Byte 3: Control Register

Byte 4: Control Register

tiB#niPemaNDWPepyTnoitpircseD

0tiB122-66V31WRdelbanE=1delbasiD=0

1tiB223-66V31WRdelbanE=1delbasiD=0

2tiB324-66V31WRdelbanE=1

delbasiD=0

3tiB425_66V31WRdelbanE=1delbasiD=0

4tiB53KLC_HCV/1_66V31WRdelbanE=1delbasiD=0

5tiB330_66V31WRdelbanE=1delbas

iD=0

6tiB- - 0 R )devreseR(

7tiB- - 0 R )devreseR(

tiB#niPemaNDWPepyTnoitpircseD

0tiB5 0F_KLCICP1WRdelbanE=1delbasiD=0

1tiB6 1F_KLCICP1WRdelbanE=1delbasiD=0

2tiB7 2F_KLCICP1WRdel

banE=1delbasiD=0

3tiB5 0F_KLCICP0WR

fonoitressahtiw0F_KLCICPfolortnocwollA

eerftoN=1,gninnuReerF=0.#POTS_ICP

ninnur

4tiB6 1F_KLCICP0WR

fonoitressahtiw1F_KLCICPfolortnocwollA

eerftoN=1,gninnuReerF=0.#POTS_ICP

gninnur

5tiB7 2

F_KLCICP0WR

fonoitressahtiw2F_KLCICPfolortnocwollA

eerftoN=1,gninnuReerF=0.#POTS_ICP

gninnur

6tiB93BSU_zHM841WRd

elbanE=1delbasiD=0

7tiB83TOD_zHM841WRdelbanE=1delbasiD=0

ICS950811

0482E—08/09/07

Byte 6: Vendor ID Register

(1 = enable, 0 = disable)

tiB#niPemaNDWPepyTnoitpircseD

0tiBX 0tiBDIrodneV1R)devreseR(

1tiBX 1tiBDIrodneV1R)devreseR(

2tiBX 2tiBDIrodneV1R)devreseR(

3tiBX 3t

iBDIrodneV1R)devreseR(

4tiBX 0tiBDInoisiveR1R nodesabeblliwseulavDInoisiveR

noisivers'ecivedlaudividni

5tiBX 1tiBDIn

oisiveR1R

6tiBX 2tiBDInoisiveR1R

7tiBX 3tiBDInoisiveR1R

Byte 5: Programming Edge Rate

(1 = enable, 0 = disable)

Notes:

1. R= Read only RW= Read and Write

2. PWD = Power on Default

tiB#niPemaNDWPepyTnoitpircseD

0tiBX BSU_zHM840WRlortncetaregdeBSU

1tiBX BSU_zHM840WRlortncetaregdeBSU

2tiBX TOD_zHM840WRlortnoc

etaregdeTOD

3tiBX TOD_zHM840WRlortnocetaregdeTOD

4tiBX - 0 - )devreseR(

5tiBX - 0 - )devreseR(

6tiBX - 0 - )devreseR(

7tiBX - 0 - )devreseR(

ICS950811

0482E—08/09/07

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD + 0.3 V

Input Low Voltage VIL VSS - 0.3 0.8 V

Input High Current IIH VIN = VDD -5 5 mA

IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA

IIL2 VIN = 0 V; Inputs with pull-up resistors -200

Operating Supply

Current IDD3.3OP CL = Full load; Select @ 100 MHz 229 230 360 mA

IDD3.3OP CL =Full load; Select @ 133 MHz 220 233 360 mA

Powerdown Current IDD3.3PD IREF=5 mA 38.1 45 mA

Input Frequency FiVDD = 3.3 V 14.318 MHz

Pin Inductance L

in 7nH

CIN Logic Inputs 5 pF

COUT Output pin capacitance 6 pF

CINX X1 & X2 pins 27 36 45 pF

Transition time1Ttrans To 1st crossing of target frequency 3 ms

Settling time1TsFrom 1st crossing to 1% target frequency 3 ms

Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target frequency 1 3 ms

Time to first clock1T1C Time to first clock 1.8 ms

tPZH,tPZL Output enable delay (all outputs) 1 10 ns

tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns

1Guaranteed by design, not 100% tested in production.

Delay1

Input Capacitance1

Input Low Current

ICS950811

0482E—08/09/07

Electrical Characteristics - CPU

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current Source

Output Impedance Zo1 VO = Vx3000 Ω

Output High Voltage VOH3 IOH = -1 mA 2.4 V

Output Low Voltage VOL3 IOL = 1 mA 0.4

Rise Time tr3 VOL = 0.41V, VOH = 0.86V 175 240 700 ps

Fall Time tf3 VOH = 0.86V VOL = 0.41V 175 242 700 ps

Duty Cycle dt3 measurement from differential wavefrom -

0.35V to +035V 45 51 55 %

Skew tsk3 VT = 50% 50 100 ps

Jitter, Cycle to cycle tjcyc-cyc1VT = 50% 76 150 ps

1Guaranteed by design, not 100% tested in production.

2 IOWT can be varied and is selectable thru the MULTSEL pin.

Electrical Characteristics - PCICLK

TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency FO1 33.33 MHz

Output Impedance RDSP11VO = VDD*(0.5) 12 33 55 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.55 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA

Output Low Current IOL1VOL @MIN

= 1.95 V, VOL @MAX = 0.4 V 30 38 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 1.32 0.5to 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 1.39 0.5 to 2 ns

Duty Cycle dt11VT = 1.5 V 45 52 55 %

Skew tsk11VT = 1.5 V 247 500 ps

Jitter,cycle to cyc tjcyc-cyc1VT = 1.5 V 111 500 ps

1Guaranteed by design, not 100% tested in production.

ICS950811

0482E—08/09/07

Electrical Characteristics - 3V66

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)

PARAMETER SYMBO

CONDITIONS MIN TYP MAX UNITS

Output Frequency FO1 66.66 MHz

Output Impedance RDSP11VO = VDD*(0.5) 12 33 55 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.55 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 -33 -33 mA

Output Low Current IOL1VOL @MIN

= 1.95 V, VOL @MAX = 0.4

30 38 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 1.38 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 1.45 2 ns

Duty Cycle dt11VT = 1.5 V 45 54.4 55 %

Skew tsk11VT = 1.5 V 243 500 ps

Jitter tjcyc-cyc1VT = 1.5 V 3V66 139 300 ps

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency FO1 48 MHz

Output Impedance RDSP11VO = VDD*(0.5) 20 48 60 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.4 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA

Output Low Current IOL1VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA

48DOT Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 0.6 1 ns

48DOT Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 0.8 1 ns

VCH 48 USB Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 1 1.2 2 ns

VCH 48 USB Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1 1.3 2 ns

48 DOT Duty Cycle dt11VT = 1.5 V 45 52.8 55 %

VCH 48 USB Duty Cycle dt11VT = 1.5 V 45 53.5 55 %

48 DOT Jitter t

c-c

c1VT = 1.5 V 183 350 ps

VCH Jitter tjcyc-cyc1VT = 1.5 V 223 350 ps

1Guaranteed by design, not 100% tested in production.

ICS950811

0482E—08/09/07

Electrical Characteristics - REF

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency FO1 14.318 MHz

Output Impedance RDSP11VO = VDD*(0.5) 20 48 60 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.4 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA

Output Low Current IOL1VOL @MIN

= 1.95 V, VOL @MAX = 0.4 V 29 27 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 1 1.25 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1 1.15 2 ns

Duty Cycle dt11VT = 1.5 V 455355%

Jitter tjcyc-cyc1VT = 1.5 V 723 1000 ps

1Guaranteed by design, not 100% tested in production.

ICS950811

0482E—08/09/07

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,

there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66

by the standard skew described below as Tpci.

Un-Buffered Mode 3V66 & PCI Phase Relationship

3V66 (1:0)

3V66 (4:2)

3V66_5

PCICLK_F (2:0) PCICLK (6:0) Tpci

Group Skews at Common Transition Edges: (Un-Buffered Mode)

GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS

3V66 3V66 3V66 (5:0) pin to pin skew 0 42 500 ps

PCI PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0 130 500 ps

3V66 to PCI S3V66-PCI 3V66 (5:0) leads 33MHz PCI 1.5 2.86 3.5 ns

1Guaranteed by design, not 100% tested in production.

ICS950811

0482E—08/09/07

Normal operation transition to Suspend State S1 Entry sequence of events:

1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the

transition in the clock circuit.

2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full

clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the

remaining PCI buffer clocks stopped.

3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next

high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks.

4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks

within a short delay will transition to a stopped power-down state. The first of these driven clocks that

transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks.

5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF

clock 14.318 MHz clock will stop low.

6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to

a low power stopped condition.

7. As a note to power management calculations, please be aware that the CPU design requires that in the

Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of

the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to

45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the

output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This

results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output

differential requirements.

Suspend State S1 Exit transition to normal operation sequence of events:

1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to

return to normal running operation.

2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No

clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the

same as normal initial power-up).

3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon

as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven

output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI

outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating

feedback path before the other buffer outputs are released. This change is why the requirement is made that

pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the

PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point.

4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock

66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter

than 400 uS, and after this the other clocks are staged for a sequential release.

5. The initial clocks released after the delay are the 66Buf_0, 2 outputs.

6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released.

7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the

remaining 66Buf_0,2 first, THEN the PCI clocks.

8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are

released.

9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be

running within a 3 ms time point.

ICS950811

0482E—08/09/07

Assertion of PCI_STOP# Waveforms

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

CPU_STOP#

CPUT

CPUC

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

Assertion of CPU_STOP# Waveforms

CPU_STOP# Functionality

#POTS_UPCTUPCCUPC

1lamroNlamroN

0tluM*feritaolF

PCI_STOP#

PCI_F[2:0] 33MHz

PCI[6:0] 33MHz

tsu

The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will

latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized

by the next rising edge.

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable

via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling

as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the

output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC

signal will not be driven.

ICS950811

0482E—08/09/07

When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks

must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with

a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description

is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.

Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more

than one clock cycle to complete.

PD# - Assertion (transition from logic "1" to logic "0")

PD# Functionality

#POTS_UPCTUPCCUPC66V3TUO_zHM66 F_KLCICP

KLCICP KLCICP TOD/BSU

zHM84

1lamroNlamroNzHM66NI_zHM66NI_zHM66NI_zHM66zHM84

0tlu

M*feritaolFwoLwoLwoLwoLwoL

Power Down Assertion of Waveforms - Buffered Mode

0ns

PD#

CPUT 100MHz

CPUC 100MHz

3V66MHz

66MHz_IN

66MHz_OUT

PCI 33MHz

USB 48MHz

REF 14.318MHz

25ns 50ns

ICS950811

0482E—08/09/07

Ordering Information

ICS950811yGLFT

Designation for tape and reel packaging

Lead Free, RoHS Compliant (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

Example:

ICS XXXX y G - LF - T

INDEX

AREA

INDEX

AREA

1 2

E1 E

SEATING

PLANE

SEATING

PLANE

-C-

- C -

aaa

6.10 mm. Body, 0.50 mm. pitch TSSOP

(240 mil) (0.020 mil)

MIN MAX MIN MAX

A--1.20--.047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.17 0.27 .007 .011

c 0.09 0.20 .0035 .008

E1 6.00 6.20 .236 .244

L 0.45 0.75 .018 .030

α0° 8° 0° 8°

aaa -- 0.10 -- .004

MIN MAX MIN MAX

56 13.90 14.10 .547 .555

10-0039

VARIATIONS

ND mm. D (inch)

Reference Doc.: JEDEC Publication 95, M O-153

0.50 BASIC 0.020 BASIC

SEE VARIATIONS SEE VARIATIONS

8.10 BASIC 0.319 BASIC

SYMBOL

In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

ICS950811

0482E—08/09/07

Ordering Information

ICS950811yFLFT

Designation for tape and reel packaging

Lead Free, RoHS Compliant (Optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

Example:

ICS XXXX y F - LF - T

MINMAXMINMAX

A 2.41 2.80 .095 .110

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135

c 0.13 0.25 .005 .010

E 10.03 10.68 .395 .420

E1 7.40 7.60 .291 .299

h 0.38 0.64 .015 .025

L 0.50 1.02 .020 .040

α0° 8° 0° 8°

VARIATIONS

MINMAXMINMAX

56 18.31 18.55 .720 .730

10-0034

0.635 BASIC 0.025 BASIC

COMMON DIMENSIONS

In Millimeters In Inches

COMMON DIMENSIONS

Reference Doc.: JEDEC Publication 95, MO-118

56-Lead, 300 mil Body, 25 mil, SSOP

SEE VARIATIONS SEE VARIATIONS

D mm. D (inch)

SYMBOL

SEE VARIATIONS SEE VARIATIONS

ICS950811

0482E—08/09/07

Revision History

Rev. Issue Date Description Page #

D 12/21/06

1. Removed SSOP Package Information.

2. Added LF Ordering Information. 16

E 08/09/07 Added SSOP Package Information. 17