a'e re AdLib OCR Evaluation systems Preliminary Data Sheet May 2002 TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Features Description . Same functionality as TSWC01622 with reduced jitter specifications The Agere Systems TSWC03622 is designed for a wide variety of synchronous timing applications . It serves as a clock synthesizer and low skew clock fan-out device generating clocks at frequencies up to 622 .08 MHz that are synchronized to the system reference clock . It also serves as an intelligent clock protection switch with fast autonomous selection based on the presence of the two input clocks . Alternatively, clock switching can be controlled entirely through a software interface by the user. The TSWC03622 also delivers an output sync signal that is aligned to the input clock . If 8 kHz system sync signals are applied as the clock A and clock B inputs, the TSWC03622 will generate an output sync signal that is phase aligned to the selected input sync. A programmable phase offset is provided to allow the user to offset the output sync relative to the input sync. The output sync can be used for global alignment of cells or frames in SONET/SDH/PDH cross connects or ATM switch applications . The device allows flexible choices of LVDS or LVCMOS input technologies and LVDS, LVPECL, or LVCMOS output technologies . . Fully integrated clock synthesis . Clock or system sync protection switching . Fast autonomous switching with software override . Supports a wide choice of SONET/SDH output clock frequencies with fitter quality up to OC-12: 622 .08 MHz 51 .84 MHz 34.368 MHz 19.44 MHz 4.096 MHz 1 .544 MHz 155 .52 MHz 44 .736 MHz 32 .768 MHz 16 .384 MHz 2.43 MHz 77 .76 MHz 38 .88 MHz 24 .704 MHz 8.192 MHz 2.048 MHz . Five outputs of frequency programmable clocks . Supports multiple input clock frequencies : 51 .84 MHz 8.192 MHz 1 .544 MHz 38 .88 MHz 6.48 MHz 8 kHz 19 .44 MHz 2.048 MHz . Generates sync outputs at 8 kHz aligned to an 8 kHz input clock signal . Locks to backup reference clock if both the working and protection reference clocks are lost . Low skew clock distribution balls . Compatible with Agere Systems Inc. TDAT04622/ TADM04622 SONET/ATM/POS devices, STSI144, TSI-16, TSI-8, TMX84622 Ultramapper and TMXF28155 Supermapper . Single 3 .3 V supply . Multiple output tech nologies-CMOS, LVPECL, or LVDS . Programmable via external balls or internal resisters via serial interface Applications . SONET/SDH and PDH add/drop multiplexers, cross connects, switches, and routers The TSWC03622 is intended for clock distribution and protection switching on a line card, a switch card, or a shelf timing card . Along with the wide variety of input and output frequencies, a unique feature of the device is a guaranteed correct number of output clock cycles between output sync pulses before, during, and after a clock selection switching event . The number of clock cycles between sync pulses remains correct even during a switch between working and protection clock sources that have an arbitrary phase relationship between them . The TSWC03622 also solves the skew problem associated with timing distribution over cable or backplane traces of different lengths . The TSWC03622 can be programmed via external balls, or through a serial interface . Enhanced functionality is available through the serial interface, including programmable clock outputs through fractional synthesis and the ability to enable or disable each output individually. AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Table of Contents Contents Page Features . . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .. .1 Applications . . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .. .1 Description . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. .1 Block Diagram . . . . .. . . . .. . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . . . . . . .. . . .. .4 Ball Information . . .. . . . . . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . . . .. . . .. . . . . . . . .. . . .. .5 Functional Overview . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .14 Description of Transient Switching Behavior . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . .. . . . .14 Input Clock Specifications . . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .17 Input Clock Stability Requirements (Clock A and Clock B) . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .17 Input Frequency Selection (FINSEL[3 :0]) . . . . .. . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .17 Input Electrical Level Selection for Clock A and Clock B Input Signals (SELLVDS) . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .17 Backup Reference Clock Selection (FBUSEL[3 :0]) . . .. . . . .. . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .17 Input Clock Minimum Pulse-Width Specifications (Clock A, Clock B, CLKBU) . . . . . . .. . . . .. . . . . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .18 Input Clock Minimum Pulse Width . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . .. . . . .18 Output Clock Specifications . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .18 Available Output Clocks . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .18 Jitter Specifications . . . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .20 Synchronization Output at 8 kHz . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . .. . . .. . . . .. . . . . . . .. . . . .21 Sync Output (SYNC8K, SYLVSP/N[1 :0], SYPCLKP/N[1 :0]) . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .21 Sync Duty Cycle Selection (SYDU) . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .21 Sync Alignment . . . . . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .21 Offset Programming (SYOFF[9 :0], SYOFFPOS) . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .21 Skew Specifications .. . . .. . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .23 Output Specifications During Phase-Locked Condition (Nontransient Condition) . . . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . . 28 Maximum Time Interval Error (MTIE) Specifications . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .28 Time Deviation (TDEV) Specifications .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . .. . . . .30 Output Specifications During Transient Condition . . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .31 Maximum Time Interval Error (MTIE) Specifications . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .31 Other Input and PLL Specifications . . . . . . . . .. . . .. . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . . . .. . . .. . . . . . . . .. . . .33 Input Clock Maximum Rate of Phase Change During Transient .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .33 External 38.88 MHz VCXO Requirements . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .33 Loop Filter Components for High-Speed PLL . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .. . . . . . . . .. . . .33 Loop Filter Components for Low-Speed PLL . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . . .. . . . .33 INLOSN . . . . . . .. . . .. . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . .. . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .35 Clock Switching State Machine and Software Interface . . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .35 Clock Switching State Machine Behavior . . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .35 Operation . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .35 Software Interfacing .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .37 Loss of Clock Criteria . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .37 Interrupt Generation (INT[8 :0]) . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .38 Serial Interface and Internal Bus . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . .. . . .. . . . .. . . . . . . .. . . . .39 TSWC03622 Registers Map .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . .. . . .. . . . .. . . . . . . .. . . . .41 Control Block Registers . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .44 Input Clock Block Registers . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .45 Switch State Machine Block Registers . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . .. . . . .47 PDH Output Block Registers . . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . .. . . .. . . . .. . . . . . . .. . . . .50 Fractional Dividers Registers : 40h-66h .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .50 General Configuration Registers : 80h-83h . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . . .. . . . . . . .. . . . .50 SDH/Sync Generation Block Registers . . .. . . .. . . . .. . . . .. . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .54 Absolute Maximum Ratings . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .65 Handling Precautions . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .65 Operating Conditions . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .65 2 Agere Systems Inc AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Table of Contents (continued) Contents Page Electrical Characteristics . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . .. . . .. . . . .. . . . . . . . .. . . .66 LVPECL, LVDS, CMOS, Input and Output Balls . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .66 Timing Characteristics . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .68 Packaging Diagram . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . .. . . .. . . . .. . . . . . . . .. . . .70 208-Plastic Ball Grid Array (17 x 17)-0 .63 mm Ball Size (4-Layer-Bottom View) . .. . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .70 Ordering Information . . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .71 Agere Systems Inc. 3 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Block Diagram - ------------------ ----- ------------- ---------------- ---CLKAP CLKAN CLKA DIV M ' ' LOCA CLKBP CLKBN , CLKB + LOCB SELLVDS c-- P DIV M D PHASE COMPARE I DIVIDE FINSEL[3 :0] , CLKBU , FBUSEL[3 :0] ' ' SELCLK , SELBUN , DIV N SWCONTN ENSQLN ENLON LORSTN LOC38 ; INLOSN _F1 F ~D-E~~ CONTROL AND SWITCH STATE MACHINE VC0 ---w P SWSTATE[1 :0] INT[8:0] 0 LF[P :N] , VC[P :N] ' DIVIDE VCO SYOFF[9 :0] SYNC OFFSET EN T qT(r-.1 K SYOFFPOS SYDU D D IVIDE RESETN Q SYNC8K SYLVSP[1 :0] SYLVSN[1 :0] SYPCLP[1 :0] SYPCLN[1 :0] BASED ON SID RREF PCK622P PCK622N CK622P CK622N CKPDH5 CKPDH4 CKPDH3 CKPDH2 CKPDHI PDH CLOCK GEN. ' SONET CLOCK GEN . PDHSEL[3 :0] SERCLK SERENBLN El VCXO 38 .88 MHz O ' LSVCO ' FED AUTOSWN REVERTN LFO SERIAL I/F REGISTER CONTROL PCK155P[1 :0] PCK155N 1 CK155P[1 ::0]0] I~w CK155N[1 :0] ' CK77 CK51 R1 , CK38 CK19 SERDAT SDHSEL[3 :0] " --- ------------------ ----- ------------- ---------------- ---- " 2359 (F) Note : The grayed out portions of the figure indicate that they are test features . Figure 1 . TSWC03622 Block Diagram 4 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Ball Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2360 (F) Figure 2 . TSWC03622 208-Ball BGA (Top View) Agere Systems Inc. 5 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Ball Information (continued) Table 1 . Ball Assignments for 208-Ball BGA by Ball Number Order Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 131 B2 133 134 B5 136 137 138 B9 B10 1311 B12 B13 B14 B15 B16 Signal Name GND CLK155NO CLK155PO GND SYLVSNO SYLVSPO GND CK622N CK622P GND SYLVSN1 SYLVSPI GND CLK155N1 CLK155P1 GND PCK155NO CK19 VDDPDH CKPDH2 VDDPDH GND GND GND GND GND GND GND GND SYOFF6 TSTIVIODE I TSTCLKP Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Signal Name PCK155PO CK38 CKPDHI CKPDH3 CKPDH5 VDDLVDS GND GND GND GND VDDSDH SYOFF2 SYOFF5 SYOFF8 VDDTCLK TSTCLKN VDDPECL VDDSDH GND GND CKPDH4 VDDPDH VDDLVDS RREF VDDLVDS SYOFFO SYOFF1 SYOFF3 SYOFF4 SYOFF7 SYDU I GND Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 Signal Name SYPCLNO FINSELO FINSEL3 SYNC8K SYOFF9 VDDHSPD VDDLSVCO LSVCO SYPCLPO VDDPECL GND CK51 SYOFFPOS VDDHSPD VDDHSVCO I GND Ball G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 Signal Name VDDPECL VDDPECL VDDPECL CK77 GND GND GND GND NC INLOSN LFN VCN PCK622N VDDPECL FINSEL2 FINSELI GND GND GND GND GND GND LFP I VCP Note : - refers to no ball . NC means do not connect any traces to this solder ball . Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Ball Information (continued) Table 1 . Ball Assignments for 208-Ball BGA by Ball Number Order (continued) Ball J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 Signal Name PCK622P VDDPECL VDDPECL GND GND GND GND GND GND VDDHSDIV VDDHSVCO NC VDDPECL VDDPECL GND SDHSEL2 GND GND GND GND FBUSELO VDDHSDIV LFOZ I NC Ball L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 1-15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 Signal Name SYPCLN1 SDHSELO SDHSEL3 SDHSELI FBUSEL3 FBUSEL2 SELCLK FBUSELI SYPCLP1 VDDCNTL VDDCNTL SDH HW GND AUTOSWN REVERTN I SELBUN Ball N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name VDDPECL SERDAT SERENBLN GND INT8 INT5 INT4 VDDFF INT1 INTO SWSTATEI SELLVDS GND ENSQLN RESETN SWCONTN PCK155N1 PDHSEL3 PDHSEL2 GND GND INT6 NC RSVB VDDFF RSVA NC SWSTATEO ENLON VDDLSPLL VDDLSPLL I VDDCNTL Ball R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal Name PCK155P1 SERCLK GND GND PDHSELO INT7 INT3 GND GND INT2 GND LORSTN GND GND GND GND VDDPECL VDDCLKBU CLKBU PDHSELI GND CLKB CLKBN CLKBP GND CLKAP CLKAN CLKA GND LF2 LF1 I LFO Note : - refers to no ball . NC means do not connect any traces to this solder ball . Agere Systems Inc. 7 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Ball Information (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A GND CK155NO CK155PO GND SYLVSNO SYLVSPO GND CK622N CK622P GND SYLVSN1 SYLVSP1 GND CK155N1 CK155P1 GND B PCK155NO CK19 VDDPDH CKPDH2 VDDPDH GND GND GND GND GND GND GND GND SYOFF6 TSTMODE TSTCLKP C PCK155PO CK38 CKPDH1 CKPDH3 CKPDH5 VDDLVDS GND GND GND GND VDDSDH SYOFF2 SYOFF5 SYOFFB VDDTCLK TSTCLKN D VDDPECL VDDSDH GND GND CKPDH4 VDDPDH VDDLVDS RREF VDDLVDS SYOFFO SYOFF1 SYOFF3 SYOFF4 SYOFF7 SYDU GND E SYPCLNO FINSELO FINSEL3 SYNCBK SYOFF9 VDDHSPD VDDLSVCO LSVCO F SYPCLPO VDDPECL GND CK51 SYOFFPOS VDDHSPD VDDHSVCO GND G VDDPECL VDDPECL VDDPECL CK77 GND GND GND GND NC INLOSN LFN VCN H PCK622N VDDPECL FINSEL2 FINSELI GND GND GND GND GND GND LFP VCP J PCK622P VDDPECL VDDPECL GND GND GND GND GND GND VDDHSDIV VDDHSVCO NC K VDDPECL VDDPECL GND SDHSEL2 GND GND GND GND FBUSELO VDDHSDIV LFOZ NC L SYPCLN1 SDHSELO SDHSEL3 SDHSEL1 FBUSEL3 FBUSEL2 SELCLK FBUSEL1 M SYPCLP1 VDDCNTL VDDCNTL SDH HW GND AUTOSWN REVERTN SELBUN N VDDPECL SERDAT SERENBLN GND INTB INT5 INT4 VDDFF INT1 INTO SWSTATE1 SELLVDS GND ENSOLN RESETN SWCONTN P PCK155N1 PDHSEL3 PDHSEL2 GND GND INT6 NC RSVB VDDFF RSVA NC SWSTATEO ENLON VDDLSPLL VDDLSPLL VDDCNTL R PCK155P1 SERCLK GND GND PDHSELO INT7 INT3 GND GND INT2 GND LORSTN GND GND GND GND T VDDPECL VDDCLKBU CLKBU PDHSEL1 GND CLKB CLKBN CLKBP GND CLKAP CLKAN CLKA GND LF2 LF1 LFO Figure 3. Physical Ball Orientation (Bumps Down) Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Ball Information (continued) Table 2. Ball Descriptions-Clock Inputs and Related Signals Ball Symbol* Typet Level Name/Description T10, T11 T12 CLKAP CLKAN CLKA ID LVDS ID CMOS T8, T7 T6 CLKBP CLKBN CLKB ID LVDS ID CMOS N12 SELLVDS Iu CMOS E3, H3, H4, E2 T3 L13, L14, L16, K13 FINSEL[3 :0] Iu CMOS CLKBU FBUSEL[3 :0] ID Iu CMOS CMOS Input Clock A. Used when LVDS level is desired for interfacing to input clock A source . Input Clock A. Used when CMOS level is desired for interfacing to input clock A source . Input Clock B . Used when LVDS level is desired for interfacing to input clock B source . Input Clock B. Used when CMOS level is desired for interfacing to input clock B source . Select Clock Level (LVDS/CMOS) . Selects the LVDS or the CMOS input balls as the clock A and B sources: 0 = CMOS (CLKA, CLKB). 1 or no connection = LVDS (CLKAP/N, CLKBP/N) . Input Frequency Select . Program to indicate the input frequency of the clock A and B sources. Backup Clock. CMOS level input backup clock source . Backup Clock Frequency Select . Program to indicate the input frequency of the backup clock source. * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low. t I = input, O = output. 11 indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . Table 3. Ball Descriptions-Analog and PLL Related Signals Ball Symbol* Typet Level Name/Description E16 T14, T15 T16 K15 LSVCO LF2, LF1 LFO LFOZ I Analog Analog Iu CMOS CMOS 38.88 MHz VCXO. Connection to external VCXO output . Connect to ground . 38.88 MHz PLL Loop Filter. 38.88 MHz PLL Loop Filter Enable . CMOS logic high enables LFO . CMOS logic low sets output LFO to high-imped- H15, G15 H16, G16 G14 LFP LFN VCP VCN INLOSN Analog - D8 RREF Analog Analog Iu ance state. High-Speed PLL Loop Filter. Connect to external loop filter components and also connect LFP to VCP and LFN to VCN . High-Speed VCO Control Voltage . Connect to external loop filter components and connect VCP to LFP and VCN to LFN . CMOS Input Loss of Signal . Active-low input signal forces control voltage on high-speed oscillator to the lowest end of the oscillator frequency range : 0 = force lowest-frequency operation in high-speed oscillator. 1 or no connection = normal operation . Resistor Reference . LVDS output voltage reference resistor. Insert a 1 .5 ktl resistor from RREF to VDDLVDS . * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low. t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . Agere Systems Inc. 9 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Ball Information (continued) Table 4. Ball Descriptions-Output Clocks and Related Signals Ball Symbol* Typet Level A9, A8 J1, H1 A15, A3 A14, A2 R1, C1 P1, 131 G4 F4 C2 132 L3, K4, L4,1_2 E4 A12, A6 A11, A5 M1, F1 L1, E1 E13, C14, D14, 1314, C13, D13, D12, C12, D11, D10 F13 CK622P CK622N PCK622P PCK622N CK155P[1 :0] CK155N[1 :0] PCK155P[1 :0] PCK155N[1 :0] CK77 CK51 CK38 CK19 SDHSEL[3:0] O LVDS O O Name/Description 622 .08 MHz Output Clock . LVPECL 622 .08 MHz Output Clock . LVDS 155.52 MHz Output Clock . O LVPECL 155.52 MHz Output Clock . O O O O ID CMOS CMOS CMOS CMOS CMOS 77.76 MHz Output Clock . 51 .84 MHz Output Clock . 38.88 MHz Output Clock . 19.44 MHz Output Clock . SDH Clock Output Selection . SYNC8K SYLVSP[1 :0] SYLVSN[1 :0] SYPCLP[1 :0] SYPCLN[1 :0] SYOFF[9 :0] O O CMOS LVDS 8 kHz Output Sync. 8 kHz Sync Buffers [1 :0] . O LVPECL 8 kHz Sync Buffers [1 :0] . ID CMOS Sync Offset . Programs the magnitude of the offset of the output syncs relative to an input 8 kHz clock/sync. SYOFFPOS Iu CMOS D15 SYDU Iu CMOS C5 D5 C4 134 C3 P2, P3, T4, R5 CKPDH5 CKPDH4 CKPDH3 CKPDH2 CKPDH1 PDHSEL[3 :0] O O O O O ID CMOS CMOS CMOS CMOS CMOS CMOS Sync Offset Positive or Negative . Selects the direction of the sync offset : 1 = positive offset. The output sync is delayed in time. 0 = negative offset. The output sync is advanced in time. Sync Duty Cycle . Selects the duty cycle of the output sync signals : 1 = 50% duty cycle. 0 = sync logic high time equal to one period of the highest-frequency active SONET output clock . Selectable PDH Output Clock. Selectable PDH Output Clock. Selectable PDH Output Clock. Selectable PDH Output Clock. Selectable PDH Output Clock. PDH Clock Output Selection . * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low . t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . 10 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Ball Information (continued) Table 5. Ball Descriptions-Control and Related Signals Ball Symbol* Typet Level L15 SELCLK Iu M16 SELBUN Iu M14 AUTOSWN Iu M15 REVERTN Iu N16 SWCONTN Iu N14 ENSQLN Iu Name/Description CMOS Select Clock. Select clock A or clock B (when SELBUN = 1) : 1 = select clock A. 0 = select clock B. This signal is overridden by SELBUN when SELBUN is active . CMOS Select Backup Clock. Active-low signal selects CLKBU : 0 = select CLKBU, overrides SELCK . 1 = allow SELCK to select clock A or clock B. CMOS Auto Switching Enabled . Active-low signal allows the user to enable autonomous switching from the currently selected clock : 0 = autonomous switching is enabled. (Software Control must be disabled (SWCONTN = 1) .) 1 = autonomous switching is disabled . CMOS Revertive Switching Enabled . Active-low signal determines if the user would like to revert to the original reference source after a fault clears : 1 = state machine is nonreverting such that the switch will not return to the original clock after the fault condition ceases to exist. 0 = state machine is reverting such that the switch will return to the original state after the error condition ceases to exist and at least 256 ms have passed since the switch. CMOS Software Control . Active-low signal allows the user to explicitly choose which clock input to use. Activating this input causes SELCLK and SELBUN to override any fault checking before switching : 0 = software control is enabled . (Overrides autonomous switching (AUTOSWN) setting .) 1 = software control is disabled . CMOS Enable Squelch . Active-low signal enables automatic squelching of the clock and sync outputs whenever a fault is encountered . When squelching occurs, all output clock and sync signals will be held at a logic-low output level. If the device is outputs will be (clock A, clock 1 = automatic 0 = automatic N15 P13 RESETN ENLON Iu Iu not in software control mode (SWCONTN = 1), the squelched if squelch is enabled and all input clocks B, CLKBU) are lost : squelching of the outputs is disabled . squelching of the outputs is enabled . If the device is in the software override mode (SWCONTN = 0), then ENSQLN can be used to manually squelch the device clock outputs : 1 = normal device clock output operation . 0 = manually squelch the device clock outputs . CMOS Reset . Active-low asynchronous reset . CMOS Enable Lockout . Active-low signal allows the user to provide a lockout function to prevent excessive switching between references : 1 = free to switch for any fault. 0 = lockout the autonomous switch whenever the internal lockout flag is active due to excessive switching . * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low. t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . Agere Systems Inc. 11 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Pin Information (continued) Table 5. Pin Descriptions-Output Clocks and Related Signals (continued) Ball Symbol* Typet Level R12 LORSTN Iu N11, P12 SWSTATE [1 :0] O N5, R6, P6, N6, N7, R7, R10, N9, N10 INT[8 :0] O Name/Description CMOS Lockout Trigger Reset . Active-low signal resets the lockout counter to prevent locking out the protection switch : 0 = clear the lockout counter . 1 = normal lockout counter operation . CMOS Switch State. Reflects whether the device is currently selecting clock A, clock B, or the backup clock : 00 = select clock A. 01 =select clock B . 10 = select backup clock (previous clock source was clock A). 11 = select backup clock (previous clock source was clock B) . CMOS Interrupts. Active-high interrupts define fault conditions . See Table 28 on page 38 for individual interrupt definitions . * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low . t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . Table 6. Ball Descriptions-Test and Reserved Signals Ball Symbol* Typet R2 SERCLK Iu N3 SERENBLN Iu N2 SERDAT Iu B15 B16 C16 P10 P8 M4 TSTMODE TSTCLKP TSTCLKN RSVA RSVB SDH HW ID ID ID ID Level Name/Description CMOS Serial Interface Clock . Serial interface clock that can operate up to 25 MHz . CMOS Serial Interface Enable . This signal must be low during regis- ter access . CMOS Serial Data. This is a bidirectional ball for writing and reading software registers . CMOS Test Mode. Internal test observation signal used in test mode. LVDS Test Clock Input. CMOS Reserve Input A or B. Reserved for future feature enhancement. CMOS Internal Signal . When set to a CMOS logic high, the SDH block takes information directly from the external leads and does not use information from the internal bus . Hence, if the internal bus is functional, solder ball M4 may be designated as a ground . * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low . t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . Table 7. Ball Descriptions-No-Connect Signals Ball Symbol* Typet Level G13, J16, K16, P7, P11 NC - - Name/Description Not connected . * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low . t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . 12 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Ball Information (continued) Table 8. Ball Descriptions- Power Signals Ball Symbol* Typet Level Name/Description C11, D2 D1, F2, G1, G2, G3, H2, J2, J3, K1, K2, N1, T1 D9, C6, D7 M2, M3, P16 T2 N8, P9 P14, P15 K14, J14 J15, F15 E15 E14, F14 D6, 135, 133 C15 A1, A4, A7, A10, A13, A16, B6, B7, B8, B9, B10, 1311, 1312, 1313, C7, C8, C9, C10, D3, D4, D16, F3, F16, G7, G8, G9, G10, H7, H8, H9, 1-110,1-113,1-114, J4, J7, J8, J9, J10, J13, K3, K7, K8, K9, K10, M13, N4, N13, P4, P5, R3, R4, R8, R9, R11, R13, R14, R15, R16, T5, T9, T13 VDDSDH VDDPECL Power Power - - VDDLVDS VDDCNTL VDDCLKBU VDDFF VDDLSPLL VDDHSDIV VDDHSVCO VDDLSVCO VDDHSPD VDDPDH VDDTCLK GND Power Power Power Power Power Power Power Power Power Power Power Ground - - * Differential pairs are indicated by P and N suffixes . For nondifferential signals, N at the end of the symbol name designates active-low. t I = input, O = output. Iu indicates an internal pull-up resistor on this ball . I indicates an internal pull-down resistor on this ball . Agere Systems Inc. 13 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Functional Overview The TSWC03622 is designed to manage clock generation and timing distribution in SONET/SDH compliant line card solutions up to OC-12 data rates. Its output clocks are designed to enable hitless clock switching between a primary and secondary clock source and meet relevant output clock jitter generation specifications and maximum time interval error (MTIE) during a switching transient . It supports a range of common input frequencies from 8 kHz to 51 .84 MHz . A backup frequency source is also supported that can be used as a frequency reference when both primary and secondary input clocks are lost. During a switch from either the primary or the secondary clock inputs to the backup reference input, the TSWC03622 output clocks do not guarantee compliance with SONET MTIE specifications . An integrated digital state machine monitors the presence of all input clock signals and can provide autonomous clock switching under fault conditions . Several programmable options are available that determine the behavior of clock switching, including complete software control of the switching events . Programming of the TSWC03622 can be accomplished through external ball control or through internal registers, via a serial interface . A range of SONET and PDH clock frequencies are generated with 155 MHz and 622 MHz clocks available on multiple low-skew LVDS and LVPECL output buffers in order to provide fan-out and clock distribution sources for multiple chips within the system . An 8 kHz sync signal with a user-programmable offset is generated and is available on CMOS, LVDS, and LVPECL output buffers . The duty cycle of the 8 kHz output sync signal is selectable as either 50% or as the width of a single clock pulse determined by the maximum selected SONET/SDH related output frequency . Description of Transient Switching Behavior The TSWC03622 is designed for application in systems that utilize a number of different timing and data distribution architectures . Because the frequency and phase alignment of timing distribution signals, as well as the architectures used for frame alignment and data buffering all vary for different system architectures and product implementations, the characteristics of the TSWC03622's switching behavior must be properly exploited by the system architecture . A description of the switching transient behavior is provided here. 14 Preliminary Data Sheet May 2002 In general, two timing signals will be distributed as the clock A and clock B inputs to the TSWC03622 . These inputs may range in frequency from 8 kHz to 51 .84 MHz . In some cases, the timing source that generates clock A and clock B is designed such that the two clocks are coupled . Therefore, the relative phase of clock A and clock B will be small . In other cases, the phases of clock A and clock B will be uncontrolled with respect to each other and the phase difference between the two clocks could be up to a full period of the input frequency . When the input frequency is relatively high, the phase difference can only be a few tens of nanoseconds due to the small time period of one clock cycle. In the cases where the input frequency is relatively low and the two timing sources are not cross coupled, the phase difference can be up to many tens of microseconds due to the large time period of one clock cycle. When the input frequency is relatively low but the two timing sources have been cross coupled and the skew has been well controlled as the signals are distributed, the phase difference may be controlled within just a few tens of nanoseconds . Some system architectures rely on the fact that there will be a small phase difference between the primary and secondary timing signals, and therefore, they do not provide extensive data buffering or alignment capabilities elsewhere in the system . They rely on a hitless phase step when a switch occurs between clock A and clock B followed by a slow adjustment or "bleed out" of the phase step during a transient period . The phase bleed out adjustment must, however, comply with MTI E and TDEV requirements during a transient switching event as defined in relevant standards . System architectures that use low-frequency signals for timing distribution but do not cross couple the timing sources may have a large phase difference between clock A and clock B at the time a clock switch is initiated . In this case, the output clocks must still have a hitless phase step at the moment the switch occurs . However, SONET MTIE requirements do not generally allow the subsequent phase bleed out to completely adjust for the entire phase difference. Bleeding out the entire phase difference at a rate consistent with MTIE and TDEV transient requirements would cause the transient condition to exist for a duration longer than allowed in the standards . Therefore, systems that distribute low-frequency timing signals with arbitrary skew must provide extensive data buffering or alignment capabilities elsewhere in the system . Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Description of Transient Switching Behavior (continued) The TSWC03622 provides hitless phase switching with clock inputs of arbitrary phase difference at frequencies from 8 kHz to 51 .84 MHz . However, a complete adjustment or bleed out of the phase will occur only for phase differences less than approximately 200 ns. For all input phase differences of greater than this, the transient will cease after the maximum phase has been adjusted (maximum 250 ns) . Figure 4 shows the TSWC03622 switching transient behavior for the condition of small phase differences between input clocks. Figure 5 shows the TSWC03622 switching transient behavior for the condition of large phase differences between input clocks . INPUT CLOCKS CLOCK-A SELECTED CLOCK-B STANDBY I tPHASE < APPROX 250 ns OUTPUT CLOCKS/SYNCS PRIOR TO SWITCH PDH/SDH* CLOCK OUTPUTS SYNC OUTPUTS OUTPUT CLOCKS/SYNCS AT INSTANT OF SWITCH FROM CLOCK-A TO CLOCK-B HITLESS PHASE SWITCH PDH/SDH CLOCK OUTPUTS SYNC OUTPUTS OUPUT CLOCKS/SYNCS DURING TRANSIENT PHASE MOVEMENT MEETS MTIE/TDEV PDH/SDH CLOCK OUTPUTS ~ SYNC OUTPUTS I " "I OUTPUT CLOCKS/SYNCS AT END OF TRANSIENT OUTPUTS ALIGNED TO CLOCK-B PDH/SDH CLOCK OUTPUTS SYNC OUTPUTS 2361 (F) * This diagram shows the phase relationship of the clock outputs and the sync outputs . In the case of PDH clock outputs, the timing relationship between clock and sync is not necessarily as shown here since the phase relationship between the PDH clock outputs and an 8 kHz sync is not specified . Figure 4. Transient Behavior for Small Phase Differences in Input Clocks Agere Systems Inc. 15 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Description of Transient Switching Behavior (continued) INPUT CLOCKS CLOCK-A SELECTED STANDBY STANDBY I- - tPHASE > APPROX 250 ns OUTPUT CLOCKS/SYNCS PRIOR TO SWITCH PDH/SDH* CLOCK OUTPUTS SYNC OUTPUTS OUTPUT CLOCKS/SYNCS AT INSTANT OF SWITCH FROM CLOCK-A TO CLOCK-B HITLESS PHASE SWITCH PDH/SDH CLOCK OUTPUTS SYNC OUTPUTS OUPUT CLOCKS/SYNCS DURING TRANSIENT PHASE MOVEMENT MEETS MTIE/TDEV I ;j ;11 PDH/SDH CLOCK OUTPUTS SYNC OUTPUTS ; ;j. . . . . ............11!11~11-111 _ tPHASE= 200 ns (TAP) 250 ns (MAX) OUTPUT CLOCKS/ SYNCS AT END OF TRANSIENT MAXIMUM PHASE BLEED PDH/SDH CLOCK OUTPUTS SYNC OUTPUTS 2362 (F) * This diagram shows the phase relationship of the clock outputs and the sync outputs . In the case of PDH clock outputs, the timing relationship between clock and sync is not necessarily as shown here since the phase relationship between the PDH clock outputs and an 8 kHz sync is not specified . Figure 5. Transient Behavior for Large Phase Differences in Input Clocks 16 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Input Clock Specifications Input Clock Stability Requirements (Clock A and Clock B) The clock A and clock B inputs to the TSWC03622 must be compliant with all requirements for a SON ET minimum clock (SMC) as defined in TelcordiaTm GR-253-CORE Section 5 .4.4 .2 (Issue 3, 9/2000), or for an ITU node clock as defined in G.812, in order for the TSWC03622 to meet its output clock specifications and transient phase requirements . Input Frequency Selection (FINSEL[3 :0]) The input clock signal frequencies that are supported on the clock A and clock B inputs, as well as the appropriate frequency selection control ball programming, are given in Table 9 . Input frequency selection can be performed using external balls FINSEL[3:0] or by programming register 0x21 bits 3:0 (with SDH HW ball low) . Table 9. Input Clock A and Clock B Frequency Selection Input Frequency Clock A and Clock B FINSEL3 FINSEL2 FINSEL1 FINSELO 8 kHz 1 .544 MHz 2 .048 MHz 6 .480 MHz 8 .192 MHz 19.44 MHz 38.88 MHz 51 .84 MHz NC NC NC NC NC NC NC NC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I I I I Input Electrical Level Selection for Clock A and Clock B Input Signals (SELLVDS) When SELLVDS = 0, the CLKA and CLKB CMOS level input buffers are selected as the clock A and clock B inputs . When SELLVDS = 1 (or no connection is made to the SELLVDS ball), the CLKAP/N and CLKBP/N LVDS level input buffers are selected as the clock A and clock B inputs . Backup Reference Clock Selection (FBUSEL[3 :0]) The TSWC03622 provides the ability to switch to a backup clock under certain fault conditions . When the backup clock is selected, the TSWC03622 is not guaranteed to meet any of the transient phase response requirements associated with a switching event between the A and B clock inputs . The backup is intended to offer a frequency control reference only and is not intended to meet any of the requirements of a system holdover state. The input backup clock frequencies that are supported on the CLKBU input signal as well as the appropriate frequency selection control signal programming are given in Table 10. Backup reference frequency selection can be performed using external balls FBUSEL[3 :0] or by programming register 0x22 bits 3 :0 (with SDH HW ball low). Agere Systems Inc. 17 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Input Clock Specifications Preliminary Data Sheet May 2002 (continued) Table 10. Backup Clock Frequency Selection Input Frequency Tolerance (ppm)* CLKBU 20 8 kHz 1 .544 MHz 20 2 .048 MHz 20 20 6 .480 MHz 8 .192 MHz 20 20 19 .44 MHz 20 38.88 MHz 51 .84 MHz I 20 I FBUSEL3 FBUSEL2 FBUSEL1 FBUSELO NC NC NC NC NC NC NC NC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I I I * Tolerance needed for the TSWC03622 to maintain frequency lock with specified VCXO . This tolerance is not intended to represent a system requirement . Input Clock Minimum Pulse-Width Specifications (Clock A, Clock B, CLKBU) In order for the TSWC03622 to guarantee functionality and that all transient timing specifications are met, the input clock must maintain a minimum pulse width tPw = 8 ns for input frequencies greater than 8 kHz ; for input frequencies less than 8 kHz, a 50% duty cycle is required, as shown in Figure 6 . Input Clock Minimum Pulse Width tPW CLOCK-A, CLOCK-B, OR BACKUP CLOCK 2363 (F) Figure 6. Input Clock Minimum Pulse Width Requirement Output Clock Specifications Available Output Clocks The TSWC03622 supports the generation of the SONET/SDH and PDH frequencies given in Table 13, as well as the ability to program frequency output rates up to TBD MHz, using fractional synthesis . Not all PDH frequencies listed in Table 13 are available simultaneously. Table 11 and Table 12 illustrate the combination of output clock frequencies available simultaneously based on the PDHSEL[3 :0] and SDHSEL[3 :0] control words. There are several levels of programming the PDH1PDH5 outputs . The PDHSEL[3 :0] control word can be programmed using external balls PDHSEL[3 :0] (with mode bits 0x81 bits 4 :3 set to 00, which is the default state) or by programming register 0x80 bits 15 :12 (with mode bits 0x81 bits 4 :3 set to 10) . Additionally, each 18 PDH output can be programmed individually using registers 0x82 and 0x83 (with mode bits 0x81 bits 4 :3 set to 01 or 11) . If the mode for any PDH output is set to Ob1110, then any frequency can be programmed to the output, up to TBD MHz, using the outputs respective registers in the range 0x40 to 0x66. To program these registers, please contact Agere to get an automated program that provides programming instructions based on the desired frequency output. The SDHSEL[3 :0] control word can be programmed using external balls SDHSEL[3:0] or by programming register OxA1 bits 3 :0 (with OxAO bit 1 high and SDH HW ball low). Individual SONET/SDH output syncs and clocks can also be enabled or disabled individually using registers OxA4 and OxA5 respectively. Additionally, the CK77, CK51, CK38, and CK19 clocks can be aligned such that either the positive or the negative edge is aligned to an input 8 kHz signal using register OxA7 (with OXAO bits 1 and 2 low). Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Output Clock Specifications (continued) Table 11 . SDH Output Clock Selection (SDHSEL[3 :0]) Clock/ Sync SDHSEL[3 :0] State Value and Associated Output Signals* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CK622P/N Z 622 .08 622 .08 Z 622 .08 Z 622 .08 Z Z Z Z Z Z Z Z Z PCK622P/N Z 622 .08 Z 622 .08 Z 622 .08 0 Z 622 .08 Z Z Z Z Z Z Z CK155P/N[i] 155.52 MHz Z Z Z 155.52 MHz Z Z 155.52 MHz Z Z Z Z Z Z Z Z CK155P/N[0] 155.52 MHz Z 155.52 MHz Z 155.52 MHz Z Z 155.52 MHz Z Z Z Z Z Z Z Z PCK155P/N[i] 155.52 MHz 155.52 MHz Z Z Z 155.52 MHz Z Z Z 155.52 MHz Z Z Z Z Z Z PCK155P/N[0] 155 .52 155 .52 Z 155 .52 Z 155 .52 Z Z Z 155 .52 Z Z Z Z Z Z CK77 Z 77 .76 MHz Z Z Z Z Z Z Z Z 77 .76 77 .76 MHz MHz Z Z Z Z CK51 51 .84 MHz Z Z Z Z Z Z Z Z Z 51 .84 MHz Z 51 .84 MHz Z Z Z CK38 Z Z Z Z Z Z Z Z Z Z 38 .88 MHz Z Z 38 .88 MHz Z Z CK19 19 .44 MHz Z Z Z Z Z Z Z Z Z 19 .44 MHz Z Z Z 19 .44 MHz Z Z 8.0 kHz Z Z Z Z Z Z Z Z 8.0 kHz 8.0 kHz 8.0 kHz 8.0 kHz 8.0 kHz Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z I Z Output Name SYNC8K SYLVSP/N[i] SYLVSP/N[0] SYPCLP/N[i] SYPCLP/N[0] MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz t # t t 8.0 kHz Z 8.0 kHz Z 8.0 kHz Z Z 8.0 kHz t # t t t t 8.0 kHz 8.0 kHz 8.0 kHz Z 8.0 kHz Z 8.0 kHz 8.0 kHz t t t Z 8.0 kHz Z 8.0 kHz Z 8.0 kHz Z Z I 8.0 kHzt I 8.0 kHzt I Z I 8.0 kHz t I Z I 8.0 kHzt I Z I Z MHz Z Z Z 8.0 kHz t I 8.0 kHz$ I 8.0 kHz t I Z I Z I Z I Z I * Z = high impedance . t If SYDU = 0, duty cycle = 50% . If SYDU = 1, sync logic high time equal to one period of a 155 .52 MHz clock (6 .43 ns) $ If SYDU = 0, duty cycle = 50% . If SYDU = 1, sync logic high time equal to one period of a 622 .08 MHz clock (1 .6075 ns) Table 12 . PDH Output Clock Selection (PDHSEL[3 :0]) Clock/ Sync Output Name CKPDH5 CKPDH4 PDHSEL[3 :0] State Value and Associated Output Signals* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2.43 MHz Z 1 .544 MHz 1 .544 MHz Z Z Z Z Z Z Z Z Z Z Z 2.048 MHz 1 .544 MHz 1 .544 MHz Z 2.43 MHz Z Z Z Z Z Z Z Z Z Z 2.048 MHz Z 4.096 MHz 8.192 MHz Z Z Z Z Z Z Z CKPDH3 1 .544 MHz 2.048 MHz Z 24 .704 MHz 24 .704 MHz CKPDH2 32 .768 Z 32 .768 32 .768 Z Z Z Z Z Z 16 .384 Z 32 .768 Z Z Z CKPDH1 44 .736 MHz Z 34 .368 MHz 44 .736 MHz Z Z Z Z Z Z Z 24 .704 MHz Z 34 .368 MHz 44 .736 MHz Z MHz 2.048 MHz MHz MHz 2.048 MHz MHz MHz Z = high impedance. Agere Systems Inc. 19 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Jitter Specifications The clock frequencies listed in Table 13 are normally available at their respective output balls under the indicated conditions . The jitter specifications listed apply whenever input clock A is selected or input clock B is selected, as well as during any transients due to a switching event between clock A and clock B. The jitter specifications are met if the input clocks comply with the input clock stability requirements. Table 13. Output Clock Jitter Specifications Ball Output Frequency Jitter (stnd) Jitter (device) Unit CKPDH5 CKPDH5 CKPDH4 CKPDH4 CKPDH3 CKPDH3 CKPDH3 CKPDH2 CKPDH3 CKPDH1 CKPDH2 CKPDH1 CKPDH1 2 .43 MHz 1 .544 MHz <1 .0 <0.05 TBD TBD Ulp-p 2.048 MHz <0.05 TBD Ulp-p 20 Hz-100 kHz 4.096 MHz 8.192 MHz 16 .384 MHz 24 .704 MHz - - - - 32 .768 MHz 34 .368 MHz 44 .736 MHz <0.05 <0.01 <0.10 <0.01 <0.10 TBD TBD TBD TBD Ulp-p Ulrms Ulp-p Ulrms Ulp-p 100 Hz-800 kHz 10 Hz-400 kHz 10 Hz-400 kHz 12 kHz-400 kHz 12 kHz-400 kHz <0.01 <0.10 <0.01 <0.10 <0.01 <0.10 <0.01 <0.10 TBD TBD TBD TBD TBD TBD TBD TBD Ulrms Ulp-p Ulrms Ulp-p Ulrms Ulp-p Ulrms Ulp-p CK19 CK38 CK51 CK77 20 19.44 MHz 38.88 MHz 51 .84 MHz 77 .76 MHz CK155P/N 155.52 MHz PCK155P/N 155.52 MHz CK622P/N 622 .08 MHz PCK622P/N 622 .08 MHz - - - Measurement Bandwidth 10 Hz-40 kHz 12 12 12 12 12 12 12 12 - kHz-2 kHz-2 kHz-2 kHz-2 kHz-5 kHz-5 kHz-5 kHz-5 MHz MHz MHz MHz MHz MHz MHz MHz Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Synchronization Output at 8 kHz Sync Output (SYNC8K, SYLVSP/N[1 :0], SYPCLKP/N[1 :0]) The TSWC03622 generates an output 8 kHz synchronization signal for use in frame and cell alignment in systems that require this capability. Typically, the output sync is meaningful only in systems that distribute 8 kHz synchronization signals as the timing references on clock A and clock B. In these cases, the alignment of the output sync to the input sync (8 kHz on clock A and clock B inputs) is a critical aspect of system synchronization . When higher-speed clocks are distributed, the alignment of the sync with respect to the input clock becomes arbitrary. Sync outputs can be configured along with the SONET/SDH clock outputs with the SDHSEL[3 :0] control word. The SDHSEL[3:0] control word can be programmed using external balls SDHSEL[3 :0] or by programming register OxA1 bits 3 :0 (with OxAO bit 1 high and SDH_HW ball low). Individual SONET/SDH output syncs can also be enabled or disabled individually using register OxA4. Sync Duty Cycle Selection (SYDU) There are several methods of controlling the sync output duty cycle . In the first method, the SDHSEL[3 :0] output frequency is used. In this method, the duty cycle of the 8 kHz sync signals is selectable as either 50% or as the width of a single SONET clock pulse width. When the duty cycle is selected to be a single clock pulse width, the pulse width is determined to be equal to one period of the highest-frequency active SONET output clock . The frequencies of the active PDH clocks are not considered. Sync duty cycle selection can be performed using external ball SYDU or by programming register OxA2 bit 0 (with register OxAO bit 2 high and SDH HW ball low) . Clock Synthesizer and Protection Switch OxA4 in conjunction with register OxA6. The last method is to adjust the falling edge of the sync outputs using register OxB2, which, in effect, adjusts the duty cycle . (The rising edge can be adjusted using the sync offset programming explained below.) Sync Alignment When 8 kHz synchronization signals are applied as input timing on clock A and clock B, the output sync is phase aligned to the input sync to. Adjustments of this delay may be made using the TSWC03622 sync offset programmability feature . Offset Programming (SYOFF[9:0], SYOFFPOS) Some system applications require the 8 kHz synchronization to be offset according to the demands of the system architecture . The TSWC03622 provides the capability of offsetting the output sync in increments of 1 .6075 ns (one 622 .08 MHz clock) . The sync offset will apply to all output syncs (SYN8K, SYLVSP/N[1 :0], SYPCLP/N[1 :0]) simultaneously . There are two types of offset capability on the TSWC . The first has to capability to offset up to 1 .644 ps with a resolution of 1 .6075 ns (1023 periods of a 622 .08 MHz clock with a resolution of one period of the 622 .08 MHz clock) . This offset can be performed using external balls SYOFF[9 :0] and SYOFFPOS or by programming register OxA3 bits 10 :0 (with register OxAO bit 3 high and SDH HW ball low) . Programming of the sync offset is described in Table 15. Table 14. Sync Duty Cycle Selection (SYDU) SYDU 1 0 SYNC8K Duty Cycle 50% High for one period of highest-frequency active SONET clock output A second method is used when the sync outputs are individually enabled through register OxA4. In this method, pulse-width options remain selectable as either 50% or as the width of a single SONET clock pulse width . Pulse widths are selected using register Agere Systems Inc. 21 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Synchronization Output at 8 kHz (continued) Table 15. SYNC Offset Programming Ball SYOFF[9 :0] SYOFFPOS Function Sets the magnitude of the sync offset value in increments of 1/622 .08 MHz or 1 .6075 ns: SYOFF[9 :0] = 0000000000 equals zero offset. SYOFF[9 :0] = 1111111111 equals 1 .644 ps (1023/622 .08 MHz) offset. Sets the sign or direction of the sync offset: SYOFFPOS = 1 is a positive offset. The output sync is delayed in time. SYOFFPOS = 0 is a negative offset. The output sync is advanced in time . The second type of sync offset is an enhanced capability that enables the sync to be offset over the entire 125 ps period (in the same increments of 1 .6075 ns). This is accomplished using 16 bits of offset and a positive/negative directional control . This functionality is available by programming registers OxA8 and OxA9 (with register OxAO bit 3 low and SDH HW ball low) . The programming is similar to the first offset type and is shown in Figure 16. Note that there is a limit to the size of the offset so that the offset is not greater than one 125 ps period. Table 16. Enhanced SYNC Offset Programming Ball Function SYOFF[16 :0] Sets the magnitude of the sync offset value in increments of 1/622 .08 MHz or 1 .6075 ns: SYOFF[16 :0] = 0 0000 0000 0000 0000 equals zero offset. SYOFFPOS 22 SYOFF[16 :0] = 1 0010 1111 0110 0000 equals 125 ps (77760/622 .08 MHz) offset. Sets the sign or direction of the sync offset: SYOFFPOS = 1 is a positive offset. The output sync is delayed in time. SYOFFPOS = 0 is a negative offset. The output sync is advanced in time . Agere Systems Inc . AdLib OCR EvaluationTSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Skew Specifications PCK622P/N SYPCLP/N [ 1 :0] i tiol t103 2364 (F) Figure 7 . PECL Sync to PECL Clock Skew Case : Syncs Aligned to 622 MHz Clock Table 17. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol Skew Parameter Min Max Typ Unit PCK622P/N SYPCLP/N[1 :0] PCK622P/N PCK622P/N SYPCLP/N[1 :0] t100 Clock falling to sync rising 0 0.5 - ns t101/t103 t102 Clock duty cycle Clock falling to sync falling 45 0 55 0.5 50 - ns Agere Systems Inc. 23 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Skew Specifications (continued) tzoo tzoz PCK155P/N [0] SYPCLP/N [0] tzo1 tzos tz~o tz~z PCK155P/N[i ] SYPCLP/N[i ] tzl tz~s 2365 (F) Figure 8. PECL Sync to PECL Clock Skew Case : Sync Aligned to 155 MHz Clock Table 18. PECL Sync to PECL Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol Skew Parameter Min Max Typ Unit PCK155P/N[0] SYPCLP/N[0] PCK155P/N[0] PCK155P/N[0] SYPCLP/N[0] PCK155P/N[1 ] SYPCLP/N[1 ] PCK155P/N[l] PCK155P/N[1 ] SYPCLP/N[1 ] t200 Clock Falling to Sync Rising -1 .0 0 - ns t201/t203 t202 Clock Duty Cycle Clock Falling to Sync Falling 45 -1 .0 55 0 50 - ns t210 Clock Falling to Sync Rising -1 .0 0 - ns t211/t213 Clock Duty Cycle Clock Falling to Sync Falling 45 -1 .0 55 0 50 - ns 24 t212 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Skew Specifications (continued) CK622P/N SYLVSP/N [1 :0] 2366 (F) Figure 9. LVDS Sync to LVDS Clock Skew Case : Sync Aligned to 622 MHz Clock Table 19. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Applicable Balls Symbol Skew Parameter Min Max Typ Unit CK622P/N SYLVSP/N[1 :0] CK622P/N CK622P/N SYLVSP/N[1 :0] t300 Clock Falling to Sync Rising 0 0 .5 - ns t301 /t303 t302 Clock Duty Cycle Clock Falling to Sync Falling 45 0 55 0 .5 50 - ns Agere Systems Inc. 25 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Skew Specifications (continued) taoo taoz CK 155P/N [0] SYLVSP/N [0] tao1 taos taro ta~z CK155P/N[i] SYLVSP/N[i] -------------------------------------------ta>> tags 2367 (F) Figure 10. LVDS Sync to LVDS Clock Skew Case : Sync Aligned to 155 MHz Clock Table 20. LVDS Sync to LVDS Clock Skew Parameters (Single Clock Pulse Sync Output Shown) Symbol CK155P/N[0] SYLVSP/N[0] CK155P/N[0] CK155P/N[0] SYLVSP/N[0] CK155P/N[1] SYLVSP/N[1 ] CK155P/N[1] CK155P/N[1] SYLVSP/N[1 ] t400 26 Applicable Balls Min Max Typ Unit Clock Falling to Sync Rising -1 .0 0 - ns t401/t403 t402 Clock Duty Cycle Clock Falling to Sync Falling 45 -1 .0 55 0 50 - ns t410 Clock Falling to Sync Rising -1 .0 0 - ns t411/t413 Clock Duty Cycle Clock Falling to Sync Falling 45 -1 .0 55 0 50 - ns t412 Skew Parameter Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Skew Specifications (continued) ~ ; t500 ;~ I I CK19, CK38, CK51, CK77 SYNC8K I I I I I I I I I I I I I I I I I 1502 II I I :-III*- I I I II I I I I I I I I t 'I I I II I 1503 I Figure 11 . CMOS Sync to CMOS Clock Skew Case: Sync Aligned to 622 MHz Clock Table 21 . CMOS Sync to CMOS Clock Skew Parameters (15 pF, 50 52) (Single Clock Pulse Sync Output Shown) Applicable Balls CK19, CK38, CK51, CK77, SYNC8K CK19, CK38, CK51, CK77 CK19, CK38, CK51, CK77, SYNC8K Agere Systems Inc. Symbol t500 t501 /t503 t502 Skew Parameter Clock Falling to Sync Rising Min Max Typ Unit - ns - ns Clock Duty Cycle Sync Rising to Clock Rising 27 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Output Specifications During Phase-Locked Condition (Nontransient Condition) Maximum Time Interval Error (MTIE) Specifications During the phase-locked condition, the TSWC03622 output clocks will meet wander generation as given in Table 22 and shown in Figure 12. When in the locked condition, the MTIE performance will be dominated by the MTIE of the incoming timing signals on clock A and clock B. The TSWC03622 will not add significantly to the MTIE performance . Table 22 . Wander Generation (Nontransient)-MTIE Observation Interval (s) TSWC03622 (ns) GR-253-CORE Figure 5-17 (9/2000) (ns) GR-1244-CORE Figure 5-2 (6/95) (ns) ITU-T G.813 Option 2 Table 4 (8/96) (ns) S < 0 .1 0 .1 < S < 1 .0 1 <S<10 10 < S < 100 100 < S < 1000 S > 1000 NA TBD TBD TBD TBD - NA 20 20XS0.48 60 - NA 40 40XS0 .40 100 100 100 NA 20 20XS0 .48 60 60 - I I I I 1000 GR-1244 CORE 100 ITU-T G.813 OPTION 2 10L_ 0 .1 GR-253 CORE 10 100 1000 OBSERVATION INTERVAL (s) 2368 (F) Figure 12. MTIE Wander Generation in Locked Condition 28 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Output Specifications During Phase-Locked Condition (Nontransient Condition) (continued) 1000 GR-253-CORE/ITU-T G .183 Opt 2 MTIE Requirement 100 c w 10 0. 0 .01 0 .10 1 .00 10.00 Time (sec) 100 .00 1000 .00 Figure 13. Measured MTIE Wander Generation Performance Agere Systems Inc. 29 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Output Specifications During Phase-Locked Condition (Nontransient Condition) (continued) Time Deviation (TDEV) Specifications During the phase-locked condition, the TSWC03622 output clocks will meet TDEV as given in Table 23 and shown in Figure 14. When in the locked condition, the TDEV performance will be dominated by the incoming timing signals on clock A and clock B and the TSWC03622 will not add significantly to the TDEV performance. Table 23. Wander Generation (Nontransient)-TDEV Integration Interval (s) TSWC03622 (ns) GR-253-CORE Figure 5-18 (9/2000) (ns) GR-1244-CORE Figure 5-1 (6/95) (ns) 0.1 <ti<2 .5 2.5<ti<40 40<ti<1000 ti > 1000 1000 < ti < 10,000 TBD TBD TBD TBD TBD 3.2xti-0 .5 2 0.32xti0.5 10 - 3.2xti-0 .5 2 0 .32xti0.5 10 - I I I ITU-T G.813 Option 2 Table 5 (8/96) (ns) 3 .2xti-0 .5 I 2 0 .32xti0 .5 10 100 w 0 F- 10 0.1 ITU-T G .813 OPTION 2 1 GR-253 11111111 1 1 CORE MT 1 NIIfl AND GR-1244 CORE 10 100 1000 10000 OBSERVATION INTERVAL (s) 2369 (F) Figure 14. Wander Generation in Locked Condition 30 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Output Specifications During Transient Condition Maximum Time Interval Error (MTIE) Specifications During the transient condition, the TSWC03622 output clocks will meet wander generation as given in Table 24 and shown in Figure 15. Table 24. Wander Generation (Transient)-MTIE Observation Interval (s) TSWC03622 (ns) GR-253-CORE Figure 5-19 (9/2000) (ns) GR-1244-CORE R5-10 (6/95)* (ns) ITU-T G.813 Option 2 Table 14 (8/96) (ns) ti < 0 .014 0 .014 <,r < 0 .16 0.16 <,r < 0 .5 0.5 <,r < 2.33 2 .33 <,r < 280 NA TBD TBD TBD TBD NA 7.6 + 885ti 7.6 + 885ti 300 + 300ti 1000 1000 1000 1000 1000 1000 NA 7.6 + 885ti 7.6 + 885ti 300 + 300ti 1000 I I I I * Requirement 5-10 also indicates that the maximum phase slope or discontinuity be less than 81 ns for any measurement period of 1 .326 ms . 10000 GR-1244 CORE 1000 w 100 10 L0.01 ITU-T G.813 OPTION 2 AND GR-253 CORE 0 .1 1 10 100 OBSERVATION INTERVAL (s) 1000 2370 (F) Figure 15. MTIE Wander Generation During Transient Condition Agere Systems Inc. 31 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Output Specifications During Transient Condition (continued) 1000 GR-253-CORE FIGURE 5-19 (1/99) 100 \A0 >_ 250 ns A0- 10 ns w 10 0.01 0.10 1 .00 TIME (s) Figure 16. Measured MTIE Performance at Two Different Phase Offsets 32 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Other Input and PLL Specifications Loop Filter Components for High-Speed PLL Input Clock Maximum Rate of Phase Change During Transient The recommended loop filter is shown in Figure 17. Connect the filter components and also connect LFP to VCP and connect LFN to VCN . The component values can be varied to adjust the loop dynamic response. Table 25 provides a set of recommended values to meet output jitter generation requirements in Table 13. In order for the TSWC03622 to guarantee functionality and that all transient MTIE specifications are met, the clock A and clock B inputs must have an instantaneous maximum rate of change consistent with the ITU G.812 requirements for a node clock and Telcordia GR-253CORE Section 5 .4.4.2 (Issue 3, 9/2000) . Table 25. High-Speed Loop Filter Recommended Values Components External 38 .88 MHz VCXO Requirements The following is a brief specification for the 38 .88 MHz VCXO unit: . Supply voltage : 3 .30 V 5% . Control voltage range : 0 .3 V minimum, 2 .7 V maximum . Temperature range (ambient) : -40 C to +85 C . Output buffer : - Technology : CMOS (3 .30 V) - Duty cycle: 45/55% - Transient times: 1 ns maximum (20% to 80%) . Frequency (nominal) : 38 .88 MHz . APR : 20 ppm Note : The APR must include the effects of temperature, supply voltage, shock, vibration, aging, and manufacturing (i.e ., withstanding two solder ref lows). . Linearity : 20% (best linear fit 0.3 V to 2.7 V) . Transfer function : monotonic, positive slope . Center voltage : VDD/2 (nominal 1 .65 V) . Modulation bandwidth : 10 kHz at 38.88 MHz . Input leakage current : <1 pA . Input resistance : >3 MS2 . Reference signal for control voltage : ground . Phase jitter : 1 ps (RMS) maximum 12 kHz to 20 MHz (alternate spec may be expressed in dBc if required) . Start-up time: 2 ms at maximum control voltage Agere Systems Inc. C1* R1 Recommended Values 0 .1 pFor1 .0pF10% 3 .9 ktl 5% * Capacitor C1 should be either ceramic or nonpolar . LFP VCP C1 R1 VCN LFN Figure 17. High-Speed Loop Filter Recommended Circuit Loop Filter Components for Low-Speed PLL The recommend loop filter for phase offsets of Clock A and clock B of less than 30 ns (including all input frequencies for 19 .44 MHz, 38 .88 MHz, and 51 .84 MHz) is shown in Figure 19 and Table 26 . If the phase offset of clock A and clock B is unknown or will be greater than 30 ns, then the recommended filter is shown in Figure 19 and corresponding component values are shown in Table 27 . Analog switches are included in both circuits to reduce the lock time at start-up. This part of the circuitry is only active when the LSPLL is out of lock, it will not become active during a clock switch . In the filter for smaller phase offsets, the addition of the analog switch will reduce the nominal lock time from tens of seconds to less than 6 seconds . In the filter for larger phase offsets, the nominal lock time is reduced from a few minutes to less than 40 seconds . 33 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Other Input and PLL Specifications (continued) Table 26. Low-Speed Loop Filter Recommended Values for Smaller Phase Offsets Components C1 * C2* R1 R2 R3 U1 VCX01 Recommended Values 10 pF 20% 4.7 pF 10% 392 ktl 1 % (390 ktl 5%) 1 .21 ktl 1 % (1 .2 ktl 5%) 20 ktl to 110k52 5% (lower value yields faster lock time) Analog switch See VCXO requirements. * Capacitors C1 and C2 should be either ceramic or nonpolar . t 1 % resistors are recommended for R1 and R2, since the lowspeed PLL filter has high sensitivity to these resistors . However, if these 1 % resistors are not available, the 5% resisters indicated in parentheses are compatible and will make the loop filter function correctly. $ Contact factory for information on Analog Switch requirements . R1 LFO 0:: Vc INT5 U1 RF OUT Preliminary Data Sheet May 2002 Table 27. Low-Speed Loop Filter Recommended Values for all Phase Offsets Components Recommended Values for All Clock A and Clock B Phase Offsets (See Figure 19.) C1 C2 C3 C4 C5 R1 * R2* R3* R4 R5 R6* R7* R8* U1 VCX01 1000 pF 10% 47 pF 20% 47 pF 20% 4.7 pF 20% 4.7 pF 20% 4.99 ktl 1 % (5.1 ktl 5%) 2.49 ktl 1 % (2.4 ktl 5%) 750 ktl 1 % (750 ktl 5%) 20 ktl 5% 10 ktl 5% 2.21 ktl 1 % (2.2 ktl 5%) 383 ktl 1 % (390 kn 5%) 110 kn 5% Analog switch See VCXO requirements. * 1 % resistors are recommended for R1, R2, R3 and R6, since the low-speed PLL filter has high sensitivity to these resistors . However, if these 1 % resistors are not available, the 5% resisters indicated in parentheses are compatible and will make the loop filter function correctly. t Contact factory for information on Analog Switch requirements LSVCO 0- Figure 18. Low-Speed Phase-Lock Loop (LSPLL) Filter Recommended Circuit for Smaller Phase Offsets LFO LFOZ VCX01 F UT INT5 LSVCO Figure 19. Low-Speed Phase-Lock Loop (LSPLL) Filter Recommended Circuit for all Phase Offsets 34 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 INLOSN The INLOSN signal will force the high-speed PLL to drift towards a lower clamped frequency, preventing an excessive high-frequency clock output under invalid input signal conditions . INLOSN may be used to limit the internal clock frequency ensuring proper state machine and control behavior under severe clock fault conditions . Clock Synthesizer and Protection Switch mode of operation, the control circuit will enforce a time-out period between switching events to allow the internal phase-locked loops time to acquire phase lock to the currently selected reference clock. The state diagram of the control circuit state machine is shown in Figure 20 . RREF should be tied to VDDLVDS through a 1 .5 ktl resistor. Clock Switching State Machine and Software Interface More complete documentation of state machine behavior and software interfacing requirements is in preparation . Only a minimal description of behavioral characteristics is included here. Clock Switching State Machine Behavior 2371 (F) Figure 20. Clock Protection Control Circuit State Diagram The TSWC03622 is designed to perform fast, automatic protection switching between primary and secondary clock inputs to the device . The clock switching control circuit implements the following functional requirements : . Autonomously switch from the selected clock to the other clock if the selected clock fails . . Manually switch to any clock input . . Provide a lockout control to prevent excessive autonomous switching . . Provide an override to allow revertive switching, but force the minimum time for reversion to 256 ms from the time the switch was initially made. . Provide a squelch function to bring the device clock outputs to a logic low state (squelched) if clock A, clock B, and CLKBU signals all have a fault. Operation The operation of the clock protection switching control circuit depends on the device inputs and internally generated control signals . This control is performed by a finite state machine containing three states, and there are two modes of operation : autonomous switching (circuit makes decision on what action to take) and nonautonomous switching (external controller makes decision on what action to take). However, in either Agere Systems Inc. 35 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Clock Switching State Machine and Software Interface (continued) The device will select the reference clocks based upon the internal state: reference A if in state A, reference B if in state B, and reference BU if in state BU . The autonomous mode of operation is selected by setting the device signal AUTOSWN to a logic low. In this mode, after the initial reset of the device, the state machine is in state A selecting reference clock A. If the internal loss of clock detector on clock A indicates the absence of clock A, the initial clock reference selected depends on the condition of the SELCLK, SELBUN, and ENSQLN device signals and the status of the internal loss of clock detectors for clock B and clock BU . If the user selects clock BU as the wanted reference, the state machine will check the status of clock BU. If it is present, the device will switch to the back-up reference for the initial phase-lock. However, if the backup reference is absent, the device will check the status of reference B, and if B is present, it will switch to reference B to initially phase-lock to, and if the user selected clock B as the desired reference, the device would check the status of the reference B loss of clock detector. If clock B is present, the device will switch to reference B for initial phase-lock, and if clock B is absent, the device would check for clock BU . If no reference is present and the ENSQLN signal is low, the device will select the reference desired as determined by the SELCLK and SELBUN signals and will force the output clock and sync signals to a logic low level. Upon selecting a reference clock to initially lock to (defaults to reference A) and if the clock is present, the state machine initiates a time-out period to allow the device to phaselock to the selected reference clock. While waiting for the time-out period, the device will activate the switch in progress interrupt, indicate if the selected reference agrees with the wanted reference on the consistent interrupt, and output the selected reference on the SWSTATE signals . After the initial start-up of the clock protection switch control circuit, the state machine will monitor the SELCLK and SELBUN signals and the internal loss of clock flags. If the user initially wants a reference other that which is selected, the state machine will check the status of the desired reference, and it will switch to the desired reference if it is present . This will then initiate a new time-out period to allow the new reference to phase-lock . The circuit will prioritize clocks A and B over clock BU such that if B is selected and disappears, A is checked first for switching before deciding to switch to clock BU . 36 Preliminary Data Sheet May 2002 If the selected clock disappears, the state machine will autonomously switch to another reference that is present . If the REVERTN signal is low, the state machine will automatically return to the originally selected reference after the time-out period has expired . This could cause an oscillation between references, and to limit the length of this oscillation, the state machine has a counter to count the number of transitions between references . If the ENLON signal is low, the state machine will allow 3 transitions to occur before prohibiting further switching . To resume switching, the internal transition counter is cleared by pulsing the LORSTN signal low . This allows external control of the time period monitored by the transition counter . The nonautonomous mode is selected by forcing the AUTOSWN signal high or a no-connection on this signal . The start-up condition causes the device to initially be selecting reference A. If A is absent, the device checks the reference desired (reference selected by SELCLK and SELBUN signals) for presence, and if it is present, the device immediately switches to this reference. If the desired reference is absent, the device will look at the ENSQLN signal for direction . If ENSQLN is low, the state machine will select the desired reference and squelch the output clock and sync signals, and if ENSQLN is high or not-connected, the state machine will remain in the state selecting reference A. If reference A is present, the state machine will initiate the time-out period, and on the expiration of the time-out period, it will check for the presence of the desired clock . If the desired clock is present, the device will switch to the desired clock and initiate another time-out period. If the desired clock is absent, the state machine will remain in state A, and the state consistency interrupt will be active . After the initial start-up of the device, the clock protection switch control circuit will monitor the SELCLK, SELBUN, and ENSQLN signals and the loss of clock interrupts for changes . If the loss of clock interrupt on the currently selected reference goes active, the device will either do nothing or squelch the output clock and sync signals depending on the ENSQLN condition . If ENSQLN is low, the device output clock and sync signals will be forced low . If the desired clock reference changes and the time-out period has expired, the state machine will check the status of the desired reference loss of clock interrupt. If the interrupt is low, the state machine will switch to the desired reference and initiate another time-out period . Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Switching State Machine and Software Interface (continued) Because there are times when a switch to a faulty (absent) reference is desired, the state machine has an override in the form of the SWCONTN signal . Whenever the SWCONTN signal is low, all fault checking done prior to a switch is ignored ; i.e ., the device will unconditionally switch to the reference desired on SELCLK and SELBUN . This override also allows the user to squelch the output clock and sync signals manually by bringing the ENSQLN signal low. There are three interrupts generated by the clock protection switch circuit : clock switch in progress, user selected clock is not consistent with the internal clock selection, and a lockout condition exists due to excessive number of switching events . The clock switch in progress interrupt is active whenever a switching event occurs, and it will remain active until the time-out period after the actual switch expires . The consistency interrupt is active whenever the internal clock selection disagrees with the user desired selection . If a switch request comes from an external source through the SELCLK and SELBUN signals before the internal timeout period has expired, then a consistency interrupt will be generated. This can be prevented by monitoring the clock switch in progress interrupt. If the desired clock reference is absent, the consistency interrupt will be generated, and if the state machine has locked out further switching events, the consistency interrupt will be generated . The lock-out interrupt is generated whenever the number of switching events exceed 3 clock switches . The time period for this count is controlled externally by the period between pulses on the LORSTN signal . Clock Synthesizer and Protection Switch . The external controller may either use an active edge of one of the interrupts or a polling method (monitoring SWSTATE[1 :0], INT[8:0]) to determine the input clock status and the occurrence of an autonomous switch . . Whenever an autonomous switch occurs as indicated by the SWSTATE[1 :0] flag, the software polls the INT[8:0] signals to determine the cause of switching and validates the selection . . Whenever a nonautonomous fault occurs as indicated by the INT[8 :0] flag, the software polls the INT[8 :0] signals and selects the proper action to perform. . After validation of an autonomous switch, the software must pulse AUTOSWN high and reinitialize the clock selection inputs SELCLK and SELBU to match the SWSTATE[1 :0] output signals . If a lockout occurs, the software must pulse LORSTN low to clear the lockout . Loss of Clock Criteria Loss of clock detectors continuously monitor the condition of clock A, clock B, and CLKBU . A loss of clock condition is declared when transitions are absent on the clock input for between 2 and 4 periods of the input frequency . Software Interfacing The clock protection switching circuit is configured by an external controller via software . Whenever interaction with this software is needed, the following guidelines should be followed : . The software must provision the device as desired, appropriately setting SELCLK, SELBUN, AUTOSWN, REVERTN, SWCONTN, ENSQLN, and ENLON upon powerup and after the initial reset completes . Agere Systems Inc. 37 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Clock Switching State Machine and Software Interface (continued) Interrupt Generation (INT[8 :0]) Interrupts are available on external balls INT[8 :0] and via the serial interface in register OxEO. Table 28 defines the conditions under which interrupts are generated for the external balls INT[8 :0]. All of these interrupts are available in register OxEO with the addition of another interrupt that indicates when squelch is active or inactive . Table 28. Interrupt Generation (INT[8 :0]) Active-High INT 8 7 6 5 4 3 2 1 0 Condition Lockout condition exists due to excessive number of switching events User selected clock not consistent with internal clock selection state Loss of lock-high-speed PLL Loss of lock-38 .88 MHz PLL Clock switch in progress Loss of external VCXO clock Loss of CLKBU Loss of CLKB I Loss of CLKA Interrupts 4 and 7 are not meant to be alarms, but more of a status report . INT4 indicates that a switch between any of the clocks is occuring . INT7 indicates to the user that the active clock is the not the clock that the user has selected . For example, in autonomous mode, the default selected state is clock A (cannot be changed), so if clock A is not present and clock B or BU is the working clock, INT7 will be active . Another example is in manual mode with SWCONTN active (SWCONTN active prevents a bad clock from be switched to), if the user selects a clock that is not present (and the original clock is still present), the TSWC will not go to that clock; thus the selected clock is not consistent with the internal clock selection state . 38 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Serial Interface and Internal Bus The TSWC internal registers can be programmed via a serial interface . This serial interface allows reading or writing any of the registers . Internally, the TSWC uses two different lines to transmit and receive data from the outside . Those two lines must be multiplexed by an input/output buffer to the single serial line (simplex communication) . The serial line will be driven by the external controller except when a read process is requested . In that case, the TSWC will drive the line during the time it needs to transmit the requested data. During a period when no read nor write process is requested, SERDAT is pulled internally to a CIVIOS logic high. As shown on Figure 21, there are three external pins related to the serial interface : the serial interface clock SERCLK, the serial interface data line SERDAT and the serial interface enable SERENBLN . r - - - - - - - - - - - - - - - - - - - - - - - - - - - _i I TSWC03622 I I I I I I OUT I SERDAT EXTERNAL CONTROLLER I I SERCLK I SERENBLN IN INTERFACE CONTROLLER I I I I I I I I I I - - - - - - - - - - - - - - - - - - - - - - - - - - - Figure 21 . TSWC03622 Serial Interface The serial interface frames are composed of 32 bits. The two first bits are used to indicate the beginning of the frame (01) . Then the address is transmitted in the next 8 bits, followed by 6 bits indicating if it is a read or write request . Finally the 16 bits of data are transmitted by the external controller (write) or by the TSWC (read process). In case of a read process, the last 17 bits of the frame are driven by the TSWC, following a bit where no device is driving the line, leaving it in high impedance . As soon as the data has been transmitted, the external user continues to drive the line to a high logic state waiting for the next frame to transmit . A representation of a WRITE is shown in Figure 22, and a READ in Figure 23 . The transmission for both the data and address bits starts with the most significant bit . 8-bit Address SERDAT 0 1 A1 A A A4 A A A 16-bit Data A8 0 n0 0 n0 Di D D D D D D D D o~ o>> o~ o~ o~ o~ o~ SERCLK SERENBLN 1 Figure 22. Serial Interface WRITE Frame Format Agere Systems Inc. 39 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Serial Interface and Internal Bus (continued) Driven by External Controller Driven by TSWC01622 8-bit Address 0 SERDAT 1 A1 A A A4 A A A 16-bit Data A8 1 0 0 0 Z 0 /DiXDD3~D4~DD6~D7XD8~Do~c~o>>~o~o~o~a~o~o~~ SERCLK SERENBLN 1 Figure 23. Serial Interface READ Frame Format Timing for the serial interface is shown in Figure 24. It is suggested that data be written to the TSWC03622 on the falling edge and also be read from the TSWC03622 on the falling edge . 1 1 1 SERDAT 1 i 1 1 1 1 1 1 1 tsoz ^ 1 1 1 1 1 1 I~ 1 1 1 1 11 1 1 1 1 1 I 1 tsm 1 1 1 1 1 1 1 1 1 1 1 1 1 r~l SERCLK 1 t501 tsoo 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 1 1 1 1 1 tsoa I I 1 1 I SERENBLN 1 1 1 1 1 Figure 24. Serial Interface Timing Table 29. Serial Interface Timing Symbol SERCLK SERENBLN SERCLK SERCLK SERDAT SERDAT SERCLK SERCLK SERDAT SERDAT SERCLK SERCLK SERCLK SERENBLN FMAX t500 Maximum Serial Interface Clock Frequency Enable to Clock Setup t501 WRITE Clock to Data Setup WRITE Data Hold READ Clock to Data Setup READ Data Hold Clock Period Enable Hold After Last Clock 40 Applicable Balls t502 t501 t502 t503 t504 Parameter Min Max Typ Unit - 25 - MHz ns -1 .0 ns 3.6 ns 18 ns ns 40 ns ns Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch TSWC03622 Registers Map Next table summarizes all the TSWC registers . Table 30. TSWC03622 Registers Address Hex TSWC03622 Block Description Bits 00 01 02-1 F 20 21 22 23 24 25 26 27 28 29 2A 213 2C 2D 2E 2F 30 31 32 33 34 35-3F 40 41 42 43 44 45 46 47 48 49 4A 413 4C 4D 4E Control Control Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Clock Input Sw. State Mach Sw. State Mach Sw. State Mach Sw. State Mach Sw. State Mach PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs I PDH Outputs Reset register. Serial interface or pin control . Not used. Software reset and software override . FINSEL[3 :0] . FBUSEL[3 :0] . Threshold . For test purposes, set to 0x0002 . For test purposes, set to 0x0002 . For test purposes, set to 0x0002 . For test purposes, set to 0x0002 . For test purposes, set to 0x0003 . For test purposes, set to 0x0001 . For test purposes, set to 0x0001 . For test purposes, set to 0x0001 . For test purposes, set to 0x0001 . For test purposes, set to 0x0001 . Hysteresis . Not used. Software reset and software override . Ensqln, lorstn, enlon, swcontn, revertn, autoswn, selbun, selclk LOCNT-Lock-out counter. TOCNT-Time-out counter. IFREO-Divide by 19440 counter. Not Used. Programmable output variable RO for channel 1 . Programmable output variable R1 for channel 1 . Programmable output variable R2 for channel 1 . Programmable output variable R3 for channel 1 . Programmable output variable R4 for channel 1 . Programmable output variable R5 for channel 1 . Programmable output variable R6 for channel 1 . Not used. Programmable output variable RO for channel 2 . Programmable output variable R1 for channel 2 . Programmable output variable R2 for channel 2 . Programmable output variable R3 for channel 2 . Programmable output variable R4 for channel 2 . Programmable output variable R5 for channel 2. I Programmable output variable R6 for channel 2 . I 15 :8 0 1 :0 3:0 3:0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 15 :0 8:0 7:0 15 :0 15 :0 15 :0 9:0 9:0 9:0 9:0 9:0 9:0 2:0 9:0 9:0 9:0 9:0 9:0 9:0 2:0 Agere Systems Inc. Reset OxFFFF OxFFFF OxFFFF Ox000F Ox000F 0x0002 0x0002 0x0002 0x0002 0x0002 0x0003 0x0001 0x0001 0x0001 0x0001 0x0001 0x0004 OxFFFF Ox00FF 0x0003 0x0800 Ox4BEF 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I 0x0000 41 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 TSWC03622 Registers Map (continued) Table 30. TSWC03622 Registers (continued) Address Hex TSWC03622 Block 4F 50 51 52 53 54 55 56 57 58 59 5A 513 5C 5D 5E 5F 60 61 62 63 64 65 66 67-7F 80 81 82 83 84 85 86-9F AO PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs PDH Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs A1 A2 A3 A4 42 Description Bits Reset 9 :0 9 :0 9 :0 9 :0 9 :0 9 :0 2 :0 9 :0 9 :0 9 :0 9 :0 9 :0 9 :0 2 :0 9 :0 9 :0 9 :0 9 :0 9 :0 9 :0 2 :0 15:12,0 9 :0 15 :0 15 :12 3:0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x0000 0x0000 0x0000 Ox000F SDHSEL register. 3 :0 0x0000 Duty cycle register. 0 0x0001 Sync offset and direction . 10 :0 0x0000 Sync enables . 11 :0 0x0000 Not used. Programmable output variable RO for channel Programmable output variable R1 for channel Programmable output variable R2 for channel Programmable output variable R3 for channel Programmable output variable R4 for channel Programmable output variable R5 for channel Programmable output variable R6 for channel Not used. Programmable output variable RO for channel Programmable output variable R1 for channel Programmable output variable R2 for channel Programmable output variable R3 for channel Programmable output variable R4 for channel Programmable output variable R5 for channel Programmable output variable R6 for channel Not used. Programmable output variable RO for channel Programmable output variable R1 for channel Programmable output variable R2 for channel Programmable output variable R3 for channel Programmable output variable R4 for channel Programmable output variable R5 for channel Programmable output variable R6 for channel Not used. Mode (PDHSEL) and power-down. DIV2, CKMXSEL, MODESEL, and DELAY. Modes for CO, C1, C2, and C3 . Modes for C4, C5, C6, and C7. Reserved. Reserved. Not used. Software reset and overrides . 3. 3. 3. 3. 3. 3. 3. 4. 4. 4. 4. 4. 4. 4. 5. 5. 5. 5. 5. 5. 5. Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch TSWC03622 Registers Map (continued) Table 30. TSWC03622 Registers (continued) Address Hex TSWC03622 Block A5 SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs SDH/SYNC Outputs Control A6 A7 A8 A9 AA-AF BO 131 132 133 134 135 136 137 138 139 BA BB BC-DF EO I Agere Systems Inc. Description Bits Reset Clock enables. 9 :0 0x0000 Individual duty cycle changes . 2 :0 0x0007 Clock edge selection . 3 :0 Ox000F Sync offset when software override . 15 :0 0x0000 Additional sync offset when software override . 1 :0 0x0000 Not used. RISE[15 :0] . 15 :0 Ox2FC0 0 0x0001 FALL . 15 :0 Ox97E0 DELTA. 3:0 0x0016 Not used. - 0x0016 Not used. - 0x0016 DELTARISE . 4:0 Ox000B Not Used. For test purposes, read only. 0 0x0000 0x0001 For test purposes, read only. 15 :0 Ox2FAA For test purposes, read only. 0 0x0000 For test purposes, read only. 15 :0 Ox97CA 8 :0 0x0060 RISE(16) . Not used. I Interrupt register. I I 43 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Control Block Registers Table 31 . Hardware Reset for all TSWC03622 Blocks Address (Hex) Bit Name 0x00 15 RHSLOLN 14 RLOSCLKN 13 RSWSTATN 12 RESETFFN 11 RLSPLLN 10 RSYNCN 9 RPDHCLKN 8 RCONFIGN 7:0 I - Description High-speed PLL powerdown . 1 = Block active . 0 = Block powered down . Loss-of-clock block powerdown . 1 = Block active . 0 = Block powered down . Switch state machine powerdown . 1 = Block active . 0 = Block powered down . Feed-forward counters powerdown . 1 = Block active . 0 = Block powered down . Low-speed PLL powerdown . 1 = Block active . 0 = Block powered down . SDH/Sync generation block powerdown . 1 = Block active . 0 = Block powered down . PDH block powerdown . 1 = Block active . 0 = Block powered down . Control block reset . 1 = Block active . 0 = Block reset for one 155.52 MHz clock cycle . I Unused : program to one . Reset Value 1 1 1 1 1 1 1 1 I 00000000 Register 00h contains power downs for all the TSWC blocks . Setting a bit to a low level in this register will power down the corresponding block . The block will remain powered down until the bit is again set to high, except for bit 00h(8), which resets the control block only for one 155 MHz clock cycle . This register is initialized to all zeros, and bits 00h[7 :0] are not used. The reset register can be written at any time to reset a specific block, although the software reset implemented in each block can also be used . After a general hardware reset, the control block will be setting the reset register bits to high level following a certain reset sequence . If a block is powered down and it is desired to power it up, a hardware reset is necessary. Table 32 . Software Override Address (Hex) Bit Name 0x01 15:1 0 OVERRIDE Description Unused : program to one . Software override bit . 1 = Software programming disabled (hardware mode) . 0 = Software programming enabled (software mode) . Reset 111111111111111 1 Register 01 h contains the software override bit, which must be set to low prior to any write operation . If bit 01 h(0) is high, the control block will not write any register except for 01 h itself . This register is initialized to all ones, although bits 01 h[15:1 ] are not used, so right after initialization no write process is allowed . Bit 01 h(0) must be set low . 44 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Input Clock Block Registers The loss of clock block monitors the input clocks CLKA, CLKB and CLKBU, and the 38.88 MHz clock generated by the external VCXO. Table 33. Loss of Clock Block Software Override and Reset Address (Hex) Bit Name 20 15 :2 1 0 SWOVRDN SWRSTN Description Unused : program to one . Reserved . Input clock block powerdown . 1 = Block active . 0 = Block powered down . Reset 11111111111111 1 1 Register 20h contains only 2 bits . Those bits are the software power down 20h(0) and the software override 20h(1) . Both are active-low level, so register 20h is initialized to all ones. if bit 20h(1) is low, the input clock block will be operating in software mode, enabling all the programming capabilities and allowing access to the full flexibility of the block . Table 34. FINSEL[3:0] Register Address (Hex) Bit Name 21 15 :4 3 :0 FINSEL[3:0] Description Unused : program to one . Clock A and clock B input frequency select . (Bit 3 is a don't care.) 1111, 0111 = 51 .84 MHz . 1110, 0110 = 38 .88 MHz . 1101, 0101 = 19.44 MHz . 1100, 0100 = 8 .192 MHz . 1011, 0011 = 6.480 MHz . 1010, 0010 = 2 .048 MHz . 1001, 0001 = 1 .544 MHz . 1000, 0000 = 8 kHz . Reset 111111111111 1111 Register 21 h is written by the control block, which monitors the external pin FINSEL for any change . The FINSEL register must indicate the input clocks frequency (FINSEL for CLKA and CLKB) . This register is initialized to all ones. It can be written at any time via serial interface (even in hardware mode), but only in hardware mode will any change in these registers reprogram the fractional dividers by rewriting registers 24h-2Dh . Agere Systems Inc. 45 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Input Clock Block Registers (continued) Table 35. FBUSEL[3:0] Register Address (Hex) Bit Name 22 15:4 3:0 FBUSEL[3:0] Description Unused : program to one . Backup clock input frequency select . (Bit 3 is a don't care.) 1111, 0111 = 51 .84 MHz . 1110, 0110 = 38 .88 MHz . 1101, 0101 = 19.44 MHz . 1100, 0100 = 8 .192 MHz . 1011, 0011 = 6.480 MHz . 1010, 0010 = 2.048 MHz . 1001, 0001 = 1 .544 MHz . 1000, 0000 = 8 kHz . Reset 111111111111 1111 Register 22h is written by the control block, which monitors the external pin FBUSEL for any change. The FBUSEL register must indicate the input clocks frequency (FBUSEL for CLKBU) . This register is initialized to all ones. It can be written at any time via serial interface (even in hardware mode), but only in hardware mode will any change in these registers reprogram the fractional dividers by rewriting registers 24h-2Dh . Table 36. Loss of Clock Threshold Address (Hex) Bit Name Description Reset 23 15:0 THRESHOLD Loss of clock threshold value (number of missing consecutive clock cycles needed to trigger loss of clock interrupt) . 0000000000000010 Register 23h is used to program the threshold time, that is, the number of absent input cycles needed to raise the loss of clock interrupt. This values is shared by all the loss of clock detectors . Register 23h can be written at any time (even in hardware mode). The minimum value for this register is a value of 2. If a lower value is written, the threshold will be set to a values of 2 . Table 37. Loss of Clock Hysteresis Address (Hex) Bit Name Description Reset 2E 15:0 HYSTERESIS Loss of clock hysteresis value (number of consecutive clock cycles needed to erase loss of clock interrupt, once clock is back) . 0000000000000100 Register 2Eh is used to program the hysteresis time, that is, the number of input clock cycles needed to erase the loss of clock flag once the clock is back. This values is shared by all the loss of clock detectors . Register 2Eh can be written at any time (even in hardware mode). The minimum value for this register is a value of 4. If a lower value is written, the hysteresis will be set to a values of 4. 46 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Switch State Machine Block Registers The address space for the clock protection switch control circuit is 30h-34h . Table 38. Switch Block Control Register Address (Hex) 30 Bit Name 15 :9 8 LOCBUN 7 LOCBN 6 LOCAN 5 BUSYBN 4 BUSYAN 3 TESTN 2 Reserved 1 SWOVRDN 0 SWRSTN Description Reset Unused : program to ones. 1111111 For test purposes, set to 1 . 1 For test purposes, set to 1 . 1 For test purposes, set to 1 . 1 For test purposes, set to 1 . 1 For test purposes, set to 1 . 1 For test purposes, set to 1 . 1 1 Software override bit . 1 1 = Hardware mode (registers 32, 33, and 34 use their default values) . 0 = Software mode (user can overwrite registers 32, 33, and 34) . Switch block software powerdown . 1 1 = Block active . 0 = Switch control circuits powered down except for microprocessor interface . Bits 30h[8 :3] are used for test purposes, and they must be high in normal operation mode, specially bit 30h(3), which is the test mode bit . Table 39. Switch Block State Machine Register Address (Hex) Bit Name 31 15 :8 7 ENSQLN 6 5 4 3 2 1 0 Description Unused . Squelch enable. 1 = Squelch disabled . 0 = Squelch enabled (squelch active conditions are listed in Table 40) . LORSTN Lockout reset . 1 = Counting switching events if 31 h(5) = 0. 0 = Reset. ENLON Enable lockout . 1 = Lockout disabled . 0 = Lockout enabled. SWCONTN Protection switch control circuit operation mode . REVERTN 111 = Protected manual mode (SELCLK/SELBUN selects clock . User AUTOSWN cannot switch to a bad clock) . 110 = Autonomous nonrevertive mode. 100 = Autonomous revertive mode. Oxx = Unprotected manual mode (SELCLK/SELBUN selects clock . User can switch to a bad clock .) SELBUN Input clock selection . SELCLK 11 : Clock A . 10 : Clock B. Ox : Backup clock . Conditions for use of this register : 01 h(0) = 0. Agere Systems Inc. Reset 00000000 1 1 1 1 1 1 1 1 47 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Switch State Machine Block Registers (continued) Register 31 h is initialized to all ones. Positions [15 :8] will always read as zeros . This register is updated by the TSWC control block based on the input pins state, although they can also be modified via serial interface . This register will therefore reflect the input pins with the same name given that the TSWC control block updates register 31 h via internal bus. The TSWC03622 will use the respective external balls for control when register 01 h bit 0 is high, and it will use the configuration from register 31 h when register 01 h bit 0 is low . All bits in register 31 h are active-low. Bit 31 h(5) is the lock-out enable ENLON, and bit 31 h(6) is the lock-out reset LORSTN . If ENLON is low, the lock out is enabled, so only a certain number of switches are allowed (only in autonomous mode), as indicated by register 32h . Once that limit has been reached, no more switches are allowed . The lock out only works in autonomous mode of operation, in protected or unprotected manual mode, unlimited number of clock switches are allowed no matter the value of ENLON is . In autonomous mode, if the number of switches reaches the limit and the device is locked out, the lock out count can be reset by setting bit LORSTN low, allowing new clock switches before the device is locked out again. If ENLON is high, the device will never be locked out, and unlimited number of clock switches in autonomous mode will be allowed . Bit 31 h(7) is the squelch enable ENSQLN . Setting this bit low, the SDH and PDH output clocks will be squelched if one of the next conditions are met . Table 40. Squelch Mode of Operation Conditions Needed to Squelch the Output Clocks when ENSQLN = 0 Autonomous (revertive or non- The output clocks will be squelched if the three input clocks CLKA, CLKB, and revertive) CLKBU are lost. (LOCA = 1 and LOCB = 1 and LOCBU = 1). Protected Manual Mode The output clocks will be squelched if one of the next three conditions are met : 1) Clock A is being used as reference but it is lost (LOCA = 1) . 2) Clock B is being used as reference but it is lost (LOCB = 1) . 3) Clock BU is being used as reference but it is lost (LOCBU = 1). Unprotected Manual Mode The output clocks will be squelched always if ENSQLN is low, no matter what the conditions of the input clocks are . As indicated in the previous table, when operating in external control mode, the squelch enable is used to squelch the output clocks, whereas for the other operation modes the squelch enable allows squelching when the special conditions are met . Table 41 . Lockout Threshold Address (Hex) Bit Name Description Reset 32 15:0 LOCNT Maximum number of clock switches allowed before the TSWC03622 enter lockout (autonomous mode only) . 0000000000000011 This register indicates the maximum number of clock switches that are allowed before the circuit is locked out (autonomous mode only) . In order to write this register, bit 30h(1) must be set low previously . Whenever bit 30h(1) is high, register 32h will take the default value, which is the same as initialization . That value is 0000000000000011 (three) . That means that in default mode, only three switches are allowed . At the third clock switch, the lock-out flag is risen and any extra clock switch will be prohibited . If bit 30h(1) is low, register 32h can be written with a value ranging from zero to 65535. 48 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Switch State Machine Block Registers (continued) In order to enable the lock out feature, the enable bit 31 h(5) must be set low (ENLON) and the reset bit 31 h(6) must be set high (LORSTN), although the device can only be locked out in autonomous mode (AUTOSWN = 0, SWCONTN = 1). Despite the lock out is only effective in autonomous mode, the lock-out counter keeps count of the number of clock switches in any mode of operation . This means that if the circuit is being used in manual mode and several switches have been made so that the limit has been reached, and the circuit is switched to autonomous mode, no clock switch will be allowed, as the circuit will be locked out . A software reset is suggested when switching the circuit to a different mode of operation . Setting the lock out reset low (LORSTN = 0) or bit 31 h(5) high (ENLON = 1) will disable the lock out feature . Table 42 . Switch Timeout Settings Address (Hex) Bit Name Description Reset 33 15 :0 TOCNT 0000011111111111 34 15 :0 IFREQ Time-out counter : indicates the number of internal clock cycles of the time out period . Programs the period of an internal clock which is used to measure the time elapsed since the last clock switch. 0100101111110000 These registers are used to program the time-out feature used to avoid any clock switch before a certain time after the last clock switch, unless a fault in the current reference requires a clock switch . The time out period is needed by the LSPLL to lock to the new reference clock after a clock switch, and is active in manual and automatic mode. In order to write registers 33h and 34h, bit 30h(1) must be low . Whenever bit 30h(1) is high, registers 33h and 34h will be loaded with the default value, which is the same as at initialization, that is, 2047 for 33h and 19440 for 34h . Register 34h (IFREQ[15 :0] programs the period of an internal clock which is used to measure the time elapsed since the last clock switch . That clock will be obtained by dividing the 155.52 MHz clock by the number indicated in register 34h . The default value of register 34h is 19439, which gives an internal clock frequency of 8 kHz (155 .52MHz/19440 = 8 kHz) . Register 33h indicates the number of internal clock cycles of the time-out period . After a clock switch, an internal counter will be initialized with the value indicated by register 33h, and will start to down-count each internal clock edge (whose frequency can be programmed by register 34h) . The time-out period will be expired when that counter reaches zero. The default value of this register is 2048 . The phase of the internal clock used to measure the time-out period is independent on when the clock switch occurs, so the actual time-out period is between the number indicated by register 33h and the number indicated by register 33h plus one . Calling R33 the number indicated by register 33h and R34 the number indicated by register 34h, the time out period ti will take the next value (in seconds) : R34/155520000 x (833-1) < ti < R34/155520000 x R33 For the default value, the time out period will be limited by : 255 .75 ms < ti < 255 .875 ms In order to reduce the possible range for the time-out period, it is suggested to increase R33 as much as possible keeping the product of R33 and R34 constant (that means a high frequency for the internal clock) . For example, the next range would be obtained for R33 = 32752 and R4 = 1215, the time-out period would be in the range from 255 .867 ms to 255 .875 ms. It is also suggested to software reset the circuit before registers 33h and 34h are written . Agere Systems Inc. 49 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 PDH Output Block Registers Fractional Dividers Registers : 40h-66h The PDH fractional dividers enable each of the five PDH CIVIOS output clocks to be fully programmable . Registers 40h-66h contain the parameters to set the respective frequencies . Setting the frequencies is enable in registers 80h-83h . Each fractional divider includes seven registers . Those registers are located at consecutive addresses . The address of each register can be specified by the base address of the corresponding fractional divider and the relative offset. Base address Fractional Fractional Fractional Fractional Fractional Divider Divider Divider Divider Divider 1 2 3 4 5 40h 48h 50h 58h 60h To calculate the values for the respective dividers, a software program is available to automate the process . Please contact your Agere System representative to get a copy of the program . All registers are initialized to all zero at reset . General Configuration Registers : 80h-83h Registers 80h-83h are the general configuration registers that control the operation mode of the PDH block. The first two registers 80h and 81 h, control the general behavior of the PDH block, whereas registers 82h and 83h control the five fractional dividers used to generate the PDH rates . Table 43. PDH Control Register 1 Address (Hex) Bit Name 80 15:12 PDHSEL 11 :1 0 Description Reset Software PDH output clock select . See Table 44. for preset configu0000 rations . To use this register, 81 h(4 :3) must be set to 10. Reserved. 00000000000 SWRSTN PDH block software power-down . 1 1 = Block active . 0 = PDH output block powered down except for microprocessor interface . Register 80h contains the software reset bit 80h(0) and the four PDHSEL[3 :0] bits, used to select one of the sixteen preset configurations when 81 h[4 :3] = 10 (basic software control), generating the most needed PDH rates . Bit 80h(0) is the software reset, used to power down the PDH block except for the microprocessor used to read and write registers . The microprocessor can only be reset by hardware reset . Register 80h is initialized with all bits low except for 80h(0), which is high. Bits [10 :1] can written and read as they were written, but they are not used by the PDH block . 50 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch PDH Output Block Registers (continued) Table 44. PDH Clock Outputs for the 16 Preset Configurations (Bit 81 h(3) = 0) PDHSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Clock 1 I Clock 2 Clock 3 Clock 4 Clock s Disabled 44 .736 MHz Disabled 34 .368 MHz Disabled Disabled 32 .768 MHz Disabled 24 .704 MHz Disabled Disabled 16 .384 MHz Disabled Disabled 8 .192 MHz Disabled Disabled 4.096 MHz Disabled Disabled 2 .43 MHz Disabled 2 .048 MHz Disabled Disabled 1 .544 MHz Disabled Disabled 2 .048 MHz 1 .544 MHz Disabled 44 .736 MHz 32 .768 MHz 24 .704 MHz 2 .048 MHz 1 .544 MHz 34 .368 MHz 32 .768 MHz 24 .704 MHz 2 .048 MHz 1 .544 MHz Disabled 44 .736 MHz I 32 .768 MHz I 2 .048 MHz I 1 .544 MHz I 2 .43 MHz Table 45. PDH Control Register 2 Address (Hex) Bit Name 81 15 :10 9 :8 7 :5 4 :3 DIV2N CKMXSEL MODESEL 2 :0 I Agere Systems Inc. DELAY Description Reset Reserved. 000000 For test purposes only. Program to 00. 00 For test purposes only. Program to 000 . 000 00-Hardware Control. This mode allows to control the PDH block 0 through the external PDHSEL[3 :0] pins in case the TSWC control block fails. These pins reach the PDH block, so the PDH block behavior is independent of the TSWC control block. This mode offers sixteen presets which generate the most needed PDH frequencies . Every one of those configurations programs each fractional divider to work in one of the sixteen modes listed in Table 47 . 10-Basic Software Control . This mode is intended to be used in conjunction with the TSWC control block. The PDH block operates in the same way as in hardware control offering the same sixteen presets, but this time instead of reading the external pins directly, the four PDHSEL[3 :0] bits are read from register 80h (four most significant bits) . This register is written by the control block at initialization or when any change is made on the external pins, as the control block monitors the external pins in a continuous basis. Register 80h can also be written via serial interface (software override) . X11-Enhanced Software Control. This mode can only be used by programming the PDH block via serial interface . This third alternative allows individual selection of the operating mode for each fractional divider. Registers 82h and 83h contain the 20 bits needed to specify the operating mode for each of the five fractional dividers (four bits per fractional divider) . I For test purpose only. Program to 00. I 00 51 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 PDH Output Block Registers (continued) Table 46. Enhanced Software Mode Fractional Divider Selection Address (Hex) 82 Bit Name Description 15 :12 FD 1 Mode PDH1 fractional program value. 11 :8 FD 2 Mode PDH2 fractional program value. 7:4 FD 3 Mode PDH3 fractional program value. 3 :0 FD 4 Mode PDH4 fractional program value. 15 :12 FD 5 Mode PDH5 fractional program value. 11 :0 I I Reserved . 83 Reset divider mode, see text below and Table 47 to 0000 divider mode, see text below and Table 47 to 0000 divider mode, see text below and Table 47 to 0000 divider mode, see text below and Table 47 to 0000 divider mode, see text below and Table 47 to 0000 I 0000 OOOOOO Registers 82h and 83h indicate the operation mode of each fractional divider when bit 81 h(3) is high . There are four bits for each fractional divider. These registers are reset to all zeros. Each fractional divider can be operated in sixteen different modes . These modes are described in Table 47. Table 47. Software Mode Fractional Divider Selection Mode Mode Bits [3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 I Divides By 13+211/233 18+18/179 18+63/64 25+35/193 37+31/32 75+15/16 100 + 140/193 64 151 +7/8 303+3/4 256 402 + 174/193 32 Reserved Programmable I Power down In mode 14, the fractional divider can be programmed through the registers located inside the fractional divider (see See "Fractional Dividers Registers : 40h-66h" on page 50) . Fractional dividers one through three use the 622 .08 MHz clock as input, whereas fractional dividers four and five use the 155 .52 MHz clock. Based on the previous table, the input frequency to each fractional divider, and the division factor indicated in Table 48, the sixteen presets will generate the output clocks (each clock is generated by the fractional divider with the same number) shown in Table 44. 52 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch PDH Output Block Registers (continued) Next table summarizes the operation mode for the five fractional dividers when bit 80h(3) is low . In that case, the PDH block offers sixteen preset configurations that can be selected by the external pins (when 81 h(4) = 0) or writing register 80h (when 81 h(4) = 1). Table 48. Fractional Dividers Operation Mode as a Function of the External Pins PDHSEL[3 :0] or Bits 80h[15 :12] (bit 81 h(3) must be low) PDHSEL[3 :0] or bits 80h[15 :12] FD 1 FD 2 FD 3 FD 4 FD 5 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 0 1 15 3 15 15 15 15 15 15 15 0 1 15 0 15 15 15 2 15 4 5 15 15 15 15 15 2 2 15 2 15 15 15 15 15 15 15 8 15 9 15 9 3 3 15 9 15 15 15 15 15 15 15 15 15 15 6 6 5 5 15 6 15 15 15 15 15 15 15 15 7 15 15 15 6 6 15 7 Agere Systems Inc. I I I I I 53 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 SDH/Sync Generation Block Registers Table 49. SDH/Sync Control Register Address (Hex) AO Bit Name Description Reset 15 :4 Reserved 3 SYNC OFFSET OVERRIDE Sync offset override. 1 = Sync offset read from external pins (stored in A3h). 0 = Sync offset read from registers A8h and A9h (which has a wider range than external pins, covering a complete 8 kHz cycle) . 2 DUTY CYCLE OVERRIDE Conditions for use of this feature : SDH HW pin low. Duty cycle override. 1 = Duty cycle read from external pins (stored in A2h). 0 = Duty cycle read from A6h (which allows for different duty cycles for the three kinds of output 000000000000 1 1 syncs) . 1 0 SDHSEL OVERRIDE SRESETN Conditions for use of this feature : SDH HW pin low. SDHSEL override. 1 = Output clocks enables taken from SDHSEL, read from external pins (stored in A1 h). 0 = Output clocks enables taken from register A5h . Conditions for use of this feature : SDH HW pin low. SDH/Sync block software power-down 1 = Active. 0 = Powered Down except for microprocessor interface . 1 1 Conditions for use of this feature : SDH HW pin low. Bit 0 is the software reset used to reset the SDH/Sync block. Bits 1, 2, and 3 are overrides (active-low level) . When the SDH_HW pin is high, the values used as SDHSEL, DUTY, and SYNCOFFSET are read from the external pins. When that pin is low, those values will be set via serial interface . If bits 1, 2, and 3 are high, the values will be read from the same registers as if the TSWC was in pin-control, that is, SDHSEL is stored in register A1 h, DUTY is in register A2h, and SYNCOFFSET is in register A3h . When bit A0h(1) is low (SDH HW = 0), the enables for the output clocks will be taken from register A5, which is a bit-to-enable register. If bit AOh(2) is low (SDH_HW = 0), the duty cycle is specified by register A6h, which allows different duty cycles for the three kinds of output syncs. Setting bit AOh(3) to a low level and SDH HW = 0, allows the user to specify the offset in the output sync with registers A8h and A9h . Those registers give a wider range to position the output sync than the external pins or register A3h . By using these registers, the user may be able to place the output sync in any position of the 8 kHz cycle . 54 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch SDH/Sync Generation Block Registers (continued) Table 50. SDHSEL Register Address (Hex) Bit Name Description Reset A1 15 :4 3 :0 SDHSEL Reserved SDH clock and sync selection . See SDH output clock selection (SDHSEL[3 :0]) in data sheet . 000000000000 0000 Conditions for use of this feature : A0h(1) = 1 and SDH HW pin low . This is the SDHSEL[3:0] register used to select one of the sixteen presets when the SDH HW pin is low and bit A0h(1) is high (basic software enables configuration) . Each of the sixteen presets controls the clock and sync enables as the SDHSEL[3 :0] external pins do when the SDH HW pin is high . This register is initialized at 0000, selecting the preset number zero, which disables all clock and sync outputs . Table 51 . Sync Duty Cycle Address (Hex) Bit Name A2 15 :1 0 Duty Cycle Description Reserved. Sync duty cycle . 1 = 50% . 0 = Pulse width per Table 52. Reset 000000000000000 1 Conditions for use of this feature : AOh(2) = 1 and SDH HW pin low. Register A2h is the duty cycle register, where bit A2h(0) is the duty cycle bit . That bit is used to select the duty cycle of the output syncs only when the SDH HW pin is low and the duty cycle override bit AOh(2) is high (basic software duty cycle configuration) . It works as the external pin SYDU when pin SDH HW is high . If the duty cycle bit is high, the duty cycle of all output syncs will be 50%, although it can be programmed to take a different value through the algorithm control registers B0h, 131 h, and B2h . If the duty cycle bit is zero, each output sync will have the default pulse width, depending on the selected sync for each output. Table 52 . Output Sync Duty Cycle Sync Output PECLO/PECL1 LVDSO/LVDS1 CMOs Pulse Width One cycle of the 155 MHz or 622 MHz clock. I One cycle of the 77.76 MHz, 51 .84 MHz, 38 .88 MHz or 19 .44 MHz . The duty cycle bit is initialized to one, so the output syncs will have 50% duty cycle . Agere Systems Inc. 55 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 SDH/Sync Generation Block Registers (continued) Table 53. Sync Offset Address (Hex) Bit A3 15 :11 10 9 :0 Name Description Reset Reserved . SYOFFPOS Positive of negative offset bit . 1 = Positive . 0 = Negative . SYOFF 00000 0 Conditions for use of this feature : AOh(3)=1 and SDH HW pin low. Sync offset. Value of this offset indicates number of 1/622 .08 (-1 .6) ns increments . 0 Conditions for use of this feature : AOh(3) = 1 and SDH HW pin low . This is the sync offset and direction register used in the same way as the external pins SYOFF[9 :0] and SYOFFPOS . This register will be used only when the SDH_HW pin is low and bit AOh(3) is high (basic software offset configuration) . Bits A3h[9 :0] are the sync offset, and bit A3h(10) is the direction . In order to get a positive delay, that is, to delay the output sync with respect to the negative edge of the input sync, bit A3h(10) must be high. Register A3h is reset to all zero . 56 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch SDH/Sync Generation Block Registers (continued) Table 54. Sync Source Address (Hex) Bit Name A4 15 :12 11" SYPCL6221 8 SYPCL1550 10 9 SYPCL6220 SYPCL1551 Description Reserved . LVPECL sync enable . These registers [11 :8] control the enables and sources of the LVPECL syncs. Bits 10 and 8 control SYLVSP/N[0], and bits 11 and 9 control SYLVSP/N [ 1 ] as fo ll ows: SYPCLP/N [0] XOXO = Disabled . XOX1 = Enabled, pulse width based on SYNC155, as defined in A6h(1) . X1 XO = Enabled, pulse width based on SYNC622, as defined in A6h(0) . X1 X1 =Disabled. Reset 0000 0 0 0 0 SYPCLP/N [0] OXOX = Disabled . 0X1 X = Enabled, pulse width based on SYNC155, as defined in A6h(1) . 1 XOX = Enabled, pulse width based on SYNC622, as defined in A6h(0) . 1 X1 X = SYPCLP/N[1 ] disabled . 7 6 5 4 SYNC8K78 SYNC8K51 SYNC8K38 SYNC8K1 9 Conditions for use of this feature: AOh(2) = 0 and A0h(1) = 0. CMOS sync enable . These registers [7 :4] control the enable and source of the CMOS sync . The pulse width is based on A6h(2) . If A6h(2) is high, the pulse width is 50% . If A6h ( 2 ) i s l ow, t h e pu l se wid t h i s b ase d on t h e con fi gurat i on b e l ow. (If two or more of these bits are high, the output CMOS sync will correspond to the 77 .76 MHz clock width .) 0001 = One cycle of 0010 = One cycle of 0100 = One cycle of 1000 = One cycle of Other = Disabled 3 2 1 0 SYLVS6221 SYLVS6220 SYLVS1551 SYLVS1550 the 19 .44 the 38 .88 the 51 .84 the 77 .76 MHz MHz MHz MHz 0 0 0 0 clock. clock. clock. clock. Conditions for use of this feature: AOh(2) = 0 and A0h(1) = 0 LVDS sync enable . These registers [3 :0] control the enables and sources of the LVDS syncs. Bits 2 and 0 control SYLVSP/N[0], and bits 3 and 1 control SYLVSP/N[1] as fo ll ows: 0 0 0 0 SYLVSP/N[0] XOXO = Disabled . XOX1 = Enabled, pulse width based on SYNC155, as defined in A6h(1) . X1 XO = Enabled, pulse width based on SYNC622, as defined in A6h(0) . X1 X1 =Disabled. SYLVSP/N[1 ] OXOX = Disabled . 0X1 X = Enabled, pulse width based on SYNC155, as defined in A6h(1) . 1 XOX = Enabled. pulse width based on SYNC622, as defined in A6h(0) . 1 X1 X = Disabled . Conditions for use of this feature: AOh(2) = 0 and A0h(1) = 0 . * In Version 1 .0 and 1 .1 of the TSWC03622, there is an errata with bit 11 of register A4h . This register can be written, but does not respond correctly to a read . When this bit is read, it will return a 0, regardless of the true value in the register. This register is used with register A5h for enhanced software enables configuration ; that means that it will only be used when the SDH_HW pin is low and bit A0h(1) is low (override enables) . It controls the output sync enables, so it selects the output sync pulse width when the duty cycle bit is low (not 50%) . This register is initialized to zero . Agere Systems Inc. 57 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 SDH/Sync Generation Block Registers (continued) Table 55. SONET/SDH Clock Enable Address (Hex) Bit Name A5 15 :10 9 PECL622 8 PECL1551 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 155 .52 MHz PECL differential output (PECL1551) . 1 = Enabled, 0 = Disabled. 0 7 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. PECL1550 Enable for the 155 .52 MHz PECL differential output (PECL1550) . 1 = Enabled, 0 = Disabled. 0 CK78 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 77.76 MHz single-ended CMOS output . 1 = Enabled, 0 = Disabled. 0 5 CK51 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 51 .84 MHz single-ended CMOS output . 1 = Enabled, 0 = Disabled. 0 4 CK38 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 38.88 MHz single-ended CMOS output . 1 = Enabled, 0 = Disabled. 0 3 CK19 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 19.44 MHz single-ended CMOS output . 1 = Enabled, 0 = Disabled. 0 2 LVDS622 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 622 .08 MHz LVDS differential output (LVDS622) . 1 = Enabled, 0 = Disabled. 0 1 LVDS1551 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. Enable for the 155 .52 MHz LVDS differential output (LVDS1551) . 1 = Enabled, 0 = Disabled. 0 0 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. LVDS1550 Enable for the 155 .52 MHz LVDS differential output (LVDS1550) . 1 = Enabled, 0 = Disabled. 0 6 Description Reset Reserved. Enable for the 622 .08 MHz PECL differential output (PECL622) . 1 = Enabled, 0 = Disabled. 000000 0 Conditions for use of this feature : AOh(1) = 0 and SDH HW pin low. This register controls the individual SDH clock enables when the SDH HW pin is low and bit AOh(1) = 0 (enhanced software enables configuration) . A low zero means that the corresponding output clock will be disabled . Recall that regarding the 155 .52 MHz and 622 .08 MHz clocks, only the enable signals are generated by the SDH block. The clocks are generated by other circuits external to the SDH block. Register A5h is initialized to zero (all clocks disabled) . 58 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch SDH/Sync Generation Block Registers (continued) Table 56. Sync Duty Cycle Address (Hex) Bit Name A6 15:3 2 DUTY CYCLE SYNCCMOS Description Reserved . Set Duty Cycle for the CMOS sync. 1 = 50% . 0 = Pulse width as set by A4h(7 :4) . Reset 0000000000000 1 1 Conditions for use of this feature : AOh(2) = 0 and SDH_HW pin low DUTY CYCLE SYNC155 Set Duty Cycle for the SYNC155 . 1 = 50% 0 = One 155 .52 MHz clock cycle 1 0 Conditions for use of this feature : AOh(2) = 0 and SDH_HW pin low. DUTY CYCLE SYNC622 Set Duty Cycle for the SYNC622 . 1 = 50% . 0 = One 622 .08 MHz clock cycle . 1 Conditions for use of this feature : AOh(2) = 0 and SDH_HW pin low. This register is used to control the individual syncs duty cycle when the SDH HW pin is low and bit AOh(2) = 0 (enhanced software duty cycle configuration) . Only the three least significant bits are used, as there are only three types of output syncs (SYC155, SYNC622, and CMOS) . A high duty cycle bit selects the duty cycle of the corresponding sync to be 50% . If the bit is low, the sync pulse width will be equal to one 622 .08 MHz clock cycle for SYNC622 and one 155.52 MHz clock cycle for SYNC155 ; and for the CMOS sync, the pulse width can be programmed to be one clock cycle of the 77.76 MHz, 51 .84 MHz, 38 .88 MHz, or 19.44 MHz clock. Register A6 is initialized to 111, that is, all 50% duty cycle . Agere Systems Inc. 59 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 SDH/Sync Generation Block Registers (continued) Table 57. CMOS SONET Clock Edge Selection Address (Hex) Bit Name Description A7 15 :4 3 CK78 2 CK51 Conditions for use of this feature : AOh(2) = 0 and AOh(1) = 0. Edge Selection for the 51 .84 MHz Clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync . 1 1 CK38 Conditions for use of this feature : AOh(2) = 0 and AOh(1) = 0. Edge Selection for the 38 .88 MHz Clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync . 1 0 CK19 Conditions for use of this feature : AOh(2) = 0 and AOh(1) = 0. Edge Selection for the 19 .44 MHz Clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync . 1 Reserved . Edge Selection for the 77.76 MHz clock. 1 = Rising edge of corresponding clock aligned to input sync. 0 = Falling edge of corresponding clock aligned to input sync . Reset 000000000000 1 Conditions for use of this feature : AOh(2) = 0 and AOh(1) = 0. This is the edge selection for the four SDH clocks generated by the SDH block. A high bit means that the corresponding clock's rising edge will be synchronized to the negative edge of the input sync (actually it will lead the sync by 1-2 cycles of a 622 MHz clock) . If the edge selection bit is low, the falling edge of the corresponding clock will be aligned to the input sync. This register is set to 1111 at reset, aligning the rising edges of the clocks to the input sync . 60 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch SDH/Sync Generation Block Registers (continued) Table 58. Enhanced Sync Offset Address (Hex) Bit Name A8 A9 15 :0 15 :2 1 0 SSYNCOFFSET SYOFFPOS SSYNCOFFSET(16) Description Enhanced sync offset. Bits A9h(0) (IVISB) and A8h(15 :0) contain the sync offset value, calculated in increments of 1/622 .08 (-1 .6) ns. To be used with A9h[1 :0] SSYOFFPOS . Reset 0000000000000000 00000000000000 0 0 Bit A9h(1) : Denotes whether enhanced offset is positive or negative : 1 = Positive. 0 = Negative. Bits A9h(15 :2) : Reserved . Conditions for use of this feature : AOh(3) = 0 and SDH HW pin low . These registers are used to increase the possible offset between the input and output syncs. They will be used in enhanced software offset configuration (pin SDH HW = 0 and bit AOh(3) = 0), giving 17 bits for the absolute value of the offset as opposed to the 10 bits available in hardware and basic software offset configuration . Those 17 bits are the 16 bits of register A8h and bit A9h(0), which is the most significant bit of the offset. Bit A9h(1) is the direction of the offset (1 means that the output sync will be delayed from the input sync) . These registers are initialized to zero . In order to write registers A8h and A9h, first A8h must be written . However, register A8h will not be actually written until register A9h is also written . Table 59. Sync Rising Edge Position Address (Hex) Bit Name BO 131 15 :0 15 :1 RISE - 0 Description Sync rising edge position . Bits 131 h(0) (IVISB) and B0h(15 :0) contain the sync rising edge position, calculated in increments of 1/622 .08 (-1 .6) ns. RISE(16) Bits 131 h(15:1) : Reserved. Reset Ox2FC0 0000000000000 00 1 Register BOh-B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: 1 . The SDH HW pin is high and the user change the SYOFF or SYOFFPOS pins . 2. SDH HW is low, AO(3) is high and the user writes to register A3 . 3. SDH HW is low, AO(3) is low and the user changes A8h or A9h . These registers contain the value RISE used by the algorithm to calculate the position of the rising edge of the output sync. These two registers together offer 17 bits to define the value of RISE. Bit 131 h(0) is the most significant bit . At initialization, these registers have the value 131 h(0)&Bh0 = 1001011111100000 = 77,760. These registers are also used in conjunction with register B6h to generate the parameter tcnt, used by the highspeed sync generation block . It is not recommended that rise position of the sync outputs be adjusted in this fashion, since the frequency of the sync outputs may be affected . It is recommended instead to use the offset functionality in registers A8h and A9h to control the rise of the sync outputs and then use register B2h to control the fall position. Agere Systems Inc. 61 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 SDH/Sync Generation Block Registers (continued) Table 60. Sync Falling Edge Position Address (Hex) Bit Name 132 15 :0 FALL Description Reset Sync falling edge position. Contains the sync falling edge position, calculated in increments of 1/622 .08 (-1 .6) ns. Ox97E0 Register B0h-B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur : 1) The SDH HW pin is high and the user change the SYOFF or SYOFFPOS pins . 2) SDH_HW is low, AO(3) is high and the user writes to register A3. 3) SDH HW is low, AO(3) is low and the user changes A8h or A9h . Register B2h is used to store the value of the parameter FALL used by the sync generation algorithm . This register can be modified to obtain any desired duty cycle on the output syncs. It is initialized at 1001011111100000 = 38,880. Given that value, with the initial value of registers B0h and 131 h, the output syncs will have 50% duty cycle when the corresponding duty cycle bit is high. Table 61 . Sync Delta Address (Hex) Bit Name Description Reset 133 15 :5 4:0 Reserved . 00000000000 DELTA Compensation for the delay between the negative edge of the input 10110 sync and the positive edge of the output sync when the regular offset is zero. Value of this offset indicates number of 1/622 .08 (-1 .6) ns increments . Register B0h-B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: 1 . The SDH HW pin is high and the user change the SYOFF or SYOFFPOS pins . 2. SDH HW is low, AO(3) is high and the user writes to register A3. 3. SDHHW is low, AO(3) is low and the user changes A8h or A9h . This register gives an extra offset to compensate the delay due to the circuits . This offset is always negative, as opposed to the regular offset defined by registers A3h or A8h/A9h, which can be positive or negative (positive offset increases the delay of the output sync in relation to the negative edge of the input sync) . This register is initialized to 10110 = 22. That value compensates the delay between the negative edge of the input sync and the positive edge of the output sync when the regular offset is zero . Without this extra offset, the output sync would be delayed 22 622 MHz clock cycles. Register B3h is therefore parameter DELTA used by the sync generation algorithm . 62 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch SDH/Sync Generation Block Registers (continued) Table 62 . Sync Delta Rise Address (Hex) 136 Bit Name Description 15 :5 Reserved . 4 :0 DELTARISE The 5 bits of register B6h are used in conjunction with registers B0h/B1 h to calculate the value of the parameter tcnt used by the sync generation algorithm (tcnt = RISE-136h) . The value of B6h will be subtracted form the value of registers B0h/B1 h to calculate tcnt. Reset 00000000000 01011 Register B0h-B6h will only be recalculated (and affect the sync outputs) by the internal state machine after one of the following actions occur: 1 . The SDH HW pin is high and the user change the SYOFF or SYOFFPOS pins 2. SDH HW is low, AO(3) is high and the user writes to register A3. 3. SDHHW is low, AO(3) is low and the user changes A8h or A9h . The 5 bits of register B6h are used in conjunction with registers B0h/B1 h to calculate the value of the parameter tcnt used by the sync generation algorithm (tcnt = RISE-136h) . The value of B6h will be subtracted from the value of registers B0h/B1 h to calculate tcnt. The initial value at reset is 01011 = 11 . As it can be seen in the previous algorithm description, this value is needed to generate the proper value for tcnt. It is not recommended that rise position of the sync outputs be adjusted in this fashion, since the frequency of the sync outputs may be affected . It is recommended instead to use the offset functionality in registers A8h and A9h to control the rise of the sync outputs and then use register B2h to control the fall position. Agere Systems Inc. 63 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 SDH/Sync Generation Block Registers (continued) Table 63. Interrupt Status Register Address (Hex) Bit Name EO 15:10 9 SQUELCH 8 LOCKOUT 7 CKCONTRA 6 HSLOL 5 LSLOL 4 CLKSW 3 LOCLS 2 LOCBU 1 LOCB 0 LOCA Description Reset Reserved . The output clocks have been squelched due to a problem. 1 = Squelch inactive . 0 = Squelch active . The TSWC will not allow any more clock switches . 1 = Lockout condition exist. 0 = Lockout condition does not exists . The TSWC is not working with the clock selected by the user. 1 = The TSWC is not working with the clock selected by the user. 0 = The TSWC is working with the clock selected by the user. Loss of lock-high-speed PLL . 1 = Loss of lock. 0 = I n lock. Loss of lock-low-speed PLL . 1 = Loss of lock. 0 = In lock. Clock switch in progress . 1 = Clock switch in progress . 0 = No clock switch in progress. Loss of external 38 .88 MHz VCXO clock . 1 = Loss of clock. 0 = No loss of clock. Loss of backup clock. 1 = Loss of clock. 0 = No loss of clock. Loss o -clock B. 1 = Loss of clock. 0 = No loss of clock. Loss of clock A. 1 = Loss of clock. 0 = No loss of clock. 111111 1 1 1 1 1 1 1 1 1 1 The interrupt register EOh is a read-only and clear-on-read register that reflects the status of the TSWC interrupts. Whenever there is an interrupt, the corresponding bit will be set high and will remain high until the register is read, even if the event that generated the interrupt is over. However, the interrupt external pins reflect the interrupts only while they are active, so the corresponding pin goes low as soon as the event has finished. 64 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device . These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this device specification . Exposure to absolute maximum ratings for extended periods can adversely affect device reliability . Table 64. Absolute Maximum Ratings Parameter Min Max Unit Power Supply Voltage (VDD) -0.50 TBD V Storage Temperature -40 125 Ball Voltage I GND - 0 .5 I VDD + 0 .5 I C V Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations . Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-Cl 01 (CDM) standards . Table 65. Handling Precautions Minimum HBM Threshold Device TSWC03622 I 500 V Minimum CDM Threshold I 200 V Operating Conditions Table 66. Recommended Operation Conditions Parameter Power Supply (dc voltage) Temperature : Ambient Power Dissipation Agere Systems Inc. Symbol Min Typ Max Unit VDD 3 .135 3.3 3 .465 V PD -40 - 25 1 .0 85 TBD C W 65 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Electrical Characteristics LVPECL, LVDS, CMOS, Input and Output Balls Note: For Tables 67 through 71, VDD = 3 .3 V 5%, TAMBIENT = -40 C to +85 C . Table 67. LVDS Output do Characteristics Applicable Balls CK622P/N, CK155P/N[1 :0], SYLVSP/N[1 :0] Parameter Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage Output Offset Voltage Differential Output Impedance Ro Mismatch Between AandB Change in ~VODj Between Logic 0 and Logic 1 Change in IVosl Between Logic 0 and Logic 1 Output Current Output Current Power-off Output Leakage Symbol Conditions Min Typ Max Unit VOH RLOAD = 100 SZ 1 % - - 1475 mV VOL RLOAD = 100 SZ 1 % 925 - - mV ~VODj Vos Ro RLOAD = 100 SZ 1% 250 1125 80 100 400 1275 120 mV mV W - - 20 ARo RLOAD = 100 52, 1 % Vcm = 1 .0 V and 1 .4 V Vcm = 1 .0 V and 1 .4V JAVODJ RLOAD = 100 5l 1% - - 25 mV JAVOSI RLOAD = 100 SZ 1% - - 25 mV ISA, ISB Driver shorted to GND Drivers shorted together - - - 24 mA - - 12 mA - - = pA ISAB IIXAI,IIXBI * This leakage parameter is not specified due to EDS clamp diode conducting current during forward bias test. 66 Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Electrical Characteristics (continued) Table 68. LVDS Input do Characteristics Applicable Balls Parameter Symbol Conditions Min Typ Max Unit CLKAP/N, CLKBP/N Input Common-mode Voltage Range Input Peak Differential Voltage Input Differential Threshold Differential Input Impedance* VcM AVg(VIA,VIB) 0 1200 2400 mV VDIFF VIA-VIBE 100 - 800 mV VIDTH RIN VIA-VIB Measure at do -100 80 100 100 120 mV ti * Looser than ICORE/IEEE(R) spec of 10 52,. Table 69. CMOS Input do Characteristics Applicable Balls LSVCO CLKA,CLK13, CLKBU, SDHSEL[3 :0] SYOFF [9 : 0 ], PDHSEL[3 :0] SELLVDS, FINSEL[3 :0], FBUSEL[3:0], INLOSN, SYOFFPOS, SYDU, SELCLK, SELBUN, AUTOSWN, REVERTN, SWCONTN, ENSQLN, RESETN, ENLON, LORSTN, LFOZ Agere Systems Inc. Parameter Symbol Conditions Min Max Unit - VDD -1 .0 VDD 1 .0 10 VDD 1 .0 225 - V V pA pA V V pA pA VDD 1 .0 10 - V V pA pA Input Input Input Input Input Input Input Input Voltage Voltage Current Current Voltage Voltage Current Current High Low High Leakage Low Leakage High Low High Leakage Low Leakage VIH VIL IN IIL VIH VIL IN IIL Input Input Input Input Voltage Voltage Current Current High Low High Leakage Low Leakage VIH VIL IN IIL - VIN = VDD VIN = GND - - GND -10 VDD -1 .0 VIN = VDD VIN = GND GND -10 - VDD -1 .0 - VIN = VDD VIN = GND GND -225 67 AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch Preliminary Data Sheet May 2002 Electrical Characteristics (continued) Table 70. CMOS Output do Characteristics Applicable Balls CK77, CK51, CK38, CK19, SYNC8K, CKPDH5, CKPDH4, CKPDH3, CKPDH2, CKPDH1, SWSTATE[1 :0], INT[8 :0], TSTMODE Parameter Symbol Conditions Min Max Unit VOH VOL CL IOH = -4.0 mA IOL= 4.0 mA - VDD - 0.5 GND - VDD 0.5 15 V V pF Typ Max Unit Output Voltage High Output Voltage Low Output Load Capacitance Table 71 . LVPECL Output do Characteristics Applicable Balls Parameter PCK622P/N, Output Voltage High PCK155P/N[1 :0], Output Voltage Low SYPCLP/N[1 :0] Symbol Conditions VOH VOL Load = 50 52, connected to VDD - 2 .0 V Min VDD -1 .21 VDD-1 .11 VDD -1 .06 VDD -1 .94 VDD -1 .92 VDD -1 .91 V V Timing Characteristics Table 72 . LVDS Output ac Timing Characteristics Applicable Balls Symbol CK622P/N, CK155P/N[1 :0] SYLVSP/N[1 :0] tRISE tFALL tSKEW1* Parameter Rise Time, 20% to 80% Fall Time, 20% to 80% Differential Skew Conditions Min Typ Max Unit ZLOAD = 100 n 1 % ZLOAD = 100 n 1 % - 200 200 - - 300 300 50 ps ps ps Conditions Min Typ Max Unit - - *As defined in the IEEE standard 1596 .3 -1996 . Table 73. CMOS Output ac Timing Characteristics Applicable Balls Symbol CK77, CK51, CK38, CK19, SYNC8K, CKPDH5, CKPDH4, CKPDH3, CKPDH2, CKPDH1, SWSTATE[1 :0], INT[8 :0], TSTMODE tRISE 68 tFALL tSKEW1~ Parameter Rise Time, 20% to 80% Fall Time, 20% to 80% Differential Skew - ps ps ps Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Timing Characteristics (continued) Table 74. LVPECL Output ac Timing Characteristics Applicable Balls Symbol PCK622P/N, PCK155P/N[1 :0] SYPCLP/N[1 :0] tRISE tFALL tSKEW1* Agere Systems Inc. Parameter Rise Time, 20% to 80% Fall Time, 20% to 80% Differential Skew Conditions Load = 50 n connected to VDD - 2.0 V - Min - Typ Max Unit - Ps Ps - Ps 69 AdLib OCR Evaluation Preliminary Data Sheet TSWC03622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch May 2002 Packaging Diagram 208-Plastic Ball Grid Array (17 x 17)-0.63 mm Ball Size (4-Layer-Bottom View) Dimensions are in millimeters . 17 .00 0.20 +0 .70 0.05 15 .00 A1 BALL IDENTIFIER ZONE +0 .70 15 .00 -0 .05 17 .00 0.20 1 .91 0.21 0.80 0.05 r0.61 0.06 --T 0.50 0.10 T O O O O O O O O1O O O O O O O O P O O O O O O O O1O O O O O O O O: N M L K 1 H G F E D C B A A1 BALL -/"" CORNER 70 SEATING PLANE p 0.20 SOLDER BALL 15 SPACES @ 1 .00 = 15 .00 R 11 11 1 .00 O O O O O O O O O O O O O O O O O O O O O O O O1O O O O O O O O O O O O O O O O I O O O O O O1O O O O O O O O TO O O O O O O O O O O O O O O O O O 0 00 0 O O1O O I O O O O O O O O +0 .07 0.63 -0 .13 O O O O O O O O O O O O O O O O 15 SPACES 1 .00 = 15 .00 O O O O O O O O O O O O O O O O1O O O O O O O O O O O O O O O OIO O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O OIO O O O O O O O 1 2 3 4 5 6 7 8 ~ 9 10 11 12 13 14 15 16 5-7809 .b (F) Agere Systems Inc . AdLib OCR Evaluation TSWC03622 SONET/SDH/PDH/ATM Preliminary Data Sheet May 2002 Clock Synthesizer and Protection Switch Ordering Information Device Code TSWC03622 Agere Systems Inc. Package I 208 PBGAM1 Temperature I -40 0 C to +85 0 C Comcode (Ordering Number) I 700021311 71 AdLib OCR Evaluation Telcordia is a trademark of Telcordia Technologies, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http ://www.agere.com E-MAIL: docmaster@agere.com N . AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA : Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/17, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN : (886) 2-2725-5858 (Taipei) EUROPE : Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc . reserves the right to make changes to the product(s) or information contained herein without notice . No liability is assumed as a result of their use or application . Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (R) 2002 Agere Systems Inc . All Rights Reserved May 2002 DS02-239HS P L