700021311 - Agere Systems, Inc.

a'e

re

systems

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Features

.

Same

functionality

as

TSWC01622

with

reduced

jitter

specifications

.

Fully

integrated

clock

synthesis

. Clock

or

system

sync

protection

switching

.

Fast

autonomous

switching

with

software

override

.

Supports

a wide

choice

of

SONET/SDH

output

clock

frequencies

with

fitter

quality

up

to

OC-12

:

622

.08

MHz

155

.52

MHz

77

.76

MHz

51

.84

MHz

44

.736

MHz

38

.88

MHz

34

.368

MHz

32

.768

MHz

24

.704

MHz

19

.44

MHz

16

.384

MHz

8

.192

MHz

4

.096

MHz

2

.43

MHz

2

.048

MHz

1

.544

MHz

.

Five

outputs

of

frequency

programmable

clocks

.

Supports

multiple

input

clock frequencies

:

51

.84

MHz

38

.88

MHz

19

.44

MHz

8

.192

MHz

6

.48

MHz

2

.048

MHz

1

.544

MHz

8

kHz

.

Generates

sync

outputs

at

8

kHz

aligned

to

an

8

kHz

input

clock

signal

. Locks

to

backup

reference

clock

if

both

the

work-

ing

and

protection

reference

clocks are

lost

.

Low

skew

clock

distribution

balls

. Compatible

with

Agere

Systems

Inc

.

TDAT04622/

TADM04622

SONET/ATM/POS

devices,

STSI-

144,

TSI-16,

TSI-8,

TMX84622

Ultramapper

and

TMXF28155

Supermapper

.

Single

3

.3

V

supply

.

Multiple

output

tech

nologies-CMOS,

LVPECL,

or

LVDS

.

Programmable

via

external

balls

or

internal

resist-

ers

via

serial

interface

Applications

.

SONET/SDH

and

PDH

add/drop

multiplexers,

cross

connects,

switches,

and

routers

Description

The

Agere

Systems

TSWC03622

is

designed

for

a

wide

variety

of

synchronous

timing applications

.

It

serves

as a

clock

synthesizer

and

low

skew

clock

fan-out

device

generating

clocks

at

frequencies

up

to

622

.08

MHz

that

are

synchronized

to

the

system

ref-

erence

clock

.

It

also

serves

as an

intelligent

clock

protection

switch

with

fast

autonomous

selection

based

on

the

presence

of

the

two

input

clocks

.

Alter-

natively,

clock

switching

can be

controlled

entirely

through

a

software

interface

by

the

user

.

The

TSWC03622

also

delivers

an

output

sync

signal

that

is

aligned

to

the

input

clock

.

If

8

kHz

system

sync

sig-

nals

are

applied

as

the

clock

A

and

clock

B

inputs,

the

TSWC03622

will

generate

an

output

sync

signal

that

is

phase

aligned

to

the

selected

input

sync

.

A

programmable

phase

offset

is

provided

to

allow

the

user

to

offset

the output

sync

relative

to

the

input

sync

.

The

output

sync

can

be used

for

global

align-

ment

of

cells

or

frames

in

SONET/SDH/PDH

cross

connects

or

ATM

switch

applications

.

The

device

allows

flexible

choices

of

LVDS

or

LVCMOS

input

technologies

and

LVDS,

LVPECL,

or

LVCMOS

out-

put

technologies

.

The

TSWC03622

is

intended

for

clock

distribution

and

protection

switching

on a

line

card,

a

switch

card,

or

a

shelf

timing

card

.

Along

with

the

wide

vari-

ety

of

input

and

output

frequencies,

a

unique

feature

of

the

device

is

a guaranteed

correct

number

of out-

put

clock

cycles

between

output

sync

pulses

before,

during,

and

after

a

clock

selection

switching

event

.

The

number

of

clock

cycles

between

sync

pulses

remains

correct

even

during

a

switch

between

work-

ing

and

protection

clock

sources

that

have an

arbi-

trary

phase

relationship

between

them

.

The

TSWC03622

also

solves the

skew

problem

associ-

ated

with

timing

distribution

over

cable

or

backplane

traces

of different

lengths

.

The

TSWC03622

can

be

programmed

via

external

balls,

or

through

a

serial

interface

.

Enhanced

func-

tionality

is

available

through

the

serial

interface,

including

programmable

clock

outputs

through

frac-

tional

synthesis

and

the

ability

to

enable

or

disable

each

output

individually

.

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Table

of

Contents

Page

Features

....

.

............

.

.....................................................

.

............

.

........................................

.

...........................

.

.........

.1

Applications

.....................................................

.

............

.

........................................

.

............

.

...........................

.

.........

.1

Description

.

............

.

........................................

.

............

.

........................................

.

............

.

..............

.

............

.

.........

.1

Block

Diagram

....................................

.

............

.

........................................

.

............

.

........................................

.

.........

.4

Ball

Information

.......

.

........................................

.

............

.

........................................

.

............

.

..............

.

............

.

.........

.5

Functional

Overview

........................................

.

............

.

.....................................................

.

...........................

.

.......

.14

Description

of

Transient

Switching

Behavior

...

.

............

.

........................................

.

............

.

............

.

..............

.

.......

.14

Input

Clock

Specifications

..................

.

............

.

............

.

........................................

.

............

.

...........................

.

.......

.17

Input

Clock

Stability

Requirements

(Clock

A

and

Clock

B)

...................

.

............

.

............

.

...........................

.

.......

.17

Input

Frequency

Selection

(FINSEL[3

:0])

.............................................

.

............

.

...........................

.

............

.

.......

.17

Input

Electrical

Level Selection

for

Clock

A

and Clock

B

Input

Signals

(SELLVDS)

......................

.

............

.

.......

.17

Backup

Reference Clock

Selection

(FBUSEL[3

:0])

...........................................

.

............

.

...........................

.

.......

.17

Input

Clock

Minimum

Pulse-Width

Specifications

(Clock A,

Clock

B,

CLKBU)

. .

.

............

.

...................................

.18

Input

Clock

Minimum

Pulse

Width

. .

.

............

.

............

.

.....................................................

.

............

.

..............

.

.......

.18

Output

Clock

Specifications

.............................

.

............

.

.....................................................

.

...........................

.

.......

.18

Available

Output

Clocks

...............................

.

............

.

........................................

.

............

.

...........................

.

.......

.18

Jitter

Specifications

.

........................................

.

............

.

.....................................................

.

...........................

.

.......

.20

Synchronization

Output

at

8

kHz

........

.

............

.

............

.

.....................................................

.

...........................

.

.......

.21

Sync

Output

(SYNC8K,

SYLVSP/N[1

:0],

SYPCLKP/N[1

:0])

..............................

.

............

.

............

.

......................

.21

Sync

Duty Cycle

Selection

(SYDU)

.............

.

............

.

........................................

.

............

.

...........................

.

.......

.21

Sync

Alignment

...

.

........................................

.

............

.

........................................

.

............

.

...........................

.

.......

.21

Offset

Programming

(SYOFF[9

:0],

SYOFFPOS)

......

.

............

.

........................................

.

............

.

......................

.21

Skew

Specifications

.........................................

.

............

.

.....................................................

.

...........................

.

.......

.23

Output

Specifications

During

Phase-Locked

Condition

(Nontransient

Condition)

.

........................................

.

........

28

Maximum

Time

Interval

Error

(MTIE)

Specifications

.

........................................

.

............

.

............

.

......................

.28

Time

Deviation

(TDEV)

Specifications

.........

.

............

.

............

.

........................................

.

............

.

..............

.

.......

.30

Output

Specifications

During

Transient Condition

........

.

........................................

.

............

.

...........................

.

.......

.31

Maximum

Time

Interval

Error

(MTIE)

Specifications

.

........................................

.

............

.

............

.

......................

.31

Other

Input

and

PLL

Specifications

....

.

.....................................................

.

............

.

............

.

..............

.

............

.

.......

.33

Input

Clock

Maximum

Rate

of

Phase

Change

During

Transient

.......................

.

............

.

...........................

.

.......

.33

External

38

.88

MHz

VCXO

Requirements

...

.

............

.

........................................

.

............

.

...........................

.

.......

.33

Loop

Filter

Components

for

High-Speed

PLL

.......................................

.

............

.

...........................

.

............

.

.......

.33

Loop

Filter

Components

for

Low-Speed

PLL

............

.

........................................

.

............

.

............

.

..............

.

.......

.33

INLOSN

. .

.

........................................

.

............

.

.....................................................

.

........................................

.

.......

.35

Clock

Switching

State

Machine

and

Software

Interface

...........................

.

............

.

............

.

...........................

.

.......

.35

Clock

Switching

State

Machine

Behavior

....

.

........................................

.

............

.

...........................

.

............

.

.......

.35

Operation

............

.

........................................

.

............

.

............

.

........................................

.

...........................

.

.......

.35

Software

Interfacing

.....................................

.

............

.

........................................

.

............

.

...........................

.

.......

.37

Loss

of

Clock

Criteria

...................................

.

............

.

.....................................................

.

...........................

.

.......

.37

Interrupt

Generation

(INT[8

:0])

.....................

.

............

.

........................................

.

............

.

...........................

.

.......

.38

Serial

Interface

and

Internal

Bus

.....................

.

............

.

........................................

.

............

.

...........................

.

.......

.39

TSWC03622

Registers

Map

............................

.

............

.

............

.

........................................

.

...........................

.

.......

.41

Control

Block

Registers

...................................

.

............

.

.....................................................

.

...........................

.

.......

.44

Input

Clock

Block

Registers

.............................

.

............

.

.....................................................

.

...........................

.

.......

.45

Switch

State

Machine

Block

Registers

............

.

............

.

.....................................................

.

............

.

..............

.

.......

.47

PDH

Output Block

Registers

...........................

.

............

.

.....................................................

.

...........................

.

.......

.50

Fractional

Dividers

Registers

:

40h-66h

.....

.

............

.

........................................

.

............

.

...........................

.

.......

.50

General

Configuration

Registers

:

80h-83h

.

............

.

........................................

.

............

.

............

.

..............

.

.......

.50

SDH/Sync

Generation

Block

Registers

....................................................

.

............

.

............

.

...........................

.

.......

.54

Absolute

Maximum

Ratings

................

.

............

.

............

.

........................................

.

............

.

...........................

.

.......

.65

Handling

Precautions

......................................

.

............

.

.....................................................

.

...........................

.

.......

.65

Operating

Conditions

.......................................

.

............

.

........................................

.

............

.

...........................

.

.......

.65

2

Agere

Systems

Inc

AdLib OCR Evaluation

Preliminary

Data

Sheet

TSWC03622

SONET/SDH/PDH/ATM

May

2002

Clock

Synthesizer

and

Protection

Switch

Table

of

Contents

(continued)

Contents

Page

Electrical

Characteristics

.......

.

............

.

............

.

.....................................................

.

............

.

...........................

.

.......

.66

LVPECL,

LVDS,

CMOS,

Input

and

Output

Balls

..................................

.

............

.

...........................

.

............

.

.......

.66

Timing

Characteristics

........................

.

............

.

.....................................................

.

............

.

...........................

.

.......

.68

Packaging Diagram

...............

.

............

.

............

.

........................................

.

............

.

............

.

...........................

.

.......

.70

208-Plastic

Ball

Grid

Array

(17

x

17)-0

.63

mm

Ball

Size

(4-Layer-Bottom

View)

........................

.

............

.

.......

.70

Ordering

Information

...........................

.

............

.

........................................

.

............

.

........................................

.

.......

.71

Agere

Systems

Inc

.

3

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Block

Diagram

-

CLKAP

------------------

-----

------------- ----------------

----

CLKAN

DIV

M

CLKA

'

LOCA

CLKBP

P

LFO

CLKBN

,

+

DIV

M

CLKB LOCB

D

I

El

SELLVDS

c--

PHASE VCXO

COMPARE

38

.88

MHz

DIVIDE

O

FINSEL[3

:0]

, ;

, '

CLKBU LSVCO

DIV

N

'

FED

LOC38

FBUSEL[3

:0]

'

INLOSN

0

LF[P

:N]

'

F

,

VC[P

:N]

F

1

SELCLK

,_'

SELBUN

,

AUTOSWN

REVERTN P

~D

-E~

~

VC0

VCO

DIVIDE

SWCONTN

CONTROL

---w

SYOFF[9

:0]

AND

SYNC

ENSQLN

SWITCH

EN

qT(r-

.1

K

T

OFFSET

SYOFFPOS

ENLON

STATE

SYDU

MACHINE

LORSTN D

Q

SYNC8K

DD

IVIDEIVIDE

RESETN

SYLVSP[1

:0]

SYLVSN[1

:0]

SWSTATE[1

:0]

INT[8

:0]

SYPCLP[1

:0]

SYPCLN[1

:0]

BASED

ON

SID

RREF

CKPDH5

PCK622P

PCK622N

CKPDH4

CK622P

CKPDH3

PDH

CK622N

CKPDH2

CLOCK

'

PCK155P[1

:0]

CKPDHI

GEN

.

PCK155N

1

0]

SONET

CK155P[1

:

:0]

PDHSEL[3

:0]

CLOCK

I~w

CK155N[1

:0]

GEN

.

'

CK77

R

1

CK51

SERCLK

SERIAL

I/F

REGISTER

,

CK38

SERENBLN

CONTROL

CK19

SERDAT

"

---

------------------

-----

-----------------------------

SDHSEL[3

:0]

----

"

2359

(F)

Note

:

The

grayed

out

portions

of

the

figure

indicate

that

they

are

test

features

.

Figure

1

.

TSWC03622

Block

Diagram

4

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Ball

Information

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

1

234

5 6

789

10

11 12

13 14 15

16

1

234

5 6

789

10

11 12

13 14 15

16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

2360

(F)

Figure

2

.

TSWC03622

208-Ball

BGA

(Top

View)

Agere

Systems

Inc

.

5

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Ball

Information

(continued)

Table

1

.

Ball

Assignments

for

208-Ball

BGA

by

Ball

Number

Order

Ball

Signal

Name

A1

GND

A2 CLK155NO

A3

CLK155PO

A4

GND

A5

SYLVSNO

A6

SYLVSPO

A7

GND

A8 CK622N

A9 CK622P

A10

GND

A11

SYLVSN1

A12

SYLVSPI

A13

GND

A14

CLK155N1

A15

CLK155P1

A16

GND

131

PCK155NO

B2 CK19

133

VDDPDH

134

CKPDH2

B5

VDDPDH

136

GND

137

GND

138

GND

B9

GND

B10

GND

1311

GND

B12

GND

B13

GND

B14

SYOFF6

B15 TSTIVIODE

B16

I

TSTCLKP

Ball

Signal

Name

C1

PCK155PO

C2 CK38

C3

CKPDHI

C4

CKPDH3

C5

CKPDH5

C6

VDDLVDS

C7

GND

C8

GND

C9

GND

C10

GND

C11

VDDSDH

C12

SYOFF2

C13

SYOFF5

C14

SYOFF8

C15

VDDTCLK

C16

TSTCLKN

D1

VDDPECL

D2

VDDSDH

D3

GND

D4

GND

D5

CKPDH4

D6

VDDPDH

D7

VDDLVDS

D8

RREF

D9

VDDLVDS

D10

SYOFFO

D11

SYOFF1

D12

SYOFF3

D13

SYOFF4

D14

SYOFF7

D15

SYDU

D16

I

GND

Ball

Signal

Name

E1

SYPCLNO

E2

FINSELO

E3

FINSEL3

E4

SYNC8K

E5

-

E6

-

E7

-

E8

-

E9

-

E10

-

E11

-

E12

-

E13

SYOFF9

E14

VDDHSPD

E15

VDDLSVCO

E16

LSVCO

F1

SYPCLPO

F2

VDDPECL

F3

GND

F4

CK51

F5

-

F6

-

F7

-

F8

-

F9

-

F10

-

F11

-

F12

-

F13

SYOFFPOS

F14

VDDHSPD

F15

VDDHSVCO

F16

I

GND

Note

:

-

refers

to

no

ball

.

NC

means

do

not

connect

any

traces

to this

solder

ball

.

Ball

Signal

Name

G1

VDDPECL

G2

VDDPECL

G3

VDDPECL

G4 CK77

G5

-

G6

-

G7

GND

G8

GND

G9

GND

G10

GND

G11

-

G12

-

G13

NC

G14

INLOSN

G15

LFN

G16

VCN

H1

PCK622N

H2

VDDPECL

H3

FINSEL2

H4

FINSELI

H5

-

H6

-

H7

GND

H8

GND

H9

GND

H10

GND

H11

-

H12

-

H13

GND

H14

GND

H15 LFP

H16

I

VCP

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Ball

Information

(continued)

Table

1

.

Ball

Assignments

for

208-Ball

BGA

by

Ball

Number

Order

(continued)

Ball

Signal

Name

J1

PCK622P

J2

VDDPECL

J3

VDDPECL

J4

GND

J5

-

J6

-

J7

GND

J8

GND

J9

GND

J10

GND

J11

-

J12

-

J13

GND

J14

VDDHSDIV

J15

VDDHSVCO

J16

NC

K1

VDDPECL

K2

VDDPECL

K3

GND

K4

SDHSEL2

K5

-

K6

-

K7

GND

K8

GND

K9

GND

K10

GND

K11

-

K12

-

K13

FBUSELO

K14

VDDHSDIV

K15

LFOZ

K16

I

NC

Ball

Signal

Name

L1

SYPCLN1

L2

SDHSELO

L3

SDHSEL3

L4

SDHSELI

L5

-

L6

-

L7

-

L8

-

L9

-

L10

-

L11

-

L12

-

L13

FBUSEL3

L14

FBUSEL2

1-15

SELCLK

L16

FBUSELI

M1

SYPCLP1

M2

VDDCNTL

M3

VDDCNTL

M4

SDH

HW

M5

-

M6

-

M7

-

M8

-

M9

-

M10

-

M11

-

M12

-

M13

GND

M14

AUTOSWN

M15

REVERTN

M16

I

SELBUN

Ball

Signal

Name

N1

VDDPECL

N2

SERDAT

N3

SERENBLN

N4

GND

N5

INT8

N6

INT5

N7

INT4

N8

VDDFF

N9

INT1

N10

INTO

N11

SWSTATEI

N12

SELLVDS

N13

GND

N14

ENSQLN

N15

RESETN

N16

SWCONTN

P1

PCK155N1

P2

PDHSEL3

P3

PDHSEL2

P4

GND

P5

GND

P6

INT6

P7

NC

P8

RSVB

P9

VDDFF

P10

RSVA

P11

NC

P12

SWSTATEO

P13

ENLON

P14

VDDLSPLL

P15

VDDLSPLL

P16

I

VDDCNTL

Ball

Signal

Name

R1

PCK155P1

R2

SERCLK

R3

GND

R4

GND

R5

PDHSELO

R6

INT7

R7

INT3

R8

GND

R9

GND

R10

INT2

R11

GND

R12

LORSTN

R13

GND

R14

GND

R15

GND

R16

GND

T1

VDDPECL

T2

VDDCLKBU

T3

CLKBU

T4

PDHSELI

T5

GND

T6

CLKB

T7

CLKBN

T8

CLKBP

T9

GND

T10

CLKAP

T11

CLKAN

T12

CLKA

T13

GND

T14

LF2

T15

LF1

T16

I

LFO

Note

:

-

refers

to

no

ball

.

NC

means

do

not

connect

any

traces

to

this

solder

ball

.

Agere

Systems

Inc

.

7

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Ball

Information

(continued)

1

2

3

4 5

6

7

8 9

10

11

12 13

14

15 16

A

GND

CK155NO CK155PO

GND

SYLVSNO SYLVSPO

GND

CK622N CK622P

GND

SYLVSN1

SYLVSP1

GND

CK155N1

CK155P1

GND

B

PCK155NO

CK19

VDDPDH CKPDH2

VDDPDH

GND GND

GND

GND GND

GND

SYOFF6

TSTMODE

TSTCLKP

C

PCK155PO CK38

CKPDH1

CKPDH3

CKPDH5

VDDLVDS

GND

VDDSDH

SYOFF2 SYOFF5 SYOFFB

VDDTCLK

TSTCLKN

D

VDDPECL

VDDSDH

GND GND

CKPDH4

VDDPDH

VDDLVDS

RREF

VDDLVDS

SYOFFO

SYOFF1

SYOFF3 SYOFF4 SYOFF7

SYDU

GND

E

SYPCLNO

FINSELO FINSEL3

SYNCBK SYOFF9

VDDHSPD

VDDLSVCO

LSVCO

F

SYPCLPO

VDDPECL

GND

CK51

SYOFFPOS

VDDHSPD

VDDHSVCO

GND

G

VDDPECLVDDPECL VDDPECL

CK77

GND

NC INLOSN

LFN

VCN

H

PCK622N

VDDPECL

FINSEL2

FINSELI

GND

GND GND

LFP

VCP

J

PCK622P

VDDPECL VDDPECL

GND GND

GND

VDDHSDIV

VDDHSVCO

NC

K

VDDPECLVDDPECL

GND

SDHSEL2

GND

FBUSELO

VDDHSDIV

LFOZ

NC

L

SYPCLN1 SDHSELO SDHSEL3 SDHSEL1

FBUSEL3

FBUSEL2

SELCLK

FBUSEL1

M

SYPCLP1

VDDCNTL

SDH

HW

GND

AUTOSWN

REVERTN

SELBUN

N

VDDPECL

SERDAT

SERENBLN

GND

INTB

INT5

INT4

VDDFF

INT1

INTO

SWSTATE1

SELLVDS

GND

ENSOLN

RESETN

SWCONTN

P

PCK155N1

PDHSEL3 PDHSEL2

GND GND

INT6

NC

RSVB

VDDFF

RSVA NC

SWSTATEO

ENLON

VDDLSPLL VDDLSPLL

VDDCNTL

R

PCK155P1

SERCLK

GND GND

PDHSELO

INT7 INT3

GND

INT2

GND

LORSTN

GND GND GND

GND

T

VDDPECLVDDCLKBU

CLKBU

PDHSEL1

GND

CLKB

CLKBN CLKBP

GND

CLKAP CLKAN

CLKA

GND

LF2

LF1

LFO

Figure

3

.

Physical

Ball

Orientation

(Bumps

Down)

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Ball

Information

(continued)

Table

2

.

Ball

Descriptions-Clock

Inputs

and

Related Signals

Ball

Symbol*

Typet

Level

Name/Description

T10,

CLKAP

ID

LVDS

Input

Clock

A

.

Usedwhen

LVDS

level

is

desired

for

interfac-

T11

CLKAN

ing to

input

clock

A

source

.

T12

CLKA

ID

CMOS

Input

Clock

A

.

Used

when

CMOS

level

is

desired

for

interfac-

ing to

input

clock

A

source

.

T8,

CLKBP

ID

LVDS

Input

Clock

B

.

Usedwhen

LVDS

level

is

desired

for

interfac-

T7

CLKBN

ing to

input

clock

B

source

.

T6

CLKB

ID

CMOS

Input

Clock

B

.

Used

when

CMOS

level

is

desired

for

interfac-

ing to

input

clock

B

source

.

N12

SELLVDS

Iu

CMOS

Select

Clock

Level

(LVDS/CMOS)

.

Selects

the

LVDS

or

the

CMOS

input

balls

as

the

clock

A

and

B

sources

:

0

=

CMOS

(CLKA,

CLKB)

.

1

or

no

connection

=

LVDS

(CLKAP/N,

CLKBP/N)

.

E3,

H3,

FINSEL[3

:0] Iu

CMOS

Input

Frequency

Select

.

Program

to

indicate

the

input

fre-

H4,

E2

quency

of

the

clock

A

and

B

sources

.

T3

CLKBU

ID

CMOS

Backup

Clock

.

CMOS

level

input

backup

clock

source

.

L13, L14,

FBUSEL[3

:0] Iu

CMOS

Backup

Clock

Frequency

Select

.

Program

to

indicate

the

L16,

K13

input

frequency

of

the

backup

clock

source

.

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential

signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

11

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

Table

3

.

Ball

Descriptions-Analog

and

PLL

Related Signals

Ball

Symbol*

Typet

Level

Name/Description

E16

LSVCO

I

CMOS

38

.88

MHz

VCXO

.

Connection

to

external

VCXO

output

.

T14,

T15

LF2,

LF1

Analog

-

Connect

to

ground

.

T16

LFO

Analog

-

38

.88

MHz

PLL

Loop

Filter

.

K15

LFOZ

Iu

CMOS

38

.88

MHz

PLL

Loop

Filter

Enable

.

CMOS

logic

high

enables

LFO

.

CMOS

logic

low

sets output

LFO

to

high-imped-

ance

state

.

H15,

LFP

Analog

-

High-Speed

PLL

Loop

Filter

.

Connect

to

external

loop

filter

G15 LFN

componentsand

also

connect

LFP

to

VCP

and

LFN

to

VCN

.

H16,

VCP

Analog

-

High-Speed

VCO

Control

Voltage

.

Connect

to

external

loop

G16

VCN

filter

components

and

connect

VCP

to

LFP

and

VCN

to

LFN

.

G14 INLOSN

Iu

CMOS

Input

Loss

of

Signal

.

Active-low

input

signal

forces

control

voltage

on

high-speed

oscillator

to

the

lowest

end

of

the

oscil-

lator

frequency

range

:

0 =

force

lowest-frequency

operation

in

high-speed

oscillator

.

1

or

no

connection

= normal

operation

.

D8

RREF

Analog

-

Resistor

Reference

.

LVDS

output

voltage reference

resistor

.

Insert a

1

.5

ktl resistor

from

RREF

to

VDDLVDS

.

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential

signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

Agere

Systems

Inc

.

9

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Ball

Information

(continued)

Table 4

.

Ball

Descriptions-Output

Clocks

and

Related Signals

Ball

Symbol*

Typet

Level

Name/Description

A9,

CK622P

O

LVDS

622

.08

MHz

Output

Clock

.

A8

CK622N

J1,

PCK622P

O

LVPECL

622

.08

MHz

Output

Clock

.

H1

PCK622N

A15,

A3

CK155P[1

:0]

O

LVDS

155

.52

MHz

Output

Clock

.

A14,

A2 CK155N[1

:0]

R1,

C1

PCK155P[1

:0]

O

LVPECL

155

.52

MHz

Output

Clock

.

P1,

131

PCK155N[1

:0]

G4

CK77

O

CMOS

77

.76

MHz

Output

Clock

.

F4

CK51

O

CMOS

51

.84

MHz

Output

Clock

.

C2 CK38

O

CMOS

38

.88

MHz

Output

Clock

.

132

CK19

O

CMOS

19

.44

MHz

Output

Clock

.

L3,

K4,

SDHSEL[3

:0]

ID

CMOS

SDH

Clock

Output

Selection

.

L4,1_2

E4

SYNC8K

O

CMOS

8

kHz

Output

Sync

.

A12,

A6 SYLVSP[1

:0]

O

LVDS

8

kHz

Sync

Buffers

[1

:0]

.

A11,

A5

SYLVSN[1

:0]

M1,

F1

SYPCLP[1

:0]

O

LVPECL

8

kHz

Sync

Buffers

[1

:0]

.

L1,

E1

SYPCLN[1

:0]

E13,

C14,

D14,

SYOFF[9

:0]

ID

CMOS

Sync

Offset

.

Programs

the

magnitude

of

the

offset of

the

1314,

C13,

D13,

output

syncs

relative

to

an

input 8

kHz

clock/sync

.

D12,

C12,

D11,

D10

F13

SYOFFPOS

Iu

CMOS

Sync

Offset

Positive

or

Negative

.

Selects

the

direction

of

the

sync

offset

:

1

=

positive

offset

.

The

output

sync

is

delayed

in

time

.

0 =

negative

offset

.

The

output

sync

is

advanced

in

time

.

D15

SYDU

Iu

CMOS

Sync

Duty

Cycle

.

Selects

the

duty

cycle

of

the output

sync

signals

:

1

=

50%

duty

cycle

.

0

=

sync

logic

high

time

equal

to

one

period

of

the

highest-frequency

active

SONET

output

clock

.

C5

CKPDH5

O

CMOS

Selectable

PDH

Output

Clock

.

D5

CKPDH4

O

CMOS

Selectable

PDH

Output

Clock

.

C4

CKPDH3

O

CMOS

Selectable

PDH

Output

Clock

.

134

CKPDH2

O

CMOS

Selectable

PDH

Output

Clock

.

C3

CKPDH1

O

CMOS

Selectable

PDH

Output

Clock

.

P2,

P3,

PDHSEL[3

:0]

ID

CMOS

PDH

Clock

Output

Selection

.

T4,

R5

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

10

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Ball

Information

(continued)

Table

5

.

Ball

Descriptions-Control

and

Related Signals

Ball

Symbol*

Typet

Level

Name/Description

L15

SELCLK

Iu

CMOS

Select

Clock

.

Select

clock

A

or

clock

B

(when

SELBUN

=

1)

:

1

=

select

clock

A

.

0

=

select

clock

B

.

This

signal

is

overridden

by

SELBUN

when

SELBUN

is

active

.

M16

SELBUN

Iu

CMOS

Select

Backup

Clock

.

Active-low

signal

selects

CLKBU

:

0

=

select

CLKBU,

overrides

SELCK

.

1

=

allow

SELCK

to

select

clock

A

or

clock

B

.

M14

AUTOSWN

Iu

CMOS

Auto

Switching

Enabled

.

Active-low

signal

allows

the

user

to

enable

autonomous

switching

from

the

currently

selected

clock

:

0

=

autonomous

switching

is

enabled

.

(Software

Control

must

be

disabled

(SWCONTN

=

1)

.)

1

=

autonomous

switching

is

disabled

.

M15

REVERTN

Iu

CMOS

Revertive

Switching

Enabled

.

Active-low

signal

determines

if

the

user

would

like

to

revert

to

the

original

reference

source

after

a

fault

clears

:

1

=

state

machine

is

nonreverting

such

that

the

switch

will

not

return

to

the

original

clock

after

the

fault

condition

ceases

to exist

.

0

=

state

machine

is

reverting

such

that

the

switch

will

return

to

the

original

state

after

the

error

condition

ceases

to

exist

and

at

least

256

ms

have

passed

since

the

switch

.

N16

SWCONTN

Iu

CMOS

Software

Control

.

Active-low

signal

allows

the

user

to

explicitly

choose

which

clock

input

to

use

.

Activating

this

input

causes

SEL-

CLK

and

SELBUN

to

override

any

fault

checking

before

switching

:

0

=

software

control

is

enabled

.

(Overrides

autonomous

switching

(AUTOSWN)

setting

.)

1

=

software

control

is

disabled

.

N14

ENSQLN

Iu

CMOS

Enable

Squelch

.

Active-low

signal

enables

automatic

squelching

of

the

clock

and

sync

outputs

whenever

a

fault

is

encountered

.

When

squelching

occurs,

all

output

clock

and

sync

signals

will

be

held

at

a

logic-low

output

level

.

If

the

device

is

not

in

software

control

mode

(SWCONTN

=

1),

the

outputs

will

be

squelched

if

squelch

is

enabled and

all

input

clocks

(clock

A,

clock

B,

CLKBU)

are

lost

:

1

=

automatic

squelching

of

the

outputs

is

disabled

.

0

=

automatic

squelching

of

the

outputs

is

enabled

.

If

the

device

is

in

the

software

override

mode

(SWCONTN

=

0),

then

ENSQLN

can be used

to

manually

squelch

the

device

clock

outputs

:

1

=

normal

device

clock

output

operation

.

0

=

manually

squelch

the

device

clock

outputs

.

N15

RESETN

Iu

CMOS

Reset

.

Active-low

asynchronous

reset

.

P13

ENLON

Iu

CMOS

Enable

Lockout

.

Active-low

signal

allows

the

user

to

provide

a

lock-

out

function

to

prevent

excessive

switching

between

references

:

1

=

free

to

switch

for

any

fault

.

0

=

lockout

the

autonomous

switch

whenever

the

internal

lockout

flag

is

active

due

to

excessive

switching

.

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential

signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

Agere

Systems

Inc

.

11

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Information

(continued)

Table

5

.

Descriptions-Output

Clocks

and

Related Signals

(continued)

Ball

Symbol*

Typet

Level

Name/Description

R12

LORSTN

Iu

CMOS

Lockout

Trigger

Reset

.

Active-low

signal

resets

the

lockout

counter

to

prevent

locking

out

the

protection

switch

:

0

=

clear

the

lockout

counter

.

1

=

normal

lockout

counter

operation

.

N11,

P12

SWSTATE

O

CMOS

Switch

State

.

Reflects

whether

the device

is

currently selecting

[1

:0]

clock

A,

clock

B,

or

the

backup

clock

:

00

=

select

clock

A

.

01

=select

clock

B

.

10

=

select

backup

clock

(previous

clock

source

was

clock

A)

.

11

=

select

backup

clock

(previous

clock

source

was

clock

B)

.

N5,

R6, P6,

INT[8

:0]

O

CMOS

Interrupts

.

Active-high

interrupts

define

fault

conditions

.

See

N6, N7,

R7,

Table

28

onpage38

for individual interrupt

definitions

.

R10,

N9,

N10

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

Table 6

.

Ball

Descriptions-Test

and

Reserved

Signals

Ball

Symbol*

Typet

Level

Name/Description

R2

SERCLK

Iu

CMOS

Serial

Interface

Clock

.

Serial

interface

clock

that

can

operate

up

to

25

MHz

.

N3

SERENBLN

Iu

CMOS

Serial

Interface

Enable

.

This

signal

must

be

low

during

regis-

ter

access

.

N2

SERDAT

Iu

CMOS

Serial

Data

.

This

is

a

bidirectional

ball

for

writing

and

reading

software

registers

.

B15

TSTMODE

ID

CMOS

Test

Mode

.

Internal

test

observation

signal

used

in

test

mode

.

B16

TSTCLKP

ID

LVDS

Test

Clock

Input

.

C16

TSTCLKN

P10

RSVA

ID

CMOS

Reserve

Input

A

or

B

.

Reserved

for

future

feature

enhance-

P8

RSVB

ment

.

M4

SDH

HW

ID

CMOS

Internal

Signal

.

When

set

to

a

CMOS

logic high,

the

SDH

block takes

information

directly

from

the

external

leads

and

does

not

use

information

from

the

internal

bus

.

Hence,

if

the

internal

bus

is

functional,

solder

ball

M4

may

be

designated

as

a

ground

.

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

Table 7

.

Ball

Descriptions-No-Connect

Signals

Ball

Symbol*

Typet

Level

Name/Description

G13,

J16,

NC

- -

Not connected

.

K16,

P7,

P11

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

12

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Ball

Information

(continued)

Table

8

.

Ball

Descriptions-

Power

Signals

Ball

Symbol*

Typet

Level

Name/Description

C11,

D2

VDDSDH

Power

-

D1,

F2,

G1,

VDDPECL

Power

-

G2, G3,

H2,

J2, J3,

K1,

K2,

N1,

T1

D9, C6,

D7

VDDLVDS

Power

-

M2, M3,

P16

VDDCNTL

Power

-

T2

VDDCLKBU

Power

-

N8,

P9

VDDFF

Power

-

P14,

P15

VDDLSPLL

Power

-

K14,

J14

VDDHSDIV

Power

-

J15,

F15

VDDHSVCO

Power

-

E15

VDDLSVCO

Power

-

E14,

F14

VDDHSPD

Power

-

D6,

135,

133

VDDPDH

Power

-

C15

VDDTCLK

Power

-

A1, A4, A7,

GND

Ground

-

A10,

A13, A16,

B6, B7,

B8,

B9,

B10,

1311,

1312, 1313,

C7,

C8, C9,

C10,

D3,

D4,

D16,

F3,

F16,

G7,

G8, G9,

G10,

H7, H8, H9,

1-110,1-113,1-114,

J4, J7, J8,

J9,

J10,

J13,

K3, K7,

K8,

K9,

K10,

M13,

N4,

N13,

P4,

P5,

R3, R4,

R8, R9,

R11,

R13, R14,

R15,

R16,

T5,

T9,

T13

*

Differential

pairs

are

indicated

by P

and

N

suffixes

.

For

nondifferential

signals,

N

at

the

end

of

the

symbol

name

designates

active-low

.

t

I

=

input,

O

=

output

.

Iu

indicates

an

internal

pull-up

resistor

on

this

ball

.

I°

indicates

an

internal

pull-down

resistor

on

this ball

.

Agere

Systems

Inc

.

13

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Functional

Overview

The

TSWC03622

is

designed

to

manage

clock

genera-

tion

and

timing

distribution

in

SONET/SDH

compliant

line

card

solutions

up

to

OC-12

data

rates

.

Its

output

clocks

are

designed

to

enable

hitless

clock switching

between

a

primary

and

secondary

clock

source

and

meet

relevant

output

clock

jitter

generation

specifica-

tions

and

maximum

time

interval

error

(MTIE)

during

a

switching

transient

.

It

supports

a

range

of

common

input

frequencies

from 8

kHz

to

51

.84

MHz

.

A

backup

frequency

source

is

also

supported

that

can be

used

as

a

frequency

reference

when

both

primary

and

second-

ary

input

clocks

are

lost

.

During

a

switch

from

either

the

primary

or

the

secondary

clock

inputs

to

the

backup

reference

input,

the

TSWC03622

output clocks

do

not

guarantee

compliance

with

SONET

MTIE

specifica-

tions

.

An

integrated

digital

state

machine

monitors

the

presence

of

all

input

clock

signals

and can

provide

autonomous

clock switching

under

fault

conditions

.

Several

programmable

options

are

available

that

deter-

mine

the

behavior

of

clock

switching,

including

com-

plete

software

control

of

the

switching

events

.

Programming

of

the

TSWC03622

can be accomplished

through

external

ball

control

or

through

internal

regis-

ters,

via

a

serial

interface

.

A

range

of

SONET

and

PDH

clock

frequencies

are

generated

with

155

MHz

and

622

MHz

clocks

available

on

multiple

low-skew

LVDS

and

LVPECL

output

buffers

in

order

to

provide

fan-out

and

clock

distribution

sources

for

multiple

chips

within

the

system

.

An

8

kHz

sync

signal

with

a

user-program-

mable

offset

is

generated

and

is

available

on

CMOS,

LVDS,

and

LVPECL

output

buffers

.

The

duty

cycle

of

the

8

kHz

output

sync

signal

is

selectable

as

either

50%

or

as

the

width

of

a

single

clock pulse

determined

by

the

maximum

selected

SONET/SDH

frequency

.

Description

of

Transient

Switching

Behavior

The

TSWC03622

is

designed

for

application

in

sys-

tems

that

utilize

a

number

of

different

timing

and

data

distribution

architectures

.

Because

the

frequency

and

phase

alignment

of

timing

distribution signals,

as

well

as

the architectures

used

for

frame

alignment

and

data

buffering

all

vary

for different

system

architectures

and

product

implementations,

the

characteristics

of

the

TSWC03622's

switching

behavior

must

be

properly

exploited

by

the

system

architecture

.

A

description

of

the

switching

transient

behavior

is

provided

here

.

In

general,

two

timing

signals

will

be

distributed

as

the

clock

A

and

clock

B

inputs

to

the

TSWC03622

.

These

inputs

may

range

in

frequency

from

8

kHz

to

51

.84

MHz

.

In

some

cases, the

timing

source

that

gen-

erates

clock

A

and

clock

B

is

designed such

that

the

two

clocks

are

coupled

.

Therefore,

the

relative

phase

of

clock

A

and

clock

B

will

be

small

.

In

other

cases, the

phases

of

clock

A

and

clock

B

will

be

uncontrolled

with

respect

to

each

other

and

the

phase

difference

between

the

two

clocks

could

be up

to

a

full

period

of

the

input

frequency

.

When

the

input

frequency

is

rela-

tively

high,

the

phase

difference

can

only

be a few

tens

of

nanoseconds

due

to

the

small

time

period

of

one

clock

cycle

.

In

the

cases

where

the

input

frequency

is

relatively

low

and

the

two

timing

sources

are not

cross

coupled,

the

phase

difference

can be

up

to

many

tens

of

microseconds

due

to

the

large

time

period

of

one

clock

cycle

.

When

the

input

frequency

is

relatively

low

but

the

two

timing

sources

havebeen

cross

coupled

and

the

skew

has

been

well

controlled

as

the

signals

are

distributed,

the

phase

difference

may

be

controlled

within

just

a

few

tens

of

nanoseconds

.

Some

system

architectures

rely

on

the

fact

that

there

will

be

a

small

phase

difference

between

the

primary

and

secondary

timing

signals,

and

therefore,

they

do

not

provide

extensive

data

buffering

or

alignment

capa-

bilities

elsewhere

in

the

system

.

They

rely

on a

hitless

phase

step

when

a

switch

occurs

between

clock

A

and

clock

B

followed

by a slow

adjustment

or "bleed

out" of

the

phase

step

during

a

transient

period

.

The

phase

bleed

out

adjustment

must,

however,

comply

with

MTI

E

and

TDEV

requirements

during

a

transient

switching

event

as

defined

in

relevant

standards

.

System

architectures

that

use

low-frequency

signals

for

timing

distribution

but

do

not

cross

couple

the

timing

sources

may

have a

large

phase

difference

between

clock

A

and

clock

B

at

the

time

a

clock

switch

is

initi-

ated

.

In

this

case,

the

output clocks

must

still

have a

hitless

phase

step

at

the

moment

the

switch

occurs

.

However,

SONET

MTIE

requirements

do

not

generally

allow

the

subsequent

phase

bleed

out

to

completely

adjust

for

the

entire

phase

difference

.

Bleeding

out the

entire

phase

difference

at

a

rate

consistent

with

MTIE

and

TDEV

transient

requirements

would cause

the

transient

condition

to exist

for

a

duration

longer

than

allowed

in

the

standards

.

Therefore,

systems

that

dis-

tribute

low-frequency

timing

signals with

arbitrary

skew

must

provide

extensive

data

buffering

or

alignment

capabilities

elsewhere

in

the

system

.

14

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Description

of

Transient

Switching Behavior

(continued)

The

TSWC03622

provides

hitless

phase

switching

with

clock

inputs

of arbitrary

phase

difference

at

frequencies

from

8

kHz

to

51

.84

MHz

.

However,

a

complete

adjustment

or

bleed

out

of

the

phase

will

occur

only

for

phase

dif-

ferences

less

than

approximately

200

ns

.

For

all

input

phase

differences

of

greater

than

this,

the

transient

will

cease

after

the

maximum

phase

has

been

adjusted

(maximum

250

ns)

.

Figure

4

shows

the

TSWC03622

switching

transient

behavior

for

the

condition

of

small

phase

differences

between

input

clocks

.

Figure

5

shows

the

TSWC03622

switching

transient

behavior

for

the

condition

of

large

phase

differences

between

input

clocks

.

INPUT

CLOCKS

CLOCK-A

SELECTED

CLOCK-B

STANDBY

I

tPHASE

<

APPROX

250

ns

OUTPUT

CLOCKS/SYNCS

PRIOR

TOSWITCH

PDH/SDH*

CLOCK

OUTPUTS

SYNC

OUTPUTS

PDH/SDH

CLOCK

OUTPUTS

SYNC

OUTPUTS

OUTPUT

CLOCKS/SYNCS

AT

INSTANT

OFSWITCH

FROM

CLOCK-A

TO

CLOCK-B

HITLESS

PHASE

SWITCH

OUPUT

CLOCKS/SYNCSDURING

TRANSIENT

PHASE

MOVEMENT

MEETS

MTIE/TDEV

PDH/SDH

~"

CLOCK

OUTPUTS

SYNC

OUTPUTS

I

"

I

OUTPUT

CLOCKS/SYNCS

AT

END

OF

TRANSIENT

OUTPUTS

ALIGNED

TO

CLOCK-B

PDH/SDH

CLOCK

OUTPUTS

SYNC

OUTPUTS

2361

(F)

*

This

diagram

shows

the

phase

relationship

of

the

clock

outputs

and

the

sync

outputs

.

In

the

case

of

PDH

clock

outputs,

the

timing

relationship

between

clock

and

sync

is

not

necessarily

as

shown

here

since

the

phase

relationship

between

the

PDH

clock

outputs

and an

8

kHz

sync

is

not

specified

.

Figure 4

.

Transient

Behavior

for

Small

Phase

Differences

in

Input

Clocks

Agere

Systems

Inc

.

15

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Description

of

Transient

Switching Behavior

(continued)

INPUT

CLOCKS

CLOCK-A

SELECTED

STANDBY

I-

-

tPHASE

>

APPROX

250

ns

OUTPUT

CLOCKS/SYNCS

PRIOR

TO

SWITCH

PDH/SDH*

CLOCK

OUTPUTS

SYNC

OUTPUTS

OUTPUT

CLOCKS/SYNCS

AT

INSTANT

OFSWITCH

FROM

CLOCK-A

TO

CLOCK-B

HITLESS

PHASE

SWITCH

PDH/SDH

CLOCK

OUTPUTS

SYNC

OUTPUTS

OUPUT

CLOCKS/SYNCS

DURING

TRANSIENT

PHASE

MOVEMENT

MEETS

MTIE/TDEV

I

;j

;11

PDH/SDH

C

CK

OUTPUTS

LO

;

;j

. .. .. .. .. ..

.

11!11~11-111

SYNC

OUTPUTS

_

tPHASE=

200

ns

(TAP)

250

ns

OUTPUT

CLOCKS/

SYNCS

AT

END

OF

TRANSIENT

(MAX)

MAXIMUM

PHASE

BLEED

PDH/SDH

CLOCK

OUTPUTS

SYNC

OUTPUTS

2362

(F)

*

This

diagram

shows

the

phase

relationship

of

the

clock

outputs

and

the

sync

outputs

.

In

the

case

of

PDH

clock

outputs,

the

timing

relationship

between

clock

and

sync

is

not

necessarily

as

shown

here

since

the

phase

relationship

between

the

PDH

clock

outputs

and

an

8 kHz sync

is

not

specified

.

Figure 5

.

Transient

Behavior

for

Large

Phase

Differences

in

Input

Clocks

16

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

TSWC03622

SONET/SDH/PDH/ATM

May

2002

Clock

Synthesizer

and

Protection

Switch

Input

Clock

Specifications

Input

Clock

Stability

Requirements

(Clock

A

and

Clock

B)

The

clock

A

and

clock

B

inputs

to

the

TSWC03622

must

be

compliant

with

all

requirements

for

a

SON

ET

minimum

clock

(SMC)

as

defined

in

TelcordiaTm

GR-253-CORE

Section

5

.4 .4

.2

(Issue

3,

9/2000),

or

for

an

ITU

node

clock

as

defined

in

G

.812,

in

order

for

the

TSWC03622

to

meet

its

output

clock

specifications

and

transient

phase

requirements

.

Input

Frequency

Selection

(FINSEL[3

:0])

The

input

clock

signal

frequencies

that

are

supported

on

the

clock

A

and

clock

B

inputs,

as

well

as

the

appropriate

frequency

selection

control

ball

programming,

are

given

in

Table

9

.

Input

frequency

selection

can be performed

using

external

balls

FINSEL[3

:0]

or

by

programming

register

0x21

bits

3

:0

(with

SDH

HW

ball

low)

.

Table

9

.

Input

Clock

A

and

Clock

B

Frequency

Selection

Input

Frequency

Clock

A

and

Clock

B

FINSEL3 FINSEL2

FINSEL1

FINSELO

8

kHz

NC

0

1

.544

MHz

NC

0

1

2

.048

MHz

NC

0

1

0

6

.480

MHz

NC

0

1

8

.192

MHz

NC

1

0

19

.44

MHz

NC

1

0

1

38

.88

MHz

NC

1 1

0

51

.84

MHz

I

NC

I

1

I

1

I

1

Input

Electrical

Level

Selection

for

Clock

A

and

Clock

B

Input

Signals

(SELLVDS)

When

SELLVDS

=

0,

the

CLKA

and

CLKB

CMOS

level

input

buffers

are

selected

as

the

clock

A

and

clock

B

inputs

.

When

SELLVDS

=

1

(or

no

connection

is

made

to

the

SELLVDS

ball),

the

CLKAP/N

and

CLKBP/N

LVDS

level input

buffers

are

selected

as

the

clock

A

and

clock

B

inputs

.

Backup

Reference

Clock

Selection

(FBUSEL[3

:0])

The

TSWC03622

provides

the

ability

to

switch

to

a

backup

clock

under

certain

fault

conditions

.

When

the

backup

clock

is

selected, the

TSWC03622

is

not

guaranteed

to

meet

any

of

the

transient

phase

response

requirements

associated

with

a

switching

event

between

the

A

and

B

clock

inputs

.

The

backup

is

intended

to

offer

a

frequency

control

reference

only

and

is

not

intended

to

meet

any

of

the

requirements

of

a

system

holdover

state

.

The

input

backup

clock

frequencies

that

are

supported

on

the

CLKBU

input

signal

as

well

as

the

appropriate

frequency

selection

control

signal

programming

are

given

in

Table

10

.

Backup

reference

frequency

selection

can

be

per-

formed

using

external

balls

FBUSEL[3

:0]

or

by

programming

register

0x22

bits

3

:0

(with

SDH

HW

ball

low)

.

Agere

Systems

Inc

.

17

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Input

Clock

Specifications

(continued)

Table

10

.

Backup

Clock

Frequency

Selection

Input

Frequency

CLKBU

Tolerance

(ppm)*

FBUSEL3 FBUSEL2

FBUSEL1

FBUSELO

8

kHz ±20

NC

000

1

.544

MHz

±20

NC

0 0

1

2

.048

MHz

±20

NC

0

1

0

6

.480

MHz

±20

NC

0

1 1

8

.192

MHz

±20

NC

1

0 0

19

.44

MHz

±20

NC

1

0

1

38

.88

MHz

±20

NC

1 1

0

51

.84

MHz

I

±20

I

NC

I

1

I

1

I

1

*

Tolerance

needed

for

the

TSWC03622

to

maintain

frequency

lock with

specified

VCXO

.

This

tolerance

is

not

intended

to

represent

a system

requirement

.

Input

Clock

Minimum

Pulse-Width

Specifications

(Clock

A,

Clock

B,

CLKBU)

In

order

for

the

TSWC03622

to

guarantee

functionality

and

that

all

transient timing

specifications

are

met,

the

input

clock

must

maintain

a

minimum

pulse width

tPw

= 8

ns

for input

frequencies

greater

than

8

kHz

;

for

input

frequen-

cies

less

than

8

kHz,

a

50%

duty

cycle

is

required,

as

shown

in

Figure

6

.

Input

Clock

Minimum

Pulse

Width

tPW

CLOCK-A,CLOCK-B,

OR

BACKUP

CLOCK

2363

(F)

Figure

6

.

Input

Clock

Minimum

Pulse

Width

Requirement

Output

Clock

Specifications

Available

Output Clocks

The

TSWC03622

supports

the

generation

of

the

SONET/SDH

and

PDH

frequencies

given

in

Table

13,

as

well

as

the

ability

to

program

frequency

output

rates

up

to

TBD

MHz,

using

fractional

synthesis

.

Not

all

PDH

frequencies

listed

in

Table

13

are

available

simulta-

neously

.

Table

11

and

Table

12

illustrate

the

combina-

tion

of

output

clock frequencies

available

simultaneously

based

on

the

PDHSEL[3

:0]

and

SDH-

SEL[3

:0]

control

words

.

There

are

several

levels

of

programming

the

PDH1-

PDH5

outputs

.

The

PDHSEL[3

:0]

control

word

can be

programmed

using

external

balls

PDHSEL[3

:0]

(with

mode

bits

0x81

bits

4

:3

set

to

00,

which

is

the

default

state)

or

by

programming

register

0x80

bits

15

:12

(with

mode

bits

0x81

bits

4

:3

set

to

10)

.

Additionally,

each

PDH

output

can

be

programmed

individually

using

reg-

isters

0x82

and

0x83

(with

mode

bits

0x81

bits

4

:3

set

to

01

or 11)

.

If

the

mode

for

any

PDH

output

is

set

to

Ob1110,

then

any

frequency

can be

programmed

to

the

output,

up

to

TBD

MHz,

using

the

outputs

respective

registers

in

the

range

0x40

to

0x66

.

To

program

these

registers,

please

contact

Agere

to

get

an

automated

program

that

provides

programming

instructions

based

on

the

desired

frequency

output

.

The

SDHSEL[3

:0]

control

word

can

be

programmed

using

external

balls

SDHSEL[3

:0]

or

by

programming

register

OxA1

bits

3

:0

(with

OxAO

bit

1

high

and

SDH

HW

ball

low)

.

Individual

SONET/SDH

output

syncs

and

clocks

can

also

be

enabled

or disabled

indi-

vidually

using

registers

OxA4

and

OxA5

respectively

.

Additionally,

the

CK77,

CK51,

CK38,

and

CK19

clocks

can be

aligned

such

that

either

the

positive

or

the

neg-

ative

edge

is

aligned

to

an

input

8

kHz

signal

using

reg-

ister

OxA7

(with

OXAO

bits

1

and

2

low)

.

18

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Output Clock

Specifications

(continued)

Table

11

.

SDH

Output

Clock

Selection

(SDHSEL[3

:0])

Clock/

SDHSEL[3

:0]

State

Value

and

AssociatedOutput

Signals*

Sync

Output

15 14 13 12

11

10

9 8 7 6 5 4

3

2

1

0

Name

CK622P/N Z 622

.08

622

.08

Z 622

.08

Z

622

.08

Z Z Z Z Z

Z

Z Z Z

MHz MHz MHz

MHz

PCK622P/N

Z 622

.08

Z

622

.08

Z

622

.08 0

Z

622

.08

Z Z Z

Z

Z Z Z

MHz

MHz MHz

CK155P/N[i]

155

.52

Z Z Z

155

.52

Z Z

155

.52

Z Z Z Z

Z

Z Z Z

MHz MHz MHz

CK155P/N[0]

155

.52

Z

155

.52

Z

155

.52

Z Z

155

.52

Z Z Z Z

Z

Z Z Z

MHz MHz MHz MHz

PCK155P/N[i]

155

.52

155

.52

Z Z Z

155

.52

ZZZ

155

.52

Z Z

Z

Z Z Z

MHz MHz MHz

MHz

PCK155P/N[0]

155

.52

155

.52

Z

155

.52

Z

155

.52

ZZZ

155

.52

Z Z

Z

Z Z Z

MHz MHz

MHz

CK77

Z

77

.76

Z Z Z Z Z Z Z Z

77

.76

77

.76

Z

Z Z Z

MHz MHz

MHz

CK51

51

.84

ZZZZZZZZZ

51

.84

Z

51

.84

Z Z Z

MHz MHz MHz

CK38

Z Z Z Z Z Z Z Z Z Z

38

.88

Z

38

.88

Z Z

MHz MHz

CK19

19

.44

ZZZZZZZZZ

19

.44

Z

19

.44

Z

MHz MHz

MHz

SYNC8K

Z 8

.0

kHz

Z Z Z Z Z Z Z Z 8

.0

8

.0

8

.0

8

.0

8

.0

Z

kHz

kHz kHz

t # t t

SYLVSP/N[i]

8

.0

kHz

Z 8

.0

kHz

Z

8

.0

kHz

Z Z

8

.0

kHz

Z Z Z Z

Z

Z Z Z

t # t t t t

SYLVSP/N[0]

8

.0

kHz

8

.0

kHz

8

.0

kHz

Z

8

.0

kHz

Z

8

.0

kHz

8

.0

kHz

Z Z Z Z

Z

Z Z Z

t t t t

SYPCLP/N[i]

Z

8

.0

kHz

Z

8

.0

kHz

Z 8

.0

kHz

ZZZ

8

.0

kHz

Z Z

Z

Z Z Z

t t t t $ t

SYPCLP/N[0]

I

8

.0

kHz

I

8

.0

kHz

I

Z

I

8

.0

kHz

I

Z

I

8

.0

kHz

I

Z

I

Z

I

8

.0

kHz

I

8

.0

kHz

I

Z

I

Z

I

Z

I

Z

I

Z

I

Z

*

Z

=

high

impedance

.

t

If

SYDU

=

0,

duty

cycle

=

50%

.

If

SYDU

=

1,

sync

logic

high time

equal

to

one

period

of

a 155

.52

MHz

clock

(6

.43 ns)

$

If

SYDU

=

0,

duty

cycle

=

50%

.

If

SYDU

=

1,

sync

logic

high time

equal

to

one

period

of

a

622

.08

MHz

clock

(1

.6075

ns)

Table

12

.

PDH

Output

Clock

Selection

(PDHSEL[3

:0])

Clock/

PDHSEL[3

:0]

State

Value

and

Associated

Output

Signals*

Sync

15 14 13 12

11

10

9

8765432

1 0

Output

Name

CKPDH5 2

.43

Z

1

.544

1

.544

Z Z Z 2

.43

ZZZZ

Z

Z Z

Z

MHz MHz MHz MHz

CKPDH4

1

.544

Z

2

.048

2

.048

1

.544

1

.544

Z Z Z Z Z Z

Z

Z Z

Z

MHz MHz MHz MHz MHz

CKPDH3 2

.048

Z

24

.704

24

.704

2

.048

Z

2

.048

Z

4

.096

8

.192

Z Z

Z

Z Z

Z

MHz MHz MHz MHz MHz

MHz

CKPDH2

32

.768

Z

32

.768

32

.768

Z Z Z Z Z Z

16

.384

Z

32

.768

Z Z

Z

MHz MHz MHz MHz

MHz

CKPDH1

44

.736

Z

34

.368

44

.736

ZZZZZZZ

24

.704

Z 34

.368

44

.736

Z

MHz MHz MHz MHz MHz MHz

Z=

high

impedance

.

Agere

Systems

Inc

.

19

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Jitter

Specifications

The

clock

frequencies

listed

in

Table

13

are

normally

available

at

their

respective

output

balls

under

the indicated

conditions

.

The

jitter

specifications

listed

apply

whenever

input

clock

A

is

selected

or

input

clock

B

is

selected,

as

well

as

during

any

transients

due

to

a

switching

event

between

clock

A

and

clock

B

.

The

jitter

specifications

are

met

if

the

input

clocks

comply

with

the

input

clock

stability

requirements

.

Table

13

.

Output

Clock

Jitter

Specifications

Ball

Output

Frequency

Jitter

(stnd)

Jitter

(device)

Unit

Measurement

Bandwidth

CKPDH5

2

.43

MHz

<1

.0

TBD

Ulp-p

CKPDH5

CKPDH4

1

.544

MHz

<0

.05

TBD

10

Hz-40

kHz

CKPDH4

CKPDH3

2

.048

MHz

<0

.05

TBD

Ulp-p

20

Hz-100

kHz

CKPDH3

4

.096

MHz

- - - -

CKPDH3

8

.192

MHz

- - - -

CKPDH2

16 .384

MHz

- - - -

CKPDH3

CKPDH1

24

.704

MHz

- - - -

CKPDH2

32

.768

MHz

- - - -

CKPDH1

34

.368

MHz

<0

.05

-

Ulp-p

100

Hz-800

kHz

CKPDH1

44

.736

MHz

<0

.01

<0

.10

TBD

Ulrms

Ulp-p

10

Hz-400

kHz

10

Hz-400

kHz

CK19

19

.44

MHz

- - - -

CK38

38

.88

MHz

- - - -

CK51

51

.84

MHz

<0

.01

<0

.10

TBD

Ulrms

Ulp-p

12

kHz-400

kHz

12

kHz-400

kHz

CK77

77

.76

MHz

- - - -

CK155P/N

155

.52

MHz

<0

.01

<0

.10

TBD

Ulrms

Ulp-p

12

kHz-2

MHz

12

kHz-2

MHz

PCK155P/N

155

.52

MHz

<0

.01

<0

.10

TBD

Ulrms

Ulp-p

12

kHz-2

MHz

12

kHz-2

MHz

CK622P/N

622

.08

MHz

<0

.01

<0

.10

TBD

Ulrms

Ulp-p

12

kHz-5

MHz

12

kHz-5

MHz

PCK622P/N

622

.08

MHz

<0

.01

<0

.10

TBD

Ulrms

Ulp-p

12

kHz-5

MHz

12

kHz-5

MHz

20

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Synchronization

Output

at

8

kHz

Sync

Output

(SYNC8K,

SYLVSP/N[1

:0],

SYP-

CLKP/N[1

:0])

The

TSWC03622

generates

an

output

8

kHz

synchro-

nization

signal

for

use

in

frame

and

cell

alignment

in

systems

that

require

this

capability

.

Typically,

the

out-

put

sync

is

meaningful

only

in

systems

that

distribute

8

kHz

synchronization

signals

as

the

timing

references

on

clock

A

and

clock

B

.

In

these

cases,

the

alignment

of

the

output

sync

to

the

input

sync

(8

kHz

on

clock

A

and

clock

B

inputs)

is

a

critical

aspect

of

system

syn-

chronization

.

When

higher-speed

clocks

are

distrib-

uted,

the

alignment

of

the

sync

with

respect

to

the

input

clock

becomes

arbitrary

.

Sync

outputs

can

be

config-

ured

along

with

the

SONET/SDH

clock

outputs

with

the

SDHSEL[3

:0]

control

word

.

The

SDHSEL[3

:0]

control

word

can

be

programmed

using

external

balls

SDH-

SEL[3

:0]

or

by

programming

register

OxA1

bits

3

:0

(with

OxAO

bit

1

high

and

SDH_HW

ball

low)

.

Individual

SONET/SDH

output

syncs can

also

be enabled

or

dis-

abled

individually

using

register

OxA4

.

Sync

Duty

Cycle

Selection

(SYDU)

There

are

several

methods

of

controlling

the

sync

out-

put

duty

cycle

.

In

the

first

method,

the

SDHSEL[3

:0]

output

frequency

is

used

.

In

this

method,

the

duty

cycle

of

the

8

kHz

sync

signals

is

selectable as

either

50%

or

as

the

width

of

a

single

SONET

clock pulse width

.

When

the

duty

cycle

is

selected

to

be a

single

clock

pulse

width,

the

pulse width

is

determined

to

be

equal

to

one

period

of

the

highest-frequency

active

SONET

output

clock

.

The

frequencies

of

the

active

PDH

clocks

are

not

considered

.

Sync

duty

cycle

selection

can be

performed

using

external

ball

SYDU

or

by program-

ming

register

OxA2

bit

0

(with

register

OxAO

bit

2

high

and

SDH

HW

ball

low)

.

Table

14

.

Sync

Duty

Cycle

Selection

(SYDU)

SYDU

SYNC8K

Duty

Cycle

1

50%

0

High

for

one

period

of

highest-frequency

active

SON

ET

clock

output

A

secondmethod

is

used

when

the

sync

outputs

are

individually

enabled

through

register

OxA4

.

In

this

method,

pulse-width

options

remain

selectable

as

either

50%

or

as

the

width

of

a

single

SONET

clock

pulse

width

.

Pulse

widths

are

selected using

register

OxA4

in

conjunction

with

register

OxA6

.

The

last

method

is

to

adjust the

falling

edge

of

the

sync

outputs

using

register

OxB2,

which,

in

effect,

adjusts

the

duty

cycle

.

(The

rising

edge

can

be

adjusted using

the

sync

offset

programming

explained

below

.)

Sync

Alignment

When

8

kHz

synchronization

signals

are

applied

as

input

timing

on

clock

A

and

clock

B,

the output

sync

is

phase

aligned

to

the

input

sync

to

.

Adjustments

of

this

delay

may

be

made

using

the

TSWC03622

sync

offset

programmability

feature

.

Offset

Programming

(SYOFF[9

:0],

SYOFF-

POS)

Some

system

applications

require

the

8

kHz

synchroni-

zation

to

be

offset

according

to

the

demands

of

the

sys-

tem

architecture

.

The

TSWC03622

provides

the

capability

of offsetting

the

output

sync

in

increments

of

1

.6075

ns

(one

622

.08

MHz

clock)

.

The

sync

offset

will

apply

to

all

output

syncs

(SYN8K,

SYLVSP/N[1

:0],

SYPCLP/N[1

:0])

simultaneously

.

There

are

two

types

of offset

capability

on

the

TSWC

.

The

first

has

to

capability

to offset

up

to ±1

.644

ps

with

a

resolution

of

1

.6075

ns

(±1023

periods

of a

622

.08

MHz

clock

with

a

resolution

of

one

period

of

the

622

.08

MHz

clock)

.

This

offset

can be performed

using

external

balls

SYOFF[9

:0]

and

SYOFFPOS

or

by

pro-

gramming

register

OxA3

bits

10

:0

(with

register

OxAO

bit

3

high

and

SDH

HW

ball

low)

.

Programming

of

the

sync

offset

is

described

in

Table

15

.

Agere

Systems

Inc

.

21

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Synchronization

Output

at

8

kHz

(continued)

Table

15

.

SYNC

Offset

Programming

Ball

Function

SYOFF[9

:0]

Sets

the

magnitude

of

the

sync

offset

value

in

increments

of

1/622

.08

MHz

or

1

.6075

ns

:

SYOFF[9

:0]

=

0000000000

equals

zero

offset

.

SYOFF[9

:0]

=

1111111111

equals

1

.644

ps

(1023/622

.08

MHz)

offset

.

SYOFFPOS

Sets

the

sign

or

direction

of

the

sync

offset

:

SYOFFPOS

=

1 is

a

positive

offset

.

The

output

sync

is

delayed

in

time

.

SYOFFPOS

=

0

is

a

negative

offset

.

The

output

sync

is

advanced

in

time

.

The

second

type

of

sync

offset

is

an

enhanced

capability

that

enables

the

sync

to

be

offset

over

the

entire

125

ps

period

(in

the

same

increments

of

1

.6075

ns)

.

This

is

accomplished

using

16

bits

of offset

and

a

positive/negative

directional

control

.

This

functionality

is

available

by

programming

registers

OxA8

and

OxA9

(with register

OxAO

bit

3

low

and

SDH

HW

ball

low)

.

The

programming

is

similar to

the

first

offset

type

and

is

shown

in

Figure

16

.

Note

that

there

is

a

limit

to

the

size

of

the

offset

so

that

the

offset

is

not

greater

than

one 125

ps

period

.

Table

16

.

Enhanced

SYNC

Offset

Programming

Ball

Function

SYOFF[16

:0]

Sets

the

magnitude

of

the

sync

offset

value

in

increments

of

1/622

.08

MHz

or

1

.6075

ns

:

SYOFF[16

:0]

=

0

0000 0000 0000 0000

equals

zero

offset

.

SYOFF[16

:0]

=

1

0010

1111

0110

0000

equals

125 ps

(77760/622

.08

MHz)

offset

.

SYOFFPOS

Sets

the

sign

or

direction

of

the

sync

offset

:

SYOFFPOS

=

1 is

a

positive

offset

.

The

output

sync

is

delayed

in

time

.

SYOFFPOS

=

0

is

a

negative

offset

.

The

output

sync

is

advanced

in

time

.

22

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Skew

Specifications

PCK622P/N

SYPCLP/N

[ 1

:0]

2364

(F)

Figure

7

.

PECL

Sync

to

PECL

Clock

Skew

Case

:

Syncs

Aligned

to

622

MHz

Clock

Table

17

.

PECL

Sync

to

PECL

Clock

Skew

Parameters

(Single

Clock

Pulse

Sync

Output

Shown)

Applicable

Symbol

Skew

Parameter Min

Max

Typ

Unit

Balls

PCK622P/N

t100

Clock

falling

to

sync

rising

0 0

.5

-

ns

SYPCLP/N[1

:0]

PCK622P/N

t101/t103

Clock

duty

cycle

45

55

50

PCK622P/N

t102

Clock

falling

to

sync

falling

0 0

.5

-

ns

SYPCLP/N[1

:0]

Agere

Systems

Inc

.

23

i

tiol

t103

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Skew

Specifications

(continued)

tzoo

tzoz

PCK155P/N

[0]

SYPCLP/N

[0]

tzo1

tzos

tz~o

tz~z

PCK155P/N[i

]

SYPCLP/N[i

]

tzl

tz~s

2365

(F)

Figure 8

.

PECL

Sync

to

PECL

Clock

Skew

Case

:

Sync

Aligned

to

155

MHz

Clock

Table

18

.

PECL

Sync

to

PECL

Clock

Skew

Parameters

(Single

Clock

Pulse

Sync

Output

Shown)

Applicable

Symbol

Skew

Parameter Min

Max

Typ

Unit

Balls

PCK155P/N[0]

t200

Clock

Falling to

Sync

Rising

-1

.0

0

-

ns

SYPCLP/N[0]

PCK155P/N[0]

t201/t203

Clock Duty

Cycle

45 55 50

PCK155P/N[0]

t202

Clock

Falling to

Sync

Falling

-1

.0

0

-

ns

SYPCLP/N[0]

PCK155P/N[1

]

t210

Clock

Falling to

Sync

Rising

-1

.0

0

-

ns

SYPCLP/N[1

]

PCK155P/N[l]

t211/t213 Clock Duty

Cycle

45 55 50

PCK155P/N[1

]

t212

Clock

Falling to

Sync

Falling

-1

.0

0

-

ns

SYPCLP/N[1

]

24

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Skew

Specifications

(continued)

CK622P/N

SYLVSP/N

[1

:0]

2366

(F)

Figure 9

.

LVDS

Sync

to

LVDS

Clock

Skew

Case

:

Sync

Aligned

to

622

MHz

Clock

Table

19

.

LVDS

Sync

to

LVDS

Clock

Skew

Parameters

(Single

Clock Pulse

Sync

Output

Shown)

Applicable

Symbol

Skew

Parameter Min

Max

Typ

Unit

Balls

CK622P/N

t300

Clock

Falling

to

Sync

Rising

0

.5

-

ns

SYLVSP/N[1

:0]

CK622P/N

t301

/t303

Clock

Duty

Cycle

45

55

50

CK622P/N

t302

Clock

Falling

to

Sync

Falling

0

.5

-

ns

SYLVSP/N[1

:0]

Agere

Systems

Inc

.

25

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Skew

Specifications

(continued)

taoo taoz

CK

155P/N

[0]

SYLVSP/N

[0]

tao1

taos

taro ta~z

CK155P/N[i]

SYLVSP/N[i]

-

-------------------------------------------

ta>>

tags

2367

(F)

Figure

10

.

LVDS

Sync

to

LVDS

Clock

Skew

Case

:

Sync

Aligned

to

155

MHz

Clock

Table

20

.

LVDS

Sync

to

LVDS

Clock

Skew

Parameters

(Single

Clock Pulse

Sync

Output

Shown)

Applicable

Symbol

Skew

Parameter Min

Max

Typ

Unit

Balls

CK155P/N[0]

t400

Clock

Falling to

Sync

Rising

-1

.0

0

-

ns

SYLVSP/N[0]

CK155P/N[0]

t401/t403

Clock Duty

Cycle

45 55 50

CK155P/N[0]

t402

Clock

Falling to

Sync

Falling

-1

.0

0

-

ns

SYLVSP/N[0]

CK155P/N[1]

t410

Clock

Falling to

Sync

Rising

-1

.0

0

-

ns

SYLVSP/N[1

]

CK155P/N[1]

t411/t413 Clock Duty

Cycle

45 55 50

CK155P/N[1]

t412

Clock

Falling to

Sync

Falling

-1

.0

0

-

ns

SYLVSP/N[1

]

26

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Skew

Specifications

(continued)

~

;

t500

;~

I I I

CK19,CK38,

I I I

CK51,

CK77

I I II

I I

I I II

I I

1502

:

-III*-

I

II

I

SYNC8K

I

III

I I

III

I

t

'I

I

1503

I

Figure

11

.

CMOS

Sync

to

CMOS

Clock

Skew

Case

:

Sync

Aligned

to

622

MHz

Clock

Table

21

.

CMOS

Sync

to

CMOS

Clock

Skew

Parameters

(15

pF,

50

52)

(Single

Clock

Pulse

Sync

Output

Shown)

Applicable

Symbol

Skew

Parameter Min

Max

Typ

Unit

Balls

CK19,

CK38,

t500

Clock

Falling

to

Sync

Ris-

-

ns

CK51,

CK77,

ing

SYNC8K

CK19,

CK38,

t501

/t503

Clock

Duty

Cycle

CK51,

CK77

CK19,

CK38,

t502

Sync

Rising

to

Clock

Rising

-

ns

CK51,

CK77,

SYNC8K

Agere

Systems

Inc

.

27

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Output

Specifications

During

Phase-Locked

Condition

(Nontransient Condition)

Maximum

Time

Interval

Error

(MTIE)

Specifications

During

the

phase-locked

condition,

the

TSWC03622

output

clocks

will

meet

wander

generation

as

given

in

Table

22

and

shown

in

Figure

12

.

When

in

the locked

condition,

the

MTIE

performance

will

be

dominated

by

the

MTIE

of

the

incoming

timing

signals

on

clock

A

and

clock

B

.

The

TSWC03622

will

not

add

significantly

to

the

MTIE

performance

.

Table 22

.

Wander

Generation

(Nontransient)-MTIE

Observation

Interval

(s)

TSWC03622

(ns)

GR-253-CORE

Figure

5-17

(9/2000)

(ns)

GR-1244-CORE

Figure

5-2

(6/95)

(ns)

ITU-T

G

.813

Option

2

Table 4

(8/96)

(ns)

S <

0

.1

NA NA NA NA

0

.1

<

S

<

1

.0

TBD

20

40 20

1

<S<10

TBD

20XS0

.48

40XS0

.40

20XS0

.48

10 <

S

< 100

TBD

60

100 60

100 <

S

<

1000

TBD

-

100 60

S

>

1000

I

-

I

-

I

100

I

-

1000

100

GR-1244

CORE

ITU-T

G

.813

OPTION

2

GR-253

CORE

10

100

1000

10L_

0

.1

OBSERVATION

INTERVAL

(s)

2368

(F)

Figure

12

.

MTIE

Wander

Generation

in

Locked

Condition

28

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

Output

Specifications

During

Phase-Locked

Condition

(Nontransient Condition)

(continued)

1000

c

w

100

10

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

GR-253-CORE/ITU-T

G

.183

Opt

2

MTIE

Requirement

0

.

0

.01

0

.10

1

.00

10

.00

100

.00

Time

(sec)

Figure

13

.

Measured

MTIE

Wander

Generation

Performance

1000

.00

Agere

Systems

Inc

.

29

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Output

Specifications

During

Phase-Locked

Condition

(Nontransient Condition)

(continued)

Time

Deviation

(TDEV)

Specifications

During the

phase-locked

condition,

the

TSWC03622

output clocks

will

meet

TDEV

as

given

in

Table

23

and

shown

in

Figure

14

.

When

in

the

locked

condition,

the

TDEV

performance

will

be

dominated

by

the

incoming

timing

sig-

nals

on

clock

A

and

clock

B

and

the

TSWC03622

will

not

add

significantly

to

the

TDEV

performance

.

Table

23

.

Wander

Generation

(Nontransient)-TDEV

Integration

Interval

TSWC03622

GR-253-CORE

GR-1244-CORE

ITU-T

(s)

(ns)

Figure

5-18 Figure

5-1

G

.813

Option

2

(9/2000)

(6/95)

Table 5

(ns) (ns)

(8/96)

(ns)

0

.1

<ti<2

.5

TBD

3

.2xti-0

.5

3

.2xti-0

.5

3

.2xti-0

.5

2

.5<ti<40

TBD

2 2 2

40<ti<1000

TBD

0.32xti0

.5

0

.32xti0

.5

0

.32xti0

.5

ti

> 1000

TBD

10

-

1000

<

ti

<

10,000

I

TBD

I

-

I

-

I

10

100

10

w

0

F-

ITU-T

G

.813

OPTION

2

MT

1

11111111

1

NIIfl

GR-253

CORE

AND

GR-1244

CORE

0

.1

1

10

100

1000

OBSERVATION

INTERVAL

(s)

10000

2369

(F)

Figure 14

.

Wander

Generation

in

Locked

Condition

30

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Output

Specifications

During

Transient

Condition

Maximum

Time

Interval

Error

(MTIE)

Specifications

During

the transient

condition,

the

TSWC03622

output clocks

will

meet

wander

generation

as

given

in

Table

24

and

shown

in

Figure

15

.

Table

24

.

Wander

Generation

(Transient)-MTIE

Observation

TSWC03622

GR-253-CORE GR-1244-CORE

ITU-T

Interval

(ns)

Figure

5-19

R5-10

G

.813

Option

2

(s)

(9/2000)

(6/95)*

Table

14

(ns) (ns)

(8/96)

(ns)

ti

<

0

.014

NA NA

1000

NA

0

.014

<,r

<

0 .16

TBD

7

.6

+

885ti

1000

7

.6

+

885ti

0

.16 <,r

<

0

.5

TBD

7

.6

+

885ti

1000

7

.6

+

885ti

0

.5

<,r

< 2

.33

TBD

300

+

300ti

1000

300

+

300ti

2 .33 <,r

<

280

I

TBD

I

1000

I

1000

I

1000

*

Requirement

5-10

also

indicates

that

the

maximum

phase

slope

or

discontinuity

be

less

than

81

ns

for

any

measurement

period

of

1

.326

ms

.

10000

GR-1244

CORE

1000

w

100

10

L-

0

.01

0

.1 1

10

OBSERVATION

INTERVAL

(s)

ITU-T

G

.813

OPTION

2

AND

GR-253

CORE

Figure

15

.

MTIE

Wander

Generation

During

Transient

Condition

100

1000

2370

(F)

Agere

Systems

Inc

.

31

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Output

Specifications

During

Transient

Condition

(continued)

1000

100

w

10

GR-253-CORE

FIGURE

5-19

(1/99)

\A0

>_

250

ns

A0-

10ns

0

.01

0

.10

TIME

(s)

Figure 16

.

MeasuredMTIE

Performance

at

Two

Different

Phase

Offsets

1

.00

32

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Other

Input

andPLL

Specifications

Input

Clock

Maximum

Rate

of

Phase

Change

During

Transient

In

order

for

the

TSWC03622

to

guarantee

functionality

and

that

all

transient

MTIE

specifications

are

met,

the

clock

A

and

clock

B

inputs

musthave

an

instantaneous

maximum

rate of

change

consistent

with

the

ITU

G

.812

requirements

for

a

node

clock

and

Telcordia

GR-253-

CORE

Section

5

.4 .4 .2

(Issue

3,

9/2000)

.

External

38

.88

MHz

VCXO

Requirements

The

following

is

a

brief

specification

for

the

38

.88

MHz

VCXO

unit

:

.

Supply

voltage

:

3

.30

V

±

5%

.

Control

voltage

range

:

0

.3

V

minimum,

2

.7

V

maxi-

mum

.

Temperature

range

(ambient)

:

-40

°C

to

+85

°C

.

Output

buffer

:

-

Technology

:

CMOS

(3

.30

V)

-

Duty

cycle

:

45/55%

-

Transient

times

:

1

ns

maximum

(20%

to

80%)

.

Frequency

(nominal)

:

38

.88

MHz

.

APR

:

± 20

ppm

Note

:

The

APR

must

include

the

effects

of

tempera-

ture,

supply

voltage,

shock,

vibration,

aging,

and

manufacturing

(i

.e

.,

withstanding

two

solder

ref

lows)

.

Linearity

:

±20%

(best

linear

fit

0

.3

V

to

2

.7

V)

.

Transfer

function

:

monotonic,

positive

slope

.

Center

voltage

:

VDD/2

(nominal

1

.65

V)

.

Modulation

bandwidth

:

10

kHz

at

38

.88

MHz

.

Input

leakage

current

:

<1

pA

.

Input

resistance

:

>3 MS2

.

Reference

signal

for

control

voltage

:

ground

.

Phase

jitter

:

1

ps

(RMS)

maximum

12

kHz

to

20

MHz

(alternate

spec

may

be

expressed

in

dBc

if

required)

.

Start-up

time

:

2

ms

at

maximum

control

voltage

Loop

Filter

Components

for

High-Speed

PLL

The

recommended

loop

filter

is

shown

in

Figure

17

.

Connect

the

filter

components

and

also

connect

LFP

to

VCP

and

connect

LFN

to

VCN

.

The

component

values

can be

varied

to

adjust the

loop

dynamic

response

.

Table

25

provides

a

set

of

recommended

values

to

meet

output

jitter

generation

requirements

in

Table

13

.

Table

25

.

High-Speed

Loop

Filter

Recommended

Values

Components

Recommended

Values

C1*

0

.1

pFor1

.0pF±10%

R1 3

.9

ktl

±

5%

*

Capacitor

C1

should

be

either

ceramic

or

nonpolar

.

LFP

VCP

C1

R1

VCN

LFN

Figure

17

.

High-Speed

Loop

Filter

Recommended

Circuit

Loop

Filter

Components

for

Low-Speed

PLL

The

recommend

loop

filter

for

phase

offsets

of

Clock

A

and

clock

B

of less

than

±30

ns

(including

all

input

fre-

quencies

for

19

.44

MHz,

38

.88

MHz,

and

51

.84

MHz)

is

shown

in

Figure 19

and

Table

26

.

If

the

phase

offset

of

clock

A

and

clock

B

is

unknown

or

will

be

greater

than

±30

ns,

then

the

recommended

filter

is

shown

in

Figure 19

and

corresponding

component

values

are

shown

in

Table

27

.

Analog

switches

are

included

in

both

circuits

to

reduce

the

lock

time

at

start-up

.

This

part of

the

circuitry

is

only

active

when

the

LSPLL

is

out

of lock,

it

will

not

become

active

during

a

clock

switch

.

In

the

filter

for

smaller

phase

offsets,

the

addition

of

the

analog

switch

will

reduce

the

nominal

lock

time

from

tens

of

seconds

to

less

than

6

seconds

.

In

the

filter

for

larger

phase

off-

sets,

the

nominal

lock

time

is

reduced

from

a few

min-

utes

to

less

than

40

seconds

.

Agere

Systems

Inc

.

33

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Other

Input

andPLL

Specifications

(continued)

Table

26

.

Low-SpeedLoop

Filter

Recommended

Values

for

Smaller

Phase

Offsets

Components

Recommended

Values

C1

*

10

pF

±

20%

C2*

4

.7

pF

±

10%

R1

392

ktl

±

1

%

(390

ktl

±

5%)

R2

1

.21

ktl ±

1

%

(1

.2

ktl

±

5%)

R3

20

ktl to

110k52

±

5%

(lower

value

yields faster

lock

time)

U1 Analog

switch

VCX01

See

VCXO

requirements

.

*

Capacitors

C1

and

C2

should

be

either

ceramic

or

nonpolar

.

t

1

%

resistors

are

recommended

for

R1

and

R2,

since

the

low-

speed

PLL

filter

has

high

sensitivity

to

these

resistors

.

However,

if

these

1

%

resistors

are not

available,

the

5%

resisters

indicated

in

parentheses

are

compatible

and

will

make

the

loop

filter

function

correctly

.

$

Contact

factory

for

information

on Analog

Switch requirements

.

R1

LFO

0

:

U1

INT5

LSVCO

0-

Figure

18

.

Low-Speed

Phase-Lock

Loop

(LSPLL)

Filter

Recommended

Circuit

for

Smaller

Phase

Offsets

Table

27

.

Low-SpeedLoop

Filter

Recommended

Values

for

all

Phase

Offsets

Components

Recommended

Values

for

All

Clock

A

and

Clock

B

Phase

Offsets

(See

Figure

19

.)

C1

1000

pF

±

10%

C2

47

pF

±

20%

C3

47

pF

±

20%

C4

4

.7

pF

±

20%

C5

4

.7

pF

±

20%

R1

*

4

.99

ktl ±

1

%

(5

.1

ktl ±

5%)

R2* 2

.49

ktl ±

1

%

(2 .4 ktl ±

5%)

R3*

750

ktl

±

1

%

(750

ktl

±

5%)

R4

20

ktl

±

5%

R5

10

ktl

±

5%

R6* 2

.21

ktl ±

1

%

(2

.2

ktl

±

5%)

R7*

383

ktl

±

1

%

(390

kn

±

5%)

R8*

110

kn

±

5%

U1

Analog

switch

VCX01

See

VCXO

requirements

.

*

1

%

resistors

are

recommended

for

R1,

R2,

R3

and

R6,

since

the

low-speed

PLL

filter

has

high

sensitivity

to

these

resistors

.

How-

ever,

if

these

1

%

resistors

are

not

available,

the

5%

resisters

indi-

cated

in

parentheses

are

compatible

and

will

make

the

loop

filter

function

correctly

.

t

Contact

factory

for

information

on Analog

Switch requirements

Vc

RF

OUT

LFO

LFOZ

INT5

LSVCO

VCX01

F

UT

Figure

19

.

Low-Speed

Phase-Lock

Loop

(LSPLL)

Filter

Recommended

Circuit

for

all

Phase

Offsets

34

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

INLOSN

The

INLOSN

signal

will

force

the

high-speed

PLL

to

drift

towards

a

lower

clamped

frequency,

preventing

an

excessive

high-frequency clock

output

under

invalid

input

signal

conditions

.

INLOSNmay

be used

to

limit

the

internal

clock

frequency

ensuring

proper

state

machine

and

control

behavior

under severe

clock

fault

conditions

.

RREF

should

be

tied

to

VDDLVDS

through

a

1

.5

ktl

resistor

.

Clock

Switching

State

Machine

and

Software

Interface

More

complete documentation

of

state

machine

behav-

ior

and

software

interfacing

requirements

is in

prepara-

tion

.

Only a

minimal

description

of

behavioral

characteristics

is

included

here

.

Clock

Switching

State

Machine

Behavior

The

TSWC03622

is

designed

to

perform

fast,

auto-

matic

protection

switching

between

primary

and

sec-

ondary

clock

inputs

to

the

device

.

The

clock

switching

control

circuit

implements

the

following functional

requirements

:

.

Autonomously

switch

from

the

selected

clock

to

the

other

clock

if

the

selected

clock

fails

.

Manually

switch

to

any

clock

input

.

Provide

a

lockout

control

to

prevent

excessive

auton-

omous

switching

.

Provide

an

override

to

allow

revertive

switching,

but

force

the

minimum

time

for

reversion

to

256

ms

from

the

time

the switch

was

initially

made

.

Provide

a

squelch

function

to

bring

the

device

clock

outputs

to

a

logic

low

state

(squelched)

if

clock

A,

clock

B,

and

CLKBU

signals

all

have

a

fault

.

Operation

The

operation

of

the

clock

protection

switching

control

circuit

depends

on

the device

inputs

and

internally

gen-

erated

control

signals

.

This

control

is

performed by

a

finite

state

machine

containing three

states,

and

there

are

two

modes

of

operation

:

autonomous

switching

(circuit

makes

decision

on

what

action

to

take)

and

nonautonomous

switching

(external controller

makes

decision

on

what

action

to

take)

.

However,

in

either

mode

of

operation, the

control

circuit

will

enforce

a

time-out period

between

switching

events

to

allow

the

internal

phase-locked

loops

time

to

acquire

phase

lock

to

the

currently

selected

reference

clock

.

The

state

dia-

gram

of

the

control

circuit

state

machine

is

shown

in

Figure

20

.

2371

(F)

Figure

20

.

Clock

Protection

Control

Circuit

State

Diagram

Agere

Systems

Inc

.

35

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Clock

Switching

State

Machine

and

Software

Interface

(continued)

The

device

will

select

the reference

clocks

based

upon

the

internal

state

:

reference

A

if

in

state

A,

reference

B

if

in

state

B,

and

reference

BU

if

in

state

BU

.

The

autonomous

mode

of

operation

is

selected

by

setting

the

device

signal

AUTOSWN

to

a

logic

low

.

In

this

mode,

after

the

initial

reset

of

the

device,

the

state

machine

is

in

state

A

selecting

reference

clock

A

.

If

the

internal loss of

clock

detector

on

clock

A

indicates

the

absence

of

clock

A,

the

initial

clock

reference

selected

depends

on

the

condition

of

the

SELCLK,

SELBUN,

and

ENSQLN

device

signals

and

the

status

of

the

inter-

nal

loss

of

clock

detectors

for

clock

B

and

clock

BU

.

If

the

user

selects

clock

BU

as

the

wanted

reference,

the

state

machine

will

check

the

status

of

clock

BU

.

If it

is

present,

the device

will

switch

to

the

back-up

reference

for

the

initial

phase-lock

.

However,

if

the

backup

refer-

ence

is

absent,

the device

will

check

the

status

of

refer-

ence

B,

and

if

B

is

present,

it

will

switch

to

reference

B

to

initially

phase-lock

to,

and

if

the

user

selected

clock

B

as

the

desired

reference,

the device

would

check

the

status

of

the

reference

B

loss

of

clock

detector

.

If

clock

B

is

present,

the device

will

switch

to

reference

B

for

initial

phase-lock,

and

if

clock

B

is

absent,

the

device

would check

for

clock

BU

.

If

no

reference

is

present

and

the

ENSQLN

signal

is

low,

the

device

will

select

the

reference desired

as determined by

the

SELCLK

and

SELBUN

signals

and

will

force

the

output

clock

and

sync

signals

to a logic

low

level

.

Upon

selecting

a

reference

clock

to

initially

lock

to

(defaults

to

reference

A)

and

if

the

clock

is

present,

the

state

machine

ini-

tiates

a

time-out period

to

allow

the

device

to

phase-

lock

to

the

selected

reference

clock

.

While

waiting

for

the

time-out

period,

the

device

will

activate

the

switch

in

progress

interrupt,

indicate

if

the

selected

reference

agrees

with

the

wanted

reference

on

the

consistent

interrupt,

and

output

the

selected

reference

on

the

SWSTATE

signals

.

After

the

initial

start-up

of

the

clock

protection

switch

control

circuit,

the

state

machine

will

monitor

the

SELCLK

and

SELBUN

signals

and

the

internal

loss

of

clock

flags

.

If

the

user

initially

wants a

reference

other

that

which

is

selected,

the

state

machine

will

check

the

status

of

the

desired

reference,

and

it

will

switch

to

the

desired reference

if it

is

present

.

This

will

then

initiate

a

new

time-out period

to

allow

the

new

reference

to

phase-lock

.

The

circuit

will

prioritize

clocks

A

and

B

over

clock

BU

such

that

if

B

is

selected

and

disap-

pears,

A

is

checked

first

for

switching

before

deciding

to

switch

to

clock

BU

.

If

the

selected

clock

disappears,

the

state

machine

will

autonomously

switch

to

another

reference

that

is

present

.

If

the

REVERTN

signal

is

low,

the

state

machine

will

automatically

return

to

the

originally

selected

reference

after

the

time-out period

has

expired

.

This

could

cause

an

oscillation

between

refer-

ences,

and

to

limit

the length

of

this

oscillation,

the

state

machine

has a

counter

to

count

the

number

of

transitions

between

references

.

If

the

ENLON

signal

is

low,

the

state

machine

will

allow

3

transitions

to

occur

before

prohibiting

further

switching

.

To

resume

switch-

ing,

the

internal

transition

counter

is

cleared

by

pulsing

the

LORSTN

signal

low

.

This allows

external

control

of

the

time

period

monitored

by

the

transition

counter

.

The

nonautonomous

mode

is

selected

by

forcing

the

AUTOSWN

signal

high

or

a

no-connection

on

this sig-

nal

.

The

start-up

condition

causes

the device

to

initially

be

selecting

reference

A

.

If

A

is

absent,

the device

checks

the

reference desired

(reference

selected

by

SELCLK

and

SELBUN

signals)

for

presence,

and

if it

is

present,

the

device immediately

switches

to

this

refer-

ence

.

If

the

desired reference

is

absent,

the device

will

look

at

the

ENSQLN

signal

for

direction

.

If

ENSQLN

is

low,

the

state

machine

will

select the

desired

reference

and

squelch

the

output

clock

and

sync

signals,

and

if

ENSQLN

is

high or

not-connected,

the

state

machine

will

remain

in

the

state

selecting

reference

A

.

If

refer-

ence

A

is

present,

the

state

machine

will

initiate

the

time-out

period,

and

on

the

expiration

of

the

time-out

period,

it

will

check

for

the

presence

of

the

desired

clock

.

If

the

desired

clock

is

present,

the

device

will

switch

to

the

desired

clock

and

initiate

another

time-out

period

.

If

the

desired

clock

is

absent,

the

state

machine

will

remain

in

state

A,

and

the

state

consistency

inter-

rupt

will

be

active

.

After

the

initial

start-up

of

the

device,

the

clock

protec-

tion

switch

control

circuit

will

monitor

the

SELCLK,

SELBUN,

and

ENSQLN

signals

and

the

loss

of

clock

interrupts

for

changes

.

If

the

loss

of

clock

interrupt

on

the

currently

selected

reference

goes

active,

the device

will

either

do

nothing

or

squelch

the output

clock

and

sync

signals

depending

on

the

ENSQLN

condition

.

If

ENSQLN

is

low,

the

device

output

clock

and

sync

sig-

nals

will

be

forced

low

.

If

the

desired

clock

reference

changes

and

the

time-out period

has

expired,

the

state

machine

will

check

the status

of

the

desired reference

loss

of

clock

interrupt

.

If

the

interrupt

is

low,

the

state

machine

will

switch

to

the

desired reference

and

initiate

another

time-out period

.

36

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Clock

Switching

State

Machine

and

Software

Interface

(continued)

Because

there

are

times

when

a

switch

to a

faulty

(absent)

reference

is

desired,

the

state

machine

has an

override

in

the

form

of

the

SWCONTN

signal

.

When-

ever

the

SWCONTN

signal

is

low,

all

fault

checking

done

prior to

a

switch

is

ignored

; i

.e

.,

the device

will

unconditionally

switch

to

the reference

desired

on

SELCLK

and

SELBUN

.

This override

also

allows

the

user

to

squelch

the

output

clock

and

sync

signals

man-

ually

by

bringing

the

ENSQLN

signal

low

.

There

are

three

interrupts

generated

by

the

clock

pro-

tection

switch

circuit

:

clock

switch

in

progress,

user

selected

clock

is

not

consistent

with

the

internal

clock

selection,

and

a

lockout

condition

exists

due

to

exces-

sive

number

of

switching

events

.

The

clock

switch

in

progress

interrupt

is

active

whenever

a

switching

event

occurs,

and

it

will

remain

active

until

the

time-out

period

after

the actual

switch

expires

.

The

consistency

interrupt

is

active

whenever

the

internal

clock

selection

disagrees

with

the

user

desired

selection

.

If

a

switch

request

comes

from

an

external

source

through

the

SELCLK

and

SELBUN

signals

before

the

internal

time-

out

period

has

expired,

then

a

consistency

interrupt

will

be generated

.

This

can be

prevented

by

monitoring

the

clock

switch

in

progress

interrupt

.

If

the

desired

clock

reference

is

absent,

the

consistency

interrupt

will

be

generated,

and

if

the

state

machine

has

locked

out

fur-

ther

switching events,

the

consistency

interrupt

will

be

generated

.

The

lock-out

interrupt

is

generated

when-

ever

the

number

of

switching

events

exceed

3

clock

switches

.

The

time

period

for

this

count

is

controlled

externally

by

the

period

between

pulses

on

the

LORSTN

signal

.

Software

Interfacing

The

clock

protection

switching

circuit

is

configured

by

an

external

controller

via

software

.

Whenever

interac-

tion

with

this

software

is

needed,

the following

guide-

lines

should

be

followed

:

.

The

software

must

provision

the

device

as

desired,

appropriately

setting

SELCLK,

SELBUN,

AUTOSWN,

REVERTN,

SWCONTN,

ENSQLN,

and

ENLON

upon powerup

and

after

the

initial

reset

com-

pletes

.

The

external

controller

may

either

use

an

active

edge

of

one

of

the

interrupts

or

a

polling

method

(monitoring

SWSTATE[1

:0],

INT[8

:0])

to

determine

the

input

clock

status

and

the

occurrence

of

an

autonomous

switch

.

Whenever

an

autonomous

switch

occurs

as

indi-

cated

by

the

SWSTATE[1

:0]

flag,

the

software

polls

the

INT[8

:0]

signals

to

determine

the

cause

of

switching

and

validates

the

selection

.

Whenever

a

nonautonomous

fault

occurs

as

indi-

cated

by

the

INT[8

:0]

flag,

the

software

polls

the

INT[8

:0]

signals

and

selects

the

proper

action

to

per-

form

.

After validation

of

an

autonomous

switch,

the

soft-

ware

must

pulse

AUTOSWN

high

and

reinitialize

the

clock

selection

inputs

SELCLK

and

SELBU

to

match

the

SWSTATE[1

:0]

output

signals

.

If

a

lockout occurs,

the

software

must

pulse

LORSTN

low

to

clear

the

lockout

.

Loss

of

Clock

Criteria

Loss

of

clock

detectors continuously monitor

the

condi-

tion

of

clock

A,

clock

B,

and

CLKBU

.

A

loss

of

clock

condition

is

declared

when

transitions

are

absent

on

the

clock

input

for

between

2 and 4

periods

of

the

input

frequency

.

Agere

Systems

Inc

.

37

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Clock

Switching

State

Machine

and

Software

Interface

(continued)

Interrupt

Generation

(INT[8

:0])

Interrupts

are available

on

external

balls

INT[8

:0]

and

via

the

serial

interface

in

register

OxEO

.

Table

28

defines

the

conditions

under which

interrupts

are

generated

for

the

external

balls

INT[8

:0]

.

All

of

these

interrupts

are

available

in

register

OxEO

with

the

addition

of

another

interrupt that

indicates

when

squelch

is

active

or

inactive

.

Table

28

.

Interrupt

Generation

(INT[8

:0])

Active-High

INT Condition

8

Lockout

condition

exists

due

to

excessive

number

of

switching

events

7 User

selected

clock

not

consistent

with

internal

clock

selection

state

6 Loss

of

lock-high-speed

PLL

5 Loss

of

lock-38

.88

MHz

PLL

4 Clock

switch

in

progress

3 Loss

of

external

VCXO

clock

2 Loss

of

CLKBU

1

Loss

of

CLKB

0

I

Loss

of

CLKA

Interrupts

4

and

7

are not

meant

to

be

alarms,

but

more

of

a

status

report

.

INT4

indicates

that

a

switch

between

any

of

the clocks

is

occuring

.

INT7

indicates

to

the

user

that

the

active

clock

is

the not

the

clock

that

the

user

has

selected

.

For

example,

in

autonomous

mode,

the

default

selected

state

is

clock

A

(cannot

be

changed),

so

if

clock

A

is

not

present

and

clock

B

or

BU

is

the

working

clock,

INT7

will

be

active

.

Another

example

is

in

manual

mode

with

SWCONTN

active

(SWCONTN

active

prevents

a

bad

clock

from be

switched

to),

if

the

user

selects

a

clock

that

is

not

present

(and

the

original

clock

is

still

present),

the

TSWC

will

not

go

to

that

clock

;

thus

the

selected clock

is

not

consistent

with

the

internal

clock

selection state

.

38

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

TSWC03622

SONET/SDH/PDH/ATM

May

2002

Clock

Synthesizer

and

Protection

Switch

Serial

Interface

and

Internal

Bus

The

TSWC

internal

registers

can be

programmed

via a

serial

interface

.

This

serial

interface

allows

reading

or

writ-

ing

any

of

the

registers

.

Internally,

the

TSWC

uses two

different lines to

transmit

and

receive

data

from

the

outside

.

Those

two

lines

must

be

multiplexed

by an

input/output

buffer

to

the

single

serial

line

(simplex

communication)

.

The

serial

line

will

be

driven

by

the

external

controller

except

when

a

read

process

is

requested

.

In

that

case,

the

TSWC

will

drive

the

line

during

the

time

it

needs

to

transmit

the

requested data

.

During

a

period

when

no

read

nor

write

process

is

requested,

SERDAT

is

pulled

internally

to

a

CIVIOS

logic

high

.

As

shown

on

Figure

21,

there

are

three

external

pins related

to

the

serial

interface

:

the

serial

interface

clock

SERCLK,

the

serial

interface

data

line

SERDAT

and

the

serial

interface

enable

SERENBLN

.

r

-------

-

------------

-

------

_i

I

TSWC03622

I

I I

I

SERDAT

OUT

INTERFACE

EXTERNAL

CONTROLLER

I

CONTROLLER

I

IN

I

SERCLK

II

I

SERENBLN

I

I I

I

I I

---------------------------

Figure

21

.

TSWC03622

Serial

Interface

The

serial

interface

frames

are

composed

of

32

bits

.

The

two

first

bits

are

used

to

indicate

the beginning

of

the

frame

(01)

.

Then

the

address

is

transmitted

in

the

bits,

followed

by 6

bits

indicating

if it

is

a

read

or

write

request

.

Finally

the

16

bits

of

data

are

transmitted

by

the

external

controller

(write)

or

by

the

TSWC

(read

process)

.

In

case

of

a

read

process,

the

last

17

bits

of

the

frame

are

driven

by

the

TSWC,

following

a

bit

where

no

device

is

driving

the

line,

leaving

it

in

high

impedance

.

As

soon

as

the

data

has

been

transmitted,

the

external

user

contin-

ues

to

drive

the

line

to a

high

logic

state

waiting

for

the

to

transmit

.

A

representation

of

a

WRITE

is

shown

in

Figure

22,

and

a

READ

in

Figure

23

.

The

transmission

for

both

the

data

and

address

bits

starts

with

the

most

significant

bit

.

8-bit

Address

16-bit

Data

SERDAT

0

1

A1

A A A4 A A A A8 0

n0

0

n0

Di

DDDDDDDD

o~

o>>

o~ o~ o~ o~ o~

SERCLK

SERENBLN

1

Figure

22

.

Serial

Interface

WRITE

Frame

Format

Agere

Systems

Inc

.

39

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Serial

Interface

and

Internal

Bus

(continued)

Driven

by

External

Controller

Driven

by

TSWC01622

8-bit

Address

16-bit

Data

SERDAT

0

1

A1

AAA4AAAA8

1

000

Z

0

/DiXDD3~D4~DD6~D7XD8~Do~c~o>>~o~o~o~a~o~o~~

SERCLK

SERENBLN

1

Figure

23

.

Serial

Interface

READ

Frame

Format

Timing

for

the

serial

interface

is

shown

in

Figure

24

.

It

is

suggested

that

data

be

written

to

the

TSWC03622

on

the

falling

edge

and

also

be

read

from

the

TSWC03622

on

the

falling

edge

.

1

1 1

1

SERDAT

i .

1 1 1

11 1

1

tsoz

1

1 1

^

1

I~

1

r~l

t501

1 1 1

1

SERCLK

11

1 1

1

1 1 1

1

1 I

tsm

1

1 1 1

1

1 1 1

1

tsoo

1

1 I

SERENBLN

1

1 1

tsoa

I 1

I

Figure

24

.

Serial

Interface

Timing

Table

29

.

Serial

Interface

Timing

Applicable

Symbol

Parameter

Min

Max

Typ

Unit

Balls

SERCLK

FMAX

Maximum

Serial

Interface

Clock

Frequency

-

25

-

MHz

SERENBLN

t500

Enable

to

Clock Setup

ns

SERCLK

t501

WRITE

-1

.0

ns

SERDAT

Clock

to

Data Setup

SERDAT

t502

WRITE

3

.6

ns

SERCLK

Data Hold

SERCLK

t501

READ

18 ns

SERDAT

Clock

to

Data Setup

SERDAT

t502

READ

ns

SERCLK

Data Hold

SERCLK

t503

Clock

Period

40

ns

SERCLK

t504

Enable

Hold

After

Last

Clock

ns

SERENBLN

40

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

TSWC03622

Registers

Map

summarizes

all

the

TSWC

registers

.

Table

30

.

TSWC03622

Registers

Address

Hex

TSWC03622

Block

Description

Bits

Reset

00

Control

Reset

register

.

15

:8

OxFFFF

01

Control

Serial

interface

or

control

.

0

OxFFFF

02-1

F

-

Not

used

.

- -

20

Clock

Input

Software

reset

and

software

override

.

1

:0

OxFFFF

21

Clock

Input

FINSEL[3

:0]

.

3

:0

Ox000F

22

Clock

Input

FBUSEL[3

:0]

.

3

:0

Ox000F

23

Clock

Input

Threshold

.

15

:0

0x0002

24

Clock

Input

For

test

purposes,

set

to

0x0002

.

15

:0

0x0002

25

Clock

Input

For

test

purposes,

set

to

0x0002

.

15

:0

0x0002

26

Clock

Input

For

test

purposes,

set

to

0x0002

.

15

:0

0x0002

27

Clock

Input

For

test

purposes,

set

to

0x0002

.

15

:0

0x0002

28

Clock

Input

For

test

purposes,

set

to

0x0003

.

15

:0

0x0003

29

Clock

Input

For

test

purposes,

set

to

0x0001

.

15

:0

0x0001

2A

Clock

Input

For

test

purposes,

set

to

0x0001

.

15

:0

0x0001

213

Clock

Input

For

test

purposes,

set

to

0x0001

.

15

:0

0x0001

2C

Clock

Input

For

test

purposes,

set

to

0x0001

.

15

:0

0x0001

2D

Clock

Input

For

test

purposes,

set

to

0x0001

.

15

:0

0x0001

2E

Clock

Input

Hysteresis

.

15

:0

0x0004

2F

-

Not

used

.

- -

30

Sw

.

State

Mach

Software

reset

and

software

override

.

8

:0

OxFFFF

31

Sw

.

State

Mach

Ensqln,

lorstn,

enlon,

swcontn,

revertn,

autoswn,

selbun,

selclk

7

:0

Ox00FF

32

Sw

.

State

Mach LOCNT-Lock-out

counter

.

15

:0

0x0003

33

Sw

.

State

Mach

TOCNT-Time-out

counter

.

15

:0

0x0800

34

Sw

.

State

Mach

IFREO-Divide

by

19440

counter

.

15

:0

Ox4BEF

35-3F

-

Not

Used

.

- -

40

PDH

Outputs

Programmable

output

variable

RO

for

channel

1

.

9

:0

0x0000

41

PDH

Outputs

Programmable

output

variable

R1

for

channel

1

.

9

:0

0x0000

42

PDH

Outputs

Programmable

output

variable

R2

for

channel

1

.

9

:0

0x0000

43

PDH

Outputs

Programmable

output

variable

R3

for

channel

1

.

9

:0

0x0000

44

PDH

Outputs

Programmable

output

variable

R4

for

channel

1

.

9

:0

0x0000

45

PDH

Outputs

Programmable

output

variable

R5

for

channel

1

.

9

:0

0x0000

46

PDH

Outputs

Programmable

output

variable

R6

for

channel

1

.

2

:0

0x0000

47

-

Not

used

.

- -

48

PDH

Outputs

Programmable

output

variable

RO

for

channel

2

.

9

:0

0x0000

49

PDH

Outputs

Programmable

output

variable

R1

for

channel

2

.

9

:0

0x0000

4A

PDH

Outputs

Programmable

output

variable

R2

for

channel

2

.

9

:0

0x0000

413

PDH

Outputs

Programmable

output

variable

R3

for

channel

2

.

9

:0

0x0000

4C

PDH

Outputs

Programmable

output

variable

R4

for

channel

2

.

9

:0

0x0000

4D

PDH

Outputs

Programmable

output

variable

R5

for

channel 2

.

9

:0

0x0000

4E

I

PDH

Outputs

I

Programmable

output

variable

R6

for

channel

2

.

I

2

:0

I

0x0000

Agere

Systems

Inc

.

41

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

TSWC03622

Registers

Map

(continued)

Table

30

.

TSWC03622

Registers

(continued)

Address

Hex

TSWC03622

Block

Description

Bits

Reset

4F

-

Not

used

.

- -

50

PDH

Outputs

Programmable

output

variable

RO

for

channel 3

.

9

:0

0x0000

51

PDH

Outputs

Programmable

output

variable

R1

for

channel 3

.

9

:0

0x0000

52

PDH

Outputs

Programmable

output

variable

R2

for

channel 3

.

9

:0

0x0000

53

PDH

Outputs

Programmable

output

variable

R3

for

channel 3

.

9

:0

0x0000

54

PDH

Outputs

Programmable

output

variable

R4

for

channel 3

.

9

:0

0x0000

55

PDH

Outputs

Programmable

output

variable

R5

for

channel 3

.

9

:0

0x0000

56

PDH

Outputs

Programmable

output

variable

R6

for

channel 3

.

2

:0

0x0000

57

-

Not

used

.

- -

58

PDH

Outputs

Programmable

output

variable

RO

for

channel 4

.

9

:0

0x0000

59

PDH

Outputs

Programmable

output

variable

R1

for

channel 4

.

9

:0

0x0000

5A

PDH

Outputs

Programmable

output

variable

R2

for

channel 4

.

9

:0

0x0000

513

PDH

Outputs

Programmable

output

variable

R3

for

channel 4

.

9

:0

0x0000

5C

PDH

Outputs

Programmable

output

variable

R4

for

channel 4

.

9

:0

0x0000

5D

PDH

Outputs

Programmable

output

variable

R5

for

channel 4

.

9

:0

0x0000

5E

PDH

Outputs

Programmable

output

variable

R6

for

channel 4

.

2

:0

0x0000

5F

-

Not

used

.

- -

60

PDH

Outputs

Programmable

output

variable

RO

for

channel 5

.

9

:0

0x0000

61

PDH

Outputs

Programmable

output

variable

R1

for

channel 5

.

9

:0

0x0000

62

PDH

Outputs

Programmable

output

variable

R2

for

channel 5

.

9

:0

0x0000

63

PDH

Outputs

Programmable

output

variable

R3

for

channel 5

.

9

:0

0x0000

64

PDH

Outputs

Programmable

output

variable

R4

for

channel 5

.

9

:0

0x0000

65

PDH

Outputs

Programmable

output

variable

R5

for

channel 5

.

9

:0

0x0000

66

PDH

Outputs

Programmable

output

variable

R6

for

channel 5

.

2

:0

0x0000

67-7F

-

Not

used

.

- -

80

PDH

Outputs

Mode

(PDHSEL)

and power-down

.

15

:12,0

0x0001

81

PDH

Outputs

DIV2,

CKMXSEL,

MODESEL,

and

DELAY

.

9

:0

0x0000

82

PDH

Outputs

Modes

for

CO,

C1,

C2,

and

C3

.

15

:0

0x0000

83

PDH

Outputs

Modes

for

C4,

C5,

C6,

and

C7

.

15

:12

0x0000

84

PDH

Outputs

Reserved

.

-

85

PDH

Outputs

Reserved

.

-

86-9F

-

Not

used

.

- -

AO

SDH/SYNC

Outputs Software

reset

and

overrides

.

3

:0

Ox000F

A1

SDH/SYNC

Outputs

SDHSEL

register

.

3

:0

0x0000

A2

SDH/SYNC

Outputs

Duty

cycle

register

.

0 0x0001

A3

SDH/SYNC

Outputs

Sync

offset

and

direction

.

10

:0

0x0000

A4

SDH/SYNC

Outputs

Sync

enables

.

11

:0

0x0000

42

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

TSWC03622

Registers

Map

(continued)

Table 30

.

TSWC03622

Registers

(continued)

Address

TSWC03622

Description

Bits

Reset

Hex

Block

A5

SDH/SYNC

Clockenables

.

9

:0

0x0000

Outputs

A6

SDH/SYNC

Individual

duty

cycle

changes

.

2

:0

0x0007

Outputs

A7

SDH/SYNC

Clock

edge

selection

.

3

:0

Ox000F

Outputs

A8

SDH/SYNC

Sync

offset

when

software

override

.

15

:0

0x0000

Outputs

A9

SDH/SYNC

Additional

sync

offset

when

software

override

.

1

:0

0x0000

Outputs

AA-AF

-

Not

used

.

- -

BO

SDH/SYNC

RISE[15

:0]

.

15

:0

Ox2FC0

Outputs

131

SDH/SYNC

RISE(16)

.

0 0x0001

Outputs

132

SDH/SYNC

FALL

.

15

:0

Ox97E0

Outputs

133

SDH/SYNC

DELTA

.

3

:0

0x0016

Outputs

134

SDH/SYNC

Not

used

.

-

0x0016

Outputs

135

SDH/SYNC

Not

used

.

-

0x0016

Outputs

136

SDH/SYNC

DELTARISE

.

4

:0

Ox000B

Outputs

137

-

Not

Used

.

-

0x0000

138

SDH/SYNC

For

test

purposes,

read only

.

0 0x0001

Outputs

139

SDH/SYNC

For

test

purposes,

read only

.

15

:0

Ox2FAA

Outputs

BA

SDH/SYNC

For

test

purposes,

read only

.

0

0x0000

Outputs

BB

SDH/SYNC

For

test

purposes,

read only

.

15

:0

Ox97CA

Outputs

BC-DF

-

Not

used

.

- -

EO

I

Control

I

Interrupt

register

.

I

8

:0

I

0x0060

Agere

Systems

Inc

.

43

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Control

Block

Registers

Table

31

.

Hardware

Reset

for

all

TSWC03622

Blocks

Address

Bit

Name

Description

Reset

(Hex)

Value

0x00 15

RHSLOLN

High-speed

PLL

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

14

RLOSCLKN

Loss-of-clock

block

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

13

RSWSTATN

Switch

state

machine

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

12

RESETFFN

Feed-forward

counters

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

11

RLSPLLN

Low-speed

PLL

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

10

RSYNCN

SDH/Sync

generation block

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

9

RPDHCLKN

PDH

block

powerdown

.

1

=

Block

active

.

0 =

Block

powered

down

.

8

RCONFIGN

Control

block

reset

.

1

=

Block

active

.

0 =

Block

reset

for

one

155

.52

MHz

clock cycle

.

7

:0

I

-

I

Unused

:

program

to

one

.

I

00000000

Register

00h

contains

power

downs

for

all

the

TSWC

blocks

.

Setting

a

bit

to

a

low

level

in

this

register

will

power

down

the

corresponding

block

.

The

block

will

remain

powered

down

until

the

bit

is

again

set

to high,

except

for

bit

00h(8),

which

resets

the

control

block

only

for

one 155

MHz

clock

cycle

.

This

register

is

initialized

to

all

zeros,

and

bits

00h[7

:0]

are not

used

.

The

reset

register

can

be

written

at

any

time

to

reset

a

specific

block,

although

the

soft-

ware

reset

implemented

in

each

block

can

also

be

used

.

After a

general

hardware

reset,

the

control

block

will

be

setting

the

reset

register

bits

to

high

level

following

a

certain

reset

sequence

.

If

a

block

is

powered

down

and

it

is

desired

to

power

it

up,

a hardware

reset

is

necessary

.

Table 32

.

Software

Override

Address

Bit

Name

Description

Reset

(Hex)

0x01

15

:1

-

Unused

:

program

to

one

.

111111111111111

0

OVERRIDE

Software

override

bit

.

1

=

Software

programming

disabled

(hardware

mode)

.

0 =

Software

programming

enabled

(software

mode)

.

Register

01 h

contains

the

software

override

bit,

which must be

set

to

low

prior to

any

write

operation

.

If

bit

01

h(0)

is

high,

the

control

block

will

not

write

any

register

except

for 01 h

itself

.

This

register

is

initialized

to

all

ones, although

bits

01 h[15

:1

]

are not

used,

so

right

after

initialization

no

write

process

is

allowed

.

Bit

01 h(0)

must

be

set

low

.

44

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Input

Clock

Block

Registers

The

loss

of

clock

block monitors

the

input

clocks

CLKA,

CLKB

and

CLKBU,

and

the

38

.88

MHz

clock

generated

by

the

external

VCXO

.

Table

33

.

Loss

of

ClockBlock

Software

Override

and

Reset

Address

Bit

Name

Description

Reset

(Hex)

20

15

:2

-

Unused

:

program

to

one

.

11111111111111

1

SWOVRDN

Reserved

.

1

0

SWRSTN

Input

clock

block

powerdown

.

1

=

Block

active

.

0

=

Block

powered

down

.

Register

20h

contains

only

2

bits

.

Those

bits

are the

software

power

down

20h(0)

and

the

software

override

20h(1)

.

Both

are

active-low

level,

so

register

20h

is

initialized

to

all

ones

.

if

bit

20h(1)

is

low,

the

input

clock

block

will

be

operating

in

software

mode,

enabling

all

the

programming

capabilities

and

allowing

access

to

the

full

flexibil-

ity

of

the

block

.

Table

34

.

FINSEL[3

:0]

Register

Address

(Hex)

Bit

Name

Description

Reset

21 15

:4

-

Unused

:

program

to

one

.

111111111111

3

:0

FINSEL[3

:0]

Clock

A

and

clock

B

input

frequency

select

.

1111

(Bit

3

is

a

don't

care

.)

1111,

0111

=

51 .84

MHz

.

1110,

0110

=

38

.88

MHz

.

1101,

0101 = 19

.44

MHz

.

1100,

0100

=

8

.192

MHz

.

1011,

0011

=

6

.480

MHz

.

1010,

0010

= 2

.048

MHz

.

1001,

0001 =

1

.544

MHz

.

1000,

0000

= 8

kHz

.

Register

21

h

is

written

by

the

control

block,

which

monitors

the

external

FINSEL

for

any

change

.

The

FINSEL

register

must

indicate

the

input

clocks

frequency

(FINSEL

for

CLKA

and

CLKB)

.

This

register

is

initialized

to

all

ones

.

It

can be

written

at

any

time

via serial

interface

(even

in

hardware mode),

but

only

in

hardware

mode

will

any

change

in

these

registers

reprogram

the

fractional

dividers

by

rewriting registers

24h-2Dh

.

Agere

Systems

Inc

.

45

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Input

Clock

Block

Registers

(continued)

Table

35

.

FBUSEL[3

:0]

Register

Address

(Hex)

Bit

Name

Description

Reset

22 15

:4

-

Unused

:

program

to

one

.

111111111111

3

:0

FBUSEL[3

:0]

Backup

clock

input

frequency

select

.

1111

(Bit

3

is

a

don't

care

.)

1111,

0111

=

51

.84

MHz

.

1110,

0110

=

38

.88

MHz

.

1101,

0101 = 19

.44

MHz

.

1100,

0100 = 8

.192

MHz

.

1011,

0011

= 6

.480

MHz

.

1010,

0010

= 2

.048

MHz

.

1001,

0001 =

1

.544

MHz

.

1000,

0000

= 8

kHz

.

Register

22h

is

written

by

the

control

block,

which

monitors

the

external

FBUSEL

for

any

change

.

The

FBUSEL

register

must

indicate

the

input

clocks

frequency

(FBUSEL

for

CLKBU)

.

This

register

is

initialized

to

all

ones

.

It

can

be

written

at

any

time

via

serial

interface

(even

in

hardware mode),

but

only

in

hardware

mode

will

any

change

in

these

registers

reprogram

the

fractional

dividers

by

rewriting

registers

24h-2Dh

.

Table

36

.

Loss

of

Clock

Threshold

Address

Bit

Name

Description

Reset

(Hex)

23 15

:0

THRESHOLD

Loss

of

clock

threshold

value

(number

of

miss-

0000000000000010

ing

consecutive

clock

cycles

needed

to

trigger

loss

of

clock

interrupt)

.

Register

23h

is

used

to

program

the

threshold

time,

that

is,

the

number

of

absent

input

cycles

needed

to raise

the

loss

of

clock

interrupt

.

This

values

is

shared by

all

the

loss

of

clock

detectors

.

Register

23h

can be

written

at

any

time

(even

in

hardware

mode)

.

The

minimum

value

for

this

register

is

a

value

of

2

.

If

a

lower

value

is

written,

the

threshold

will

be

set

to

a

values

of

2

.

Table

37

.

Loss

of

Clock

Hysteresis

Address

Bit

Name

Description

Reset

(Hex)

2E

15

:0

HYSTERESIS

Loss

of

clock hysteresis

value

(number

of

con-

0000000000000100

secutive

clock

cycles

needed

to

erase

loss

of

clock

interrupt,

once

clock

is

back)

.

Register

2Eh

is

used

to

program

the

hysteresis

time,

that

is,

the

number

of

input clock

cycles

needed

to

erase

the

loss

of

clock

flag

once

the

clock

is

back

.

This

values

is

shared

by

all

the

loss

of

clock

detectors

.

Register

2Eh

can

be

written

at

any

time

(even

in

hardware

mode)

.

The

minimum

value

for this

register

is

a

value

of

4

.

If

a

lower

value

is

written,

the

hysteresis

will

be

set

to

a

values

of

4

.

46

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

State

Machine

Block

Registers

The

address

space

for

the

clock

protection switch

control

circuit

is

30h-34h

.

Table

38

.

Switch

Block

Control

Register

Address

(Hex)

Bit

Name

Description

Reset

30

15

:9

-

Unused

:

program

to

ones

.

1111111

8

LOCBUN

For

test

purposes,

set

to

1

.

1

7

LOCBN

For

test

purposes,

set

to

1

.

1

6

LOCAN

For

test

purposes,

set

to

1

.

1

5

BUSYBN

For

test

purposes,

set

to

1

.

1

4

BUSYAN

For

test

purposes,

set

to

1

.

1

3

TESTN

For

test

purposes,

set

to

1

.

1

2

Reserved

-

1

SWOVRDN

Software

override

bit

.

1

=

Hardware

mode

(registers

32,

33,

and

34

use

their

default

values)

.

0 =

Software

mode

(user

can

overwrite

registers

32,

33,

and

34)

.

1

0

SWRSTN

Switch

block software

powerdown

.

1

=

Block

active

.

0 =

Switch

control

circuits

powered

down

except

for

microprocessor

inter-

face

.

1

Bits

30h[8

:3]

are

used

for test

purposes,

and

they

must

be

high

in

normal

operation

mode,

specially

bit

30h(3),

which

is

the

test

mode

bit

.

Table

39

.

Switch

Block

State

Machine

Register

Address

Bit

Name

Description

Reset

(Hex)

31 15

:8

-

Unused

.

00000000

7

ENSQLN

Squelch enable

.

1

= Squelch

disabled

.

0

= Squelch enabled

(squelch

active

conditions

are

listed

in

Table

40)

.

6

LORSTN

Lockout

reset

.

1

=

Counting

switching

events

if

31

h(5)

= 0

.

0

= Reset

.

5

ENLON

Enable

lockout

.

1

=

Lockout

disabled

.

0

=

Lockout

enabled

.

4

SWCONTN

Protection

switch

control

circuit

operation

mode

.

1

3

REVERTN

111 =

Protected

manual

mode

(SELCLK/SELBUN

selects

clock

.

User

1

2

AUTOSWN

cannot

switch

to

a

bad

clock)

.

1

110 =

Autonomous

nonrevertive

mode

.

100 =

Autonomous

revertive

mode

.

Oxx

=

Unprotected

manual

mode

(SELCLK/SELBUN

selects

clock

.

User

can

switch

to

a

bad

clock

.)

1

SELBUN

Input

clock

selection

.

1

0

SELCLK

11

:

Clock

A

.

1

10

:

Clock

B

.

Ox

:

Backup

clock

.

Conditions

for

use

of

this

register

:

01

h(0)

= 0

.

Agere

Systems

Inc

.

47

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Preliminary

Data

Sheet

Clock

Synthesizer

and

Protection

Switch

May

2002

Switch

State

Machine

Block

Registers

(continued)

Register

31

h

is

initialized

to

all

ones

.

Positions [15

:8]

will

always

read

as

zeros

.

This

register

is

updated

by

the

TSWC

control

block

based

on

the

input

pins

state,

although

they

can

also

be

modified

via

serial

interface

.

This

reg-

ister

will

therefore

reflect

the

input

pins

with

the

samename

given

that

the

TSWC

control

block

updates

register

31

h via internal

bus

.

The

TSWC03622

will

use

the

respective

external

balls for

control

when

register

01

h

bit

0

is

high,

and

it

will

use

the configuration

from

register

31

h

when

register

01

h

bit

0

is

low

.

All

bits in

register 31 h

are

active-low

.

Bit

31

h(5)

is

the

lock-out

enable

ENLON,

and

bit

31

h(6)

is

the

lock-out

reset

LORSTN

.

If

ENLON

is

low,

the

lock

out

is

enabled,

so

only

a

certain

number

of

switches

are

allowed

(only

in

autonomous

mode),

as

indicated

by

regis-

ter

32h

.

Once

that

limit

has

been

reached,

no

more

switches

are

allowed

.

The

lock

out

only

works

in

autonomous

mode

of

operation,

in

protected

or

unprotected

manual

mode,

unlimited

number

of

clock

switches

are

allowed

no

matter

the

value

of

ENLON

is

.

In

autonomousmode,

if

the

number

of

switches

reaches

the

limit

and

the

device

is

locked

out,

the

lock

out

count

can

be

reset

by

setting

bit

LORSTN

low,

allowing

new

clock

switches

before the

device

is

locked out

again

.

If

ENLON

is

high,

the

device

will

never

be

locked

out,

and

unlimited

number

of

clock

switches

in

autonomous

mode

will

be

allowed

.

Bit

31

h(7)

is

the

squelch

enable

ENSQLN

.

Setting

this

bit

low,

the

SDH

and

PDH

output clocks

will

be

squelched

if

one

of

the

are

met

.

Table

40

.

Squelch

Mode

of

Operation

Conditions

Needed

to

Squelch

the

OutputClocks

when

ENSQLN

=

0

Autonomous

(revertive or

non-

The

output clocks

will

be squelched

if

the

three

input

clocks

CLKA,

CLKB,

and

revertive)

CLKBU

are

lost

.

(LOCA

=

1

and

LOCB

=

1

and

LOCBU

=

1)

.

Protected

Manual

Mode

The

output clocks

will

be squelched

if

one

of

the

conditions

are

met

:

1)

Clock

A

is

being

used

as

reference

but

it

is lost

(LOCA

=

1)

.

2)

Clock

B

is

being

used

as

reference

but

it

is lost

(LOCB

=

1)

.

3)

Clock

BU

is

being

used

as

reference

but

it

is lost

(LOCBU

=

1)

.

Unprotected

Manual

Mode

The

output clocks

will

be squelched

always

if

ENSQLN

is

low,

no matter

what

the

conditions

of

the

input

clocks

are

.

As

indicated

in

the

when

operating

in

external

control

mode,

the

squelch

enable

is

used

to

squelch

the

output

clocks,

whereas

for

the

other

operation

modes

the

squelch

enable

allows

squelching

when

the

special

conditions

are

met

.

Table

41

.

Lockout

Threshold

Address

Bit

Name

Description

Reset

(Hex)

32 15

:0

LOCNT

Maximum

number

of

clock switches

allowed

before

the

0000000000000011

TSWC03622

enter

lockout

(autonomous

mode

only)

.

This

register

indicates

the

maximum

number

of

clock

switches

that

are

allowed

before the

circuit

is

locked out

(autonomous

mode

only)

.

In

order

to

write

this register,

bit

30h(1)

must

be

set

low

previously

.

Whenever

bit

30h(1)

is

high,

register

32h

will

take

the

default

value,

which

is

the

same

as

initialization

.

That

value

is

0000000000000011

(three)

.

That

means

that

in

default

mode,

only

three switches

are

allowed

.

At

the

third

clock

switch,

the

lock-out

flag

is

risen

and any

extra clock

switch

will

be

prohibited

.

If

bit

30h(1)

is

low,

register

32hcan

be

written

with

a

value

ranging

from

zero

to

65535

.

48

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

TSWC03622

SONET/SDH/PDH/ATM

May

2002

Clock

Synthesizer

and

Protection

Switch

State

Machine

Block

Registers

(continued)

In

order

to

enable

the

lock

out

feature,

the

enable

bit

31

h(5)

must

be

set

low

(ENLON)

and

the

reset

bit

31

h(6)

must

be

set

high

(LORSTN),

although

the

device

can

only

be

locked

out

in

autonomous

mode

(AUTOSWN

=

0,

SWCONTN

=

1)

.

Despite

the

lock

out

is

only

effective

in

autonomous

mode,

the

lock-out

counter

keeps

count

of

the

number

of

clock switches

in

any

mode

of

operation

.

This

means

that

if

the

circuit

is

being

used

in

manual

mode

and

several

switches

havebeen

made

so

that

the

limit

has

been

reached,

and

the

circuit

is

switched

to

autono-

mous

mode, no

clock

switch

will

be

allowed, as

the

circuit

will

be

locked out

.

A

software

reset

is

suggested

when

switching

the

circuit

to a

different

mode

of

operation

.

Setting

the

lock

out

reset

low

(LORSTN

=

0)

or

bit

31

h(5)

high

(ENLON

=

1)

will

disable

the

lock

out

feature

.

Table

42

.

Switch

Timeout

Settings

Address

Bit

Name

Description

Reset

(Hex)

33

15

:0

TOCNT

Time-out

counter

:

indicates

the

number

of internal

clock

0000011111111111

cycles

of

the

time

out period

.

34

15

:0

IFREQ

Programs

the

period

of

an

internal

clock

which

is

used

to

0100101111110000

measure

the

time

elapsed

since

the

last

clock

switch

.

These

registers

are

used

to

program

the

time-out

feature

used

to

avoid

any

clock

switch before

a

certain

time

after

the

last

clock

switch,

unless

a

fault

in

the

current

reference

requires

a

clock

switch

.

The

time

out

period

is

needed

by

the

LSPLL

to

lock

to

the

new

reference

clock

after

a

clock

switch,

and

is

active

in

manual

and

automatic

mode

.

In

order

to

write

registers

33h

and

34h,

bit

30h(1)

must be

low

.

Whenever

bit

30h(1)

is

high,

registers

33h

and34h

will

be

loaded

with

the

default

value,

which

is

the

same

as

at

initialization,

that

is,

2047

for

33h

and

19440

for

34h

.

Register

34h

(IFREQ[15

:0]

programs

the period

of

an

internal

clock

which

is

used

to

measure

the

time

elapsed

since

the

last

clock

switch

.

That

clock

will

be

obtained

by

dividing

the

155

.52

MHz

clock

by

the

number

indicated

in

register

34h

.

The

default

value

of

register

34h

is

19439,

which

gives

an

internal

clock

frequency

of

8

kHz

(155

.52MHz/19440

= 8

kHz)

.

Register

33h

indicates

the

number

of internal

clock

cycles

of

the

time-out period

.

After a

clock

switch,

an

internal

counter

will

be

initialized

with

the

value

indicated

by

register

33h,

and

will

start

to

down-count

each

internal

clock

edge

(whose

frequency

can

be

programmed

by

register

34h)

.

The

time-out period

will

be

expired

when

that

counter

reaches

zero

.

The

default

value

of

this register

is

2048

.

The

phase

of

the

internal

clock

used

to

measure

the

time-out

period

is

independent

on

when

the

clock

switch

occurs,

so

the

actual

time-out period

is

between

the

number

indicated

by

register

33hand

the

number

indicated

by

register

33h

plus

one

.

Calling

R33

the

number

indicated

by

register

33hand

R34

the

number

indicated

by

register

34h,

the

time

out

period

ti

will

take

the

(in

seconds)

:

R34/155520000

x

(833-1)

<

ti

<

R34/155520000

x

R33

For

the

default

value,

the

time

out

period

will

be

limited

by

:

255

.75

ms

<

ti

<

255

.875

ms

In

order

to

reduce

the

possible

range

for

the

time-out

period,

it

is

suggested

to

increase

R33

as

much

as

possible

keeping

the

product

of

R33

and

R34

constant

(that

means

a

high

frequency

for

the

internal

clock)

.

For

example,

the

would

be

obtained

for

R33

=

32752

and

R4

=

1215,

the

time-out

period

would be

in

the

range

from

255

.867

ms

to

255

.875

ms

.

It

is

also

suggested

to

software

reset

the

circuit

before

registers

33h and34h

are

written

.

Agere

Systems

Inc

.

49

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Preliminary

Data

Sheet

Clock

Synthesizer

and

Protection

Switch

May

2002

PDH

Output

Block

Registers

Fractional

Dividers

Registers

:

40h-66h

The

PDH

fractional

dividers

enable

each

of

the

five

PDH

CIVIOS

output

clocks

to

be

fully

programmable

.

Registers

40h-66h

contain

the

parameters

to set

the

respective

frequencies

.

Setting

the

frequencies

is

enable

in

registers

80h-83h

.

Each

fractional

divider

includes

seven

registers

.

Those

registers

are

located

at

consecutive

addresses

.

The

address

of

each

register

can be

specified

by

the

base

address

of

the

corresponding

fractional

divider

and

the

rela-

tive

offset

.

Base

address

Fractional

Divider

1

40h

Fractional

Divider

2 48h

Fractional

Divider

3 50h

Fractional

Divider

4 58h

Fractional

Divider

5 60h

To

calculate

the values

for

the

respective

dividers, a

software

program

is

available

to

automate

the

process

.

Please

contact

your

Agere

System

representative

to

get

a

copy

of

the

program

.

All

registers

are

initialized

to

all

zero

at

reset

.

General

Configuration Registers

:

80h-83h

Registers

80h-83h

are

the

general

configuration

registers

that

control

the

operation

mode

of

the

PDH

block

.

The

first

two

registers

80h

and

81

h,

control

the

general

behavior

of

the

PDH

block,

whereas

registers

82h and

83h

con-

trol

the

five

fractional

dividers

used

to

generate

the

PDH

rates

.

Table

43

.

PDH

Control Register

1

Address

Bit

Name

Description

Reset

(Hex)

80 15

:12

PDHSEL

Software

PDH

output

clock

select

.

See

Table

44

.

for

preset

configu-

0000

rations

.

To use

this register,

81

h(4

:3)

must

be

set

to

10

.

11

:1

-

Reserved

.

00000000000

0

SWRSTN

PDH

block

software

power-down

.

1

=

Block

active

.

0

=

PDH

output

block

powered

down

except

for

microprocessor

interface

.

Register

80h

contains

the

software

reset

bit

80h(0)

and

the

four

PDHSEL[3

:0]

bits,

used

to

select

one

of

the

sixteen

preset

configurations

when

81

h[4

:3]

= 10

(basic

software

control),

generating

the

most

needed

PDH

rates

.

Bit

80h(0)

is

the

software

reset,

used

to

power

down

the

PDH

block

except

for

the

microprocessor

used

to

read

and

write

registers

.

The

microprocessor

can

only

be

reset

by hardware

reset

.

Register

80h

is

initialized

with

all

bits

low

except

for

80h(0),

which

is

high

.

Bits

[10

:1]

can

written

and

read

as

they

were

written,

but

they

are

not

used by

the

PDH

block

.

50

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

PDH

Output

Block

Registers

(continued)

Table

44

.

PDH

Clock

Outputs

for

the 16

Preset

Configurations

(Bit

81

h(3)

=

0)

PDHSEL

Clock

1

Clock

2

Clock

3

Clock

4

Clock

s

0000

Disabled

0001 44

.736

MHz

Disabled

0010

34

.368

MHz

Disabled

0011 Disabled

32

.768

MHz

Disabled

0100

24

.704

MHz

Disabled

0101

Disabled

16 .384

MHz

Disabled

0110

Disabled

8

.192

MHz

Disabled

0111

Disabled

4

.096

MHz

Disabled

1000

Disabled

2 .43

MHz

1001

Disabled

2

.048

MHz

Disabled

1010

Disabled

1

.544

MHz

Disabled

1011

Disabled

2

.048

MHz

1

.544

MHz

Disabled

1100 44

.736

MHz

32

.768

MHz

24

.704

MHz

2

.048

MHz

1

.544

MHz

1101

34

.368

MHz

32

.768

MHz

24

.704

MHz

2

.048

MHz

1

.544

MHz

1110

Disabled

1111

I

44

.736

MHz

I

32

.768

MHz

I

2

.048

MHz

I

1

.544

MHz

I

2 .43

MHz

Table

45

.

PDH

Control

Register2

Address

Bit

Name

Description

Reset

(Hex)

81

15

:10

-

Reserved

.

000000

9

:8

DIV2N

For

test

purposes

only

.

Program

to

00

.

00

7

:5

CKMXSEL

For

test

purposes

only

.

Program

to

000

.

000

4

:3

MODESEL

00-Hardware

Control

.

This

mode

allows

to

control

the

PDH

block

0

through

the

external

PDHSEL[3

:0]

pins

in

case

the

TSWC

control

block

fails

.

These

pins

reach

the

PDH

block,

so

the

PDH

block

behavior

is

independent

of

the

TSWC

control

block

.

This

mode

offers

sixteen

pre-

sets

which

generate

the

most

needed

PDH

frequencies

.

Every

one

of

those

configurations

programs

each

fractional

divider

to

work

in

one

of

the

sixteen

modes

listed

in

Table

47

.

10-Basic

Software

Control

.

This

mode

is

intended

to

be

used

in

con-

junction with

the

TSWC

control

block

.

The

PDH

block

operates

in

the

sameway

as

in

hardware

control

offering

the

same

sixteen

presets,

but

this

time

instead

of

reading

the

external

pins

directly,

the

four

PDH-

SEL[3

:0]

bits

are

read

from

register

80h

(four

most

significant

bits)

.

This

register

is

written

by

the

control

block

at

initialization

or

when

any

change

is

made

on

the

external

pins,

as

the

control

block monitors

the

external pins

in

a

continuous

basis

.

Register

80hcan

also

be

written via

serial

interface

(software

override)

.

X11-Enhanced

Software

Control

.

This

mode

can

only

be used by

programming

the

PDH

block

via serial

interface

.

This

third

alternative

allows

individual

selection

of

the

operating

mode

for

each

fractional

divider

.

Registers

82h

and

83h

contain

the

20

bits

needed

to

specify

the

operating

mode

for

each

of

the

five

fractional

dividers

(four

bits

per

frac-

tional

divider)

.

2

:0

I

DELAY

I

For

test

purpose

only

.

Program

to

00

. I

00

Agere

Systems

Inc

.

51

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

PDH

Output

Block

Registers

(continued)

Table

46

.

Enhanced

Software

Mode

Fractional Divider

Selection

Address

Bit

Name

Description

Reset

(Hex)

82

15

:12

FD

1

Mode PDH1

fractional

divider

mode,

see

text

below and

Table

47

to

0000

program

value

.

11

:8

FD

2

Mode

PDH2

fractional

divider

mode,

see

text

below and

Table

47

to

0000

program

value

.

7

:4

FD

3

Mode

PDH3

fractional

divider

mode,

see

text

below and

Table

47

to

0000

program

value

.

3

:0

FD

4

Mode

PDH4

fractional

divider

mode,

see

text

below and

Table

47

to

0000

program

value

.

83

15

:12

FD

5

Mode

PDH5

fractional

divider

mode,

see

text

below and

Table

47

to

0000

program

value

.

11

:0

I

-

I

Reserved

.

I

0000

OOOOOO

Registers

82h

and

83h

indicate

the

operation

mode

of

each

fractional divider

when

bit

81

h(3)

is

high

.

There

are

four

bits

for

each

fractional

divider

.

These

registers

are

reset

to

all

zeros

.

Each

fractional

divider

can

be

operated

in

sixteen

different

modes

.

These

modes

are

described

in

Table

47

.

Table

47

.

Software

Mode

Fractional

Divider

Selection

Mode

Bits

[3

:0]

Divides

By

0

0000

13+211/233

1

0001

18+18/179

2

0010

18+63/64

3

0011

25+35/193

4

0100

37+31/32

5 0101

75+15/16

6

0110

100 +

140/193

7

0111

64

8

1000

151

+7/8

9 1001

303+3/4

10

1010

256

11

1011

402

+

174/193

12 1100

32

13

1101

Reserved

14

1110

Programmable

15

I

1111

I

Power

down

In

mode

14,

the

fractional

divider

can be

programmed

through

the

registers

located

inside the

fractional

divider

(see

See

"Fractional

Dividers

Registers

:

40h-66h"

on

page

50)

.

Fractional

dividers

one

through

three

use

the

622

.08

MHz

clock

as

input,

whereas

fractional

dividers

four

and

five

use

the

155

.52

MHz

clock

.

Based

on

the

input

frequency

to

each

fractional

divider,

and

the

divi-

sion

factor

indicated

in

Table

48,

the

sixteen

presets

will

generate

the

output clocks

(each

clock

is

generated

by

the

fractional

divider

with

the

same

number)

shown

in

Table

44

.

52

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

PDH

Output

Block

Registers

(continued)

summarizes

the

operation

mode

for

the

five

fractional

dividers

when

bit

80h(3)

is

low

.

In

that

case,

the

PDH

block

offers

sixteen

preset

configurations

that

can be

selected

by

the

external

pins

(when

81

h(4)

=

0)

or

writ-

ing

register

80h

(when

81

h(4)

=

1)

.

Table

48

.

Fractional

Dividers

Operation

Mode

as

a

Function

ofthe

External

Pins

PDHSEL[3

:0]

or

Bits

80h[15

:12]

(bit

81

h(3)

must

be

low)

PDHSEL[3

:0]

or

bits

80h[15

:12]

FD

1

FD

2

FD

3

FD

4

FD

5

0000

15

15 15

0001

0

15

15 15

0010

1

15

15 15

0011

15

2

15

15 15

0100

3

15

15 15

0101

15

4

15

15 15

0110

15

5

15

15 15

0111

15

15 8 15 15

1000

15

7

1001

15

15 9 15 15

1010

15

6

15

1011

15

15 9

6

15

1100

0 2

3 5

6

1101

1

2

3 5

6

1110

15

15 15

1111

I

0

I

2

I

9

I

6

I

7

Agere

Systems

Inc

.

53

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

SDH/Sync

Generation

Block

Registers

Table

49

.

SDH/Sync

Control

Register

Address

Bit

Name

Description

Reset

(Hex)

AO

15

:4

-

Reserved

000000000000

3

SYNC

OFFSET

OVERRIDE

Sync

offset

override

.

1

=

Sync

offset

read from

external

pins

(stored

in

A3h)

.

0

=

Sync

offset

read from

registers

A8h

and

A9h

(which

has a

wider

range

than

external

pins,

covering

a complete 8

kHz

cycle)

.

Conditions

for

use

of this

feature

:

SDH

HW

low

.

2

DUTY

CYCLE

OVERRIDE

Duty

cycle

override

.

1

=

Duty

cycle

read

from

external

pins

(stored

in

A2h)

.

0

=

Duty

cycle

read from

A6h

(which

allows

for

dif-

ferent

duty

cycles

for

the

three kinds

of

output

syncs)

.

Conditions

for

use

of this

feature

:

SDH

HW

low

.

1

SDHSEL

OVERRIDE

SDHSEL

override

.

1

= Output

clocks

enables

taken

from

SDHSEL,

read from

external

pins

(stored

in

A1

h)

.

0

= Output

clocks

enables

taken

from

register

A5h

.

Conditions

for

use

of this

feature

:

SDH

HW

low

.

0

SRESETN

SDH/Sync

block software

power-down

1

=

Active

.

0

=

Powered

Down

except

for

microprocessor

interface

.

Conditions

for

use

of this

feature

:

SDH

HW

low

.

Bit

0

is

the

software

reset

used

to

reset

the

SDH/Sync

block

.

Bits

1,

2,

and 3

are

overrides

(active-low

level)

.

When

the

SDH_HW

is

high,

the values

used

as

SDHSEL,

DUTY,

and

SYNCOFFSET

are

read

from

the

external

pins

.

When

that

is

low,

those values

will

be

set via

serial

interface

.

If

bits 1, 2,

and

3

are

high,

the

values

will

be

read

from

the

same

registers

as

if

the

TSWC

was

in

pin-con-

trol,

that

is,

SDHSEL

is

stored

in

register

A1

h,

DUTY

is

in

register

A2h, and

SYNCOFFSET

is in

register

A3h

.

When

bit

A0h(1)

is

low

(SDH

HW

=

0),

the

enables

for

the

output

clocks

will

be

taken

from

register

A5,

which

is

a

bit-to-enable

register

.

If

bit

AOh(2)

is

low

(SDH_HW

=

0),

the

duty

cycle

is

specified

by

register

A6h,

which

allows

different

duty cycles

for

the

three kinds

of

output

syncs

.

Setting

bit

AOh(3)

to

a

low

level

and

SDH

HW

=

0,

allows

the

user

to

specify

the

offset

in

the

output

sync

with

reg-

isters

A8h

and

A9h

.

Those

registers

give

a

wider

range

to

position

the output

sync

than

the

external

pins or

register

A3h

.

By

using

these

registers,

the

user

may

be

able

to

place

the

output

sync

in

any

position

of

the

8

kHz

cycle

.

54

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

SDH/Sync

Generation

Block

Registers

(continued)

Table

50

.

SDHSEL

Register

Address

(Hex)

Bit

Name

Description

Reset

A1 15

:4

-

Reserved

000000000000

3

:0

SDHSEL

SDH

clock

and

sync

selection

.

0000

See

SDH

output

clock

selection

(SDHSEL[3

:0])

in

data

sheet

.

Conditions

for

use

of

this

feature

:

A0h(1)

=

1

and

SDH

HW

low

.

This

is

the

SDHSEL[3

:0]

register

used

to

select

one

of

the

sixteen presets

when

the

SDH

HW

is

low

and

bit

A0h(1)

is

high

(basic

software

enables

configuration)

.

Each

of

the

sixteen

presets

controls

the

clock

and

sync

enables

as

the

SDHSEL[3

:0]

external

pins

do

when

the

SDH

HW

is

high

.

This

register

is

initialized

at

0000,

selecting

the

preset

number

zero,

which

disables

all

clock

and

sync

outputs

.

Table

51

.

Sync

Duty

Cycle

Address

(Hex)

Bit

Name

Description

Reset

A2

15

:1

-

Reserved

.

000000000000000

0

Duty

Cycle

Sync

duty

cycle

.

1

=

50%

.

0 =

Pulse

width

per

Table

52

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

1

and

SDH

HW

low

.

Register

A2h

is

the

duty

cycle

register,

where

bit

A2h(0)

is

the

duty

cycle

bit

.

That

bit

is

used

to

select

the

duty

cycle

of

the

output

syncs

only

when

the

SDH

HW

is

low

and

the

duty

cycle

override

bit

AOh(2)

is

high

(basic

software

duty

cycle

configuration)

.

It

works as

the

external

SYDU

when

SDH

HW

is

high

.

If

the

duty

cycle

bit

is

high,

the

duty

cycle

of

all

output

syncs

will

be

50%,

although

it

can

be

programmed

to

take

a

different

value

through

the

algorithm

control registers

B0h,

131

h,

and

B2h

.

If

the

duty

cycle

bit

is

zero,

each

output

sync

will

have

the

default

pulse

width,

depending

on

the

selected

sync

for

each

output

.

Table

52

.

Output

Sync

Duty

Cycle

Sync

Output

Pulse

Width

PECLO/PECL1

LVDSO/LVDS1

One

cycle

of

the

155

MHz

or

622

MHz

clock

.

CMOs

I

One

cycle

of

the

77

.76

MHz,

51

.84

MHz,

38

.88

MHz

or

19

.44

MHz

.

The

duty

cycle

bit

is

initialized

to

one,

so

the

output

syncs

will

have

50%

duty

cycle

.

Agere

Systems

Inc

.

55

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

SDH/Sync

Generation

Block

Registers

(continued)

Table

53

.

Sync

Offset

Address

Bit

Name

Description

Reset

(Hex)

A3

15

:11

-

Reserved

.

00000

10

SYOFFPOS

Positive

of

negative

offset

bit

.

0

1

=

Positive

.

0

=

Negative

.

Conditions

for

use

of

this

feature

:

AOh(3)=1

and

SDH

HW

low

.

9

:0

SYOFF

Sync

offset

.

0

Value

of this offset

indicates

number

of

1/622

.08 (-1

.6)

ns

increments

.

Conditions

for

use

of

this

feature

:

AOh(3)

=

1

and

SDH

HW

low

.

This

is

the

sync

offset

and

direction register

used

in

the

sameway

as

the

external

pins

SYOFF[9

:0]

and

SYOFF-

POS

.

This

register

will

be

used

only

when

the

SDH_HW

is

low

and

bit

AOh(3)

is

high

(basic

software

offset

con-

figuration)

.

Bits

A3h[9

:0]

are

the

sync

offset,

and

bit

A3h(10)

is

the

direction

.

In

order

to

get

a

positive

delay, that

is,

to

delay

the

output

sync

with

respect

to

the

negative

edge

of

the

input

sync,

bit

A3h(10) must be

high

.

Register

A3h

is

reset

to

all

zero

.

56

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

SDH/Sync

Generation

Block

Registers

(continued)

Table

54

.

Sync

Source

Address

Bit

Name

Description

Reset

(Hex)

A4

15

:12

-

Reserved

.

0000

11"

SYPCL6221

LVPECL

sync

enable

.

0

10

SYPCL6220

These

registers

[11

:8]

control

the

enables

and

sources

of

the

LVPECL 0

9

SYPCL1551

syncs

.

Bits

10

and

8

control

SYLVSP/N[0],

and

bits

11

and

9

control

SYLVSP/N

1

f

ll

0

8

SYPCL1550

[

]

as

o

ows

:

0

SYPCLP/N

[0]

XOXO

=

Disabled

.

XOX1

= Enabled, pulse

width

based

on

SYNC155,

as

defined

in

A6h(1)

.

X1

XO

= Enabled, pulse

width

based

on

SYNC622,

as

defined

in

A6h(0)

.

X1 X1

=Disabled

.

SYPCLP/N

[0]

OXOX

=

Disabled

.

0X1

X

=

Enabled, pulse

width

based

on

SYNC155,

as

defined

in

A6h(1)

.

1

XOX

=

Enabled, pulse

width

based

on

SYNC622,

as

defined

in

A6h(0)

.

1

X1

X

=

SYPCLP/N[1

]

disabled

.

Conditions

for

use

of

this

feature

:

AOh(2)

= 0

and

A0h(1)

=

0

.

7

SYNC8K78

CMOS

sync

enable

.

0

6

SYNC8K51

These

registers

[7

:4]

control

the

enable

and

source

of

the

CMOS

sync

.

0

5

SYNC8K38

The

pulse

width

is

based

on A6h(2)

.

If

A6h(2)

is

high,

the

pulse

width

is

50%

If

A6h

2

i

l

h

l

id

h

i

b d h

fi

i

b

l

0

4

SYNC8K1

9

. (

)

s ow,

t

e pu

se

w

s

ase

on

t

e

con

gurat

on e

ow

.

t

0

(If

two

or

more

of

these

bits

are

high,

the

output

CMOS

sync

will

corre-

spond

to

the

77

.76

MHz

clock

width

.)

0001

=

One

cycle

of

the 19

.44

MHz

clock

.

0010

=

One

cycle

of

the

38

.88

MHz

clock

.

0100

=

One

cycle

of

the

51

.84

MHz

clock

.

1000

=

One

cycle

of

the

77

.76

MHz

clock

.

Other

=

Disabled

Conditions

for

use

of

this

feature

:

AOh(2)

=0

and

A0h(1)

= 0

3

SYLVS6221

LVDS

sync

enable

.

0

2

SYLVS6220

These

registers

[3

:0]

control

the

enables

and

sources

of

the

LVDS

syncs

.

0

1

SYLVS1551

Bits

2

and

0

control

SYLVSP/N[0],and

bits

3

and

1

control

SYLVSP/N[1]

f

ll

0

SYLVS1550

as

o

ows

:

0

SYLVSP/N[0]

XOXO

=

Disabled

.

XOX1

= Enabled, pulse

width

based

on

SYNC155,

as

defined

in

A6h(1)

.

X1

XO

= Enabled, pulse

width

based

on

SYNC622,

as

defined

in

A6h(0)

.

X1 X1

=Disabled

.

SYLVSP/N[1

]

OXOX

=

Disabled

.

0X1

X

=

Enabled, pulse

width

based

on

SYNC155,

as

defined

in

A6h(1)

.

1

XOX

=

Enabled

.

pulse

width

based

on

SYNC622,

as

defined

in

A6h(0)

.

1

X1

X

=

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(2)

=0

and

A0h(1)

= 0

.

*

In

Version

1

.0

and

1 .1

of

the

TSWC03622,

there

is

an

errata

with

bit

11 of

register

A4h

.

This

register

can be

written,

but

does

not

respond

cor-

rectly to

a

read

.

When

this

bit

is

read,

it

will

return

a

0,

regardless

of

the

true

value

in

the

register

.

This

register

is

used

with

register

A5h

for

enhanced

software

enables

configuration

;

that

means

that

it

will

only

be

used

when

the

SDH_HW

is

low

and

bit

A0h(1)

is

low

(override

enables)

.

It

controls

the

output

sync

enables,

so

it

selects

the

output

sync

pulse width

when

the

duty

cycle

bit

is

low

(not

50%)

.

This

register

is

initialized

to

zero

.

Agere

Systems

Inc

.

57

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

SDH/Sync

Generation

Block

Registers

(continued)

Table

55

.

SONET/SDH

Clock

Enable

Address

Bit

Name

Description

Reset

(Hex)

A5

15

:10

-

Reserved

.

000000

9

PECL622

Enable

for

the

622

.08

MHz

PECL

differential

output

(PECL622)

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

8

PECL1551

Enable

for

the

155

.52

MHz

PECL

differential

output

(PECL1551)

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

7

PECL1550

Enable

for

the

155

.52

MHz

PECL

differential

output

(PECL1550)

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

6

CK78

Enable

for

the

77

.76

MHz

single-ended

CMOS

output

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

5

CK51

Enable

for

the

51

.84

MHz

single-ended

CMOS

output

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

4

CK38

Enable

for

the

38

.88

MHz

single-ended

CMOS

output

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

3

CK19

Enable

for

the

19

.44

MHz

single-ended

CMOS

output

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

2

LVDS622

Enable

for

the

622

.08

MHz

LVDS

differential

output

(LVDS622)

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

1

LVDS1551

Enable

for

the

155

.52

MHz

LVDS

differential

output

(LVDS1551)

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

0

LVDS1550

Enable

for

the

155

.52

MHz

LVDS

differential

output

(LVDS1550)

.

0

1

=

Enabled,

0 =

Disabled

.

Conditions

for

use

of

this

feature

:

AOh(1)

=

0 and

SDH

HW

low

.

This

register

controls

the

individual

SDH

clock

enables

when

the

SDH

HW

is

low

and

bit

AOh(1)

= 0

(enhanced

software

enables

configuration)

.

A

low

zero

means

that

the

corresponding

output

clock

will

be

disabled

.

Recall

that

regarding

the

155

.52

MHz

and

622

.08

MHz

clocks,

only

the

enable

signals

are

generated

by

the

SDH

block

.

The

clocks

are

generated by

other

circuits

external

to

the

SDH

block

.

Register

A5h

is

initialized

to

zero

(all

clocks

disabled)

.

58

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

SDH/Sync

Generation

Block

Registers

(continued)

Table

56

.

Sync

Duty

Cycle

Address

Bit

Name

Description

Reset

(Hex)

A6

15

:3

-

Reserved

.

0000000000000

2

DUTY

CYCLE

Set

Duty

Cycle

for

the

CMOS

sync

.

1

SYNCCMOS

1

=

50%

.

0

=

Pulse

width

as

set

by

A4h(7

:4)

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

SDH_HW

low

1

DUTY

CYCLE

SYNC155

Set

Duty

Cycle

for

the

SYNC155

.

1

=

50%

0

=

One

155

.52

MHz

clock

cycle

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

SDH_HW

low

.

0

DUTY

CYCLE

SYNC622

Set

Duty

Cycle

for

the

SYNC622

.

1

=

50%

.

0

=

One

622

.08

MHz

clock

cycle

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

SDH_HW

low

.

This

register

is

used

to

control

the

individual

syncs

duty

cycle

when

the

SDH

HW

is

low

and

bit

AOh(2)

=

0

(enhanced

software

duty

cycle

configuration)

.

Only

the

three

least significant

bits

are

used,

as

there

are

only

three

types

of output

syncs

(SYC155,

SYNC622,

and

CMOS)

.

A

high

duty

cycle

bit

selects

the

duty

cycle

of

the

corre-

sponding sync

to

be

50%

.

If

the

bit

is

low,

the

sync

pulse

width

will

be

equal

to

one622

.08

MHz

clock cycle

for

SYNC622

and one

155

.52

MHz

clock cycle

for

SYNC155

;

and

for

the

CMOS

sync,

the

pulse

width

can be

pro-

grammed

to

be

one

clock

cycle

of

the

77

.76

MHz,

51

.84

MHz,

38

.88

MHz,

or

19

.44

MHz

clock

.

Register

A6

is ini-

tialized

to 111,

that

is, all

50%

duty

cycle

.

Agere

Systems

Inc

.

59

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

SDH/Sync

Generation

Block

Registers

(continued)

Table

57

.

CMOS

SONET

Clock

Edge

Selection

Address

Bit

Name

Description

Reset

(Hex)

A7

15

:4

-

Reserved

.

000000000000

3

CK78

Edge

Selection

for

the

77

.76

MHz

clock

.

1

=

Rising

edge

of

corresponding

clock

aligned

to

input

sync

.

0 =

Falling

edge

of

corresponding

clock

aligned

to

input

sync

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

AOh(1)

= 0

.

2

CK51

Edge

Selection

for

the

51

.84

MHz

Clock

.

1

=

Rising

edge

of

corresponding

clock

aligned

to

input

sync

.

0 =

Falling

edge

of

corresponding

clock

aligned

to

input

sync

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

AOh(1)

= 0

.

1

CK38

Edge

Selection

for

the

38

.88

MHz

Clock

.

1

=

Rising

edge

of

corresponding

clock

aligned

to

input

sync

.

0 =

Falling

edge

of

corresponding

clock

aligned

to

input

sync

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

AOh(1)

= 0

.

0

CK19

Edge

Selection

for

the

19

.44

MHz

Clock

.

1

=

Rising

edge

of

corresponding

clock

aligned

to

input

sync

.

0 =

Falling

edge

of

corresponding

clock

aligned

to

input

sync

.

Conditions

for

use

of

this

feature

:

AOh(2)

=

0

and

AOh(1)

= 0

.

This

is

the

edge

selection

for

the

four

SDH

clocks

generated

by

the

SDH

block

.

A

high

bit

means

that

the

corre-

sponding

clock's

rising

edge

will

be

synchronized

to

the

negative

edge

of

the

input

sync

(actually

it

will

lead

the

sync by

1-2

cycles

of

a

622

MHz

clock)

.

If

the

edge

selection

bit is

low,

the

falling

edge

of

the

corresponding

clock

will

be

aligned

to

the

input

sync

.

This

register

is

set

to

1111

at

reset,

aligning

the

rising

edges

of

the

clocks

to

the

input

sync

.

60

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

TSWC03622

SONET/SDH/PDH/ATM

May

2002

Clock

Synthesizer

and

Protection

Switch

SDH/Sync

Generation

Block

Registers

(continued)

Table

58

.

Enhanced

Sync

Offset

Address

Bit

Name

Description

Reset

(Hex)

A8

15

:0

SSYNCOFFSET

Enhanced

sync

offset

.

0000000000000000

A9

15

:2

-

Bits

A9h(0)

(IVISB)

and

A8h(15

:0)

contain

the

sync

00000000000000

1

SYOFFPOS

offset

value,

calculated

in

increments

of

0

SSYNCOFFSET(16)

1/622

.08 (-1

.6)

ns

.

To be used

with

A9h[1

:0]

-

0

SSYOFFPOS

.

Bit

A9h(1)

:

Denotes

whether

enhanced

offset

is

positive

or

negative

:

1

=

Positive

.

0 =

Negative

.

Bits

A9h(15

:2)

:

Reserved

.

Conditions

for

use

of this

feature

:

AOh(3)

=

0 and

SDH

HW

low

.

These

registers

are

used

to

increase

the

possible

offset

between

the

input

and

output

syncs

.

They

will

be

used

in

enhanced

software

offset

configuration

(pin

SDH

HW

=

0

and

bit

AOh(3)

=

0),

giving

17

bits

for

the

absolute value

of

the

offset

as

opposed

to

the

10

bits

available

in

hardware

and

basic

software

offset

configuration

.

Those

17

bits

are

the

16

bits

of

register

A8h

and

bit

A9h(0),

which

is

the

most

significant

bit

of

the

offset

.

Bit

A9h(1)

is

the

direc-

tion of

the

offset

(1

means

that

the

output

sync

will

be delayed

from

the

input

sync)

.

These

registers

are

initialized

to

zero

.

In

order

to

write

registers

A8h

and

A9h,

first

A8h

must

be

written

.

However,

register

A8h

will

not

be

actually

written

until

register

A9h

is

also

written

.

Table

59

.

Sync

Rising

Edge

Position

Address

Bit

Name

Description

Reset

(Hex)

BO

15

:0

RISE Sync

rising

edge

position

.

Ox2FC0

131

15

:1

-

Bits

131

h(0)

(IVISB)

and

B0h(15

:0)

contain

the

sync

rising

edge

0000000000000

position,

calculated

in

increments

of

1/622

.08 (-1

.6)

ns

.

00

0

RISE(16)

Bits

131

h(15

:1)

:

Reserved

.

1

Register

BOh-B6h

will

only

be

recalculated

(and

affect

the

sync

outputs)

by

the

internal

state

machine

after

one

of

the

following

actions

occur

:

1

.

The

SDH

HW

is

high

and

the

user

change

the

SYOFF

or

SYOFFPOS

pins

.

2

.

SDH

HW

is

low,

AO(3)

is

high

and

the

user

writes

to register

A3

.

3

.

SDH

HW

is

low,

AO(3)

is

low

and

the

user

changes

A8h

or

A9h

.

These

registers

contain

the

value

RISE

used

by

the

algorithm

to

calculate

the

position

of

the

rising

edge

of

the

out-

put

sync

.

These

two

registers

together

offer

17

bits to

define the

value

of

RISE

.

Bit 131

h(0)

is

the

most

significant

bit

.

At

initialization,

these

registers

have

the

value

131

h(0)&Bh0

=

1001011111100000

=

77,760

.

These

registers

are

also

used

in

conjunction

with

register

B6h

to

generate

the

parameter

tcnt,

used

by

the

high-

speed

sync

generation

block

.

It

is

not

recommended

that

rise

position

of

the

sync

outputs

be

adjusted

in

this

fash-

ion,

since

the

frequency

of

the

sync

outputs

may

be

affected

.

It

is

recommended

instead

to

use

the

offset

function-

ality

in

registers

A8h

and

A9h

to

control

the

rise

of

the

sync

outputs

and

then

use

register

B2h

to

control

the

fall

position

.

Agere

Systems

Inc

.

61

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

SDH/Sync

Generation

Block

Registers

(continued)

Table

60

.

Sync

Falling

Edge

Position

Address

(Hex)

Bit

Name

Description

Reset

132

15

:0

FALL Sync

falling

edge

position

.

Ox97E0

Contains

the

sync

falling

edge

position,

calculated

in

increments

of

1/622

.08 (-1

.6)

ns

.

Register

B0h-B6h

will

only

be

recalculated

(and

affect

the

sync

outputs)

by

the

internal

state

machine

after

one

of

the

following

actions

occur

:

1)

The

SDH

HW

is

high

and

the

user

change

the

SYOFF

or

SYOFFPOS

pins

.

2)

SDH_HW

is

low,

AO(3)

is

high

and

the

user

writes

to

register

A3

.

3)

SDH

HW

is

low,

AO(3)

is

low

and

the

user

changes

A8h

or

A9h

.

Register

B2h

is

used

to

store

the

value

of

the

parameter

FALL

used by

the

sync

generation

algorithm

.

This

register

can be

modified

to

obtain

any

desired

duty

cycle

on

the output

syncs

.

It

is

initialized

at

1001011111100000

=

38,880

.

Given

that

value,

with

the

initial

value

of

registers

B0h and

131

h,

the

output

syncs

will

have

50%

duty

cycle

when

the

corresponding

duty

cycle

bit

is

high

.

Table

61

.

Sync

Delta

Address

(Hex)

Bit

Name

Description

Reset

133

15

:5

-

Reserved

.

00000000000

4

:0

DELTA

Compensation

for

the

delay

between

the

negative

edge

of

the

input

10110

sync

and

the

positive

edge

of

the

output

sync

when

the

regular

offset

is

zero

.

Value

of this offset

indicates

number

of

1/622

.08 (-1

.6)

ns

incre-

ments

.

Register

B0h-B6h

will

only

be

recalculated

(and

affect

the

sync

out-

puts)

by

the

internal state

machine

after

one

of

the

following

actions

occur

:

1

.

The

SDH

HW

is

high

and

the

user

change

the

SYOFF

or

SYOFFPOS

pins

.

2

.

SDH

HW

is

low,

AO(3)

is

high

and

the

user

writes

to register

A3

.

3

.

SDH

HW

is

low,

AO(3)

is

low

and

the

user

changes

A8h

or

A9h

.

This

register

gives

an

extra

offset

to

compensate

the

delay

due

to

the

circuits

.

This

offset

is

always

negative,

as

opposed

to

the

regular

offset

defined

by

registers

A3h

or

A8h/A9h, which can

be

positive

or negative

(positive

off-

set

increases the

delay

of

the

output

sync

in

relation

to

the

negative

edge

of

the

input

sync)

.

This

register

is

initial-

ized

to

10110 = 22

.

That

value

compensates

the

delay

between

the

negative

edge

of

the

input

sync and

the

positive

edge

of

the

output

sync

when

the

regular

offset

is

zero

.

Without

this

extra

offset,

the

output

sync would be

delayed

22 622

MHz

clock

cycles

.

Register

B3h

is

therefore

parameter

DELTA

used

by

the

sync

generation

algo-

rithm

.

62

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

SDH/Sync

Generation

Block

Registers

(continued)

Table

62

.

Sync

Delta

Rise

Address

(Hex)

Bit

Name

Description

Reset

136

15

:5

-

Reserved

.

00000000000

4

:0

DELTARISE

The

5

bits

of

register

B6h

are

used

in

conjunction with

registers

01011

B0h/B1

h to

calculate

the

value

of

the

parameter

tcnt

used

by

the

sync

generation

algorithm

(tcnt

=

RISE-136h)

.

The

value

of

B6h

will

be

subtracted

form

the

value

of

registers

B0h/B1

h to

calculate

tcnt

.

Register

B0h-B6h

will

only

be

recalculated

(and

affect

the

sync

outputs)

by

the

internal

state

machine

after

one

of

the

following

actions

occur

:

1

.

The

SDH

HW

is

high

and

the

user

change

the

SYOFF

or

SYOFFPOS

pins

2

.

SDH

HW

is

low,

AO(3)

is

high

and

the

user

writes

to

register

A3

.

3

.

SDH

HW

is

low,

AO(3)

is

low

and

the

user

changes

A8h

or

A9h

.

The

5

bits

of register

B6h

are

used

in

conjunction

with

registers

B0h/B1

h to

calculate the

value

of

the

parameter

tcnt

used by

the

sync

generation

algorithm

(tcnt

=

RISE-136h)

.

The

value

of

B6h

will

be

subtracted

from

the

value

of

registers

B0h/B1

h

to

calculate

tcnt

.

The

initial

value

at

reset

is

01011 =

11

.

As

it

can be

seen

in

the

rithm

description,

this

value

is

needed

to

generate

the

proper

value

for tcnt

.

It

is

not

recommended

that

rise

position

of

the

sync

outputs

be

adjusted

in

this

fashion,

since

the

frequency

of

the

sync

outputs

may

be

affected

.

It

is

recommended

instead

to

use

the

offset

functionality

in

registers

A8h

and

A9h

to

control

the

rise

of

the

sync

outputs

and

then

use

register

B2h

to

control

the

fall

position

.

Agere

Systems

Inc

.

63

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

SDH/Sync

Generation

Block

Registers

(continued)

Table

63

.

Interrupt

Status

Register

Address

Bit

Name

Description

Reset

(Hex)

EO

15

:10

-

Reserved

.

111111

9

SQUELCH

The

output clocks

have

been

squelched

due

to

a problem

.

1

=

Squelch

inactive

.

0

=

Squelch

active

.

8

LOCKOUT

The

TSWC

will

not

allow

any

more

clock

switches

.

1

=

Lockout

condition

exist

.

0

=

Lockout

condition

does

not

exists

.

7

CKCONTRA

The

TSWC

is

not

working

with

the

clock

selected

by

the

user

.

1

=

The

TSWC

is

not

working

with

the

clock

selected

by

the

user

.

0

=

The

TSWC

is

working

with

the

clock

selected

by

the

user

.

6

HSLOL

Loss

of

lock-high-speed

PLL

.

1

= Loss

of

lock

.

0

=

I

n

lock

.

5

LSLOL

Loss

of

lock-low-speed

PLL

.

1

= Loss

of

lock

.

0

=

In

lock

.

4

CLKSW

Clock

switch

in

progress

.

1

=

Clock

switch

in

progress

.

0

=

No

clock

switch

in

progress

.

3

LOCLS

Loss

of

external

38

.88

MHz

VCXO

clock

.

1

= Loss

of

clock

.

0

=

No

loss

of

clock

.

2

LOCBU

Loss

of

backup

clock

.

1

= Loss

of

clock

.

0

=

No

loss

of

clock

.

1

LOCB

Loss o

-clock

B

.

1

= Loss

of

clock

.

0

=

No

loss

of

clock

.

0

LOCA

Loss

of

clock

A

.

1

= Loss

of

clock

.

0

=

No

loss

of

clock

.

The

interrupt register

EOh

is

a

read-only

and

clear-on-read

register

that

reflects

the status

of

the

TSWC

interrupts

.

Whenever

there

is

an

interrupt,

the

corresponding

bit

will

be

set

high

and

will

remain

high

until

the

register

is

read,

even

if

the

event

that

generated

the

interrupt

is

over

.

However,

the

interrupt

external

pins

reflect

the

interrupts

only

while

they

are

active,

so

the

corresponding

goes

low

as

soon as

the

event

has

finished

.

64

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Absolute

Maximum

Ratings

Stresses

in

excess

of

the

absolute

maximum

ratings

can

cause

permanent

or

latent

damage

to

the device

.

These

are

absolute

stress

ratings

only

.

Functional

operation

of

the device

is

not

implied

at

these

or

any

other conditions

in

excess

of

those

given

in

the

operational

sections

of this

device

specification

.

Exposure

to

absolute

maximum

rat-

ings

for

extended

periods

can

adversely

affect

device

reliability

.

Table

64

.

Absolute

Maximum

Ratings

Parameter

Min

Max

Unit

Power

Supply

Voltage

(VDD)

-0

.50

TBD

V

Storage

Temperature

-40

125

°C

Ball

Voltage

I

GND

-

0

.5

I

VDD

+

0

.5

I

V

Handling

Precautions

Although

electrostatic

discharge

(ESD)

protection

circuitry

has

been

designed

into this

device,

proper

precautions

must

be

taken

to

avoid

exposure

to

ESD

and

electrical

overstress

(EOS)

during

all

handling,

assembly,

and

test

operations

.

Agere

employs

both

a

human-body

model

(HBM)

and

a

charged-device

model

(CDM)

qualification

requirement

in

order

to

determine

ESD-susceptibility

limits

and

protection

design

evaluation

.

ESD

voltage

thresh-

olds

are

dependent

on

the

circuit

parameters

used

in

each

of

the

models,

as

defined

by

JEDEC's

JESD22-A114

(HBM)

and

JESD22-Cl

01

(CDM)

standards

.

Table

65

.

Handling

Precautions

Device

Minimum

HBM

Threshold

Minimum

CDM

Threshold

TSWC03622

I

500

V

I

200

V

Operating Conditions

Table

66

.

Recommended

Operation

Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Power

Supply

(dc

voltage)

VDD

3

.135

3

.3

3

.465

V

Temperature

:

Ambient

-

-40

25 85

°

C

Power

Dissipation

PD

-

1

.0

TBD

W

Agere

Systems

Inc

.

65

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Electrical

Characteristics

LVPECL,

LVDS,

CMOS,

Input

and

Output

Balls

Note

:

For Tables

67

through

71,

VDD

=

3

.3

V

±

5%,

TAMBIENT

=

-40

°C

to

+85

°C

.

Table

67

.

LVDS

Outputdo

Characteristics

Applicable

Balls

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

CK622P/N,

Output

Voltage

High,

VOH

RLOAD

=

100

SZ

±

1

%

- -

1475

mV

CK155P/N[1

:0],

VOA

or

VOB

SYLVSP/N[1

:0]

Output

Voltage

Low,

VOL

RLOAD

=

100

SZ

±

1

%

925

- -

mV

VOA

or

VOB

Output

Differential

Voltage

~VODj

RLOAD

=

100SZ±

1%

250

-

400

mV

Output

Offset

Voltage

Vos

RLOAD

=

100

52,

±

1

%

1125

-

1275

mV

Differential

Output

Ro Vcm

=

1

.0

V

and

80 100 120

W

Impedance

1

.4

V

Ro

Mismatch

Between

ARo

Vcm

=

1

.0

V

and

- -

20

AandB

1

.4V

Change

in

~VODj

Between

JAVODJ

RLOAD

=

1005l±

1%

- -

25

mV

Logic

0

and

Logic

1

Change

in

IVosl

Between

JAVOSI

RLOAD

=

100SZ±

1%

- -

25

mV

Logic

0

and

Logic

1

Output

Current

ISA,

ISB

Driver

shorted

to

- -

24

mA

GND

Output

Current

ISAB

Drivers

shorted

- -

12

mA

together

Power-off

Output

Leakage

IIXAI,IIXBI

-

- -

=

pA

*

This

leakage

parameter

is

not

specified

due

to

EDS

clamp

diode

conducting

current

during

forward

bias

test

.

66

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Electrical

Characteristics

(continued)

Table

68

.

LVDS

Input

do

Characteristics

Applicable

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Balls

CLKAP/N,

Input

Common-mode

VcM

AVg(VIA,VIB)

0

1200

2400

mV

CLKBP/N

Voltage

Range

Input

Peak

Differential

VDIFF VIA-VIBE

100

-

800

mV

Voltage

Input

Differential

Threshold

VIDTH

VIA-VIB

-100

-

100

mV

Differential

Input

RIN

Measure

at

do 80

100

120

ti

Impedance*

*

Looser

than

ICORE/IEEE®

spec

of

±10

52,

.

Table

69

.

CMOS

Input

do

Characteristics

Applicable

Parameter

Symbol

Conditions

Min

Max

Unit

Balls

LSVCO

Input

Voltage

High

VIH

-

VDD

-1

.0

VDD V

Input

Voltage

Low

VIL

-

GND

1 .0

V

Input

Current

High

Leakage

IN

VIN

=

VDD

-

10

pA

Input

Current

Low

Leakage

IIL

VIN

=

GND

-10

-

pA

CLKA,CLK13,

Input

Voltage

High

VIH

-

VDD

-1

.0

VDD V

CLKBU,

Input

Voltage

Low

VIL

-

GND

1 .0

V

SDHSEL[3

:0]

SYOFF

9

0

Input

Current

High

Leakage

IN

VIN

=

VDD

-

225

pA

[

:

],

Input

Current

Low

Leakage

IIL

VIN

=

GND

-10

-

pA

PDHSEL[3

:0]

SELLVDS,

Input

Voltage

High

VIH

-

VDD

-1

.0

VDD V

FINSEL[3

:0],

Input

Voltage

Low

VIL

-

GND

1 .0

V

FBUSEL[3

:0],

Input

Current

High

Leakage

IN

VIN

=

VDD

-

10

pA

INLOSN,

Input

Current

Low

Leakage

IIL

VIN

=

GND

-225

-

pA

SYOFFPOS,

SYDU,

SELCLK,

SELBUN,

AUTOSWN,

REVERTN,

SWCONTN,

ENSQLN,

RESETN,

ENLON,

LORSTN,

LFOZ

Agere

Systems

Inc

.

67

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Electrical

Characteristics

(continued)

Table

70

.

CMOS

Output

do

Characteristics

Applicable

Parameter

Symbol

Conditions

Min

Max

Unit

Balls

CK77,

CK51,

Output

Voltage

High

VOH

IOH

=

-4

.0

mA

VDD

- 0

.5

VDD

V

CK38,

CK19,

Output

Voltage

Low VOL

IOL= 4

.0

mA GND

0

.5

V

SYNC8K,

Output

Load

Capacitance

CL

-

15

pF

CKPDH5,

CKPDH4,

CKPDH3,

CKPDH2,

CKPDH1,

SWSTATE[1

:0],

INT[8

:0],

TSTMODE

Table

71

.

LVPECL

Output

do

Characteristics

Applicable

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Balls

PCK622P/N,

Output

Voltage

High

VOH

Load

= 50

52,

VDD

-1

.21

VDD-1

.11

VDD

-1

.06

V

PCK155P/N[1

:0],

Output

Voltage

Low VOL

connected

to

VDD

-1

.94

VDD

-1

.92

VDD

-1

.91

V

SYPCLP/N[1

:0]

VDD-

2

.0

V

Timing

Characteristics

Table 72

.

LVDS

Outputac

Timing

Characteristics

Applicable

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Balls

CK622P/N,

tRISE

Rise

Time,

20%

to

80%

ZLOAD

=

100

n

±

1

%

200

-

300

ps

CK155P/N[1

:0]

tFALL

Fall

Time,

20%

to

80%

ZLOAD

=

100

n

±

1

%

200

-

300

ps

SYLVSP/N[1

:0]

tSKEW1*

Differential

Skew

-

50

ps

*As

defined

in

the

IEEE

standard

1596

.3

-1996

.

Table

73

.

CMOS

Output

ac

Timing

Characteristics

Applicable

Balls

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CK77,

CK51,

tRISE

Rise

Time,

20%

to

80%

-

ps

CK38,

CK19,

tFALL

Fall

Time,

20%

to

80%

-

ps

SYNC8K,

tSKEW1~

Differential

Skew

-

ps

CKPDH5,

CKPDH4,

CKPDH3,

CKPDH2,

CKPDH1,

SWSTATE[1

:0],

INT[8

:0],

TSTMODE

68

Agere

Systems

Inc

.

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Timing

Characteristics

(continued)

Table

74

.

LVPECL

Output

ac

Timing

Characteristics

Applicable

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Balls

PCK622P/N,

tRISE

Rise

Time,

20%

to

80%

Load

= 50

n

con-

-

Ps

PCK155P/N[1

:0]

tFALL

Fall

Time,

20%

to

80%

nected

to

-

Ps

SYPCLP/N[1

:0]

VDD

-

2

.0

V

tSKEW1*

Differential

Skew

-

Ps

Agere

Systems

Inc

.

69

AdLib OCR Evaluation

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Preliminary

Data

Sheet

May

2002

Packaging

Diagram

208-Plastic

Ball

Grid

Array

(17

x

17)-0

.63

mm

Ball

Size

(4-Layer-Bottom

View)

Dimensions

are

in

millimeters

.

A1

BALL

IDENTIFIER

ZONE

15

.00

+0

.70

-0

.05

17

.00

±0

.20

r

0

.61

±0

.06

0

.80

±0

.05

1

.91

±0

.21

--T

11

SEATINGPLANE

p

0

.20

0

.50

±0

.10

SOLDER

BALL

15

SPACES

@

1

.00

= 15

.00

T

OOOOOOO

O1O

OOOOOOO

R

OOOOOOOO

O

OOOOOOO

P

OOOOOOO

O1O

OOOOOOO

:

N

OOOOOOO

O1O

OOOOOOO

M OOOO OOOO

L

OOOO

I

OOOO

K

OOOO O

O1O

O OOOO

1

OOOO 0

00

0 OOOO

H

OOOO OO

TO

O OOOO

G OOOO O

O1O

O OOOO

F

OOOO

I

OOOO

E

OOOO OOOO

D

OOOOOOO

O1O

OOOOOOO

C

OOOOOOO

OIO

OOOOOOO

B

OOOOOOOO

O

OOOOOOO

A

OOOOOOO

OIO

OOOOOOO

A1

BALL

-/""

1

2345

678

~

9

10

11

12

13 14 15 16

CORNER

1

.00

0

.63

+0

.07

-0

.13

15

SPACES

1

.00

=

15

.00

5-7809

.b

(F)

70

Agere

Systems

Inc

.

17.00

±0

.20

15

.00

+0

.70

0

.05

AdLib OCR Evaluation

Preliminary

Data

Sheet

May

2002

TSWC03622

SONET/SDH/PDH/ATM

Clock

Synthesizer

and

Protection

Switch

Ordering

Information

Device

Code

Package

Temperature

Comcode

(Ordering

Number)

TSWC03622

I

208

PBGAM1

I

-40

0

C

to

+85

0

C

I

700021311

Agere

Systems

Inc

.

71

AdLib OCR Evaluation

Telcordia

is

a

trademark

of

Telcordia

Technologies,

Inc

.

IEEE

is

a

registered

trademark

of

The

Institute

of

Electrical

and

Electronics

Engineers,

Inc

.

For

additional

information,

contact

your

Agere

Systems

Account

Manager

or

the

following

:

INTERNET

:

http

://www

.agere

.com

E-MAIL

:

docmaster@agere

.com

N

.

AMERICA

:

Agere

Systems

Inc

.,

555

Union

Boulevard,

Room

30L-15P-BA,

Allentown,

PA

18109-3286

1-800-372-2447,

FAX

610-712-4106

(In

CANADA

:

1-800-553-2448,

FAX

610-712-4106)

ASIA

:

Agere

Systems

Hong

Kong

Ltd

.,

Suites

3201

&

3210-12,

32/17,

Tower

2,

The

Gateway,

Harbour

City,

Kowloon

Tel

.

(852)

3129-2000,

FAX

(852)

3129-2020

CHINA

:

(86)

21-5047-1212

(Shanghai),

(86)

10-6522-5566

(Beijing),

(86)

755-695-7224

(Shenzhen)

JAPAN

:

(81)

3-5421-1600

(Tokyo),

KOREA

:

(82)

2-767-1850

(Seoul),

SINGAPORE

:

(65)

6778-8833,

TAIWAN

:

(886)

2-2725-5858

(Taipei)

EUROPE

:

Tel

.

(44)

7000

624624,

FAX

(44)

1344

488

045

Agere

Systems

Inc

.

reserves

the

right

to

make

changes

to

the

product(s)

or

information

contained

herein

without

notice

.

No

liability is

assumed

as a

result

of

their

use

or

application

.

Agere,

Agere Systems, and

the

Agere

logo

are

trademarks

of

Agere

Systems

Inc

.

Copyright

®

2002

Agere

Systems

Inc

.

All

Rights

Reserved

May

2002

DS02-239HS

P

L

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