WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE 128Kx8 CMOS MONOLITHIC EEPROM aovancen- FEATURES FIG. 1 @ Access Times of 150, 200, 250, 300ns PIN CONFIGURATION M JEDEC Approved Packages 32 DIP 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300} TOP VIEW 32 lead, Hermetic Ce.ramic, 0.400" SOU (Package 101) M Organized as 128Kx8. RY/BY [1 327] Vee Ae L]2 31] WE m CMOS: ats ()3 30[] RESET Radiation Tolerant with Epitaxial Layer Die Al2(]4 29] A14 . . ye A7O5 28] A13 M@ Commercial, Industrial and Military Temperature Ranges A6]6 27] As . as 7 26] Ag M Write Endurance 10,000 Cycles a4(|8 25] Att M@ Data Retention at 25C, 10 Years eH ssHlato M@ Low Power CMOS Operation adi zat cs M@ Automatic Page Write Operation oor 0 5 on e Internal Address and Data Latches for 128 Bytes vor F114 191] vos e Internal Control Timer vo2 (15 18] ] vo4 M@ Page Write Cycle Time 10ms Max. Vss [] 16 177] vos . . . M@ Data Polling for End of Write Detection M@ Hardware and Software Data Protection @ TTL Compatible Inputs and Outputs PIN DESCRIPTION P P P M5 Volt Power Supply Ao-16 Address Inputs * This data sheet describes a product that may or may not be under VOo7 Data Input/Output development and is subject to change or cancellation without notice. cs Chip Select OE Output Enable WE Write Enable Vec +5.0V Power Vss Ground RESET Reset RY/BY Ready/Busy September 1998 1 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE ABSOLUTE MAXIMUM RATINGS TRUTH TABLE Parameter Symbol Unit cS | OE | WE | RESET| ARY/BY Mode Data 1/0 Operating Temperature TA -55 to +125 Cc L L H H* High Z Read Data Out Storage Temperature TsTg -65 to +150 ae H X X X - High Z Standby High Z ; ; L H L H High Z to Vou Write Data In Signal Voltage Relative to GND Ve -0.6 to +6.25 Vv L H H H High Z Out Disable High Z Voltage on OE and AQ -0.6 to +13.5 v X X H X Write NOTE: X L X X Inhibit Stresses above those listed under "Absolute Maximum Ratings may cause L L H H VoL Data Polling | Data Out (1/07) permanent damage to the device. This is a stress rating only and functional X X X L High Z__ [ProgramReset| High Z operation of the device at these or any other conditions above those indicated : : : . cee oo NOTE: eaters rare fed ya "Reto eeorena 0 petng corto device reliability. X= Don't care CAPACITANCE RECOMMENDED OPERATING CONDITIONS (TA = +25C) Parameter Symbol Min Max Unit Parameter Symbol Conditions Max | Unit Supply Voltage Voc 45 5.5 v Input capacitance Cin | Vin =OV,f=1.0MHz}] 20 | pF Input High Voltage Vii 2.0 Vec + 0.3 v Output capacitance Cour |Vour=O0V,f=1.0MHz| 20 | pF Input Low Voltage Vit -0.5 +0.8 Vv This parameter is guaranteed by design but not tested. Operating Temp. (Mil.) TA -55 +125 C Operating Temp. (Ind.) TA -40 +85 C DC CHARACTERISTICS (Vec = 5.0V, Vss = OV, TA = -55C to +125C) Parameter Symbol Conditions Min Max Unit Input Leakage Current lu Vec = 5.5, Vin = GND to Vec 10 pA Output Leakage Current ILo CS = Vin, OE = Vin, Vout = GND to Vcc 10 pA Operating Supply Current x 32 Mode lec CS = Vii, OF = Vin, f = 5MHz 60 mA Standby Current Is3 CS = Vin, OE = Vin, f = 5MHz 1 mA Output Low Voltage VoL lo. = 2.1mA, Vcc = 4.5V 0.40 Vv Output High Voltage Vou loH = -400pA, Vcc = 4.5V 24 Vv NOTE: DC test conditions: Vin = Vcc -0.3V, ViL = 0.3V FIG. 2 AC TEST CONDITIONS AC TEST CIRCUIT | lon Parameter Typ Unit Current Source Input Pulse Levels Vit = 0, Vin = 3.0] V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 Vv D.U.T. Vz = 1.5V Output Timing Reference Level 1.5 Vv Co = 50 pf (Bipolar Supply) NOTES: Vz is programmable from -2V to +7V. lo. & loH programmable from 0 to 16mA. Tester Impedance Zo=75Q. Vz is typically the midpoint of Vou and Vo. lon lo. & loHare adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. 4 Current Source White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 2WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE AC WRITE CHARACTERISTICS WRITE (Vec = 5.0V, Vss= OV, TA= -55C to +125C} A write cycle is initiated when OE is high and a low pulse is on WE ; " ; or CS with CS or WE low. The address is latched on the falling Write Cycle Parameter Symbol _| Min | Max | Unit edge of CS or WE whichever occurs last. The data is latched by Write Cycle Time, TYP = 6ms twe 10 | ms the rising edge of CS or WE, whichever occurs first. A byte write Address Set-up Time tas 0 ns operation will automatically continue to completion. Write Pulse Width (WE or CS) twe | 250 ns Chip Select Set-up Time tes 0 ns WRITE CYCLE TIMING Address Hold Time tan | 150 ns Figures 3 and 4 show the write cycle timing relationships. A Data Hold Time - tH 10 ns write cycle begins with address application, write enable and Chip Select Hold Time tc 9 ns chip select. Chip select is accomplished by placing the CS line Data Set-up Time tos 100 ns low. Write enable consists of setting the WE line low. The Output Enable Set-up Time toes 0 ns write cycle begins when the last of either CS or WE goes low. Output Enable Hold Time toEH 0 ns The WE line transition from high to low also initiates an Byte Load Cycle tL 1 ps internal 150 psec_delay timer to permit page mode operation. Reset High Time tRES 1 us Each subsequent WE transition from high to low that occurs Reset Protect Time tre | 100 us before the completion of the 150 usec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE FIG. 3 WRITE WAVEFORMS WE CONTROLLED ADDRESS DATA IN Vec FIG. 4 WRITE WAVEFORMS CS CONTROLLED ADDRESS DATA IN RY/BY RESET Vec White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 4WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE ee 2. The WME128K8-XXXE stores data at the memory location determined by the address pins. When CS and OE are low and WE is high, this data is present on the outputs. When CS and OE are high, the outputs are in ahigh impedance state. This two line control prevents bus contention. AC READ CHARACTERISTICS (Vec = 5.0V, Vss= OV, TA= -55C to +125C} Read Cycle Parameter Symbol -150 -200 -250 -300 Unit Min Max Min Max Min Max Min Max Read Cycle Time tre 150 200 250 300 ns Address Access Time tacc 150 200 250 300 ns Chip Select Access Time tacs 150 200 250 300 ns Output Hold from Add. Change, OE or CS tou 0 0 0 0 ns Output Enable to Output Valid TOE 10 15 10 15 10 85 10 85 ns Chip Select or OE to High Z Output {DF 55 55 70 70 ns RESET Low to Output Float TDFR 350 350 350 350 ns RESET to Output Delay TRR 450 450 450 450 ns FIG. 5 READ WAVEFORMS tac ADDRESS ADDRESS VALID cs OE fe Mt HIGH Z + OUTPUT MM OUTPUT { VALID p _ tar "1 | RESET DFR NOTES: OE may be delayed up to tacs - toe after the falling edge of CS without impact on toe or by tacc - toe after an address change without impact on tacc. 5 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE DATA POLLING The WME128K8-XXXE offers a data polling feature which allows a faster method of writing to the device. Figure 6 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D? (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. DATA POLLING CHARACTERISTICS (Vec= 5.0V, Vss= OV, TA= -55C to +125C) Parameter Symbol | Min | Max | Unit Data Hold Time {DH 10 ns OE Hold Time tOEH 0 ns OE To Output Valid TOE 55 ns FIG. 6 DATA POLLING WAVEFORMS Y WE ss [\S\S\S\_ ton toe t VO7 PH HIGH Z a ae ADDRESS x x x xX. White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 6WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE PAGE WRITE OPERATION PAGE WRITE CHARACTERISTICS The WME128K8-XXXE has a page write operation that allows one (Voc= 5.0V, Vss= OV, TA= -56C to +125C) to 128 bytes of data to be written into the device and consecutively Page Mode Write Characteristics loads during the internal programming period. Successive bytes - - may be loaded in the same manner after the first data byte has Parameter - Symbol | Min | Max | Unit been loaded. An internal timer begins a time out operation at each Write Cycle Time, TYP = 6ms twe 10 |_ms write cycle. If another write cycle is completed within 30us or Address Set-up Time tas 0 ns less, a new time out period begins. Each write cycle restarts the Address Hold Time (1) taH 150 ns delay period. The write cycles can be continued as long as the Data Set-up Time tos | 100 ns interval is less than the time out period. Data Hold Time {DH 10 ns The usual procedure is to increment the least significant Write Pulse Width twe | 250 ns address lines from AQ through A6 at each write cycle. In this Byte Load Cycle Time teLe 30 | us manner a page of up to 128 bytes can be loaded in to the Byte Load Window te. | 100 us EEPROM ina burst mode before beginning the relatively long Data Latch Time io. | 300 ns interval programming cycle. ; RESET Protect Time tRP 100 us After the 30us time out is completed, the EEPROM begins an RESET High Time tres 1 us internal write cycle. During this cycle the entire page of bytes Time to Device Busy wa | 120 ns will be written at the same time. The internal programming Write Start Time tow | 460 hs cycle is the same regardless of the number of bytes accessed. 1. Page address must remain valid for duration of write cycle. FIG. 7 PAGE WRITE WAVEFORMS CS CONTROLLED ADDRESS (2) Ao-i6 taH ~ teh WE feah/ /\/ a taic two CH , rh fetocn or COBB tbH DATA IN : < + tow HIGH-Z top HIGH-Z RY/BY \ . trp RESET tRES Vec NOTES: 1 . tor and torr are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. A7- Ais are page addresses and must be same within the page write operation. 7 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE FIG. 8 SOFTWARE DATA PROTECTION ENABLE ALGORITHM LOAD DATA AA TO ADDRESS 5555 J LOAD DATA 55 TO ADDRESS 2AAA J LOAD DATA AO TO WRITES ENABLED ADDRESS 5555 J LOAD DATA XX TO ANY ADDRESS J LOAD LAST BYTE TO ENTER DATA LAST ADDRESS PROTECT STATE NOTES: 1. Data Format: D? - Do (Hex); Address Format: Ate - Ao (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 8WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE FIG. 9 SOFTWARE DATA PROTECTION DISABLE ALGORITHM EXIT DATA PROTECT STATE LOAD DATA AA TO ADDRESS 5555 J LOAD DATA 55 TO ADDRESS 2AAA J LOAD DATA 80 TO ADDRESS 5555 4 LOAD DATA AA TO ADDRESS 5555 J LOAD DATA 55 TO ADDRESS 2AAA tI LOAD DATA 20 TO ADDRESS 5555 4 LOAD DATA XX TO ANY ADDRESS J LOAD LAST BYTE TO LAST ADDRESS SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE- 128K32-XXXE has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of twc. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. HARDWARE DATA PROTECTION These features protect against inadvertent writes to the WME128K8-XXXE. These are included to improve reliability during normal operation: a) Write inhibiting _ Holding OE low and either CS or WE high inhibits write cycles. b) Noise filter Lt Pulses of <20ns (typ) on WE or CS will not initiate a write cycle. c) Protection by RESET NOTES: 1. Data Format: D? - Do (Hex); Address Format: A1s - Ao (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. 9 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE PACKAGE 101: 32 LEAD, CERAMIC SOJ 21.1 (0.830) + 0.25 (0.010) 3.96 (0.156) MAX 0.89 (0.035) Radius TYP 9.55 (0.376) + 0.25 (0.010) 0.2 (0.008) ab AT Co dd td ad ad ad ad ad a ad od rd +0.05 (0.002) 11.3 (0.446) +0.2 (0.009) L OOo oo ooo ooo PIN 1 IDENTIFIER~ r| (1.27 0.050) TYP 19.1 (0.750) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 1.27 (0.050) + 0.25 (0.010) PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED ooo ooo oo ooo a |g 42.4 (1.670) + 0.4 (0.016) > 15.04 (0.592) __ +0.3 (0.012) a t A asa (0.171) 0.79 (0.031) f PIN 1 IDENTIFIER r Sh 22 (0.125) MIN yp 0.25 (0.010) 0.84 (0.033) ++ 0.05 (0.002) ~~ ~ 0.4 (0.014) 15.25 (0.600) 2.5 (0.100) 1.27 (0.050) 0.46 (0.018) [* +0.25 (0.010) TYP +0.1 (0.005) +0.05 (0.002) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 10WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE ORDERING INFORMATION WME 128 K 8 - XXX XX E X LEAD FINISH: Blank = Gold plated leads A= Solder dip leads E = Epitaxial Layer DEVICE GRADE: Q = MIL-STD-883 Compliant M = Military Screened = -55C to +125C | = Industrial -40C to +85C C = Commercial 0 to +70C PACKAGE TYPE: C = 32 Pin Ceramic DIP (Package 300) DE = 32 Lead CSOU (Package 101) ACCESS TIME (ns) ORGANIZATION 128K x 8 EEPROM MONOLITHIC WHITE MICROELECTRONICS 11 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520