S524L50X51
16K-bit
Serial EEPROM
Data Sheet
5-1
OVERVIEW
The S524L50X51 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I2C™-bus serial
interface. It is fabricated using Samsung’s most advanced CMOS technology. One of its major features is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into
the EEPROM in a single write operation. Another significant feature of the S524L50X51 is its support for fast
mode and standard mode.
FEATURES
I2C-Bus Interface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 16 Kbits (2,048 bytes) storage area
• 16-byte page buffer
• Typical 3 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• EEPROM programming voltage generated
on chip
• 1,000,000 erase/write cycles
• 100 years data retention
Operating Characteristics
• Operating voltage: 2.0 V to 5.5 V
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 2 µA at 2.0 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
• Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 400 V (MM)
Packages
• 8-pin DIP, SOP, and TSSOP
S524L50X51 SERIAL EEPROM DATA SHEET
5-2
Start/Stop
Logic
Slave Address
Comparator Word Address
Pointer Row
decoder
EEPROM
Cell Array
2,048 x 8 bits
HV Generation
Timing Control
Control Logic
Column Decoder
Data Register
DOUT and ACK
SCL
WP
SDA
A0
A1
A2
Figure 5-1. S524L50X51 Block Diagram
DATA SHEET S524L50X51 SERIAL EEPROM
5-3
S524L50X51
VCC WP SCL SDA
A0 A1 A2 VSS
NOTE: The S524L50X51 is available in
8-pin DIP, SOP, and TSSOP package.
Figure 5-2. Pin Assignment Diagram
Table 5-1. S524L50X51 Pin Descriptions
Name Type Description Circuit
Type
A0, A1, A2
– No internal connection –
VSS – Ground pin. –
SDA I/O Bi-directional data pin for the I2C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor
must be connected to VDD.
3
SCL Input Schmitt trigger input pin for serial clock input. 2
WP Input Input pin for hardware write protection control. If you tie this pin to
VCC, the write function is disabled to protect previously written data
in the entire memory; if you tie it to VSS, the write function is
enabled. This pin is internally pulled down to VSS.
1
VCC – Single power supply. –
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
S524L50X51 SERIAL EEPROM DATA SHEET
5-4
WP
Figure 5-3. Pin Circuit Type 1
SCL Noise
Filter
Figure 5-4. Pin Circuit Type 2
SDA
VSS
Data Out
Noise
Filter Data In
Figure 5-5. Pin Circuit Type 3
DATA SHEET S524L50X51 SERIAL EEPROM
5-5
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524L50X51 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Only one S524L50X51 devices can be connected to the I2C-bus as slaves (see Figure 5-
6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines
which bus operating mode would be active.
SDA
R
V
CC
R
V
CC
SCL
S524L50X51
Slave
Bus Master
(Transmitter/
Receiver)
Master
Figure 5-6. Typical Configuration
S524L50X51 SERIAL EEPROM DATA SHEET
5-6
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remains stable whenever the clock line (SCL) is High.
The I2C-bus interface supports the following communication protocols:
• Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active.
• Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in
High level. All bus commands must be preceded by a start condition.
• Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in
High level. All bus operations must be completed by a stop condition (see Figure 5-7).
SCL
SDA
Start
Condition Data or
ACK Valid Data
Change
~
~~
~
Stop
Condition
Figure 5-7. Data Transmission Sequence
• Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.
• ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits
of data (see Figure 5-8). But the slave does not send an ACK if an internal write cycle is still in progress.
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition
to be issued by the master before returning to its stand-by mode.
DATA SHEET S524L50X51 SERIAL EEPROM
5-7
Master
SCL Line
Data from
Transmitter
ACK
ACK from
Receiver
Bit 9Bit 1
Figure 5-8. Acknowledge Response From Receiver
• Slave Address: After the master initiates a start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier.” The identifier
for the S524L50X51 is “1010B”. The next three bits (B2, B1, B0) are for block selection. They are used by the
master to select which of the blocks of internal memory (1 block=256 words) are to be accessed. (see Table
5-2 below.) These bits are in effect the three most significant bits of the word address.
• Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Table 5-2. Slave Address Byte
Function Device Identifier Block Select R/W Bit
b7
b6
b5
b4
b3 b2 b1 b0
Read 1 0 1 0 B2 B1 B0 1
Write 1 0 1 0 B2 B1 B0 0
S524L50X51 SERIAL EEPROM DATA SHEET
5-8
BYTE WRITE OPERATION
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the S524L50X51 slave device (see Figure 5-9).
Slave Address Word AddressStart
A
C
K
A
C
K
Data Stop
A
C
K
Figure 5-9. Byte Write Operation
Following a start condition, the master sends the device identifier (4 bits), three “don’t care” bits, and an R/W bit
set to “0” onto the bus. Then the addressed S524L50X51 generates an ACK, and waits for the next byte. The next
byte to be transmitted by the master is the word address. This 8-bit address is written into the word address
pointer of the S524L50X51.
When the S524L50X51 receives the word address, it responds by issuing an ACK and then waits for the next 8-
bit data. When it receives the data byte, the S524L50X51 again responds with an ACK. The master terminates
the transfer by generating a Stop condition, at which time the S524L50X51 begins the internal write cycle.
While the internal write cycle is in progress, all S524L50X51 inputs are disabled and the S524L50X51 does not
respond to any additional request from the master.
DATA SHEET S524L50X51 SERIAL EEPROM
5-9
PAGE WRITE OPERATION
The S524L50X51 can also perform 16-byte page write operation. A page write operation is initiated in the same
way as a byte write operation. However, instead of finishing the write operation after the first data byte is
transferred, the master can transmit up to 15 additional bytes. The S524L50X51 responds with an ACK each time
it receives a complete byte of data (see Figure 5-10).
Slave AddressStart
A
C
K
Word Address n
A
C
K
Data (<= n + 15) Stop
A
C
K
A
C
K
...
Data n
A
C
K
Figure 5-10. Page Write Operation
The S524L50X51 automatically increments the word address pointer each time it receives a complete data byte.
When one byte is received, the internal word address pointer increments to the next address so that the next data
byte can be received.
If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation,
the S524L50X51 word address pointer value “rolls over” and the previously received data is overwritten. If the
master transmits less than 16 bytes and generates a stop condition, the S524L50X51 writes the received data to
the corresponding EEPROM address.
During a page write operation, all inputs are disabled and there would be no response to additional requests from
the master until the internal write cycle is completed.
S524L50X51 SERIAL EEPROM DATA SHEET
5-10
POLLING FOR AN ACK SIGNAL
When the master issues a stop condition to initiate a write cycle, the S524L50X51 starts an internal write cycle.
The master can then immediately begin polling for an ACK from the slave device to determine whether the write
cycle is completed.
To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address.
As long as the S524L50X51 remains busy with the write operation, no ACK is returned. When the S524L50X51
completes the write operation, it returns an ACK and the master can then proceed with the next read or write
operation (see Figure 5-11).
Send Write
Command
Send Stop Condition to
Initiate Write Cycle
Send Start
Condition
Send Slave Address
with R/
W
bit = "0"
Start Next
Operation
ACK = "0" ?
Yes
No
Figure 5-11. Master Polling for an ACK Signal from a Slave Device
DATA SHEET S524L50X51 SERIAL EEPROM
5-11
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524L50X51. This method of write protection is
controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The S524L50X51 will acknowledge slave and word address, but it will not generate an acknowledge after
receiving first byte of data. In this situation the write cycle will not be started when a stop condition is generated.
By connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to protect data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
The WP pin is internally pulled down to VSS.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the S524L50X51 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends eight bits
of data. In a current address byte read operation the master does not acknowledge the data, and it generates a
Stop condition, forcing the S524L50X51 to stop the transmission (see Figure 5-12).
Slave Address DataStart
A
C
K
N
O
A
C
K
Stop
Figure 5-12. Current Address Byte Read Operation
S524L50X51 SERIAL EEPROM DATA SHEET
5-12
RANDOM ADDRESS BYTE READ OPERATION
Using random read operations, the master can access any memory location at any time. Before it issues the
slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. This operation
is performed in the following steps:
1. The master first issues a start condition, the slave address, and the word address to be read. (This step sets
the internal word address pointer of the S524L50X51 to the desired address.)
2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed
by another slave address, with the R/W bit set to “1”.
3. The S524L50X51 then sends an ACK and the 8-bit data stored at the pointed address.
4. At this point, the master does not acknowledge the transmission, generating a stop condition.
5. The S524L50X51 stops transmitting data and reverts to stand-by mode (see Figure 5-13).
Word
Address
Slave
AddressStart
A
C
K
A
C
K
A
C
K
Stop
Slave
AddressStart Data (n)
N
O
A
C
K
Figure 5-13. Random Address Byte Read Operation
DATA SHEET S524L50X51 SERIAL EEPROM
5-13
SEQUENTIAL READ OPERATION
Sequential read operations can be performed in two ways: current address sequential read operation, and
random address sequential read operation. The first data is sent in either of the two ways, current address byte
read operation or random address byte read operation described earlier. If the master responds with an ACK, the
S524L50X51 continues transmitting data. If the master does not issue an ACK, generating a stop condition, the
slave stops transmission, ending the sequential read operation.
Using this method, data is output sequentially from address “n” followed by address “n+1”. The word address
pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially
in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the S524L50X51
continues to transmit data for each ACK it receives from the master (see Figure 5-14).
Slave Address Data (n)Start
A
C
K
N
O
A
C
K
StopData (n+x)
A
C
K
A
C
K
~
~
Figure 5-14. Sequential Read Operation
S524L50X51 SERIAL EEPROM DATA SHEET
5-14
ELECTRICAL DATA
Table 5-3. Absolute Maximum Ratings
(TA = 25 °C)
Parameter Symbol
Conditions Rating Unit
Supply voltage VCC – – 0.3 to + 7.0 V
Input voltage VIN – – 0.3 to + 7.0 V
Output voltage VO – – 0.3 to + 7.0 V
Operating temperature TA – – 40 to + 85 °C
Storage temperature TSTG – – 65 to + 150 °C
Electrostatic discharge VESD HBM 5000 V
MM 400
Table 5-4. D.C. Electrical Characteristics
(TA = – 25 °C to + 70 °C (Commercial), – 40 °C to + 85 °C (Industrial), VCC = 2.0 V to 5.5 V)
Parameter Symbol
Conditions Min Typ Max Unit
Input low voltage VIL SCL, SDA – – 0.3 VCC
V
Input high voltage VIH 0.7 VCC
– – V
Input leakage current ILI VIN = 0 to VCC – – 10 µA
Output leakage current ILO VO = 0 to VCC – – 10 µA
Output Low voltage VOL IOL = 3 mA, VCC = 2.0 V – – 0.4 V
Supply current Write
ICC1 VCC = 5.5 V, 400 kHz – – 3 mA
ICC2 VCC = 2.0 V, 100 kHz – – 1
Read
ICC3 VCC = 5.5 V, 400 kHz – – 0.2
ICC4 VCC = 2.0 V, 100 kHz – – 60 µA
Stand-by current ICC5 VCC = SDA = SCL = 5.5 V,
all other inputs = 0 V – – 5 µA
ICC6 VCC = SDA = SCL = 2.0 V,
all other inputs = 0 V – – 2
DATA SHEET S524L50X51 SERIAL EEPROM
5-15
Table 5-4. D.C. Electrical Characteristics (Continued)
(TA = – 25 °C to + 70 °C (Commercial), – 40 °C to + 85 °C (Industrial), VCC = 2.0 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Input capacitance CIN 25 °C, 1MHz,
VCC = 5 V, VIN = 0 V,
A0, A1, A2, SCL and WP pin
– – 10 pF
Input/Output capacitance CI/O 25 °C, 1MHz,
VCC = 5 V, VI/O = 0 V,
SDA pin
– – 10
Table 5-5. A.C. Electrical Characteristics
(TA = – 25 °C to + 70 °C (Commercial), – 40 °C to + 85 °C (Industrial), VCC = 2.0 V to 5.5 V)
Parameter Symbol
Conditions
VCC = 2.0 to 5.5 V
(Standard Mode) VCC = 4.5 to 5.5 V
(Fast Mode) Unit
Min Max Min Max
External clock frequency Fclk – 0 100 (1) 0 400 (1) kHz
Clock High time tHIGH – 4 – 0.6 – µs
Clock Low time tLOW – 4.7 – 1.3 – µs
Rising time tR SDA, SCL – 1 – 0.3 µs
Falling time tF SDA, SCL – 0.3 – 0.3 µs
Start condition hold time tHD:STA
– 4 – 0.6 – µs
Start condition setup time tSU:STA
– 4.7 – 0.6 – µs
Data input hold time tHD:DAT
– 0 – 0 – µs
Data input setup time tSU:DAT
– 0.25 – 0.1 – µs
Stop condition setup time tSU:STO
– 4 – 0.6 – µs
Bus free time tBUF Before new
transmission
4.7 – 1.3 – µs
Data output valid from
clock low (2) tAA – 0.3 3.5 – 0.9 µs
Noise spike width tSP – – 100 – 50 ns
Write cycle time tWR – – 5 – 5 ms
NOTES:
1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available.
2. When acting as a transmitter, the S524L50X51 must provide an internal minimum delay time to bridge the undefined
period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop
condition.
S524L50X51 SERIAL EEPROM DATA SHEET
5-16
SCL tLOW
tFtR
SDA In
tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO
tHIGH
SDA Out
tBUFtAA
Figure 5-15. Timing Diagram for Bus Operations
8th Bit
WORDn
SCL
SDA
Start
Condition
~
~ ~
~~
~
t
WR
Stop
Condition
ACK
Figure 5-16. Write Cycle Timing Diagram
DATA SHEET S524L50X51 SERIAL EEPROM
5-17
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do
not, however, represent guaranteed operating values.
(Frequency = 100 kHz)
VCC (V)
ICC (mA)
0
0.4
0.8
1.2
1.6
2.0
1.5 2.5 3.5 4.5 5.5
Temp = -40 C
Temp = -25 C
Temp = 25 C
Temp = 70 C
Temp = 85 C
Figure 5-17. Write Current
S524L50X51 SERIAL EEPROM DATA SHEET
5-18
(Frequency = 100 kHz)
VCC (V)
ICC (uA)
0
40
80
100
120
140
1.5 2.5 3.5 4.5 5.5
Temp = -40 C
Temp = -25 C
Temp = 25 C
Temp = 70 C
Temp = 85 C
60
20
Figure 5-18. Read Current
(Frequency = 100 kHz)
VCC (V)
ICC (uA)
0
0.3
0.6
0.9
1.2
1.5
1.5 2.5 3.5 4.5 5.5
Temp = -40 C
Temp = -25 C
Temp = 25 C
Temp = 70 C
Temp = 85 C
Figure 5-19. Stand-by Current
DATA SHEET S524L50X51 SERIAL EEPROM
5-19
IOL (mA)
VOL (V)
(TA = 25 C)
1 2 3 4 60 5
VDD = 2 V
VDD = 3 V
VDD = 4 V
VDD = 5 V
VDD = 6 V
0
10
20
30
40
70
50
60
Figure 5-20. Output Low Voltage
S524L50X51 SERIAL EEPROM DATA SHEET
5-20
NOTES
