HY534256A
256Kx4, Fast Page mode
This family is a 1M bit dynamic RAM organized 262,144 x 4-bit configuration with Fast Page mode CMOS
DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design
allow this device to achieve high performance and low power dissipation. Optional features are access time(45, 50 or 60ns)
and power consumption (Normal or Low power). Hyundai’s advanced circuit design and process technology allow this
device to achieve high bandwidth, low power consumption and high reliability.
DESCRIPTION
FEATURES
Ÿ Fast Page Mode operation
Ÿ Read-modify-write Capability
Ÿ TTL compatible inputs and outputs
Ÿ /CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ Max. Active power dissipation
Speed
45
Power
550mW
Ÿ Fast access time and cycle time
Speed
45
50
tRAC
45ns
50ns
tCAC
15ns
15ns
tPC
30ns
33ns
Ÿ Refresh cycle
Part number
HY534256A
Refresh
512
Normal
8ms
L-part
64ms
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Rev.10 / Jan.98
ORDERING INFORMATION
Part Name
HY534256AJ
Refresh
512
Power
Package
20/26Pin SOJ
HY534256ALJ 512 L-part 20/26Pin SOJ
50 495mW
Hyundai Semiconductor
Ÿ JEDEC standard pinout
Ÿ 20/26-pin SOJ (300mil)
Ÿ Single power supply of 5V ± 10%
Ÿ Early Write or output enable controlled write
1
*L : Low power
60 440mW 60 60ns 15ns 40ns
HY534256A
FUNCTIONAL BLOCK DIAGRAM
WE
CAS
OE
Data Input Buffer Data Output Buffer
CAS Clock
Generator
Cloumn
Predecoder
(9)
Refresh Controller
Refresh Counter
(9)
Column Decoder
Sense Amp
I/O Gate
Memory Array
262,144 x 4
Row
Decoder
Row Predecoder
(9)
RAS Clock
Generator Substrate Bias
Generator VCC
VSS
Address Buffer
RAS
DQ0 ~ DQ3
9
9
48
4 4
A0
A1
A2
2
A3
A4
A5
A6
A7
A8
4
256Kx4,FP DRAM
Rev.10 / Jan.98
HY534256A
PIN CONFIGURATION (Marking Side)
PIN DESCRIPTION
/RAS
/CAS
Row Address Strobe
Column Address Strobe
/WE Write Enable
/OE Output Enable
A0~A8 Address Input
DQ0~DQ3 Data In/Out
Vcc Power (5V)
Vss Ground
Pin Name Parameter
3
20/26 Pin Plastic SOJ (300mil)
DQ0
DQ1
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
VSS
DQ3
DQ2
CAS
OE
A8
A7
A6
A5
A4
WE
256Kx4,FP DRAM
Rev.10 / Jan.98
HY534256A
ABSOLUTE MAXIMUM RATINGS
Symbol
TA
Parameter
Ambient Temperature
Rating
0 to 70
Unit
°C
TSTG Storage Temperature -55 to 145 °C
VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V
VCC Voltage on VCC relative to VSS -1.0 to 7.0 V
IOS Short Circuit Output Current 50 mA
PDPower Dissipation 0.9 W
TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec
Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability
Symbol
ILI
Parameter
Input Leakage Current
(Any input)
Unit
µA
Min
-10
Max
10
Test condition
VSS ≤ VIN ≤ VCC + 1.0
All other pins not under test = VSS
DC OPERATING CHARACTERISTICS
ILO Output Leakage Current
(Any input) µA-10 10
VSS ≤ VOUT ≤ VCC
/RAS & /CAS at VIH
VOL Output Low Voltage V-0.4IOL = 4.2mA
VOH Output High Voltage V2.4 -IOH = -5.0mA
4
RECOMMENDED DC OPERATING CONDITIONS
Symbol
VCC
Parameter
Power Supply Voltage
UNIT
V
Max
5.5
Typ
5.0
Min
4.5
VIH Input High Voltage VVCC+1.0-2.4
VIL Input Low Voltage V0.8--1.3
Note : All voltages are referenced to VSS.
(TA = 0°C to 70°C )
256Kx4,FP DRAM
Rev.10 / Jan.98
HY534256A
DC CHARACTERISTICS
Symbol
ICC1
Parameter
Operating Current
Speed
45
50
60
Unit
mA
(TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.)
Note
100
90
80
Test condition
/RAS, /CAS Cycling
tRC = tRC(min)
Max.
ICC2 TTL Standby
Current mA2
/RAS, /CAS ≥ VIH(min)
Other inputs ≥ VSS
ICC3 /RAS-only Refresh
Current
45
50
60 mA
100
90
80
/RAS Cycling,/CAS = VIH
tRC = tRC(min)
ICC4 Fast Page mode Current 45
50
60 mA
80
70
60
/CAS Cycling, /RAS = VIL
tPC = tPC(min)
ICC5 CMOS Standby
Current
L-part mA
µA
1
200
/RAS = /CAS ≥ VCC - 0.2V
ICC6 /CAS-before-/RAS
Refresh Current
45
50
60 mA
100
90
80
/RAS & /CAS = 0.2V
tRC = tRC(min.)
ICC7 Battery Back-up
Current (SL-part) µA
tRC=125µs
/CAS = CBR cycling or 0.2V
/OE & /WE = VCC - 0.2V
Address = Vcc-0.2V or 0.2V
DQ0~DQ3 = Vcc-0.2, 0.2V or Open
1. ICC1, ICC3, ICC4, ICC6 and Icc7 depend on output loading and cycle rates(tRC and tPC).
2. Specified values are obtained with output unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH within one cycle time tPC.
4. Only tRAS(max) = 1µs is applied to refresh of battery backup but tRAS(max) = 10µs is to applied to normal functional
operation.
5. Icc5(max.), Icc7 are applied to L-part only.
5
300
256Kx4,FP DRAM
Rev.10 / Jan.98
tRAS ≤
300ns
tRAS ≤
1us 400
tRC Random read or write cycle time 90 ns
Symbol Parameter Min Max Min Max Unit Note
50ns 60ns
AC CHARACTERISTICS
(TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.)
HY534256A
Read-modify-write cycle time 145
Fast Page mode cycle time 33
Fast Page mode read-modify-write cycle time 90
Access time from /RAS -
Access time from /CAS -
Access time from column address -
Access time from /CAS precharge -
/CAS to output low impedance
tRWC
tPC
tPRWC
tRAC
tCAC
tAA
tCPA
tCLZ 0
-
-
-
-
50
15
27
32
-
110
165
40
95
-
-
-
-
0
-
-
-
-
60
15
30
35
-
ns
ns
ns
ns
ns
ns
ns
ns
6
4,9,10
4,9
4,10
4
5
45ns
80
Min Max
135
30
90
-
-
-
-
0
-
-
-
-
45
15
25
30
-
Transition time(rise and fall)
/RAS precharge time
/RAS pulse width
/RAS pulse width(Fast Page Mode)
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
/CAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to /RAS lead time
Read command set-up time
Read command hold time referenced to /CAS
tT
tRP
tRAS
tRASP
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
2
25
50
50
15
50
15
13
11
5
10
0
8
0
10
27
0
0
50
-
10K
100K
-
-
10K
35
12
-
-
-
-
-
-
-
-
-
2
30
60
60
15
60
20
13
11
5
10
0
10
0
15
30
0
0
50
-
10K
100K
-
-
10K
45
30
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
10
13
6
Read command hold time referenced to /RAStRRH 0-0-ns 6
Write command hold time
Write command pulse width
tWCH
tWP
10
10
-
-
10
10
-
-
ns
ns
2
25
45
45
15
45
15
13
11
5
10
0
8
0
10
25
0
0
50
-
10K
100K
-
-
10K
30
20
-
-
-
-
-
-
-
-
-
0-
10
10
-
-
Write command hold time from /RAStWCR 40 -50 -ns
35 -
Column address hold time from /CAStAR 35 -40 -ns
30 -
Write command to /RAS lead timetRWL 15 -20 -ns
15 -
256Kx4,FP DRAM
Rev.10 / Jan.98
Output Buffer Turn-off Dealy TimetOFF 0 15 0 20 ns 3
0 15
Symbol Parameter Min Max Min Max Unit Note
60ns 70ns
AC CHARACTERISTICS
Continued
HY534256A
Data-in set-up time
Data-in hold time
Refresh period(512 cycles)
Refresh period(L-part)
Write command set-up time
/CAS to /WE delay time
/RAS to /WE delay time
Column address to /WE delay time
/CAS set-up time(CBR cycle)
/CAS hold time(CBR cycle)
/RAS to /CAS precharge time
/RAS hold time referenced to /OE
/OE access time
/OE to data delay
Output buffer turn-off delay time from /OE
/OE command hold time
/WE delay time from /CAS precharge
/RAS hold time from /CAS precharge
tDS
tDH
tREF
tWCS
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tROH
tOEA
tOED
tOEZ
tOEH
tCPWD
tRHCP
0
10
8
64
0
45
80
57
5
10
10
10
-
10
0
15
52
22
-
-
-
-
-
-
-
-
-
-
-
-
15
-
10
-
-
-
0
10
8
64
0
45
90
60
5
10
10
10
-
10
0
15
52
22
-
-
-
-
-
-
-
-
-
-
-
-
15
-
10
-
-
-
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
7
11
11
8
8
8
8
8
Min Max
0
10
8
64
0
45
75
55
5
10
10
10
-
10
0
15
52
22
-
-
-
-
-
-
-
-
-
-
-
-
15
-
10
-
-
-
50ns
/CAS Hold Time (CBR Cycle)tCHR 10 -10 -ns
10 -
tCWL Write command to /CAS lead time ns15 -15 -
15 -
256Kx4,FP DRAM
Rev.10 / Jan.98
HY534256A
NOTE
8
CAPACITANCE
Symbol
CIN1
Parameter
Input Capacitance (A0~A8)
Max
5
Unit
pF
CIN2 Input Capacitance (/RAS, /LCAS,/UCAS, /WE, /OE) 7pF
CDQ Data Input / Output Capacitance (DQ0~DQ3) 7pF
(TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.)
Typ.
-
-
-
256Kx4,FP DRAM
Rev.10 / Jan.98
1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of
8 /RAS-only refresh cycles are required.
2. AC measurements assume tT=3ns
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.).
4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF.
5. tOFF(max.) defines the time at which the output achieves in early write cycles and to /WE leading edge in Read-
Modify-Write cycles.
6. Either tRCH or tRRH must be satisfied for a read cycle.
7. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in
read-modify-write cycles.
8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
9. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.
10.Operation within the tRAD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference
point only. tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.
11.tREF(max.)=64ms is applied to L-parts only.(HY534256ALJ)
