LTC2756 Serial 18-Bit SoftSpan IOUT DAC Features Description Maximum 18-Bit INL Error: 1 LSB Over Temperature nn Program or Pin-Strap Six Output Ranges: 0V to 5V, 0V to 10V, -2.5V to 7.5V, 2.5V, 5V, 10V nn Guaranteed Monotonic Over Temperature nn Glitch Impulse 0.4nV * s (3V), 2nV * s (5V) nn 18-Bit Settling Time: 2.1s nn 2.7V to 5.5V Single Supply Operation nn Reference Current Constant for All Codes nn Voltage-Controlled Offset and Gain Trims nn Serial Interface with Readback of All Registers nn Clear and Power-On-Reset to 0V Regardless of Output Range nn 28-Pin SSOP Package The LTC(R)2756 is an 18-bit multiplying serial-input, current-output digital-to-analog converter. LTC2756A provides full 18-bit performance--INL and DNL of 1LSB maximum--over temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. This SoftSpanTM DAC operates from a single 3V to 5V supply and offers six output ranges (up to 10V) that can be programmed through the 3-wire SPI serial interface or pin-strapped for operation in a single range. Applications Voltage-controlled offset and gain adjustments are also provided; and the power-on reset circuit and CLR pin both reset the DAC output to 0V regardless of output range. nn Instrumentation Medical Devices nn Automatic Test Equipment nn Process Control and Industrial Automation nn Any on-chip register (including DAC output-range settings) can be read for verification in just one instruction cycle; and if you change register content, the altered register will be automatically read back during the next instruction cycle. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. nn Typical Application 18-Bit Voltage Output DAC with Software-Selectable Ranges LTC2756 Integral Nonlinearity 1.0 REF 5V + 0.6 LT1012 - 0.4 150pF RCOM REF ROFS INL (LSB) RIN RFB 4 LTC2756 5V 18-BIT DAC WITH SPAN SELECT VDD IOUT1 - IOUT2 + GND 0 -0.2 -0.6 -0.8 LT1468 GND 0.1F 0.2 -0.4 27pF SPI WITH READBACK 0V TO 10V RANGE 0.8 VOUT -1.0 0 65536 131072 CODE 196608 262143 2756 TA01b VOSADJ GEADJ 2756 TA01a GAIN ADJUST OFFSET ADJUST 2756fa For more information www.linear.com/LTC2756 1 LTC2756 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) IOUT1, IOUT2 to GND................................................0.3V RIN, RCOM, REF, RFB, ROFS, VOSADJ, GEADJ to GND.......................................................... 18V VDD to GND................................................... -0.3V to 7V Digital Inputs to GND.................................... -0.3V to 7V Digital Outputs to GND ..... -0.3V to VDD +0.3V (Max 7V) Operating Temperature Range LTC2756C................................................. 0C to 70C LTC2756I..............................................-40C to 85C Maximum Junction Temperature........................... 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec).................... 300C TOP VIEW ROFS 1 28 RFB REF 2 27 RFB RCOM 3 26 IOUT1 GEADJ 4 25 VOSADJ RIN 5 24 GND GND 6 23 LDAC IOUT2 7 22 S2 GND 8 21 S1 CS/LD 9 20 S0 SDI 10 19 M-SPAN SCK 11 18 RFLAG SRO 12 17 CLR GND 13 16 GND VDD 14 15 GND G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 150C, JA = 95C/W Order Information LEAD FREE FINISH TAPE AND REEL LTC2756BCG#PBF LTC2756BCG#TRPBF LTC2756BIG#PBF LTC2756BIG#TRPBF LTC2756ACG#PBF LTC2756ACG#TRPBF LTC2756AIG#PBF LTC2756AIG#TRPBF http://www.linear.com/product/LTC2756#orderinfo PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2756G 28-Lead Plastic SSOP 0C to 70C LTC2756G 28-Lead Plastic SSOP -40C to 85C LTC2756G 28-Lead Plastic SSOP 0C to 70C LTC2756G 28-Lead Plastic SSOP -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 2756fa For more information www.linear.com/LTC2756 LTC2756 Electrical Characteristics VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. SYMBOL PARAMETER CONDITIONS MIN LTC2756B TYP MAX MIN LTC2756A TYP MAX UNITS Static Performance Resolution l 18 18 18 Bits 18 Bits Monotonicity l DNL Differential Nonlinearity l 1 0.25 1 LSB INL Integral Nonlinearity l 2 0.5 1 LSB GE Gain Error All Output Ranges 5 28 Gain Error Temperature Coefficient Gain/Temp Bipolar Zero Error All Bipolar Ranges l Unipolar Zero-Scale Error Unipolar Ranges (Note 3) l PSR Power Supply Rejection VDD = 5V, 10% VDD = 3V, 10% l l ILKG IOUT1 Leakage Current TA = 25C TMIN to TMAX l BZE 40 l 0.25 Bipolar Zero Temperature Coefficient 0.25 24 2.5 3.2 0.03 3.2 LSB 1.6 4 0.05 0.2 0.8 2 LSB/V LSB/V 2 5 0.05 2 5 0.15 0.03 LSB ppm/C 16 0.15 0.05 LSB ppm/C nA nA VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Pins Reference Inverting Resistors (Note 4) l 16 20 k RREF DAC Input Resistance (Notes 5, 6) l 8 10 k RFB Feedback Resistors (Note 6) l 8 10 k ROFS Bipolar Offset Resistors (Note 6) l 16 20 k RVOSADJ Offset Adjust Resistors l 1024 1280 k RGEADJ Gain Adjust Resistors l 2048 CIOUT1 Output Capacitance 2560 k Full-Scale Zero-Scale 90 40 pF Output Settling Time Span Code = 0000, 10V Step. To 0.0004% FS (Note 7) 2.1 s Glitch Impulse VDD = 5V (Note 8) VDD = 3V (Note 8) 2 0.4 nV*s nV*s Digital-to-Analog Glitch Impulse VDD = 5V (Note 9) VDD = 3V (Note 9) 2.6 0.6 nV*s nV*s Reference Multiplying BW 0V to 5V Range, Code = Full Scale, -3dB Bandwidth 1 MHz Multiplying Feedthrough Error 0V to 5V Range, VREF = 10V, 10kHz Sine Wave 0.4 mV Total Harmonic Distortion (Note 10) Multiplying Output Noise Voltage Density (Note 11) at IOUT1 Dynamic Performance THD -108 13 dB nV/Hz 2756fa For more information www.linear.com/LTC2756 3 LTC2756 Electrical Characteristics VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VDD Supply Voltage IDD Supply Current, VDD Digital Inputs = 0V or VDD l VIH Digital Input High Voltage 3.3V VDD 5.5V 2.7V VDD < 3.3V l l VIL Digital Input Low Voltage 4.5V < VDD 5.5V 2.7V VDD 4.5V l l IIN Digital Input Current VIN = GND to VDD CIN Digital Input Capacitance VOH VOL l 2.7 0.5 5.5 V 1 A Digital Inputs 2.4 2 V V 0.8 0.6 V V l 1 A VIN = 0V (Note 12) l 6 pF IOH = 200A 2.7V VDD 5.5V l IOL = 200A 2.7V VDD 5.5V l Hysteresis Voltage 0.1 V Digital Outputs Timing Characteristics otherwise specifications are at TA = 25C. SYMBOL PARAMETER VDD - 0.4 V 0.4 V The l denotes specifications that apply over the full operating temperature range, CONDITIONS MIN TYP MAX UNITS VDD = 4.5V to 5.5V t1 SDI Valid to SCK Set-Up l 7 ns t2 SDI Valid to SCK Hold l 7 ns t3 SCK High Time l 11 ns t4 SCK Low Time l 11 ns t5 CS/LD Pulse Width l 9 ns t6 LSB SCK High to CS/LD High l 4 ns t7 CS/LD Low to SCK Positive Edge l 4 ns t8 CS/LD High to SCK Positive Edge l 4 ns t9 SRO Propagation Delay t10 CLR Pulse Width Low l 36 ns t11 LDAC Pulse Width Low l 15 ns t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 12) l 50 ns t13 CS/LD High to RFLAG High CLOAD = 10pF (Note 12) l 40 ns SCK Frequency 50% Duty Cycle (Note 13) l 40 MHz CLOAD = 10pF 18 l ns VDD = 2.7V to 3.3V t1 SDI Valid to SCK Set-Up l 9 ns t2 SDI Valid to SCK Hold t3 SCK High Time l 9 ns l 15 ns t4 SCK Low Time l 15 ns t5 CS/LD Pulse Width l 12 ns t6 LSB SCK High to CS/LD High l 5 ns 4 2756fa For more information www.linear.com/LTC2756 LTC2756 timing Characteristics otherwise specifications are at TA = 25C. The l denotes specifications that apply over the full operating temperature range, SYMBOL PARAMETER t7 CS/LD Low to SCK Positive Edge CONDITIONS l MIN 5 ns t8 CS/LD High to SCK Positive Edge l 5 ns t9 SRO Propagation Delay CLOAD = 10pF TYP MAX UNITS 26 l ns t10 CLR Pulse Width Low l t11 LDAC Pulse Width Low l t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 12) l 70 ns t13 CS/LD High to RFLAG high CLOAD = 10pF (Note 12) l 60 ns SCK Frequency 50% Duty Cycle (Note 13) l 25 MHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Calculation from feedback resistance and IOUT1 leakage current specifications; not production tested. In most applications, unipolar zeroscale error is dominated by contributions from the output amplifier. Note 4: Input resistors measured from RIN to RCOM; feedback resistors measured from RCOM to REF. Note 5: DAC input resistance is independent of code. Note 6: Parallel combination of the resistances from the specified pin to IOUT1 and from the specified pin to IOUT2. Note 7: Using LT1468 with CFEEDBACK = 27pF. A 0.0004% settling time of 1.8s can be achieved by optimizing the time constant on an individual basis. See Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC. 60 ns 20 ns Note 8: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1468; CFB = 50pF. Note 9: Full-scale transition; REF = 0V. Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1468. Note 11: Calculation from Vn = 4kTRB, where k = 1.38E-23 J/K (Boltzmann constant), R = resistance (), T = temperature (K), and B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full-scale. Note 12: Guaranteed by design; not production tested. Note 13: When using SRO, maximum SCK frequency fMAX is limited by SRO propagation delay t9 as follows: 1 , where t is the setup time of the receiving device. fMAX = S 2 (t 9 + tS) 2756fa For more information www.linear.com/LTC2756 5 LTC2756 Typical Performance Characteristics VDD = 5V, V(RIN) = 5V, TA = 25C, unless otherwise noted. Integral Nonlinearity (INL) 1.0 0V TO 10V RANGE 0.8 0.8 0.6 0.6 0.4 0.4 0.4 0.2 0.2 0.2 0 -0.2 INL (LSB) 0.6 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 -1.0 65536 131072 CODE 196608 262143 0 65536 131072 CODE 196608 2756 G02 INL vs Temperature 0.8 DNL vs Temperature 1.0 0V TO 10V RANGE 0.6 0.8 -INL 0 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -40 -20 0 20 40 TEMPERATURE (C) 60 +DNL -0.2 -0.4 -DNL 16 0.15ppm/C TYP 0.8 0.6 8 INL (LSB) BZE (LSB) 4 0 -4 5V 10V 2.5V -2.5V TO 7.5V -12 -16 -40 -20 0 20 40 TEMPERATURE (C) 60 80 85 2756 G07 6 16 12 -20 0 20 40 TEMPERATURE (C) 60 0 -40 80 85 -20 0 20 40 TEMPERATURE (C) 60 DNL vs Reference Voltage 1.0 5V RANGE 0.8 0.4 0.4 0.2 0.2 0 -0.2 -INL -INL -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 4 6 8 10 2756 G08 +DNL +DNL -DNL -DNL 0 -0.4 -1.0 -10 -8 -6 -4 -2 0 2 V(RIN) (V) 5V RANGE 0.6 +INL +INL 80 85 2756 G06 INL vs Reference Voltage 12 -8 20 2.5V 5V 10V 0V TO 5V 0V TO 10V -2.5V TO 7.5V 2756 G05 1.0 2756 G03 4 2756 G04 Bipolar Zero Error vs Temperature -10V TO 10V 8 -1.0 -40 80 85 0.25ppm/C TYP 24 0.2 DNL (LSB) 0 0V -5V 0V TO TO TO 5V 5V 10V OUTPUT RANGE 28 0.4 0.2 -0.2 0V TO 10V RANGE 0.6 +INL 0.4 -2.5V -2.5V TO TO 2.5V 7.5V Gain Error vs Temperature 32 GE (LSB) 1.0 262143 DNL (LSB) 0 2756 G01 INL (LSB) INL vs Output Range 1.0 0V TO 10V RANGE 0.8 DNL (LSB) INL (LSB) Differential Nonlinearity (DNL) 1.0 -1.0 -10 -8 -6 -4 -2 0 2 V(RIN) (V) 4 6 8 10 2756 G09 2756fa For more information www.linear.com/LTC2756 LTC2756 Typical Performance Characteristics VDD = 5V, V(RIN) = 5V, TA = 25C, unless otherwise noted. INL vs VDD 1.0 1.0 0V TO 10V RANGE 0.8 0.8 0.6 0 0V TO 10V RANGE -20 0.6 +INL 0.4 DNL (LSB) 0.2 0 -INL -0.2 0.2 +DNL 0 -0.2 -DNL -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 2.5 -1.0 2.5 3 3.5 4 4.5 VDD (V) 5 5.5 ATTENUATION (dB) 0.4 INL (LSB) Multiplying Frequency Response vs Digital Code DNL vs VDD -40 -60 -80 -100 ALL BITS ON D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALL BITS OFF 3 3.5 4 4.5 VDD (V) 5 2756 G10 -140 100 5.5 Mid-Scale Glitch (VDD = 3V) VOUT 5mV/DIV (AVERAGED) 2756 G14 500ns/DIV 0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. Logic Threshold vs Supply Voltage LOGIC THRESHOLD (V) 4 2 VDD = 5V 1 Supply Current vs Update Frequency 2 100 1.75 10 1.5 SUPPLY CURRENT (mA) CLR, LDAC, SDI, SCK, CS/LD TIED TOGETHER RISING 1.25 2756 G15 500ns/DIV 0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. Supply Current vs Logic Input Voltage SUPPLY CURRENT (mA) CS/LD 5V/DIV 2756 G13 LT1468 AMP; CFEEDBACK = 20pF 0V TO 10V STEP VREF = -10V; SPAN CODE = 0000 tSETTLE = 1.8s to 0.0004% (18 BITS) 10M 2nV*s TYP VOUT 5mV/DIV (AVERAGED) 3 1M Mid-Scale Glitch (VDD = 5V) CS/LD 5V/DIV CS/LD 5V/DIV 5 100k 10k FREQUENCY (Hz) 2756 G12 0.4nV*s TYP 500ns/DIV 1k 2756 G11 Settling Full-Scale Step GATED SETTLING WAVEFORM 100V/DIV (AVERAGED) 0V TO 5V OUTPUT RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 15pF -120 FALLING 1 0.75 ALTERNATING ZERO-SCALE AND FULL-SCALE 1 VDD = 5V 0.1 VDD = 3V 0.01 0.001 VDD = 3V 0 0 1 3 4 2 DIGITAL INPUT VOLTAGE (V) 5 2756 G16 0.5 2.5 3 3.5 4 4.5 5 5.5 VDD (V) 2756 G17 0.0001 1 100 10k 1M SCK FREQUENCY (Hz) 100M 2756 G18 2756fa For more information www.linear.com/LTC2756 7 LTC2756 Pin Functions ROFS (Pin 1): Bipolar Offset Resistor. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to 15V; for normal operation tie to the positive reference voltage at RIN (Pin 5). REF (Pin 2): DAC Reference Input, and Feedback Resistor for the Reference Inverting Amplifier. The external reference inverting amplifier sees as its load the 10k DAC reference input resistance in parallel with the 20k feedback resistor. For normal operation tie this pin to the output of the reference inverting amplifier (see the Typical Applications section). Typically 5V; accepts up to 15V. RCOM (Pin 3): Virtual Ground Point for the On-Chip Reference Inverting Resistors. These precision-matched 20k resistors are included on the chip to facilitate generation of the negative reference voltage needed to produce a positive output polarity. They are connected internally from RIN to RCOM and from RCOM to REF (see Block Diagram). For normal operation tie RCOM to the negative input of the external reference inverting amplifier (see the Typical Applications section). GEADJA (Pin 4): Gain Adjust Pin. This control pin can be used to null gain error or to compensate for reference errors. Nominal adjustment range is 2048 LSB for a voltage input range of VRIN (i.e., 5V for a 5V reference input). Tie to ground if not used. RIN (Pin 5): Input Resistor for Reference Inverting Amplifier. The 20k input resistor is connected internally from RIN to RCOM. For normal operation tie RIN to the external reference voltage (see the Typical Applications section). Typically 5V; accepts up to 15V. GND (Pins 6, 8, 13, 15, 16, 24): Ground; tie to ground. IOUT2 (Pin 7): Current Output Complement. Tie to ground via a clean, low-impedance path. CS/LD (Pin 9): Synchronous Chip Select and Load Input Pin. A logic low on this pin enables SDI, SCK and SRO (Pins 10, 11 and 12) for input and output of serial data. 8 SDI (Pin 10): Serial Data Input. Data is clocked in on the rising edge of the serial clock (SCK, Pin 11) when CS/LD (Pin 9) is low. SCK (Pin 11): Serial Clock. SRO (Pin 12): Serial Readback Output. Data is clocked out on the falling edge of SCK. Readback data begins clocking out after the first byte is clocked in. SRO is an active output only when the chip is selected (i.e., when CS/LD is low). Otherwise SRO presents a high-impedance output in order to allow other parts to control the bus. VDD (Pin 14): Positive Supply Input; 2.7V VDD 5.5V. Bypass with a 0.1F low-ESR capacitor to ground. CLR (Pin 17): Asynchronous Clear Input. When this pin is low, all DAC registers (both code and span) are cleared to zero. The DAC output is cleared to zero volts. RFLAG (Pin 18): Reset Flag Output. An active low output is asserted when there is a power-on reset or a clear event. Returns high when an Update command is executed. M-SPAN (Pin 19): Manual Span Control Pin. M-SPAN is used in conjunction with pins S0, S1 and S2 (Pins 20, 21 and 22) to configure the DAC for operation in a single, fixed output range. To configure the part for manual-span use, tie M-SPAN directly to VDD. The active output range is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. To configure the part for SoftSpan use, tie M-SPAN directly to GND. The output ranges are then individually controllable through the SPI port; and pins S2, S1 and S0 have no effect. See Manual Span Configuration in the Operation section. M-SPAN must be connected either directly to GND (SoftSpan configuration) or to VDD (manual-span configuration). 2756fa For more information www.linear.com/LTC2756 LTC2756 Pin Functions S0 (Pin 20): Span Bit 0 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range. These pins must be tied to either GND or VDD even if they are unused. S1 (Pin 21): Span Bit 1 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range. These pins must be tied to either GND or VDD even if they are unused. S2 (Pin 22): Span Bit 2 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range. These pins must be tied to either GND or VDD even if they are unused. LDAC (Pin 23): Asynchronous DAC Load Input. When LDAC is logic low, the DAC is updated (CS/LD must be high). VOSADJ (Pin 25): Offset Adjust Pin. This control pin can be used to null unipolar offset or bipolar zero error. The offset-voltage delta is inverted and attenuated such that a 5V control voltage applied to VOSADJ produces VOS = -2048 LSB in any output range (assumes a 5V reference voltage at RIN). See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. IOUT1 (Pin 26): Current Output Pin. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier (see the Typical Applications section). RFB (Pins 27, 28): Feedback Resistor. For normal operation tie both pins to the output of the I/V converter amplifier (see the Typical Applications section). The DAC output current from IOUT1 flows through the feedback resistor to the RFB pins. 2756fa For more information www.linear.com/LTC2756 9 LTC2756 Block Diagram 4 GEADJ 3 RCOM 2 1 REF RFB 27, 28 ROFS 2.56M 5 VOSADJ R2 20k R1 20k RIN IOUT1 18-BIT DAC WITH SPAN SELECT VDD POWER-ON RESET 14 VDD 3 SPAN REGISTERS GND (6, 8, 13, 15, 16, 24) 25 26 IOUT2 7 18 DAC REGISTER DAC REGISTER INPUT REGISTER INPUT REGISTER 3 CODE REGISTERS 18 SRO 12 CONTROL AND READBACK LOGIC RFLAG 18 M-SPAN S0 19 20 S1 21 S2 22 LDAC CS/LD SDI 23 9 10 SCK 11 CLR 17 2756 BD Timing Diagram t1 t2 t3 1 SCK t6 t4 2 31 32 t8 SDI LSB t5 t7 CS/LD t11 LDAC t9 SRO 10 Hi-Z LSB 2756 TD 2756fa For more information www.linear.com/LTC2756 LTC2756 Operation Output Ranges Input and DAC Registers The LTC2756 is a current-output, serial-input precision multiplying DAC with selectable output ranges. Ranges can either be programmed in software for maximum flexibility--the DAC can be programmed to any one of six output ranges--or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (2.5V, 5V, 10V and -2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. The output ranges for other reference voltages are easy to calculate by observing that each range is a multiple of the external reference voltage. The ranges can then be expressed: 0 to 1x, 0 to 2x, 0.5x, 1x, 2x, and -0.5x to 1.5x. The LTC2756 has two sets of double-buffered registers-- one set for the code data, and one for the output range of the DAC--plus one readback register, for a total of five registers. Double buffering provides the capability to simultaneously update the span (output range) and code, which allows smooth voltage transitions when changing output ranges. Manual Span Configuration DAC register: The Update operation copies the contents of an Input register to its associated DAC register. The contents of a DAC register directly updates the associated DAC output voltage or output range. Multiple output ranges are not needed in some applications. To configure the LTC2756 to operate in a single span without additional operational overhead, tie the M-SPAN pin directly to VDD. The active output range is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. See Figure 1 and Table 2. Each set of double-buffered registers comprises an Input register and a DAC register. Input register: The Write operation shifts data from the SDI pin into a chosen Input register. The Input registers are holding buffers; Write operations do not affect the DAC outputs. Note that updates always include both Code and Span register sets; but the values held in the DAC registers will only change if the associated Input register values have previously been altered via a Write operation. Tie the M-SPAN pin to ground for normal SoftSpan operation. VDD LTC2756 VDD M-SPAN - + S2 S1 10V S0 CS/LD SDI SCK 2756 F01 Figure 1. Using M-SPAN to Configure the LTC2756 for Single-Span Operation (10V Range Shown) 2756fa For more information www.linear.com/LTC2756 11 LTC2756 Operation Serial Interface When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock (SCK pin). The loading sequence required for the LTC2756 is one byte consisting of a 4-bit command word (C3 C2 C1 C0) and four zeros, then three bytes (24 bits) of data. When writing a code, the code data is left (MSB) justified; so that the 24-bit data field consists of 18 code bits followed by 6 don't-care bits. When writing an output range, the span data should occupy the last 4 bits of the second data byte, ordered S3 through S0. Figure 2 shows the SDI input word syntax for writing. When CS/LD is low, the SRO pin (Serial Readback Output) is an active output. The readback data begins after the first byte has been shifted in to SDI. SRO outputs a logic low from the falling edge of CS/LD until the Readback data begins. When CS/LD is high, the SRO pin presents a high impedance (three-state) output. LDAC is an asynchronous update pin. When LDAC is taken low, the DAC is updated with code and span data (data in the Input buffers is copied into the DAC buffers). CS/ LD must be high during this operation; otherwise LDAC is locked out and will have no effect. The use of LDAC is functionally identical to the serial input command. The codes for the command (C3-C0) are defined in Table 1. Readback In addition to the Code and Span register sets, the LTC2756 has one Readback register. At the end of every instruction cycle, the contents of one of the on-chip registers is copied into the Readback register and serially shifted out through the SRO pin. Readback data always appears in the 24-bit data field, starting on the falling SCK edge immediately after the first byte is shifted in on SDI. When reading a code, code data occupies the first 18 bits of the 24-bit field; and the span bits are the last four bits of the second data byte when checking the output range. In both cases, all other 12 bits in the 24-bit data field are filled by zeros. Figure 2 shows the input and readback sequences. The data outputted by SRO is always in the same position and sequence as the input data. Note, however, that this means that the SRO data shifts out one-half clock cycle earlier than the corresponding bit shifting in on SDI. For example, code bit D9, which is shifted in to SDI on the rising edge of SCK clock 17, is clocked out of SRO on the falling edge of clock 16. This allows D9 to be clocked to an external microprocessor on the rising edge of clock 17. For Read commands, the requested data is shifted out of SRO in the 3-byte (24-bit) data field immediately after the command byte. There is no instruction-cycle latency for Read commands; the data shifts out in the same instruction cycle in which it was requested. For non-read (i.e., Write and/or Update) commands, SRO automatically shifts out the contents of the buffer that was acted upon in the preceding command. This "rolling readback" default mode of operation can dramatically reduce the number of instruction cycles needed, since most commands can be verified during subsequent commands with no additional overhead. A conceptual flow diagram is shown in Figure 3. Table 1 shows, for each antecedent command, which register (`readback pointer') will be copied into the Readback register and outputted from SRO during the following instruction cycle. Span Readback in Manual Span Configuration If the Span DAC register is chosen for readback, SRO responds by outputting the actual output span; this is true whether the LTC2756 is configured for SoftSpan (M-SPAN tied to GND) or manual span (M-SPAN tied to VDD). In SoftSpan configuration, SRO outputs the span code from the Span DAC register (programmed through the SPI port). In manual span configuration, the active output range is controlled by pins S2, S1 and S0, so SRO outputs the logic values of these pins. The span code bits S2, S1 and S0 always appear in the same order and positions in the SRO output sequence; see Figure 2. 2756fa For more information www.linear.com/LTC2756 LTC2756 Operation Table 1. Command Codes C3 CODE C2 C1 C0 COMMAND READBACK POINTER- CURRENT INPUT WORD W0 READBACK POINTER- NEXT INPUT WORD W+1 0 0 1 0 Write Span Set by Previous Command Input Span Register 0 0 1 1 Write Code Set by Previous Command Input Code Register 0 1 0 0 Update Set by Previous Command DAC Span Register 0 1 1 0 Write Span; Update Set by Previous Command DAC Span Register 0 1 1 1 Write Code; Update Set by Previous Command DAC Code Register 1 0 1 0 Read Input Span Register Input Span Register Input Span Register 1 0 1 1 Read Input Code Register Input Code Register Input Code Register 1 1 0 0 Read DAC Span Register DAC Span Register DAC Span Register 1 1 0 1 Read DAC Code Register DAC Code Register DAC Code Register 1 1 1 1 No Operation Set by Previous Command DAC Code Register -- System Clear -- DAC Span Register -- Initial Power-Up or Power Interrupt -- DAC Span Register Codes not shown are reserved--do not use. Table 2. Span Codes S3 S2 S1 S0 SPAN 0 0 0 0 Unipolar 0V to 5V 0 0 0 1 Unipolar 0V to 10V 0 0 1 0 Bipolar -5V to 5V 0 0 1 1 Bipolar -10V to 10V 0 1 0 0 Bipolar -2.5V to 2.5V 0 1 0 1 Bipolar -2.5V to 7.5V Codes not shown are reserved-do not use. 2756fa For more information www.linear.com/LTC2756 13 14 SRO SRO SDI C3 SDI 0 0 C1 3 C1 0 0 0 0 COMMAND C2 READBACK SPAN Hi-Z 2 COMMAND C2 READBACK CODE Hi-Z WRITE SPAN C3 WRITE CODE 1 SCK CS/LD 0 0 C0 C0 4 0 0 0 0 5 0 0 0 0 0 0 4 ZEROS 0 4 ZEROS 0 6 7 0 0 0 0 8 0 D17 X D17 9 0 D16 X D16 10 0 0 D14 X D14 12 0 D13 X D13 X D12 14 X D11 15 0 D12 0 D11 12 DON'T-CARE 13 0 D10 X D10 D9 17 D8 18 0 D9 X 0 D8 X 19 0 D7 X D7 18-BIT DAC CODE 16 0 D6 X D6 20 S3 D5 S3 D5 21 Figure 2. Serial Input and Output Sequences D15 X D15 11 S2 D4 23 S1 D3 S1 D3 SPAN S2 D4 22 S0 D2 S0 D2 24 0 D1 X D1 25 0 D0 X D0 26 0 0 X X X X X 29 0 0 X 30 X 0 0 0 0 X 6 DON'T-CARE 28 8 DON'T-CARE 27 0 0 X X 31 0 0 X X 32 2756 F02 LTC2756 operation 2756fa For more information www.linear.com/LTC2756 LTC2756 Operation SDI WRITE CODE WRITE SPAN UPDATE WRITE CODE ... SRO ... READ CODE INPUT REGISTER READ SPAN INPUT REGISTER READ SPAN DAC REGISTER READ CODE INPUT REGISTER 2756 F03 Figure 3. Rolling Readback Example 2756fa For more information www.linear.com/LTC2756 15 LTC2756 operation Examples 1. Load 5V range with the output at 0V. Note that since span and code are updated together, the output stays at 0V throughout the example. 3. Write and update mid-scale code in 0V to 10V range (VOUT = 5V) using readback to check the contents of the Input registers before updating. a) CS/LD . Clock SDI: 00100000 XXXXXXXX XXXX0010 XXXXXXXX a) CS/LD . Clock SDI: 00110000 10000000 00000000 00XXXXXX b) CS/LD Span Input register - range set to bipolar 5V. b) CS/LD Code Input register set to mid-scale. c) CS/LD . Clock SDI: 00110000 10000000 00000000 00XXXXXX c) CS/LD . Clock SDI: 00100000 XXXXXXXX XXXX0001 XXXXXXXX Data out on SRO: 00000000 10000000 00000000 00000000 Verifies Code Input register set to mid-scale. d) CS/LD Code Input register - code set to mid-scale. e) CS/LD . Clock SDI: 01000000 XXXXXXXX XXXXXXXX XXXXXXXX f) CS/LD Update code and range. Alternatively steps e and f could be replaced with LDAC . 2. Load 10V range with the output at 5V, changing to -5V. a) CS/LD . Clock SDI: 00110000 11000000 00000000 00XXXXXX b) CS/LD Code Input register set to 3/4-scale code. c) CS/LD . Clock SDI: 01100000 XXXXXXXX XXXX0011 XXXXXXXX d) CS/LD Span Input register set to 0V to 10V range. e) CS/LD . Clock SDI: 10100000 XXXXXXXX XXXXXXXX XXXXXXXX Data out on SRO: 00000000 00000000 00000001 00000000 Verifies Span Input register set to 0V to 10V range. f) CS/LD g) CS/LD . Clock SDI: 01000000 XXXXXXXX XXXXXXXX XXXXXXXX h) CS/LD Update code and range. Output goes to 5V. d) CS/LD Span Input register set to 10V range. Update code and range. Output goes to 5V. g) CS/LD . Clock SDI: 01110000 01000000 00000000 00XXXXXX h) CS/LD Code Input register set to 1/4-scale code. Update code and range (note update does not change range, since no new range has been written). Output goes to -5V. 16 2756fa For more information www.linear.com/LTC2756 LTC2756 operation System Offset and Reference Adjustments Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the LTC2756, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps. The offset adjust pin VOSADJ can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range: VOS [LSB] = -V(VOSADJ ) * 2048 V(RIN ) In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.) VOS = -(1/128)VOSADJ [0V to 5V, 2.5V spans] VOS = -(1/64)VOSADJ [0V to 10V, 5V, -2.5V 7.5V spans] VOS = -(1/32)VOSADJ [10V span] The gain error adjust pins GEADJ can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range: GE = The VOSADJ pin has an input impedance of 1.28M. It should be driven with a Thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2756. The VOSADJ pin should be shorted to GND if not used. The GEADJ pin has an input impedance of 2.56M, and is intended for use with fixed reference voltages only. It should be shorted to GND if not used. Power-On Reset and Clear A 5V control voltage applied to VOSADJ produces VOS = -2048 LSB in any output range, assuming a 5V reference voltage at RIN. to quality, low-noise inputs are required to maintain the best DAC performance. V(GE ADJ ) * 2048 V(RIN ) The gain-error delta is non-inverting for positive reference voltages. Note that this pin compensates the gain by altering the inverted reference voltage V(REF). In voltage terms, the V(REF) delta is inverted and attenuated by a factor of 128. V(REF) = -(1/128)GEADJ When power is first applied to the LTC2756, the DAC powers up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All internal DAC registers are reset to 0 and the DAC output initializes to zero volts. If the part is configured for manual span operation, the DAC will be set into the pin-strapped range at the first Update command. This allows the user to simultaneously update span and code for a smooth voltage transition into the chosen output range. When the CLR pin is taken low, a system clear results. The DAC buffers are reset to 0 and the DAC output is reset to zero volts. The Input buffers are left intact, so that any subsequent Update command (including the use of LDAC) restores the DAC to its previous state. If CLR is asserted during an instruction, i.e., when CS/LD is low, the instruction is aborted. Integrity of the relevant Input buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. The RFLAG pin is used as a flag to notify the system of a loss of data integrity. The RFLAG output is asserted low at power-up, system clear, or if the supply VDD dips below approximately 2V; and stays asserted until any valid Update command is executed. The nominal input range of these pins is 5V; other voltages of up to 15V may be used if needed. However, do not use voltages divided down from power supplies; reference2756fa For more information www.linear.com/LTC2756 17 LTC2756 Applications Information Op Amp Selection Because of the extremely high accuracy of the 18-bit LTC2756, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Table 3. Coefficients for the Equations of Table 4 OUTPUT RANGE A1 A2 A3 A4 A5 5V 1.1 2 1 - 1 10V 2.2 3 0.5 - 1.5 5V 2 2 1 1 1.5 10V 4 4 0.83 1 2.5 2.5V 1 1 1.4 1 1 -2.5V to 7.5V 1.9 3 0.7 0.5 1.5 Tables 3 and 4 contain equations for evaluating the effects of op amp parameters on the LTC2756's accuracy when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Table 5 contains a partial list of LTC precision op amps recommended for use with the LTC2756. The easy-to-use design equations simplify the selection of op amps to meet the system's specified error budget. Select the amplifier from Table 5 and insert the specified op amp parameters in Table 4. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate. Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp. UNIPOLAR BIPOLAR GAIN BIPOLAR ZERO UNIPOLAR GAIN DNL (LSB) INL (LSB) OFFSET (LSB) ERROR (LSB) ERROR (LSB) ERROR (LSB) 5V 5V 5V 5V 5V 5V VOS1 (mV) VOS1 * 12.1* V VOS1 *3.1* V A3*VOS1 *52.4 * V A3*VOS1 *78.6 * V VOS1 *52.4 * V VOS1 * 52.4* V REF REF REF REF REF REF 5V 5V 5V 5V 5V 5V IB1 (nA) IB1 *0.0012* V IB1 *0.00032 * V IB1 *0.524* V IB1 *0.524* V IB1 *0.0072 * V IB1 *0.0072* V REF REF REF REF REF REF 66 6 524 524 AVOL1 (V/mV) A1* A A2 * A 0 0 A5* A5* AVOL1 AVOL1 VOL1 VOL1 5V 5V 5V 0 0 0 A4*VOS2 *52.4 * V V VOS2 (mV) *104.8* *104.8* VREF VREF OS2 VREF OS2 5V 5V 5V 0 0 0 IB2 (nA) A4*IB2 *0.524 * IB2 *1.048* IB2 *1.048* VREF VREF VREF 524 524 0 0 0 AVOL2 (V/mV) A4* 262 AVOL2 AVOL2 AVOL2 OP AMP ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Table 5. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2756 with Relevant Specifications AMPLIFIER SPECIFICATIONS CURRENT NOISE pA/Hz SLEW RATE V/s GAIN BANDWIDTH PRODUCT MHz tSETTLING with LTC2756 s POWER DISSIPATION mW AMPLIFIER VOS V IB nA A VOL V/mV VOLTAGE NOISE nV/Hz LTC1150 10 0.05 5600 90 0.0018 3 2.5 10ms 24 LT1001 25 2 800 10 0.12 0.25 0.8 120 46 LT1012 25 0.1 2000 14 0.02 0.2 1 120 11.4 LT1097 50 0.35 2500 14 0.008 0.2 0.7 120 11 LT1468 75 10 5000 5 0.6 22 90 2.1 117 18 2756fa For more information www.linear.com/LTC2756 LTC2756 Applications Information Op amp offset contributes mostly to DAC output offset and gain error, and has minimal effect on INL and DNL. For example, consider the LTC2756 in unipolar 5V output range. (Note that for this example, the LSB size is 19V.) An op amp offset of 35V will cause 1.8LSB of output offset, and 1.8LSB of gain error; but 0.4LSB of INL, and just 0.1LSB of DNL. While not directly addressed by the simple equations in Tables 3 and 4, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp's data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 4 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, offers a thorough discussion of 18-bit DAC settling time and op amp selection. Recommendations For DC or low-frequency applications, the LTC1150 is the simplest 18-bit accurate output amplifier. An auto-zero amp, its exceptionally low offset (10V max) and offset drift (0.01V/C) make nulling unnecessary. For swings above 8V, add an LT(R)1010 buffer to boost the load current capability. The settling of auto-zero amps is a special case; see Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, Appendix E, for details. The LT1012 and LT1001 are good intermediate output-amp solutions that achieve moderate speed and good accuracy. They are also excellent choices for the reference inverting amplifier in fixed-reference applications. For high speed applications, the LT1468 settles in 2.1s. Note that the 75V max offset will degrade the INL at the DAC output by up to 0.9LSB. For high-speed applications demanding higher precision, the amplifier offset can be nulled with a digital potentiometer. Figure 5 shows a composite output amplifier that achieves fast settling (8s) and very low offset (3V max) without offset nulling. This circuit offers high open-loop gain (1000V/mV min), low input bias current (0.15nA max), fast slew rate (25V/s min), and a high gain-bandwidth product (30MHz typ). The high speed path consists of an LTC6240HV, which is an 18MHz ultralow bias current amplifier, followed by an LT1360, a 50MHz fast-slewing amplifier which provides additional gain and the ability to swing to 10V at the output. Compensation is taken from the output of the LTC6240HV, allowing the use of a much larger compensation capacitor than if taken after the gain-of-five stage. An LTC2054HV auto-zero amplifier senses the voltage at IOUT1 and drives the non-inverting input of the LTC6240HV to eliminate the offset of the high speed path. The 100:1 attenuator and input filter reduce the low frequency noise in this stage while maintaining low DC offset. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC2756 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2756 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 18-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LTC6655 (0.025%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference's output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit's INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. 2756fa For more information www.linear.com/LTC2756 19 LTC2756 Applications Information Table 6. Partial List of LTC Precision References Recommended for Use with the LTC2756 with Relevant Specifications INITIAL TOLERANCE TEMPERATURE DRIFT 0.1Hz to 10Hz NOISE LT1019A-5, LT1019A-10 0.05% max 5ppm/C max 12VP-P LT1236A-5, LT1236A-10 0.05% max 5ppm/C max 3VP-P LT1460A-5, LT1460A-10 0.075% max 10ppm/C max 20VP-P LT1790A-2.5 0.05% max 10ppm/C max 12VP-P LTC6652A-5 0.05% max 5ppm/C max 2.8ppmP-P LTC6655A-2.5 LTC6655A-5 0.025% max 2ppm/C max 0.25ppmP-P REFERENCE As precision DAC applications move to 18-bit performance, reference output voltage noise may contribute a dominant share of the system's noise floor. This in turn can degrade system dynamic range and signal-to-noise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references like the LT1236 or LTC6655 produce low output noise in the 0.1Hz to 10Hz region, well below the 18-bit LSB level in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. 20 Grounding As with any high-resolution converter, clean grounding is important. A low-impedance analog ground plane is necessary, as are star grounding techniques. Keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept without using separate star traces. The IOUT2 pin is of particular importance; INL will be degraded by the code-dependent currents carried by IOUT2 if voltage drops to ground are allowed to develop. The best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part. Alternatively, the pin may be routed to the star ground point if necessary; route a trace of no more than 30 squares of 1oz copper. In the rare case in which neither of these alternatives is practicable, a force/sense amplifier should be used as a ground buffer (see Figure 4). Note, however, that the voltage offset of the ground buffer amp directly contributes to the effects on accuracy specified in Table 4 under `VOS1'. The combined effects of the offsets can be calculated by substituting the total offset from IOUT1 to IOUT2 for VOS1 in the equations. 2756fa For more information www.linear.com/LTC2756 LTC2756 Applications Information CIRCUIT B CIRCUIT A + 2 1000pF LT1468 ZETEX BAT54S 7 6 IOUT2 3 LT1012 + 1 - 6 IOUT2 2 - 7 200 200 1 2 3 ZETEX* BAT54S 3 2 3 *SCHOTTKY BARRIER DIODE VREF 5V 1 ROFS RFB 27, 28 5 RIN + 6 3 4 LT1012 27pF GEADJ DAC 3 RCOM 2 IOUT1 26 2 - IOUT2 7 3 + LT1468 6 VOUTA VOSADJ 25 - 150pF 2 REF LTC2756 2756 F05 Figure 4. If a Low-Impedance GND Plane Is Unavailable, Drive IOUT2 with a Force/Sense Amplifier As Shown. Use Circuit A to Minimize Impact on Settling Time, or Circuit B for Lower Power Consumption and Better Accuracy 2756fa For more information www.linear.com/LTC2756 21 LTC2756 Package Description Please refer to http://www.linear.com/product/LTC2756#packaging for the most recent package drawings. G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 9.90 - 10.50* (.390 - .413) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1.25 0.12 7.8 - 8.2 5.3 - 5.7 0.42 0.03 7.40 - 8.20 (.291 - .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RECOMMENDED SOLDER PAD LAYOUT 2.0 (.079) MAX 5.00 - 5.60** (.197 - .221) 0 - 8 0.09 - 0.25 (.0035 - .010) 0.65 (.0256) BSC 0.55 - 0.95 (.022 - .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.22 - 0.38 (.009 - .015) TYP 0.05 (.002) MIN G28 SSOP 0204 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 22 2756fa For more information www.linear.com/LTC2756 LTC2756 Revision History REV DATE DESCRIPTION A 12/16 Updated amplifier part numbers. PAGE NUMBER 19, 24 2756fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC2756 23 LTC2756 Typical Application 15V 12V IN LTC6655-5 + OUT LT1012 0.1F 10F - -15V 1 14 10k 23 10k 17 25 4 19 20 21 22 VDD ROFS 5 3 RIN RCOM 100pF 2 REF RFB LDAC IOUT1 27, 28 26 LTC2756 CLR VOUT 1k 10k VOSADJ 10k - 1F LTC2054HV GEADJ M-SPAN S0 S2 CS/LD 9 SDI SCK 10 SRO 11 1k -5V 5V 100pF 15V + LTC6240HV + + IOUT2 7 6, 8, 13, 15, 16, 24 GND S1 - 5V 10 LT1360 - -5V 5pF 1F -15V 2756 TA02 12 4.02k 1k SPI BUS Figure 5. Composite Amplifier Provides Both 18-Bit Precision and Fast Settling Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2757 Single Parallel 18-Bit IOUT SoftSpan DAC 1LSB INL/DNL, Software-Selectable Ranges, 7mm x 7mm LQFP-48 Package LTC1592 Single Serial 16-/14-/12-Bit IOUT SoftSpan DACs 1LSB INL/DNL, Software-Selectable Ranges, 16-Lead SSOP Package LTC2751 Single Parallel 16-/14-/12-Bit IOUT SoftSpan DACs 1LSB INL/DNL, Software-Selectable Ranges, 5mm x 7mm QFN-38 Package LTC1597/LTC1591 Single Parallel 16-/14-Bit IOUT DACs 1LSB INL/DNL, Integrated 4-Quadrant Resistors, 28-Lead SSOP Package LTC2758 Dual Serial 18-Bit IOUT SoftSpan DAC 1LSB INL/DNL, Software-Selectable Ranges, 7mm x 7mm LQFP-48 Package LTC2754 Quad Serial 16-/12-Bit IOUT SoftSpan DACs 1LSB INL/DNL, Software-Selectable Ranges, 7mm x 8mm QFN-52 Package LTC2704 Quad Serial 16-/14-/12-Bit VOUT SoftSpan DACs 1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers LTC2641/LTC2642 16-/14-/12-Bit VOUT DACs 1LSB INL/DNL, 0.5nV*s Glitch, 1s Settling, 3mm x 3mm DFN LTC6655A-2.5/ LTC6655A-5 Low Drift Precision Buffered Reference 0.025% Max Tolerance, 2ppm/C Max, 0.25ppmP-P 0.1Hz to 10Hz Noise LT1236A-5/ LT1236A-10 Precision Reference 0.05% Max Tolerance, 5ppm/C Max, 3VP-P 0.1Hz to 10Hz Noise LT1460A-5/ LT1460A-10 Micropower Precision Series Reference 0.075% Max Tolerance, 10ppm/C Max, 20VP-P 0.1Hz to 10Hz Noise LT1790A-2.5 Micropower Low Dropout Reference 0.05% Max Tolerance, 10ppm/C Max, 12VP-P 0.1Hz to 10Hz Noise LTC6652A-5 Precision Low Drift Low Noise Buffered Reference 0.05% Max Tolerance, 5ppm/C Max, 2.8ppmP-P 0.1Hz to 10Hz Noise LTC1150 Zero-Drift Op Amp with Internal Capacitors 10V Max Offset, 16V High Voltage Operation, 1.8VP-P Noise LT1012 Precision Op Amp 25V Max Offset, 100pA Max Input Current, 0.5VP-P Noise, 380A Supply Current LT1001 Precision Op Amp 25V Max Offset, 0.3VP-P Noise, High Output Drive LT1468 Single 16-Bit Accurate Op Amp 900ns Settling, 90MHz GBW, 22V/s Slew Rate, 75V Max Offset References Amplifiers 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2756 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2756 2756fa LT 1216 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2012