Application Note September 2001 Using the T8535B/T8536B Quad Programmable Codec Introduction The Agere Systems Inc. T8536 is a four-channel voiceband codec with digital impedance synthesis. Digital impedance synthesis makes it possible to digitally configure any of the numerous tip/ring termination impedances that have been mandated worldwide for different applications. This application note provides a detailed description of device operation. It is intended to be used in conjunction with the T8535B/36B Quad Programmable Codec Data Sheet and the Aquarium Coefficient Software. Codec Overview The T8536 is a four-channel device. A reducedpinout version coded T8535 is also available. The algorithmic functionality of the T8535 and T8536 is identical. For documentation flow, this document only refers to the T8536; however, all discussions apply equally to the T8535. Interfacing between the tip/ring interface of a customer loop and digital PCM buses requires, in addition to the T8536, a subscriber line interface circuit (SLIC) to perform functions such as the following: Ringing signal generation Off-hook and ring trip detection Battery feed Line drive and sense amplifiers Agere offers a variety of SLIC devices. Figure 1 shows the signals in such a cascade. Note that this figure shows a per-channel illustration; only one quarter of the T8536 is really being used. Some SLICs are multichannel also. RVFxI CC1 TIP SLIC RING VFXI VFROP VFRON DX 1/4 T8536 DR 5-8084A(F) Figure 1. Using the T8536 with a SLIC The T8536 reads a PCM encoding from a specified time slot of the DR PCM bus and outputs the differential mode signals VFROP and VFRON to the SLIC. The signal VFXI from the SLIC is capacitively coupled to the T8536 which processes it and, ultimately, writes the appropriate signal to a specified time slot on the outgoing PCM bus DX. The differential output pair and the capacitive coupling on VFXI are a consequence of the desire to have the T8536 as a single power supply device. Most Agere SLICs generate an output signal (VFXI) that is proportional to loop current. Such SLICs are called current-sensing, to distinguish them from SLICs having an output proportional to tip/ring voltage. Although the T8536 is more generally applicable, the assumption here is that the SLIC being used is current-sensed. The two-wire impedance that is seen at the tip/ring junction, when looking back into the SLIC and towards the digital network, can be controlled by programming the T8536. This is what is meant by digital termination impedance synthesis. Depending on application and country of deployment, different standards have been established for this impedance. Digital termination impedance synthesis is commercially important because it alleviates stocking and inventorying many minor permutations of one product. Digital impedance synthesis is accomplished by bleeding some of the incoming VF XI signal into the VFROP/VFRON output. Digital control of this synthesized impedance requires that the bulk of the bleeding variability be in a bleed path that includes the D/A and A/D converters. The inevitable delay entailed in the antialiasing and reconstruction filters associated with these converters greatly complicates digital impedance synthesis. Echo can be defined as any incoming signal on DR being returned on DX. Echo strength is determined by how closely the actual two-wire impedance seen at the tip/ring junction, when looking out towards the customer loop, matches a design impedance called a balance impedance. Note that the two-wire impedance of consequence for digital impedance synthesis and the two-wire impedance of consequence for hybrid balance are impedances seen looking in opposite directions. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Table of Contents Contents Page Introduction .................................................................1 Codec Overview .........................................................1 Analog Interface ..........................................................3 Digital Interfaces .........................................................3 PCM Bus Timing ......................................................3 BCLK .....................................................................3 FS ..........................................................................3 DR and DX .............................................................4 Serial Control Interface ............................................4 Codec Initialization ......................................................6 Addresses Used During Call Processing.....................7 Resets .........................................................................8 Scanning......................................................................8 Refresh Operations .....................................................8 Configuring Impedance Synthesis Parameters ..........8 Hybrid Balance Taps Control Word (HBALTAPS) ........................................................11 Sigma-Delta Control Word (SDCTRL) ...................11 CTZ Control Word (CTZCTRL) ..............................11 Impedance Equalization Control Word (ZEQCTRL) ..........................................................11 Additional Functions .................................................12 T8536 Latch Control Words ...................................12 SLIC 3-State Control Word (SLICTS) ..................12 SLIC Write Control Word (SLICWR) ....................12 SLIC Read Control Word (SLICRD) ....................12 Loopbacks ..............................................................12 Miscellaneous Control Words ...................................13 Reset Control Word (RESCTRL) ...........................13 Sigma-Delta Time-Slot Interchanger Control Word (SDTSI) .......................................................13 PCM Control Word (PCMCTRL1 and 2) .................13 Verify Control Word (VERIFY) ...............................13 Board Layout and Decoupling ...................................14 2 Figures Page Figure 1. Using the T8536 with a SLIC ...................... 1 Figure 2. Nominal Timing on the PCM Bus ............... 3 Figure 3. Timing on the Serial Control Interface with INTS = 0 ................................................... 4 Figure 4. Timing on the Serial Control Interface with INTS = 1 ................................................... 5 Figure 5. Block Diagram for Impedance Synthesis and Level Setting .................................... 10 Figure 6. Model for Agere SLIC ............................... 10 Tables Page Table 1. Codec Memory Locations Generally Used Only at Initialization .................................... 6 Table 2. Codec Memory Locations Used on a Per-Call Basis............................................. 7 Table 3. Gain Resolution ............................................ 9 Table 4. Control Words Associated with Impedances and Levels .......................... 10 Table 5. Nonzero Bytes Default Settings.................. 11 Table 6. Decomposition of SDCTRL ....................... 11 Table 7. Decomposition of CTZCTRL ..................... 11 Table 8. Decomposition of ZEQCTRL ..................... 11 Table 9. Decomposition of SLICTS, SLICWR, and SLICRD .................................................... 12 Table 10. Decomposition of SDTSI .......................... 13 Table 11. Decomposition of PCMCTRL1 ................. 13 Table 12. Decomposition of PCMCTRL2 ................. 13 Agere Systems Inc. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Analog Interface The codec only requires a 5 V, 5% supply to operate. With a single supply, the analog input and output signals are referenced to 2 V. This reference is internally generated; therefore, signals must be capacitively coupled (ceramic capacitor or equivalent) to VFXI (see Figure 1). A 20 M, 5% resistor (RVFxI) is required from VFXI to AGND when complex termination impedances are to be synthesized. RVFxI is also recommended for resistive termination impedances (it is required for resistive termination impedances when the XAG amplifier gain is +12.04 dB or greater). Most Agere SLICs provide a transmit gain of 300 V/A or 400 V/A. For this gain, the XAG amplifier will normally be set for either 0 dB or 6.02 dB. RVFxI can be reduced to a value of 10 M if the XAG amplifier is set for 0 dB or +6.02 dB. For unused channels, leave transmit inputs and receive outputs floating. Digital Interfaces PCM Bus Timing The T8536 easily interfaces to standard PCM buses. Figure 2 shows nominal timing. BCLK ... ... ... FS ... ... ... DR s a b c w x y z s DX a b c w x y z 5-8080 (F) Figure 2. Nominal Timing on the PCM Bus BCLK The BCLK signal is an input clock which must be one of the following frequencies: 16,384 kHz 8,192 kHz 4,096 kHz 3,072 kHz 2,048 kHz 1,536 kHz 1,024 kHz 512 kHz The codec checks the frequency of the BCLK input every frame strobe. If the frequency is not one of the allowable frequencies, it resets the codec (the same Agere Systems Inc. reset as bit 0 of address 128). The codec will reset if the frequency is inaccurate or if the BCLK is removed (assuming FS is not removed). Removing a bit from a 1.544 MHz clock source to obtain a 1.536 MHz clock is not allowed. FS The FS signal is an 8 kHz frame strobe. It nominally transitions on the positive-going edges of BCLK. It can be up more than one BCLK clock period if desired. What counts is the first BCLK clock period in which FS is up. The chip strobes the FS signal with the negativegoing edges of an internal version of BCLK. Thus, the actual timing specification requires a small setup and hold relative to the negative-going clock edge of the external BCLK. 3 Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Digital Interfaces (continued) two adjacent time slots. MSB first or LSB first is programmable using bit 5 of PCMCTRL1. The codec defaults to LSB first. With LSB first, bit 16 is the MSB and the sign bit. Bits 3 through 15 are the intervals. Bits 1 and 2 are insignificant. PCM Bus Timing (continued) DR and DX The receive-in PCM bus signal (DR) is another chip input which nominally transitions on the positive-going edge of BCLK. It is also sampled midperiod so that the timing specification requires a set and hold time relative to the negative-going clock transition. The delay in clock periods between the 8 kHz frame strobe and the first bit to be read from DR is user selectable, and is specified by writing particular data to the time-slot offset (RXOFF) and bit offset (RXBITOFF) control words. The signal DX is the PCM output. The delay in clock periods between FS and the start of the PCM output data is independent of the DR timing. The time-slot offset is controlled by TXOFF, and the bit offset by TXBITOFF control words. Transitions are nominally lined up with the positive-going edges of BCLK. The actual specification allows for up to 30 ns of delay. When output data is not being written, the DX output is 3-stated. On the chip, the DR input and the DX output are separate pins. The two could be tied together, if desired, in which case it would be necessary to arrange timing so that the input and output were in nonoverlapping time slots. The DR input and DX output can be selectably -law or A-law encoded. They can also be 16-bit linear encodings. These are set by the PCM control word (PCMCTRL1). For -law or A-law, bit 1 is the MSB and the sign bit. Bits 2 through 4 are the chord bits. Bits 5 through 8 are the interval bits. The assumed form for the 16-bit linear encodings is two's complement, using Serial Control Interface The chip is controlled via a serial interface that has been designed for convenient interfacing to standard microprocessors and microcontrollers. The serial control interface is extremely simple in structure. Only reading and writing of bytes in on-chip memory takes place. Nothing is masked out, so care must be taken in programming only the user-defined memory space. User controls are all contained in memory bank 0. It is possible to initiate multibyte transfers to sequential memory addresses, but this is just a convenience. Logically, everything is byte oriented. In order to maintain compatibility with other interfaces, two slightly different variations for the timing on the serial control interface are available. If the INTS pin to the chip is held low, nominal timing on the serial interface is as shown in Figure 3. The serial interface clock (DCLK) need not be synchronous with the PCM interface clock BCLK. It can range in frequency up to 4096 kHz. The chip select (CS) signal strobes bytes of data across the serial interface. It is an active-low signal. Under the INTS = 0 timing option, the transitions on CS are nominally aligned with negative-going edges of DCLK. The chip strobes this signal midperiod with the other edge of DCLK so the actual timing specification is a setup and hold relative to the positive-going edge. ... DCLK ... CS DI DO b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 5-8082(F) Figure 3. Timing on the Serial Control Interface with INTS = 0 4 Agere Systems Inc. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 The command byte indicates whether reading or writing is desired and which of the four channels is to be read or written. It is also possible to specify a desire to write to all four channels simultaneously. Digital Interfaces (continued) Serial Control Interface (continued) Serial data going to the chip is read from the data in (DI) lead. Data coming from the chip is placed on the data out (DO) lead. The DI input is sampled midperiod so that there is a setup and hold requirement relative to the positive-going edge of DCLK. The output is specified to be ready within a delay of the negative-going edge of DCLK. The DO lead is 3-stated and only actively driven when output data is present. The starting-address byte gives the memory address for the lowest-addressed byte to be read or written. The length byte tells how many bytes are to be read or written. For lengths greater than one, the bytes being read or written must be at contiguous addresses. If data is being written to the chip, then the actual data bytes can be concatenated with the 3-byte initiation request if desired. In other words, CS can stay low for both the 24 clock periods needed to pass the initiation bytes and whatever multiple of eight clock periods is needed to move the data. If the INTS lead is held high (or floated, since it has an internal pull-up), timing on the serial interface is slightly different, as shown in Figure 4. In this timing mode, DCLK is inverted and CS is advanced a half-clock period relative to its usage in the other timing mode. As usual for the chip, received signals are strobed in the middle of their nominal steady regions and transmitted signals are available after a specified small delay from the clock edge of nominal transition. If data is being read from the chip, CS must be deasserted between the strobe to initiate the request and the strobe to actually read the chip data. A delay is required between these two strobes. This is necessary because time is needed by the chip to retrieve the requested data. Under either timing mode, CS should stay low for a multiple of eight serial clock periods whenever it goes low at all. Not staying low for a multiple of eight clock periods implies a request to reset the serial interface. In a multibyte read or write transaction, the user selects whether or not CS comes up between bytes. This is true under either timing mode1. The T8535B/36B Quad Programmable Codec Data Sheet provides more detailed information on the clocking and timing necessary for proper serial interface operation. 1. The data sheet implies that coming up between bytes is an option only under INTS = 0 mode. The data sheet is describing customary usage of the two timing protocols. The chip actually allows breaks under either timing mode. 2. There is a special fast scan mode intended for efficient reading of on-hook/off-hook status that is somewhat different. See the data sheet for details. Notice that data on the serial bus is always transmitted with the least significant bit first. In multibyte transactions, the bytes are ordered from lowest address to highest address. The T8536 never initiates any serial interface transactions. If the external microprocessor wishes to initiate a transaction it sends a 3-byte sequence2. These 3 bytes are called the command byte, the starting-address byte, and the length byte. ... DCLK ... CS DI b0 DO b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 5-8081(F) Figure 4. Timing on the Serial Control Interface with INTS = 1 Agere Systems Inc. 5 Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Codec Initialization The codec has many programmable functions, including gain settings, termination impedance synthesis coefficients, balance impedance coefficients, internal feature controls, time-slot assignments, power controls, reset controls, programmable I/O for control of other line card components, etc. In general, most of these settings are fixed for a given application and locale. It is possible to initialize the device once with all the fixed settings and then only change a few bytes of memory for call setup and tear-down. Table 1 shows the memory map and the settings that are usually fixed on a per-application/locale basis. These settings generally do not need to be changed on a per-call basis. It should be noted that some of these controls are useful for system diagnostic purposes, so there may be a reason to modify them, at least temporarily, after initialization. In general, the settings to be used for the initialization of these locations are generated by the Aquarium Coefficient Software. The initial state of addresses not generated by the Aquarium Coefficient Software are, in general, either the device default, settings, or easily obtained from the data sheet and the system design. Special mention should be made of the SLICTS register. This register controls the direction of six (per channel) parallel I/O (PIO) leads that can be used to control other line card components. The configuration of this address is a direct function of the line card hardware design. Bits 0 and 1 of these six PIO bits are reported by the special one-byte FASTSCAN command for all four channels. Table 1. Codec Memory Locations Generally Used Only at Initialization 6 Control Register Name Address (decimal) HBALTAPS RESCTRL RXBITOFF GRX2 CTZCTRL PCMCTRL2 SDCTRL SDTSI ZEQCTRL GTX1 TXBITOFF PCMCTRL1 SLICTS 0--27, 64--91 128 130 134--135 140--143 145 146 147 150--152 153--154 155 157 158 Function Hybrid Balance Coefficients Reset Control Word Receive PCM Bus Bit Offset Receive Tweak Amplifier Gain CTZ Bleed Coefficients Second PCM Bus Control Sigma-Delta Control Internal TSI Control Transmit Equalizer Coefficients Transmit Tweak Amplifier Gain Transmit Bit Offset PCM Control PIO Direction Controls Agere Systems Inc. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Addresses Used During Call Processing Table 2 shows the addresses in the codec memory that are typically used on a call-by-call basis for call setup and tear-down. These words (addresses) are grouped by function, and it should be noted that different system designs may not require all these controls to be set for each call. The time-slot assignments, for example, may be fixed in a system design and not change from call to call. On the other hand, some system designs place call progress tones and/or tone receivers in specific time slots, so assigning those specific time slots would have the effect of connecting the associated equipment. The gain transfer settings are a function of the network loss plan, and will vary from jurisdiction to jurisdiction and type of call. For example, it is common in a PBX application to use transfer gains of 0 dB for internal PBX calls, but insert a loss into the circuit for calls connected to the public switched telephone network (PSTN). Similarly, in a local exchange, it may be necessary to insert a loss in a toll connection that is different from a local connection or a tandem connection. The SLICWR register holds the data to be placed on the PIO leads designated as outputs in the SLICTS register. This is commonly used to control the other portions of the line card, such as the SLIC and/or LCAS devices. Clearly, the data is a function of both the devices to be controlled and the interconnecting wiring. Generally, any change in the SLICWR register may take up to one frame time (125 s) to appear on the output lead. The SLICRD register contains the current state of all six of the PIO leads, both inputs and outputs. It is commonly read to determine the state of the signaling leads external to the codec. Since various SLIC devices have transient behavior that may be misleading, it is very important to understand the transitions of external signaling leads and to process the data appropriately. The CHACTIVE register contains only one bit that determines the active/standby state of the channel. In general, the channel should be placed in standby mode between active calls to minimize power dissipation and avoid having the echo canceler (if the device is so equipped) converge on an open circuit loop. As an example, the typical steps in setting up a call are as follows: 1. The normal scan function (likely using the FASTSCAN command) detects off-hook. 2. The channel is activated to provide dial tone: -- The appropriate time slot for dial tone is programmed into RXOFF. -- The appropriate time slot for a digit tone receiver is programmed into TXOFF. -- The SLIC controls are placed in the active state (SLICWR) and the channel is activated in CHACTIVE. -- Upon receipt of the first digit, the RXOFF is changed to a quiet time slot. 3. The call is set up: -- After the digits are received, GTX2, GRX1, TXOFF, and RXOFF are programmed for the call. -- Scanning continues for the on-hook condition indicating disconnect. There are several other call setup/tear-down scenarios that are similar. Table 2. Codec Memory Locations Used on a Per-Call Basis Control Register Name Address (decimal) RXOFF TXOFF GRX1 GTX2 SLICWR SLICRD CHACTIVE 131 156 132--133 148--149 159 160 129 Agere Systems Inc. Function Receive Direction Time-slot Assignment Transmit Direction Time-slot Assignment Receive Direction Transfer Gain Transmit Direction Transfer Gain PIO Data Register Read-only Indicator of PIO States Active/Standby Control 7 Using the T8535B/T8536B Quad Programmable Codec Addresses Used During Call Processing (continued) Notice that, depending on system design, some of the memory locations listed in Table 2 may be treated as if they were in Table 1. For example, a system that uses fixed time slots for the PCM bus could easily load the time-slot information at initialization and not bother to reload it at call setup time. This mode of operation may be desirable, particularly in small line count systems with additional processing (perhaps forming packets or voice compression) between the network and the PCM bus. Similarly, if the network loss plan is fixed, the GTX2 and GRX1 settings can be set at initialization and never reloaded at call setup time. Unless the system leaves all channels active, the CHACTIVE word is changed during call setup and tear-down. The controls for the SLIC and other line components invariably require adjustment for different call processing states. It is important that the response of other line card devices, such as the SLIC, be understood so that appropriate filtering in the scan data can be used to generate accurate signaling information. Resets Care must be taken when writing into the reset register (word 128) and applying a hardware reset because these operations may result in resetting all the codec memory to the default state. If a hardware reset is issued or bit zero in word 128 is set, it will be necessary to reload all of the fixed addresses listed in Table 1, i.e., a full initialization is required. Bit 1 of word 128 clears the processing but does not affect programmed registers. It also should be used carefully to avoid disrupting a call in progress, but it will not be necessary to reload the initialization set of addresses. If the source of BCLK is switched, or if the BCLK source is glitched, a hardware reset must be performed and the registers must be reprogrammed. Scanning Historically, for test reasons, the telephone network has never embraced interrupt driven signaling systems. The technique that is commonly used is to scan the signaling state of each channel periodically, typically every few milliseconds. This can easily be accomplished by reading the SLICRD register periodically. A 8 Application Note September 2001 normal read of this register requires the sending of a three-byte command followed by a single byte read data transfer. This procedure has to be repeated for each of the four channels. Normally, however, the signaling information from the SLIC is only one or two bits, typically off-hook detection and/or ring trip and/or ring ground detection. Often ring trip and off-hook or ring ground detection are multiplexed on a single lead. This codec has a special command for scan purposes known as the FASTSCAN command. This special command is only one byte long instead of three bytes and returns a single byte containing two bits of the PIO interface for each of the four channels. Use of this feature can greatly speed up the routine scan operation and is the preferred method of performing periodic signaling checks. Notice that there are hardware implications to this technique since the required signaling inputs must be connected to the SLIC0 and SLIC1 leads. Refresh Operations Some users prefer to periodically refresh the contents of memory. For words that are constant, i.e., do not change with time, this refresh operation may take place at any time with the channel either active or in standby mode. Users are cautioned, however, to refrain from writing any memory addresses other than those listed in the data sheet, since they may be (and probably are) used for temporary storage of intermediate processing results. A similar prohibition against writing into readonly locations, for the same reasons, is prudent. Refreshing the memory is not required because the constants listed in the data sheet are contained in static memory and are not erased when the channel is in standby mode. Configuring Impedance Synthesis Parameters Figure 5 shows the important blocks for level setting and impedance synthesis. The five variable gains GRX1, GRX2, XAG, GTX1, and GTX2 affect transmission levels. All of the blocks are digital gain blocks except XAG. XAG can be programmed from 0 dB to 24.12 dB in 6.02 dB steps. GRX1 and GTX2 are the transfer gain blocks. These are defined by the user to set transmission level points (TLP). Agere Systems Inc. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Configuring Impedance Synthesis Parameters (continued) The maximum recommended setting for GRX1 is 0 dB of gain. Additional transfer gain can be realized by boosting the gain of GRX2. Up to 6 dB of gain can be transferred from GRX1 to GRX2. If an RX TLP of +6 dB is desired, permanently set GRX2 6 dB higher than the value calculated by the Aquarium Coefficient Software. (To perform this in the Aquarium Coefficient Software, one needs to first compute to get the base gain settings, then increase GRX2 by the desired amount by setting the gain, and then compute again). In use, all the GRX1 levels would then be offset. For instance, if +6 dB of RX transfer gain is desired, for RX TLPs of +6 dB, 0 dB, and -7 dB, GRX1 would be set for 0 dB, -6 dB, and -13 dB, respectively. Note that when using GTX2, if the transmit TLP is to be set for 0 dB, program GTX2 for 0x03ff instead of using the 0x0400 default setting. There is inherent gain in both transmission paths, -2.146 dB in the transmit path, and +1.63 dB in the receive path. These inherent gains are compensated for by the Aquarium Coefficient Software. These gains only need to be considered when performing loopback tests. Resolution of the digital gain blocks is much finer than 0.1 dB. All digital gains are binary multiplication in two's complement form. GRX1 and GRX2 are 11-bit or 2048 step gain blocks. GTX1 and GTX2 are 12-bit or 4056 step gain blocks. Unity gain is set as 1024 steps. Other gains are set relative to the unity gain value. Table 3. Gain Resolution Decimal Bit Assignment 0 128 256 512 1024 2048 4096 Gain off 1/8 1/4 1/2 1 2 4 dB -infinity -18 -12 -6 0 6 12 The resolution between 0 dB (1024) and -6 dB (512) is 6 dB divided by 512 steps, or 0.0117 dB per step. Likewise, the resolution between -6 dB (512) and -12 dB (256) is 6 dB divided by 256 steps, or 0.023 dB per step. To set the digital gain code, use the following formulas: dB to digital gain code (1) y = 1024 x 10(dB/20) Convert y from decimal to hexadecimal. Insert hexadecimal representation into the gain addresses. The LSB goes into the lower address. Digital gain code to dB Convert digital gain code from hexadecimal to decimal, decimal numbers = y (2) dB = 20 x log10(y/1024) The bleed through the RTZ and CTZ blocks is controllable and determines the impedance synthesized. The ZEQ block is necessary because of the assumed current sensitivity of the SLIC. Conventional codec usage requires that the signal encoded onto the PCM output (DX) be proportional to tip/ring voltage rather than loop current. Hence, it is necessary to equalize with a transfer function proportional to |ZS()|. This is the purpose of the ZEQ block. The BAL block is a 28-tap FIR filter. Its 28-tap weights can be downloaded over the serial interface. Given an impedance ZB() for which balance is to be perfect, the proper coefficients for BAL can be computed. The mathematics to properly set these various gains and bleeds, given a desired operating environment, is complex. Among other things, to minimize noise, gains must be set so that the codec functional blocks run near maximum signal levels. The Aquarium Coefficient Software manipulates information meaningful to a system engineer into the actual data that must be downloaded to the T8536 to configure it as desired. The SLIC model used by this program is shown in Figure 6. The RX gain is the gain from the differential signal across VFROP and VFRON to the differential signal across tip and ring when the customer loop is open-circuited. Protection resistances of RP/2 are in each of the tip and ring leads. The loop current (ILOOP) is sensed and multiplied by a transconductance (TX gain) to create the output signal VFXI. The resolution between 0 dB (1024) and +6 dB (2048) is 6 dB divided by 1024 steps, or 0.0058 dB per step. Agere Systems Inc. 9 Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Configuring Impedance Synthesis Parameters (continued) Table 4 shows the serial control words associated with impedance synthesis and level setting. Notice that the logical control words are variable numbers of bytes in length. Therefore, word in this context is the normal English usage and not as in C programming, where it often denotes exactly 2 bytes or 4 bytes. For the most part, the names given to the control words make it obvious which function they control. Table 4. Control Words Associated with Impedances and Levels Control Word Starting Address (Hex) Bytes Default (Hex) HBALTAPS GRX1 GRX2 CTZCTRL SDCTRL GTX2 ZEQCTRL GTX1 0x00 0x84 0x86 0x8c 0x92 0x94 0x96 0x99 128 2 2 4 1 2 3 2 See text 0x0400 0x01ac 0x07ed0000 0x19 0x0400 0x000000 0x051a The default settings on the T8536 for each of these control words are the settings computed by the Aquarium Coefficient Software when the synthesis impedance and the balance impedance are both a flat 600 resistance, along with the following: RX Gain = 2.0 (3) RP = 100 (4) and TX Gain = -300 V/A DEFAULT - 7.58 dB DR 1.63 dB + VFROP + GRX2 GRX1 (5) D/A BAL + + CTZ RTZ - DX GTX2 GTX1 + ZEQ XAG A/D VFXI -2.146 dB DEFAULT + 2.11 dB 5-8085B(F) Figure 5. Block Diagram for Impedance Synthesis and Level Setting VFROP + VFRON - RX GAIN RP/2 TIP + TX GAIN VFXI ILOOP VDRIVE CURRENT SENSE ZTR - RING RP/2 5-8079 (F) Figure 6. Model for Agere SLIC 10 Agere Systems Inc. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Configuring Impedance Synthesis Parameters (continued) Hybrid Balance Taps Control Word (HBALTAPS) The remaining subword (IRTZ) selects one of eight available bleed strengths through the analog bleed block RTZ. The available bleed strengths start at zero and are equally spaced. Larger values of IRTZ give stronger bleeds. To turn termination impedance off, both IRTZ and CTZCTRL should be set to 0. The Aquarium Coefficient Software provides the coefficients for the 28 HBALTAPS settings. Use these settings for normal operation. CTZ Control Word (CTZCTRL) Default settings for HBALTAPS are all zeros except for three bytes. Table 5 gives the three exceptions. This 4-byte control word affects the bleed through the CTZ block. This control word is decomposed into subwords as shown in Table 7. Table 5. Nonzero Bytes Default Settings Address (hex) Contents (hex) 0x03 0x05 0x45 0x80 0x80 0x88 Hybrid balance can be disabled by setting all 28 taps to 0. From the default state, only the addresses in Table 5 need to be set to 0. Table 7. Decomposition of CTZCTRL Bits 31 27--30 16--26 14--15 00--13 Subword X CTZL CTZGR CTZM CTZGC Sigma-Delta Control Word (SDCTRL) The control words CTZGR and CTZGC map to gains. The control words CTZL and CTZM provide a floatingpoint quantization of a cutoff frequency. To turn off, set all bits to 0. Values for this and the next two control words are all calculated by the Aquarium Coefficient Software. Further modification is usually unnecessary. Impedance Equalization Control Word (ZEQCTRL) The SDCTRL control word is decomposed into subwords as shown in Table 6. This control word sets the coefficients for the digital portion of the termination impedance. Table 6. Decomposition of SDCTRL Bits 7 6 3--5 0--2 Subword X DLPBK3 IRTZ IXAG The most significant bit is ignored. Bit 6 is normally set to zero but can be set to one to force a certain loopback for testing. The analog gain (XAG) can be set to any of five discrete levels. The subword IXAG controls which of these levels is selected. The gain through the analog gain block will vary over 1, 2, 4, 8, and 16 (0 dB to 24 dB) as IXAG varies from 0 to 4. Writing values of 5, 6, or 7 to IXAG will lead to unpredictable results. Agere Systems Inc. The impedance equalization control word decomposes as shown in Table 5. This control sets the transmit equalization coefficients to accommodate currentsensing SLICs. For voltage-sensing SLICs, this control word should be turned off by setting all bits to 0. Table 8. Decomposition of ZEQCTRL Bits 21--23 16--20 12--15 00--11 Subword X ZEQM ZEQL ZEQG The subword ZEQG sets a gain. The subwords ZEQM and ZEQL are a floating-point quantization of a cutoff frequency. 11 Using the T8535B/T8536B Quad Programmable Codec Additional Functions T8536 Latch Control Words Latch control bits are readable and writable over the serial interface. This feature allows the serial control interface of the codec to access standard SLIC registers or other devices and to gain access to such important things as on-hook versus off-hook status. Note that latches 0 and 1 are reported by the fast scan command. SLICTS, SLICWR, and SLICRD have the subwords shown in Table 9. Table 9. Decomposition of SLICTS, SLICWR, and SLICRD Bits 6--7 5 4 3 2 1 0 Subword X SLIC5 SLIC4 SLIC3 SLIC2 SLIC1 SLIC0 Each channel is written or read once every 125 s. Channel 0 is updated approximately 30 s after frame strobe, channel 1 at about 60 s after frame strobe, channel 2 at 90 s, and channel 3 at 120 s. Beware, if multiple commands are written to the latch registers within a frame strobe period, only the last command will be executed. For lowest power dissipation, unused latches should be set as outputs and programmed low. This would apply to latches that are unavailable in certain package options. SLIC 3-State Control Word (SLICTS) The SLIC 3-state control word defines a latch interface as either an input (bit set to 0) or an output (bit set to 1). Latches 2 and 3 on each channel are output defaults at powerup, after a hardware reset, or after a RESCTRL bit 0 reset. They provide a logic-low output in the default state (assuming BCLK and FS are present). The other latches are input defaults. Pull-ups or pull-downs may be required to ensure stable levels until this word is loaded by the initialization routine. The control inputs of many Agere SLICs have integrated pull-up resistors. Latches 2 and 3 can be 12 Application Note September 2001 used to force the SLIC into the low-power scan state before initialization occurs, thereby avoiding additional external components. SLIC Write Control Word (SLICWR) The SLIC write control word writes control data to latches designated as outputs. Updates will occur within 125 s. Only the last update will be recognized within a 125 s period, so allow 125 s between writes to the same channel or between write all channel commands. Besides SLIC control, latch outputs can be used to sink current to control other devices. SLIC Read Control Word (SLICRD) The SLIC read control word reads control data from any latch whether designated as an input or an output. Latches are strobed every 125 s (coincident with frame strobe). Loopbacks Signal loopback controls reside in three words, SDCTRL, SDTSI, and PCMCTRL. All loopbacks must be programmed prior to channel activation. Two analog and three digital loopbacks are provided per channel. The analog loopbacks allow a signal applied to the codec analog input (VFXI) to be looped back to the codec analog outputs (VFROP and VFRON). The signal is allowed to pass to the codec digital output (DX) during this operation, but incoming digital signals (on DR) are disconnected. The digital loopbacks allow a signal applied to the codec digital input (DR) to be looped back to the codec digital output (DX). The signal is allowed to pass to the codec analog outputs (VFROP and VFRON) during this operation, but incoming analog signals (at VFXI) are disconnected. Expect no loss through any loopback except digital loopback 3. Digital loopback 3 attenuates signals by 0.5 dB. In addition, digital loopback 3 occurs prior to the differential driver, so loopback signals will appear 6 dB lower. For digital loopback 3 and the analog loopbacks, be sure to consider the inherent gains (-2.146 dB for TX, +1.63 dB for RX) shown in Figure 5. Agere Systems Inc. Using the T8535B/T8536B Quad Programmable Codec Application Note September 2001 Miscellaneous Control Words Reset Control Word (RESCTRL) The reset control word provides the following two perchannel software reset controls: Bit 0 resets all control words to default values. Bit 1 resets all state variables. Sigma-Delta Time-Slot Interchanger Control Word (SDTSI) SDTSI has subwords as shown in Table 10. Table 10. Decomposition of SDTSI Bits 7 6 4--5 3 2 0--1 Subword X DLPBK2 DATSI ARXIDLE ALPBK1 ADTSI The sigma-delta time-slot interchanger control word allows the user to map any channel's analog circuitry section to any channel's digital circuitry section (DATSI and ADTSI). This is primarily used in testing, but it could be employed to minimize group delay for a given connection. ARXIDLE inserts alternating bit idle code into the analog receive section of the codec. The loopbacks are discussed in the data sheet. PCM Control Word (PCMCTRL1 and 2) The PCM control words have subwords as shown in Table 11 and Table 12. 3-STATE allows the user to turn off an assigned time slot of the PCM output. When this bit is selected, whatever time slot is assigned to the transmit channel being addressed will be 3-stated. TXLOW sets all bits low for the assigned transmit time slot. Agere Systems Inc. LINSB selects whether linear mode operation will be MSB first or LSB first. The choice applies to both TX and RX for a given channel. RXIDLE inserts idle channel code after the -law, A-law conversion block into the receive path. Bits 2 and 3 set loopback modes. Bit 1 selects linear mode and bit 0 selects -law or A-law mode. Each channel can be set for its own mode of operation. DX1 and DR1 select PCM port 1 for a given channel. Any transmit or receive time-slot for any channel can be assigned to either PCM port. DBLCLK selects double-clock mode where the BCLK runs at twice the rate of DX and DR. The EDGE registers allow data and frame strobe to be latched on a rising or falling edge of BCLK. Table 11. Decomposition of PCMCTRL1 Bits 7 6 5 4 3 2 1 0 Subword 3-STATE TXLOW LINSB RXIDLE DLPBK1 ALPBK2 LIN COMP Table 12. Decomposition of PCMCTRL2 Bits 7 6 5 4 3 2 1 0 Subword X X DX1 DR1 DBLCLK TXEDGE RXEDGE FSEDGE Verify Control Word (VERIFY) The verify control word is a register that can be used to test the integrity of the serial interface. 13 Using the T8535B/T8536B Quad Programmable Codec Board Layout and Decoupling Concentrating four sets of analog/digital conversions in an integrated device places an extra burden on the board layout. Highly sensitive analog nodes and noisy digital circuits are placed in close proximity. The high dynamic range of the codec, which allows low noise transmission of very small signal levels with minimal crosstalk, could be jeopardized if proper grounding and decoupling practices are not followed. Furthermore, the codec will fail distortion and noise requirements if proper grounding is not provided. For best performance, a multilayer board is recommended. One inner layer should be used for a common, low-impedance ground plane. For a multilayer board, the user has the option of keeping analog and digital grounds separate; however, it is recommended that they be shorted together. It is perfectly acceptable to short SLIC AGND and the codec AGND, DGND, and SGND pins directly to the inner ground layer. If separate ground planes are used, make sure the planes are adequately sized for low impedance and short the analog and digital grounds together at the edge connector or supply. Use individual vias for each device ground pin. If a two-layer board is to be used, a low-impedance ground plane must be established. A microisland (flooded ground plane) and fat ground traces must be Application Note September 2001 used. To get the lowest-impedance ground plane possible, tie AGND, DGND, and SGND leads together at the chip. Provide a dedicated ground plane under the device to connect these pins together. Fill unused areas around the device and board with ground. Minimize the use of vias in ground planes. If the ground plane must transfer to the other layer, use multiple vias for a better connection. Give the ground planes routing priority over signal traces. Keep clock traces short and guard, if possible. If a 16.384 MHz BCLK is to be used, a multilayer board design is the prudent choice. For all designs, place a 0.1 F or 0.047 F ceramic capacitor on all power pins to ground and at the power input to the board. Keep leads short by placing vias as close to solder pads as possible. Use individual vias for each power pin. Use a large bulk storage capacitor at power distribution points and at the power input to the board. Decouple tip and ring leads and use commonmode ferrites to minimize EMI. To minimize harmonic interference, keep analog leads to the SLIC and digital leads to the microprocessor and PCM control separate from one another. Digital traces require a continuous adjacent return path to minimize emissions. Decouple any power or ground discontinuities. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved September 2001 AP01-071ALC (Replaces AP01-044ALC)