CY7C130
1 K × 8 Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06002 Rev. *J Revised November 12, 2013
1 K × 8 Dual-Port Static RAM
Features
■True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■1 K × 8 organization
■0.65 micron CMOS for optimum speed and power
■High speed access: 55 ns
■Low operating power: ICC = 110 mA (maximum)
■Fully asynchronous operation
■Automatic power-down
■BUSY output flag on CY7C130
■INT flag for port-to-port communication
■Available in 48-pin DIP (CY7C130)
Functional Description
The CY7C130 is a high speed CMOS 1 K by 8 dual-port static
RAMs. Two ports are provided permitting independent access to
any location in memory. The CY7C130 can be used as a
standalone 8-bit dual-port static RAM. It is the solution to
applications requiring shared or buffered data, such as cache
memory for DSP, bit-slice, or multiprocessor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FE for the left port and 3FF for the right
port). An automatic power down feature is controlled
independently on each port by the chip enable (CE) pins.
The CY7C130 is available in 48-pin DIP.
R/WL
BUSYL
CEL
OEL
A9L
A0L A0R
A9R
R/WR
CER
OER
CER
OER
CEL
OEL
R/WLR/WR
I/O7L
I/O0L
I/O7R
I/O0R
BUSYR
INTLINTR
ARBITRATION
LOGIC
(7C130)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
DECODER
[1]
[2] [2]
Logic Block Diagram
[1]
Notes
1. CY7C130 (Master): BUSY is open drain output and requires pull-up resistor.
2. Open drain outputs: pull-up resistor required.
CY7C130
Document Number: 38-06002 Rev. *J Page 2 of 18
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................6
Switching Waveforms ...................................................... 8
Typical DC and AC Characteristics ..............................13
Ordering Information ...................................................... 14
Ordering Code Definitions .........................................14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support ..................................................... 18
CY7C130
Document Number: 38-06002 Rev. *J Page 3 of 18
Pin Configurations
Figure 1. 48-pin DIP pinout (Top View)
13
14
15
16
17
18
19
20
21
22
23 26
27
28
32
31
30
29
33
36
35
34
24 25
GND
1
2
3
4
5
6
7
8
9
10
11 38
39
40
44
43
42
41
45
48
47
46
12 37
R/WL
CEL
BUSYL
INT
L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
CER
R/WR
BUSY
R
INT
R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
VCC
7C130
Pin Definitions
Left Port Right Port Description
CELCERChip enable
R/WLR/WRRead/write enable
OELOEROutput enable
A0L–A9L A0R–A9R Address
I/O0L–I/O7L I/O0R–I/O7R Data bus input/output
INTLINTRInterrupt flag
BUSYLBUSYRBusy flag
VCC Power
GND Ground
Selection Guide
Parameter 7C130-55 Unit
Maximum access time 55 ns
Maximum operating current Commercial 110 mA
Maximum standby current Commercial 35 mA
CY7C130
Document Number: 38-06002 Rev. *J Page 4 of 18
Maximum Ratings
Exceeding maximum ratings [3] may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground potential
(pin 48 to pin 24) ..........................................–0.5 V to +7.0 V
DC voltage applied to outputs
in high Z State ..............................................–0.5 V to +7.0 V
DC input voltage ..........................................–3.5 V to +7.0 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0 °C to +70 °C 5 V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter [4] Description Test Conditions 7C130-55 Unit
Min Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage IOL = 4.0 mA – 0.4 V
IOL = 16.0 mA [5] –0.5V
VIH Input HIGH voltage 2.2 – V
VIL Input LOW voltage – 0.8 V
IIX Input leakage current GND < VI < VCC –5 +5 µA
IOZ Output leakage current GND < VO < VCC, output disabled –5 +5 µA
IOS Output short circuit current [6, 7] VCC = Max, VOUT = GND – –350 mA
ICC VCC operating supply current CE = VIL, outputs open, f = fMAX[8] Commercial – 110 mA
ISB1 Standby current both ports, TTL
inputs
CEL and CER > VIH, f = fMAX[8] Commercial – 35 mA
ISB2 Standby current one port, TTL
inputs CEL or CER > VIH,
active port outputs open,
f = fMAX[8]
Commercial – 75 mA
ISB3 Standby current both ports,
CMOS inputs
Both ports
CEL and CER > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0
Commercial – 15 mA
ISB4 Standby current one port, CMOS
inputs
One port
CEL or CER > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
active port outputs open, f = fMAX[8]
Commercial – 70 mA
Notes
3. The voltage on any input or I/O pin cannot exceed the power pin during power up.
4. See the last page of this specification for Group A subgroup testing information.
5. BUSY and INT pins only.
6. Duration of the short circuit should not exceed 30 seconds.
7. This parameter is guaranteed but not tested.
8. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3 V.
CY7C130
Document Number: 38-06002 Rev. *J Page 5 of 18
Capacitance
Parameter [7] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 5.0 V 15 pF
COUT Output capacitance 10 pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.0 V
5 V
OUTPUT
R1 893
R2
347
30 pF
INCLUDING
JIGAND
SCOPE
GND
90% 90%
10%
5ns 5ns
5 V
OUTPUT
R1 893
R2
347
5pF
INCLUDING
JIGAND
SCOPE
(a) (b)
OUTPUT 1.40 V
Equivalent to: THÉVENIN EQUIVALENT
5 V
281
30
pF
BUSY
OR
INT
BUSY Output Load
(CY7C130)
10%
ALL INPUT PULSES
250
CY7C130
Document Number: 38-06002 Rev. *J Page 6 of 18
Switching Characteristics
Over the Operating Range
Parameter [9, 10] Description 7C130-55 Unit
Min Max
Read Cycle
tRC Read cycle time 55 –ns
tAA Address to data valid [11] –55 ns
tOHA Data hold from address change 0 – ns
tACE CE LOW to data valid [11] –55 ns
tDOE OE LOW to data valid [11] –25 ns
tLZOE OE LOW to low Z [12, 13, 14] 3 – ns
tHZOE OE HIGH to high Z [12, 13, 14] –25 ns
tLZCE CE LOW to low Z [12, 13, 14] 5 – ns
tHZCE CE HIGH to high Z [12, 13, 14] –25 ns
tPU CE LOW to power-up [12] 0 – ns
tPD CE HIGH to power-down [12] –35 ns
Write Cycle [15]
tWC Write cycle time 55 –ns
tSCE CE LOW to write end 40 –ns
tAW Address set-up to write end 40 –ns
tHA Address hold from write end 2 – ns
tSA Address set-up to write start 0 – ns
tPWE R/W pulse width 30 –ns
tSD Data set-up to write end 20 –ns
tHD Data hold from write end 0 – ns
tHZWE R/W LOW to high Z [14] –25 ns
tLZWE R/W HIGH to low Z [14] 0 – ns
Notes
9. See the last page of this specification for Group A subgroup testing information.
10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
IOL/IOH, and 30 pF load capacitance.
11. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V.
12. This parameter is guaranteed but not tested.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of Figure 2 on page 5. Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C130
Document Number: 38-06002 Rev. *J Page 7 of 18
Busy/Interrupt Timing
tBLA BUSY LOW from address match –30 ns
tBHA BUSY HIGH from address mismatch [16] –30 ns
tBLC BUSY LOW from CE LOW –30 ns
tBHC BUSY HIGH from CE HIGH[16] –30 ns
tPS Port set-up for priority 5 – ns
tWB R/W LOW after BUSY LOW 0 – ns
tWH R/W HIGH after BUSY HIGH 35 –ns
tBDD BUSY HIGH to valid data –45 ns
tDDD Write data valid to read data valid –Note 17 ns
tWDD Write pulse to data delay –Note 17 ns
Interrupt Timing
tWINS R/W to INTERRUPT set time –45 ns
tEINS CE to INTERRUPT set time –45 ns
tINS Address to INTERRUPT set time –45 ns
tOINR OE to INTERRUPT reset time [18] –45 ns
tEINR CE to INTERRUPT reset time [18] –45 ns
tINR Address to INTERRUPT reset time [18] –45 ns
Switching Characteristics (continued)
Over the Operating Range
Parameter [9, 10] Description 7C130-55 Unit
Min Max
Notes
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
18. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of Figure 2 on page 5. Transition is measured ±500 mV from steady state voltage.
CY7C130
Document Number: 38-06002 Rev. *J Page 8 of 18
Switching Waveforms
Figure 3. Read Cycle No. 1 [19, 20]
Figure 4. Read Cycle No. 2 [19, 21]
Figure 5. Read Cycle No. 3 [20]
tACE
tLZOE
tDOE tHZOE
tHZCE
DATA VALID
DATAOUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
Either Port CE/OE Access
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSY
L
DOUTL
tPS
tBLA
Read with BUSY, Master: CY7C130
tRC
tPWE
VALID
tHD
Notes
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
21. Address valid prior to or coincident with CE transition LOW.
CY7C130
Document Number: 38-06002 Rev. *J Page 9 of 18
Figure 6. Write Cycle No. 1 (OE Three-States Data I/Os – Either Port [22, 23]
Figure 7. Write Cycle No. 2 (R/W Three-States Data I/Os – Either Port) [24, 25]
Switching Waveforms (continued)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA tPWE
tHD
tSD
tHA
CE
R/W
ADDRESS
tHZOE
OE
DATAOUT
DATAIN
Either Port
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
DATA VALID
tLZWE
ADDRESS
CE
R/W
DATAOUT
DATAIN
Notes
22. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
24. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
25. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
CY7C130
Document Number: 38-06002 Rev. *J Page 10 of 18
Figure 8. Busy Timing Diagram No. 1 (CE Arbitration)
Figure 9. Busy Timing Diagram No. 2 (Address Arbitration)
Switching Waveforms (continued)
ADDRESS MATCH
tPS
CEL Valid First:
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS L,,R
BUSYR
CEL
CER
BUSYL
CER
CEL
ADDRESSL,R
CER Valid First:
Left Address Valid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSY
R
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY
L
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
CY7C130
Document Number: 38-06002 Rev. *J Page 11 of 18
Figure 10. Busy Timing Diagram No. 3
Switching Waveforms (continued)
tPWE
tWB tWH
Write with BUSY
BUSY
R/W
CE
CY7C130
Document Number: 38-06002 Rev. *J Page 12 of 18
Figure 11. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 3FF
tINS
tWC
tEINS
Right Side Clears INTR
tHA
tSA tWINS
READ 3FF
tRC
tEINR
tHA tINT
tOINR
WRITE 3FE
tINS
tWC
tEINS
tHA
tSA tWINS
Right Side Sets INTL
Left Side Sets INTR
Left Side Clears INTL
READ 3FE
tEINR
tHA tINR
tOINR
tRC
ADDRESSR
CEL
R/WL
INTL
OEL
ADDRESSR
R/WR
CER
INTL
ADDRESSR
CER
R/WR
INTR
OER
ADDRESSL
R/WL
CEL
INTR
CY7C130
Document Number: 38-06002 Rev. *J Page 13 of 18
Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0 –55 25 125
1.2
1.0
120
100
80
60
40
20
0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
0.8
0.6
0.6
NORMALIZED ICC, ISB
VCC = 5.0V
VIN = 5.0V
VCC = 5.0V
TA = 25C
0
ICC
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.8
1.25
1.0
0.75
10 40
NORMALIZED ICC
0.50
NORMALIZED ICC vs. CYCLE TIME
CYCLE FREQUENCY (MHz)
3.0
2.5
2.0
1.5
0.5
0 1.0 2.0 3.0 5.0
NORMALIZED tPC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
DELTA tAA (ns)
0
15.0
0.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0 1000
1.0
20 30
0.2
0.6
1.2
ISB3 0.2
0.4
25
1.1
VCC = 4.5V
VIN = 0.5V
NORMALIZED ICC, ISB
ICC
ISB3
TA = 25CVCC = 5.0V
VCC = 5.0V
TA = 25C
TA = 25C
VCC = 4.5V
VCC = 4.5V
TA = 25C
CY7C130
Document Number: 38-06002 Rev. *J Page 14 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY7C130-55PC P25 48-pin (600 Mil) Molded DIP Commercial
Temperature Range:
C = Commercial
Package Type:
P = 48-pin Molded DIP
Speed: 55 ns
Part Number Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
130C-55PCCY 7
CY7C130
Document Number: 38-06002 Rev. *J Page 15 of 18
Package Diagrams
Figure 12. 48-pin PDIP (2.460 × 0.550 × 0.170 inches) P48.6 Package Outline, 51-85020
51-85020 *D
CY7C130
Document Number: 38-06002 Rev. *J Page 16 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
DIP Dual In-line Package
I/O Input/Output
OE Output Enable
PDIP Plastic Dual In-line Package
SRAM Static Random Access Memory
TTL Transistor-Transistor Logic
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
ms millisecond
mV millivolt
ns nanosecond
pF picofarad
Vvolt
Wwatt
CY7C130
Document Number: 38-06002 Rev. *J Page 17 of 18
Document History Page
Document Title: CY7C130, 1 K × 8 Dual-Port Static RAM
Document Number: 38-06002
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 110169 SZV 09/29/01 Change from Spec number: 38-00027 to 38-06002
*A 122255 RBI 12/26/02 Power up requirements added to Maximum Ratings Information
*B 236751 YDT See ECN Removed cross information from features section
*C 325936 RUY See ECN Added pin definitions table, 52-pin PQFP package diagram and Pb-free infor-
mation
*D 393153 YIM See ECN Added CY7C131-15JI to ordering information
Added Pb-Free parts to ordering information:
CY7C131-15JXI
*E 2623540 VKN /
PYRS
12/17/08 Added CY7C130A and CY7C131A parts
Removed military information
Updated ordering information.
*F 2897217 RAME 03/22/2010 Updated Ordering Information.
Updated Package Diagrams.
*G 3054633 ADMU 10/11/2010 Updated Ordering Information and added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*H 3402163 ADMU 10/12/2011 Removed pruned part CY7C131-25NC from Ordering Information
Updated Package Diagrams.
*I 3796621 SMCH 10/29/2012 Updated Features (Removed CY7C130A, CY7C131, CY7C131A related
information; removed 52-pin PLCC, 52-pin TQFP package related
information).
Updated Functional Description (Removed CY7C130A, CY7C131, CY7C131A
related information; removed 52-pin PLCC, 52-pin TQFP package related
information).
Updated Pin Configurations (Removed 52-pin PLCC, 52-pin TQFP package
related information).
Updated Selection Guide (Removed CY7C130A, CY7C131, CY7C131A
related information; removed 15 ns, 25 ns, 30 ns, 35 ns, 45 ns speed bins
information, removed Industrial temperature range information).
Updated Operating Range (Removed Industrial temperature range and Military
temperature range information).
Updated Electrical Characteristics (Removed CY7C130A, CY7C131,
CY7C131A related information; removed 15 ns, 25 ns, 30 ns, 35 ns, 45 ns
speed bins information).
Updated Switching Characteristics (Removed CY7C130A, CY7C131,
CY7C131A related information; removed 15 ns, 25 ns, 30 ns speed bins
information).
Updated Switching Characteristics (Removed CY7C130A, CY7C131,
CY7C131A related information; removed 35 ns, 45 ns speed bins information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (Removed 52-pin PLCC, 52-pin TQFP package
related information).
*J 4189630 SMCH 11/12/2013 Updated in new template.
Completing Sunset Review.
Document Number: 38-06002 Rev. *J Revised November 12, 2013 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C130
© Cypress Semiconductor Corporation, 2001-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
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