TOSHIBA THLY641681FG-80,-80L,-10,-10L TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THLY641681FG is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of eight TC59SM716FT/FTL DRAMs on a printed circuit board. FEATURES @ 16,777,216-word by 64-bit organization Single power supply of 3.3V + 0.3V @ Pipeline architecture -80 -10 e Auto-refresh and Self-refresh capability tex Clock Cycle Time (CL = 2) 10 ns 12ns @ All inputs and outputs LVTTL-compatible tras Active-to-Precharge Command 48 60 e 4096 refresh cycles per 64 ms Period (min) ns ns e@ Package: 144-pin small-outline DIMM tac Access Time from CLK (CL = 2) 6ns 8ns (gold contacts) tec Ref/Active-to-Ref/Active 68 ns 84 ns e JEDEC Standard Command Period (min) PIN ASSIGNMENT PIN NAMES AO to All Address In FRONT \ = In i Row Address Strobe Column Address Strobe Write Enable BACK LOTT |) OTT In O02 60~ 62 1440 E | Clock for PD Power (+3.3 000707EBA2 @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. @ The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION far any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 2000-07-14 1/13TOSHIBA THLY641681FG-80,-80L,-10,-10L Serial Presence Detect (Rev.1.2A) Byte ; ; -80 -10 Number Function Described Entry Value Entry Entry Value Entry 0 mio bytes Written into Serial Memory at Module 128bytes 80h 128bytes 80h 1 Total # bytes of SPD Memory Device 256bytes 08h 256bytes 08h 2 (PPM EDO. SDRAM) frome Appendix A SDRAM 04h SDRAM 04h 3 # Row Addresses on this Assembly RAO-RA11 0Ch RAO-RA11 0Ch 4 # Column Addresses on this Assembly CA0-CAB 09h CA0-CAB 09h 5 # Module Banks on this Assembly 2Bank 02h 2Bank 02h 6 Data Width of this Assembly... x64 40h x64 40h 7 ..Data Width Continuation x64 00h x64 00h 8 Voltage Interface Standard of this Assembly LVTTL Oth LVTTL Oth 9 epRam Cycle Time at Max. Supported CAS Latency (CL), CL = 3, 8.0ns 80h CL = 3, 10ns Aoh 10 SDRAM Access from Clock @ CL = X CL = 3, 6.0ns 60h CL = 3, 7.0ns 70h 11 DIMM Configuration Type (Non-parity, Parity, ECC) Non-Parity 00h Non-Parity 00h 12 Refresh Rate/Type 15.625 ysiselt 80h 15.625 ysiself 80h 13 SDRAM Width, Primary DRAM x16 10h x16 10h 14 Error Checking SDRAM Data Width N/A 00h N/A 00h 15 minimum Clock Delay, Back to Back Random Column 41CLK Oth 1CLK Oth 16 Burst Lengths Supported 1,2,4,8 Full page 8Fh 1,2,4,8 Full page 8Fh 17 # Banks on each SDRAM Device 4Bank 04h 4Bank 04h 18 CAS # Latencies Supported 2,3 06h 2,3 06h 19 Cs # Latency Oth Oth 20 WE # Latency Oth Oth 21 SDRAM Module Attributes 00h 00h 22 SDRAM Device Attributes: General OEh OEh 23 Minimum Clock Cycle Time at CL- X-1 CL = 2, 10 ns AOdh CL = 2, 12 ns coh 24 Maximum Data Access Time from Clock @ CL X-1 CL = 2, 6.0ns 60h CL = 2, 8.0ns 80h 25 Minimum Clock Cycle Time at CL X-2 00h 00h 26 Maximum Data Access Time from Clock @ CL X-2 00h 00h 27 Minimum Row Precharge Time 20ns 14h 24ns 18h 28 Minimum Row Active to Row Active Delay 20 ns 14h 20 ns 14h 29 Minimum RAS to CAS Delay 20 ns 14h 24ns 18h 30 Minimum RAS Pulse Width 48 ns 30h 60 ns 3Ch 31 Madule/Bank Density 64 MB 10h 64 MB 10h 32 Command & Address signal Input Setup Time 2ns 20h 2.5 ns 25h 33 Command & Address Signal Input Hald Time Ins 10h Ins 10h 34 Data signal Input Setup Time 2ns 20h 2.5 ns 25h 35 Data signal Input Hold Time Ins 10h Ins 10h 36-61 Superset Information (may be used in future) FFh FFh 62 SPD Revision Rev.1.2A 12h Rev.1.2A 12h 63 Checksum for bytes 0-62 1ED2h D2h 1F60h 60h Option Manufacturers JEDEC ID Code per JEP-106E Manufacturing Location Manufacturer's Part Number Revision Code Manufacturing Date Serial Number Manufacturer Data Reserved Reserved Intel Specification Intel Specification Intel Specification Intel Specification 2000-07-14 2/13TOSHIBA THLY641681FG-80,-80L,-10,-10L BLOCK DIAGRAM CKEO cso CKE1 CLK LbQqm - pamBo e Loam CLK vor F pao oF 1 cee! = M1 to feo foe MI fea! upam /o pams1 oJ upem |=! _ RAS | 1 RAS} AA 1CAS! 1Q9 [7 DQs oF a9 1 CAS! b\AA 1_~ "1 ' : i : i ~ PSI LWE} = AO~11,BSO1 ote bio pais of org AO~TBSO.1 | WE! CLK LbQM - pams2 { Loam CLK vo1 FO pee =e, 01 cee) = M2 F203 foe = MI Ec 'RAS! upam /o pamBs3 o] upem RAS! Lod CLKO o4 rT CAS! Qa FO pQ2za4 OF E9 | CAS! to CLK1 LWE; = AO~11,BS0,1 gig Lko gar oH org = 89711, BS0,1 | WE} CLK LbqM - pams4 o4 Loam CLK vol F-a3z, of 01 FCKE! M3 = F- ows oF wos M3 ice! 'RAS! UDQM -o pames o{ UDQeM |=! ou | I ; RAS; a LWA 1CAS! Q9 _o DQ40 oF Q9 | EAS! MA a7 1 : : : ' ~ SSI (WE } = AO~11,BS0,1 gig ko pqay Of voig = A071 BSO,1 | WE! CLK LobqM - paves o{ Loam CLK vol F peas. Oo 01 cee] = Mtoe fe oss ows MA fee RAS! upgm /o pams7 oJ upom | RAS! -, 1 Lo o 1 i=? 'CAS| a9 DQsE ] vas | Cas! 1_~ "1 : : ' : ' ~ pel LWE} AO~11,BSQ1 nig bio pages of voig O71 BSO.1 | WE! /RAS, /CAS, (WE A0~11, BAO, 1 Vpp T T M1~4 Vop E2PROM Vv T Ci~4 F C5~8 F CI~12 V > C13 SS 0 M1~4 3S 6 E2PROM 102, 10P 5 CLK1 rr scLoJsc. FE2PROM cpal , con AO Al A2 WC LJ} T 777 2000-07-14 3/13TOSHIBA THLY641681FG-80,-80L,-10,-10L ABSOLUTE MAXIMUM _ RATINGS SYMBOL ITEM RATING UNIT NOTES Vin Input Voltage -0.5 to Vpp + 0.3 Vv 1 Vout Output Valtage -0.5 to Vpp + 0.3 Vv 1 Vop Power Supply Voltage -0.5 to 46 Vv 1 Topr Operating Temperature 0 to 70 c 1 Tst Storage Temperature -55 to 125 C 1 Pp Power Dissipation 2.4 Ww 1 lout Short Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES Vopp Supply Voltage 3.0 3.3 3.6 Vv 2 Vin LVTTL Input High Voltage 2.0 - Vop + 0.3 V 2 VIL LVTTL Input Low Voltage -0.5 - 0.8 Vv 2 CAPACITANCE (Vpp = 3.3V,f = 1MHz, Ta = 0 to 70C) SYMBOL PARAMETER MIN MAX UNIT C, Input Capacitance (AO to A11) - 50.0 pF CG Input Capacitance (RAS, CAS, WE) - 50.0 pF C3 Input Capacitance (CLKO,1) - 40.0 pF Ca Input Capacitance (C50) - 35.0 pF Cs Input Capacitance (DQMBO to 7) - 20.0 pF Cog \/O Capacitance (DQO to DQ63) - 20.0 pF 2000-07-14 4/13TOSHIBA THLY641681FG-80,-80L,-10,-10L DC CHARACTERISTICS (Vpp = 3.3V + 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL ITEM UNIT | NOTES MIN MAX MIN MAX lec OPERATING CURRENT 4 . Active-Precharge Command Cycling . without Burst Operation, 1-Bank 1 Row Operation ~ 480 ~ 420 mA 3,5 lcc1B_ | Operation (tex = tre min) STANDBY CURRENT lec2 | (ey = min, &S = Vu, CKE = Viy - 320 - 280 ; ; Vine = Vin (min) / Vi, (max) CKE = Vi " lcc2e_ | Bank: Inactive State) (Power-down Mode) - 8 - 8 STANDBY CURRENT lec2s (CLK - VIL, CS - Vin, CKE = Vin - 80 - 80 A Viet = Vin (min) / Vi, (max) CKE = Vi, m Iccaps_ | Bank: Inactive State) (Power-down Mode) 7 8 ~ 8 lecg__ | NO OPERATING CURRENT CKE = Viq - 360 - 320 (tex = min, CS = Viy (min) CKEZV mA . : = VIL lec3p Bank: Active State (2 Banks)) (Power-down Mode) - 80 - 80 BURST OPERATING CURRENT leca _ . . ; - 600 - 500 mA 3,4 (tck = min, CS = Viyq (min) Read/Write Command Cycling) AUTO-REFRESH CURRENT lees ; - 1440 - 720 mA 3 (tex = min, Auto-Refresh Command Cycling) SELF-REFRESH CURRENT THLY641681FG-80,-10 - 16 - 16 C5 | (Selt-Refresh Mode, CKE = 0.2V my) 3 (Self-Refresh Mode, = 0.2V) | THLY641681FG-80L,-10L - 6.4 - 6.4 INPUT LEAKAGE CURRENT (OV = Vin = Vpp, All Other Pins Not under Test = 0V) OUTPUT LEAKAGE CURRENT (Doyt Is Disabled, OV S Vout s Vpp) OUTPUT LEVEL Vou 2.4 - 24 - Vv LVTTL Output H Level Voltage (lout = - 2mA) OUTPUT LEVEL VoL - 0.4 - 0.4 Vv LVTTL Output L Level Voltage (lout = 2 mA) 2000-07-14 5/13TOSHIBA THLY641681FG-80,-80L,-10,-10L AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Vpp = 3.3V + 0.3V, Ta = 0 to 70C) SYMBOL PARAMETER aT 80 AX ae 10 TAX] UNIT | NOTES tre Ref/Active-Ref/Active Command Period 68 84 tras Active- Precharge Command Period 48 100000 60 100000 ns trep Active-Read/Write Command Delay Time 20 24 teen Read/Write(a) -Read/Write(b) 1 1 cycle 7 Command Period tre Precharge-Active Command Period 20 24 treo Active(a)-Active(b) Command Period 20 20 twre Write Recovery Time CL* =2 10 12 CL* = 3 8 10 tek CLK Cycle Time CL* = 2 10 1000 12 1000 CL* = 3 8 1000 10 1000 tc CLK High Level Width 3 3 10 tet CLK Low Level Width 3 3 tac Access Time from CLK CL* =2 6 8 CL* = 3 6 7 tou Output Data Hold Time 3 3 tuz Output Data High Impedance Time 3 8 3 10 8 tiz Output Data Low Impedance Time 0 0 ns tsp Power-down Mode Entry Time 0 8 0 10 tr Transition Time of CLK (Rise and Fall) 0.5 10 0.5 10 tps Data-in Set-up Time 2 2.5 toy Data-in Hold Time 1 1 tas Address Set-up Time 2 2.5 tay Address Hold Time 1 1 teks CKE Set-up Time 2 2.5 teKH CKE Hold Time 1 1 tems Command Set-up Time 2 2.5 tomy Command Hold Time 1 1 trer Refresh Time 64 64 ms trsc Mode Register Set Cycle Time 16 20 ns 9 * CL is CAS latency. 2000-07-14 6/13TOSHIBA THLY641681FG-80,-80L,-10,-10L NOTES: 1. Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and their values are measured at the minimum cycle rate values tcx and trc. Input signals are changed once during tcx. 4, These parameters depend on the output loading. The specified values are obtained with the output open. 5. These valves are measured with the following conditions. Front side (or back side) : the measuring condtions on the data sheet Back side (or front side) : Stand by (measured with Iccg conditions) 6. The power-up sequence is described in Note 12. 7. AC TEST CONDITIONS Reference Level of Output Signals 1AV/1.4V Output Load See the diagram for AC Test Load (B) below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signals 2ns Reference Level of Input Signals 1.4V 3.3V 1.4V 1.2kQ ,, o Output Output Tr pF 8700 i pF AC TEST LOAD (A) AC TEST LOAD (B) 8. Transition times are measured between the Vjyq and Vy, levels. Transition (rise and fall) of input signals has a fixed slope. 9. tuz, defines the time at which the outputs go open circuit and are not reference levels. 10. These parameters depend on the number of clock cycles and depend on the operating frequency of the clock as follows: Number of clock cycles = Specified value of timing /Clock period (Round up fractions to a whole number.) 2000-07-14 7/13TOSHIBA THLY641681FG-80,-80L,-10,-10L 11. 12. tcy is the pulse width of CLK measured from the positive edge to the negative edge and referenced to Vyiy (min). tcy, is the pulse width of CLK measured from the negative edge to the positive edge and referenced to Viz (max). Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Vpp and VppQ (simultaneously) with all input signals heldin the NOP state. The CLK signal must be started at the same time as power is applied. 2) After power-up a pause of at least 200 seconds is required. Then, DQM and CKE must be held High (at the Vpp level) to ensure that the DQ output is high-impedance. 3) Both banks must be precharged. 4) The Mede Register Set command must be asserted to initialize the Mode register. 5) An Auto-Refresh operation must consist of at least eight Auto-Refresh cycles. The order in which 4) and 5) are performed is interchangeable. 2000-07-14 8/13TOSHIBA THLY641681FG-80,-80L,-10,-10L TIMING DIAGRAMS Read Timing Read CAS Latency af \_S \f WF VF LS Go (C51) RAS U4 CAS YW 7 A0 to A11, BAO, 1 teac tac tac _| tuz A tz ton ton DQO to 63 VALID VALID \ A DATA-OUT DATA-OUT y Read Command I | sdhas Burst Length 2000-07-14 9/13TOSHIBA THLY641681FG-80,-80L,-10,-10L Command Input Timing tek tet tcH (Le) vi _ \ i \_ \ cf \_f \ T i | of T tr tems, | stew, town tc s LLP We up Co ug Cou) crs Yi, L/L ecMis | few, ( tas taH @ ABAD, | ZA WIZ. teks} tcKH teks} tcKH teks teKH J CKE =Y | \ \ \ j 4 2000-07-14 10/13TOSHIBA THLY641681FG-80,-80L,-10,-10L Control Timing for Input Data (Word Mask) ao_f \_f WF Ly tomy tems} tcmy tems ocMeo to 7 tyr vy tos} ton tos} ton tps} toy tps tpy <_$<_\_| (SS) $< | VALID VALID VALID VALID DQO to 63 DATA-IN DATA-IN DATA-IN DATA-IN 4 pL (Clock Mask) CLKO (CLK1) } tekH teks | tcKH teks <> CKE XY \ / L_\ / tos} ton tps | ton tps} toy tos] tpn ed | ~<a |~<___>-| fe} <___>} fe }<_>-| oco 10 63 IK sien, YK seen YS TK, en. VK. YO Control Timing for Output Data (Output Enable) cx) __ FN F VF VF LL tcMH tems | tcmH tems <> DQMBO to 7 f - \ \ Lj i tac tac _, tuz | tou | tou | ton VALID VALID DQO to 63 DATA-OUT DATA-OUT (Clock Mask) CLKO (CLK1) } tcKH teks | tekH teks <> 1 Y J fy CKE LK Li tac \ tac _| tac _| tac _| tou | tou ton toH VALID VALID DQO to 63 DATA-OUT VALID DATA-OUT DATA-OUT 2000-07-14 11/13TOSHIBA THLY641681FG-80,-80L,-10,-10L Mode Register Set Cycle CLKO (CLK1) G0 (CS1) RAS CAS AOD toA11, BAO, 1 Ty ms| tem trsc "I \', tems} = temH Yj ] tems] temH <>} tems] temH LL. A _ tas tay <> Set Register Data VY owe VW Ad Al Burst Length A2 A3 | Addressing Mode A4 AS CAS Latency A6 A7 | 0 | (Test Mode) A8 | 0 Reserved Ad Write Mode A110} 0 BAO] 0 Reserved BA1] 0 Ll > N =//=[,=]/ ol o]|olo =!//0],0//||/olo =/O)};/-7,O]-| oO}; -| oO I Next Command Burst uential Interleave 1 1 2 4 8 Reserved Reserved Full A3 Addressing Mode 0 Sequential 1 Interleave CAS Reserved Reserved 2 3 4 AQ Single-Write Mode Oo Burst Read and Burst Write Burst Read and Single Write 2000-07-14 12/13TOSHIBA THLY641681FG-80,-80L,-10,-10L PACKAGE DIMENSIONS (THLY641681FG) Unit: mm FRONT 67.60 +0.13 a |< 3.80 max d Elz @ eof || ff J-pop 5>e 02 -F bbe = "| 7 o A _& | |: nf oEas| ies 2! | al S U Oo U S S Sy ele} e O8 [J oO fo) = oO os * | 1 mpi usw | 2.50,| | 3.30+0.13 23.20 4.60 32.80 +0040.10 2.00+0.13 63.60 REF 2-31.80 BACK 3.70 +0.13 | | 2.10 i TT ) TTT 5 go o 30 0 UU L O U ) y C O U o U CONTACT DIMENSIONS @ THLY641681FG ; Full R rH FRONT o I H : E E S E . i N i i o6o+0.05|_ | |rsoro10|_ | o.20| re 2.50 i I 4.60 Contacts: gold Weight : 8.49 (Typ.) 2000-07-14 13/13